JP2010181818A - Gamma circuit and display drive circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a through current in a push-pull amplifier of a gamma circuit 31. <P>SOLUTION: In the gamma circuit 31, in place of the push-pull amplifier 10, N-top regulators 40-4 to 40-1 for inputting mutually adjacent reference potentials and for outputting output voltages, with potentials equal to those of the inputted reference potentials, and P-top regulators 50-3 to 50-0 are arranged. Consequently, even if a load connected to output terminals VH0-VH63 and VL0-VL63 of gradation potentials becomes "L" or "H", an N-top regulator 40 and a P-top regulator 50 adjacent to each other can operate complementarily to operate in a similar way on the push-pull amplifier 10. Since a through-current generated in the push-pull amplifier 10 hardly occurs, current consumption in the gamma circuit 31 can be lowered significantly. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a low-current-consumption gamma circuit that corrects a gradation potential for displaying an image or the like in a display device such as a liquid crystal display, and a display driving circuit using the same.

FIG. 7 is a block diagram showing a gamma circuit used in a conventional display driving circuit.
This gamma circuit has a positive polarity circuit portion and a negative polarity circuit portion (not shown) having substantially the same configuration. 7, the positive circuit portion of the gamma circuit includes input terminals VHI63, VHI55,..., VHI0 having a plurality of positive reference potentials VHI63, VHI55,. Yes. The positive reference potential is the highest at the input terminal VHI63, and then decreases in the order of VHI55, VHI31, VHI7, and VHI0.

  A plurality of push-pull amplifiers 10-4, 10-3,..., 10-0 are connected to the input terminals VHI63 to VHI0, respectively. Between the push-pull amplifier 10-4 and the push-pull amplifier 10-0, a resistance ladder 20 in which a plurality of resistance elements 20-63, 20-62,... 20-1 are connected in series is disposed. ing.

  A plurality of output terminals VH63, VH62,... VH0 are connected between the resistance elements 20-63 to 20-1 in order to output a potential obtained by sequentially reducing the output voltage of the push-pull amplifier 10-4. Has been. A plurality of output terminals VH63 to VH0 are connected to a digital / analog converter (hereinafter referred to as “DAC”) 25 for converting display data, which is a digital signal indicating the gradation of the display element, into a plurality of analog voltages. Yes.

  .., VHI0 and the plurality of output terminals VH63, VH62,..., VH0, instead of the plurality of input terminals VHI63, VHI62,. , VLI62,... VLI0 and a plurality of output terminals VL63, VL62,. The negative reference potential is the highest at the input terminal VLI63, and thereafter decreases in the order of VLI55, VLI31, VLI7, and VLI0.

  The comma circuit having such a configuration performs the following operation. The positive reference potential input to the input terminal VHI63 is output as a positive gradation potential with the current supply capability enhanced by the push-pull amplifier 10-4 while maintaining the potential as it is. Similarly, the positive reference potential input to the input terminal VHI55 is input to the push-pull amplifier 10-3, VHI31 is input to 10-2, VHI7 is input to 10-1, and VHI0 is input to 10-0. As it is, the current supply capability is enhanced and output as a positive polarity gradation potential. The same operation is performed in the negative polarity circuit section. In this way, an image or the like is displayed by the positive polarity circuit portion and the negative polarity circuit portion.

FIG. 8 is a configuration diagram showing the push-pull amplifier 10-2 in FIG.
The push-pull amplifier 10-2 has an input terminal IN that is an input terminal VHI31 and an output terminal OUT that is an output terminal VH31. An operational amplifier 11 is connected to the input terminal IN and the output terminal OUT. On the output side, a gate of a P-channel MOS transistor (hereinafter referred to as “PMOS”) 12 and an N-channel MOS transistor (hereinafter referred to as “NMOS”) 13 are provided. Is connected to the gate.

  The power supply terminal node VDD, the PMOS 12, the output terminal OUT, the NMOS 13, and the ground node GND are connected in series.

  Here, it is assumed that VH9 is selected from the state in which VL59 has been selected so far because the gradation of a certain liquid crystal element has been switched. Since VH9 which is higher than VL59 is selected from the state where VL59 has been selected so far, the load of the output terminal VH9 becomes “L” and the output terminal of the push-pull amplifier 10-2 is divided by the resistance ladder 20 The potential of OUT also becomes “L”. Since this “L” is fed back and input to the non-inverting input terminal of the operational amplifier 11, the operational amplifier 11 outputs “L”. As a result, the PMOS 12 is turned on, the NMOS 13 is turned off, and the push-pull amplifier 10-2 performs an operation of discharging the current I1.

  Next, it is assumed that VL15 is selected from the state where VH9 is selected. Since VH9> VL15, a high level (hereinafter referred to as “H”) load is connected to the output terminal VL15, and the push-pull amplifier 10-1 draws the current I2, The operation of discharging the load and reducing it to VL15 is performed.

  As a technique relating to such a gamma circuit and a display driving circuit, for example, there are the following patent documents. Patent Document 1 describes a technology of a display drive circuit using a P-top operational amplifier and an N-top operational amplifier. Patent Document 2 describes a technology of a display drive circuit using a resistance ladder.

JP-A-5-224621

Japanese Patent Laid-Open No. 2001-100711

  However, in the conventional gamma circuit using the push-pull amplifier 10 (= 10−4 to 10−0), there is a timing when the PMOS 12 and the NMOS 13 in the push-pull amplifier 10 are turned on at the same time. There is a problem that a through current I0 flows from VDD to the ground node GND. Therefore, it is conceivable to replace the push-pull amplifier 10 with a P-top type regulator or an N-top type regulator that consumes less current. However, since only one of the pull-in and discharge operations can be operated, there is a problem that a display abnormality occurs. was there.

  The gamma circuit of the present invention inputs the first potential among the adjacent first and second potentials in a reference voltage having a plurality of different potentials, and outputs the first output voltage based on the first potential. A plurality of first regulators for holding the first output voltage at a constant voltage by suppressing fluctuations on the first polarity side in the first input, and the second potential, and based on the second potential, A plurality of second regulators that suppress a variation of the second polarity side opposite to the first polarity side in the output voltage of 2 and hold the second output voltage at a constant voltage; And a voltage dividing circuit that divides one output voltage and the plurality of second output voltages to output a plurality of analog voltages having gradation levels.

  According to the gamma circuit of the present invention and the display driving circuit using the same, a plurality of reference voltages having different potentials are input, and a plurality of voltages having gradation levels are output by a push-pull amplifier and a voltage dividing circuit. In the gamma circuit, a first regulator and a second regulator are used in place of the push-pull amplifier, and the reference potentials adjacent to each other are input to each.

  Therefore, regardless of whether the analog voltage varies on the first polarity side or on the second polarity side, the first and second regulators adjacent to each other operate in a complementary manner to suppress the variation. Therefore, the same operation as the push-pull amplifier can be performed. In the present invention, since no push-pull amplifier is used, almost no through current is generated, and therefore the current consumption of the gamma circuit and the display drive circuit using the gamma circuit can be greatly reduced.

FIG. 1 is a configuration diagram showing a gamma circuit 31 according to the first embodiment of the present invention. FIG. 2 is a configuration diagram illustrating the entire display drive circuit according to the first embodiment of the present invention. FIG. 3 is a configuration diagram showing the N-top regulator 40 in FIG. FIG. 4 is a block diagram showing the P-top regulator 50 in FIG. FIG. 5 is a waveform diagram showing the operation of the display drive circuit of FIG. FIG. 6 is a configuration diagram illustrating the gamma circuit 31B according to the first embodiment of the present invention. FIG. 7 is a block diagram showing a gamma circuit used in a conventional display driving circuit. FIG. 8 is a configuration diagram showing the push-pull amplifier 10-2 in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Display Driving Circuit of Example 1)
FIG. 2 is a configuration diagram illustrating the entire display drive circuit according to the first embodiment of the present invention.

  The display driving circuit is configured as one integrated circuit, and by using a plurality of the integrated circuits, a display data signal for one line is output to the display panel.

  This display driving circuit has a differential input interface section 32 for inputting display data X0P, X0N, Y0P, Y0N, Z0P, Z0N,... With three sets of red, green and blue as one set. ing. A data latch unit 33 that temporarily captures a signal from the differential input interface unit 32 is connected to the output side of the differential input interface unit 32.

  The buffer 34 has a function of inputting a pair of signals CKP and CKN and supplying a clock signal to the data latch unit 33 and the shift register circuit 35. The shift register circuit 35 is configured to input and output SPOI and SPIO, which are signals for starting or completing a shift operation, and a display data latch unit 36 that captures display data is connected to the output side.

  The display data latch unit 36 is configured to receive an output instruction signal LS, and a digital / analog converter (for example, DAC (= D / A converter)) 37 is connected to the output side thereof. The DAC 37 is also connected to a gamma circuit 31 that outputs a plurality of analog voltages (for example, gradation potentials) VH63 to VH0 and gradation potentials VL63 to VH0 having gradation levels. An output buffer 38 for driving a display element (for example, a liquid crystal display element) (not shown) is connected to the output side of the DAC 37.

  A Y electrode line (not shown) for driving the liquid crystal display element is connected to the output side of the output buffer 38. Hereinafter, the configuration of the liquid crystal panel and the like will be described without using the drawings. In the liquid crystal panel, Y electrode lines are arranged orthogonally to a plurality of X electrode lines in a matrix, and liquid crystal cells are arranged at the intersections.

  This liquid crystal cell is formed of an active element such as a thin film transistor (hereinafter referred to as “TFT”) and a display element (for example, a liquid crystal display element), and the liquid crystal display element operates as a capacitor.

  The X electrode line is also called a scanning signal line, and is connected to an output terminal of a scanning signal circuit that outputs a scanning signal. The Y electrode line is also called a data signal line, and is connected to the output buffer 38 of the display drive circuit that outputs a display data signal for each liquid crystal display element.

(Configuration of Gamma Circuit 31 of Example 1)
FIG. 1 is a configuration diagram showing a gamma circuit 31 according to the first embodiment of the present invention.

  The gamma circuit 31 has a positive polarity circuit portion and a negative polarity circuit portion (not shown) having substantially the same configuration. As shown in FIG. 1, the positive polarity circuit unit of the gamma circuit 31 has input terminals VHI63, VHI63, VHI55,..., VHI0 having reference potentials having different potentials (for example, positive reference potentials) VHI63, VHI55,. VHI55,..., VHI0 are provided. The positive reference potential is the highest at the input terminal VHI63, and then decreases in the order of VHI55, VHI31, VHI7, and VHI0.

  Each input terminal VHI63 to VHI0 includes a plurality of first regulators (for example, N-top type regulators) 40 (= 40-4, 40-3,..., 40-1) and second regulators (for example, , P top type regulator) 50 (= 50-3, 50-2,... 50-0) are respectively connected. A voltage dividing circuit in which a plurality of resistance elements 60-63, 60-62,... 60-1 are connected in series between the N top regulator 40-4 and the P top regulator 50-0 ( For example, a resistance ladder) 60 is installed.

  A plurality of output terminals VH63, VH62,... VH0 are provided between the resistance elements 60-63 to 60-1 in order to output a potential obtained by sequentially dropping the output voltage of the N-top regulator 40-4. It is connected. A plurality of output terminals VH63 to VH0 are connected to a DAC 37 for converting display data, which is a digital signal indicating the gradation of the display element, into a plurality of analog voltages.

  The negative circuit portion of the gamma circuit 31 includes a plurality of input terminals instead of the plurality of input terminals VHI63, VHI62,..., VHI0 and the plurality of output terminals VH63, VH62,. VLI63, VLI62,... VLI0 and a plurality of output terminals VL63, VL62,. The negative reference potential is the highest at the input terminal VLI63, and thereafter decreases in the order of VLI55, VLI31, VLI7, and VLI0.

FIG. 3 is a configuration diagram showing the N-top regulator 40 in FIG.
The N top regulator 40 includes an inverting input terminal IN that inputs a reference voltage that is a first potential, and an operational amplifier (for example, an operational amplifier) 41 that has a non-inverting input terminal that feeds back and outputs the output voltage of the output terminal OUT; A first transistor (for example, PMOS) 43 that is connected to the first power supply node VDD and the output terminal OUT and inputs the output of the operational amplifier 41 to the gate, an output terminal OUT and a second power supply node (for example, ground node) GND And a constant current source 42 connected between them.

FIG. 4 is a block diagram showing the P-top regulator 50 in FIG.
The P-top regulator 50 includes an operational amplifier (for example, an operational amplifier) 51 having an inverting input terminal IN that inputs a reference voltage that is a second potential and a non-inverting input terminal that inputs and feeds back the voltage of the output terminal OUT; A second transistor (for example, NMOS) 53 connected between the output terminal OUT and the ground node GND and inputting the output of the operational amplifier 51 to the gate, and a constant current source 52 connected to the power supply node VDD and the output terminal OUT. And have.

(Schematic operation of the display drive circuit of Example 1)
In FIG. 2, in the display drive circuit, display data in which three colors of red, green, and blue are set as one set is input to the differential input interface unit 32. Display data is complementarily input as a pair of P and N such as X0P, X0N, Y0P, Y0N..., And X, Y, and Z represent differences in color. The differential input interface unit 32 converts the input signal into a signal based on the amplitude of the power supply and outputs the signal to the data latch unit 33. The data latch unit 33 temporarily captures a signal from the differential input interface unit 32 and outputs display data of 6 bits (64 gradations) × 3 colors according to a clock signal from the buffer 34.

  The shift register circuit 35 starts the operation by the SPOI signal, performs the shift operation by the clock from the buffer 34, and outputs the SPIO signal to another integrated circuit (not shown) when the series of shift operations is completed. The shift register circuit 35 and the display data latch unit 36 are connected by 160 × 3 colors = 480 signal lines.

  A control signal is output from the shift register circuit 35 to the display data latch unit 36 at the input timing of the clock signal CK. Based on this control signal, the display data latch unit 36 takes in the display data of 6 bits × 3 colors from the data latch unit 33 to a predetermined location of the display data latch unit 36.

  The display data latch unit 36 outputs 160 × 3 colors = 480 6-bit display data to the DAC 37 in response to the output instruction signal LS.

  A reference voltage having positive reference potentials VH0 to VH63 and negative reference potentials VL0 to VL63 is applied to the gamma circuit 31. The gamma circuit 31 divides these reference voltages and outputs a plurality of voltages having gradation levels as gradation potentials.

  The DAC 37 selects a corresponding gradation potential based on the value of 6-bit display data input from the display data latch unit 36, and outputs an output buffer as an analog display data signal at the timing of the positive / negative polarity inversion signal REV. 38.

  In the output buffer 38, the input display data signal is driven and applied to the liquid crystal display element of the line activated by the scanning signal.

  When displaying on the liquid crystal display element, the scanning signal circuit sequentially activates scanning signals corresponding to the X electrode lines to scan the X electrode lines. The TFT connected to each X electrode line is turned on during a period when the activated scanning signal is given. In synchronization with this scanning, a voltage having a gradation level for each display data is supplied from the display driving circuit as a display data signal, so that the liquid crystal display element for one line passes through the TFT in which the display data signal is on. Each liquid crystal element is displayed as a line by the potential difference from the common electrode. The display data signal has a potential corresponding to the gradation level, and the light transmittance of each liquid crystal element is variably controlled in accordance with the potential of the display data signal.

  The liquid crystal deteriorates when an electric field in a certain direction is applied for a long time due to electrochemical characteristics. Therefore, in the LCD, the liquid crystal display element needs to be AC driven with respect to the potential of the common electrode at a constant period. .

(Description of Detailed Operation of Display Driving Circuit of Example 1)
FIG. 5 is a waveform diagram showing the operation of the display drive circuit of FIG.

  The operation of the gamma circuit 31 and the display drive circuit will be described with reference to FIG. In FIG. 5, the output of the display data latch unit 36, data: 3b, data: 09 and data: 0f are hexadecimal numbers indicating the value of 6-bit display data. For example, hexadecimal number 2b is decimal number 59, and similarly, 09 is 9 and 0f is 15. The waveforms of VL59, VH9, and L15 output from the DAC 37 in FIG. 5 indicate the waveforms of the gradation potentials output from the DAC 37. The waveforms of VL59, VH9, and VL15 in the output buffer are output from the output buffer 38 to the liquid crystal display element. This is the waveform of the display data signal.

  Here, if display data “3b” corresponding to a certain liquid crystal element is input to the DAC 37, the DAC 37 selects the gradation potential VL 59 corresponding to the display data “3b”, and the same potential is output via the output buffer 38. Display data signal is output. Next, assuming that the display data for the liquid crystal element transits from “3b” to “09”, the DAC 37 selects the gradation potential VH9 corresponding to the display data “09” and outputs the same through the output buffer 38. A potential display data signal is output. The same applies to the display data “0f”.

  Next, the operation viewed from the gamma circuit 31 side will be described with reference to FIGS. For example, if the display data corresponding to a certain liquid crystal element transitions from “3b” to “09”, the DAC 37 selects the grayscale potential VH9 corresponding to the display data “09” and outputs the same via the output buffer 38. A potential display data signal is output.

  Since VL59 <VH9, a load of “L” is connected to the output terminal VH9, and the first terminal (for example, negative polarity) fluctuates in the output terminal VH9. As a result, the potential of the output terminal OUT of the N-top regulator 40-2 becomes “L” due to the voltage division of the resistance ladder 60, and the N-top regulator 40-2 charges the corresponding load to change the potential of the VH9 terminal to VH9. The operation of pulling up is performed.

  This will be described in more detail with reference to FIG. Assuming that the display data corresponding to a certain liquid crystal element transitions from “3b” to “09”, the potential VH9 is selected from the state where the potential VL59 has been selected so far, so the load of the output terminal VH9 is “L”. ", And the potential of the output terminal OUT of the N-top regulator 40-2 is also" L ". Since this “L” is fed back and input to the non-inverting input terminal of the operational amplifier 41, the operational amplifier 41 outputs “L”. As a result, the PMOS 43 is turned on, the current I1 is discharged, the load is charged, and the potential of the VH9 terminal is raised to VH9.

  Next, assuming that the display data for the liquid crystal element has transitioned from “09” to “0f”, the DAC 37 selects the gradation potential VL15 corresponding to the display data “0f” and outputs the same through the output buffer 38. A potential display signal is output. Since VL15 <VH9, a load of “H” is connected to the output terminal VL15, and the second polarity side (for example, positive polarity) fluctuation occurs.

  As a result, although not shown, the potential of the output terminal OUT of the P top regulator 50A-1 having the same configuration as that of the P top regulator 50 shown in FIG. 4 becomes “H”, the corresponding load is discharged, and the VL15 terminal is connected. An operation of lowering the potential to VL15 is performed. That is, since the load becomes “H”, the potential of the output terminal OUT of the P top regulator 50A also becomes “H”, the NMOS A12 (not shown) is turned on, and the current I2 is drawn.

(Effect of Example 1)
According to the first embodiment, in the gamma circuit 31, instead of the push-pull amplifier 10, an N-top regulator 40- that inputs adjacent reference potentials and outputs an output voltage having the same potential as the input reference potential is input. 4 to 40-1 and N top type regulators 40A-4 to 40A-1, P top type regulators 50-3 to 50-0, and P top type regulators 50A-3 to 50A-0 are provided.

  As a result, the N-top regulator 40 (A) and the P-top type that are adjacent to each other regardless of whether the load connected to the output terminals VH63 to VH0 and VL63 to VL0 of the gradation potential becomes “L” or “H”. The regulator 50 (A) can operate in a complementary manner and can operate in the same manner as the push-pull amplifier 10. Furthermore, since the through current generated in the push-pull amplifier 10 hardly occurs, the current consumption of the gamma circuit 31 can be greatly reduced.

(Configuration of Example 2)
In the first embodiment, input terminals VHI56, VHI32, VHI8, VLI56, VLI32, and VLI8 are newly added to a plurality of input terminals to which a plurality of reference voltages having different potentials are applied, and a reference potential is input to each of them. It has a configuration. On the other hand, in the second embodiment, a resistor ladder 70 is provided between the input terminals of the existing reference voltage without newly adding a reference voltage potential.

  FIG. 6 is a block diagram showing a gamma circuit 31B according to the second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

  The gamma circuit 31B includes a positive polarity circuit portion and a negative polarity circuit portion (not shown) having substantially the same configuration. 6, the positive polarity circuit unit of the gamma circuit 31B includes input terminals VHI63, VHI55,..., VHI0 having a plurality of positive reference potentials VHI63, VHI55,. ing. The positive reference potential is the highest at the input terminal VHI63, and then decreases in the order of VHI55, VHI31, VHI7, and VHI0.

  Between the input terminals VHI63 and VHI0, a resistance ladder 70 in which a plurality of resistance elements 70-n, 70-n-1,... 70-1 are connected in series is disposed. Input terminals VHI56, VHI32, and VHI18 having potentials of VHI56, VHI32, and VHI18 are provided by voltage division of the resistance ladder 70.

  As in the first embodiment, each of the input terminals VHI63, VHI56, VHI32, VHI18, VHI17, VHI0 includes a plurality of N top regulators 40-4, 40-3,. Regulators 50-3, 50-2,... 50-0 are connected to each other. Other configurations of the positive polarity circuit unit in the second embodiment are the same as those in the first embodiment.

  .., VHI0 and a plurality of output terminals VH63, VH62,..., VH0 in place of the plurality of input terminals VHI63, VHI62,. VLI63, VLI62,... VLI0 and a plurality of output terminals VL63, VL62,.

(Operation of Example 2)
In the operation of the second embodiment, an operation of dividing the reference voltage in the resistance ladders 70 and 70A is added. Other operations are the same as those in the first embodiment.

(Effect of Example 2)
According to the second embodiment, as in the first embodiment, the load connected to the grayscale potential output terminals VH63 to VH0 and VL63 to VL0 is adjacent regardless of whether the load is “L” or “H”. The N top type regulator 40 (A) and the P top type regulator 50 (A) operate in a complementary manner and can operate in the same manner as the push-pull amplifier 10. Furthermore, since almost no through current is generated in the push-pull amplifier 10, the current consumption of the gamma circuit 31B can be greatly reduced.

  In addition to the effects of the first embodiment, the resistor ladder 70 is provided and divided to generate a new reference voltage. Therefore, it is not necessary to change the existing circuit for generating the reference voltage. Implementation becomes easy.

(Modification)
The present invention is not limited to the above-described embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (e) are available as usage forms and modifications.

  (A) In the first and second embodiments, the example of display data of 6 bits representing 64 gradations has been described. However, display data of 5 bits, 6 bits, 8 bits, or the like may be used.

  (B) In the first and second embodiments, the display driving circuit having the configuration of FIG. 2 has been described. However, a display driving circuit having other configurations and operations may be used.

  (C) In the first and second embodiments, the LCD is described as an example of the display device, but other display devices such as an EL display and a plasma display may be used.

  (D) In the first and second embodiments, the N top regulator 40 is connected to the input terminal having the higher potential and the P top regulator 50 is connected to the input terminal having the lower potential among the pair of adjacent reference potentials. The P top regulator 50 may be connected to a high input terminal, and the N top regulator 40 may be connected to an input terminal having a low potential.

  (E) The present invention is not limited to use in display devices, and can be widely applied to various circuits using push-pull amplifiers.

31 Gamma Circuit 32 Differential Input Interface Unit 33 Data Latch Unit 34 Buffer 35 Shift Register Circuit 36 Display Data Latch Unit 37 D / A Converter Circuit 38 Output Buffer 40-1 to 40-4 N Top Type Regulator 50-0 to 50- 3 P top type regulator 41, 51 Operational amplifier 42, 52 Constant current source 43 PMOS
53 NMOS
60, 70 Resistance ladder

Claims (6)

Among the first and second potentials adjacent to each other in a plurality of reference voltages having different potentials, the first potential is input, and on the basis of the first potential, the first polarity side of the first output voltage A plurality of first regulators that suppress fluctuations and hold the first output voltage at a constant voltage;
Based on the second potential, the second potential is input, and the second output voltage is suppressed by suppressing the fluctuation of the second polarity opposite to the first polarity in the second output voltage. A plurality of second regulators that maintain a constant voltage;
A voltage dividing circuit that divides the plurality of first output voltages and the plurality of second output voltages to output a plurality of analog voltages having gradation levels;
A gamma circuit comprising:   The first regulator inputs the highest potential of the positive or negative reference voltages having a plurality of different potentials as the first potential, and based on the first potential, the first regulator 2. The gamma circuit according to claim 1, wherein the first output voltage is held at a constant voltage by suppressing a fluctuation on the first polarity side in the output voltage.   The second regulator inputs the lowest potential of the positive or negative reference voltages having a plurality of different potentials as the second potential, and based on the second potential, the second regulator 3. The gamma circuit according to claim 1, wherein the second output voltage is held at a constant voltage by suppressing a fluctuation on the second polarity side in the output voltage. The first regulator includes:
A first operational amplifier for inputting the first potential and the first output voltage output from a first output terminal, and canceling a difference between the first potential and the first output voltage;
A first transistor connected between a first power supply node and the first output terminal, the conduction state of which is controlled based on the output of the first operational amplifier;
The gamma circuit according to claim 1, wherein The second regulator includes:
A second operational amplifier for inputting the second potential and the second output voltage output from a second output terminal, and canceling a difference between the second potential and the second output voltage;
A second transistor connected between the second power supply node and the second output terminal, the conduction state of which is controlled based on the output of the second operational amplifier;
5. The gamma circuit according to claim 1, wherein the gamma circuit is provided. A gamma circuit according to any one of claims 1 to 5,
A digital / analog converter for inputting a plurality of analog voltages having the gradation level and display data which is a digital signal indicating a gradation of a display element, and converting the display data into the analog voltage;
An output circuit for driving the display element by the converted analog voltage;
A display driving circuit.

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