JP2010177694A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of forming a conductive film as a floating gate electrode in a self-matching manner using an element isolating-insulating film, and forming a conductive film as a semiconductor element. <P>SOLUTION: In this semiconductor device, conductive films 9 as floating gate electrodes are formed on a semiconductor substrate 1 among a plurality of element isolation parts 36 through an insulating film 8. A conductive film 9 as a semiconductor element, formed of the same material as that of the conductive film 9 as the floating gate electrode, is embedded in an element isolation part 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for forming a conductive film that can be used as a gate electrode of a transistor in a semiconductor device in a self-aligning manner using an element isolation insulating film.

  Conventionally, various technologies have been proposed for a nonvolatile semiconductor memory device including a memory cell having a floating gate electrode and a peripheral circuit including a sense amplifier circuit and a sub-decoder circuit. For example, Non-Patent Documents 1 to 3 propose a method of forming a floating gate electrode of a memory cell transistor in a self-aligned manner using an element isolation insulating film formed on a semiconductor substrate.

  Patent Document 1 proposes a technique for forming a diode element made of polysilicon on an element isolation insulating film in a region where a peripheral circuit is formed. Since the diode element formed on the element isolation insulating film in this manner is not easily affected by the potential of the well region formed on the semiconductor substrate, good characteristics can be obtained.

  Patent Documents 2 and 3 disclose other technologies related to nonvolatile semiconductor memory devices.

Japanese Patent Laid-Open No. 11-224939 Japanese Patent Laid-Open No. 7-130892 Japanese Unexamined Patent Publication No. 7-111319

Al Fazio, et. Al., “ETOXTM Flash Memory Technoligy: Scaling and Integration Challenges,” Intel Technology Journal, May 16, 2002, pp.23-30. Albert Fazio, “A High Density High Performance 180 nm Generation Etox ™ Flash Memory Technology,” IEEE IEDM Tech. Digest, 1999, pp.267-270. Stephen N. Keeney, “A 130nm Generation High Density EtoxTM Flash Memory Technology,” IEEE IEDM Tech. Digest, 2001, pp.41-44.

  When forming a nonvolatile semiconductor memory device including a memory cell and a peripheral circuit using the techniques described in Non-Patent Documents 1 to 3, a floating gate is formed on the element isolation insulating film in a region where the peripheral circuit is formed. No conductive film material for the electrode remains. Therefore, when forming a diode element or a resistance element made of a conductive film such as polysilicon on the element isolation insulating film in the region where the peripheral circuit is formed, the conductive film material of the floating gate electrode can be used. However, a separate process for forming a conductive film is required.

  Therefore, the present invention has been made in view of the above points. A conductive film as a floating gate electrode is formed in a self-aligned manner with respect to an element isolation insulating film, and at the same time, a conductive film as a semiconductor element is formed. It aims at providing the technology that can be.

  The semiconductor device according to the present invention includes a semiconductor substrate, first to third separation grooves provided apart from each other in the upper surface of the semiconductor substrate, and first and second filling grooves filled in the first and second separation grooves. First and second isolation insulating films having a first protruding portion protruding from an upper surface of the semiconductor substrate on the upper side, and the first and second isolation insulating films A second insulating film sandwiched between projecting portions and formed on the upper surface of the semiconductor substrate, and a second insulating film sandwiched between the first projecting portions of the first and second isolation insulating films. A first conductive film made of a conductive material formed on the first insulating film; and a first insulating film filled in the third isolation trench and having a second protruding portion protruding from an upper surface of the semiconductor substrate at an upper portion. A third isolation insulation having a recess on an upper surface so as to be surrounded by the second projecting portion; And a second conductive film made of the conductive material at least partially embedded in the recess, wherein the first conductive film is a floating gate electrode formed in a memory cell region, The conductive film 2 is a semiconductor element formed in the peripheral circuit region.

  According to the present invention, the second conductive film made of the same material as the first conductive film formed on the semiconductor substrate between the first and second isolation insulating films via the second insulating film is the third. Since the first conductive film as the floating gate electrode is formed in a self-aligned manner with respect to the first and second isolation insulating films, the third isolation insulation is formed at the same time. A second conductive film as a semiconductor element can be formed over the film. As a result, an element that is not easily affected by the potential in the active region of the semiconductor substrate can be formed without adding so many steps.

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Embodiment 1 FIG.
1 to 51 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. The semiconductor device according to the first embodiment is a nonvolatile semiconductor memory device such as a flash memory, and includes a region where a plurality of memory cells are formed (hereinafter referred to as “memory cell region”), a sense amplifier circuit, A region in which a peripheral circuit including a sub-decoder circuit is formed (hereinafter referred to as a “peripheral circuit region”). 1 to 50, odd-numbered figures and FIG. 36 show both the peripheral circuit area and the memory cell area, and are cross-sectional views along the gate width direction of the MOS transistor and the memory cell transistor included in the peripheral circuit. The other drawings show only the memory cell region, and are cross-sectional views along the gate length direction of the memory cell transistor. FIG. 51 shows a cross-sectional structure along the gate width direction of the peripheral circuit region and a cross-sectional structure along the gate length direction of the memory cell region.

  Unlike a memory cell transistor such as a flash memory, unlike a MOS transistor used in a logic circuit, a gate electrode is not provided with a floating gate electrode insulated from the surroundings, and a potential is applied from the outside. A MOS transistor having only a gate electrode is referred to herein as a “normal MOS transistor”.

  As shown in FIGS. 1 and 2, first, the upper surface of a semiconductor substrate 1 made of, for example, a silicon substrate is thermally oxidized to form a silicon oxide film 2 having a thickness of about 10 nm on the semiconductor substrate 1. Then, a silicon nitride film 3 having a thickness of about 100 nm is formed on the silicon oxide film 2. Next, a photoresist 100 having a predetermined opening pattern is formed on the silicon nitride film 3 using photolithography.

  Next, using the photoresist 100 as a mask, the silicon nitride film 3 and the silicon oxide film 2 are sequentially dry etched, and then the photoresist 100 is removed. Then, the semiconductor substrate 1 is dry-etched using the patterned silicon nitride film 3 as a mask. Thereby, as shown in FIGS. 3 and 4, trenches (separation grooves) 4 and 34 having a depth of about 200 to 300 nm are formed in the upper surface of the semiconductor substrate 1 in the peripheral circuit region and the memory cell region, respectively. . 3 and 4, each of the trenches 4 and 34 includes a plurality of partial regions that are separated from each other.

  Next, after the inner surface of the semiconductor substrate 1 exposed by the trenches 4 and 34 is thermally oxidized, as shown in FIGS. 5 and 6, a silicon oxide film 5 having a film thickness of, for example, about 500 nm is formed on the entire surface. Thereby, the trenches 4 and 34 are filled with the silicon oxide film 5. Then, the silicon oxide film 5 is planarized from the upper surface by using the CMP method, and the silicon oxide film 5 on the upper surface of the silicon nitride film 3 is removed. As a result, as shown in FIG. 7.8, an element isolation insulating film made of a silicon oxide film and having a plurality of element isolation portions 6 and a plurality of element isolation portions 36 is formed in the upper surface of the semiconductor substrate 1. .

  The plurality of element isolation portions 6 are formed apart from each other in the upper surface of the semiconductor substrate 1 in the peripheral circuit region, and the plurality of element isolation portions 36 are formed apart from each other in the upper surface of the semiconductor substrate 1 in the memory cell region. Yes. The plurality of element isolation portions 6 and the plurality of element isolation portions 36 are connected to each other by an element isolation portion (not shown). Each of the element isolation portions 36 has a protruding portion 36a protruding from the upper surface of the semiconductor substrate 1 on the upper portion, as shown in FIG. Since the element isolation portions 36 are provided apart from each other, a recess 37 is formed by the protruding portion 36a of the adjacent element isolation portions 36 and the upper surface of the semiconductor substrate 1 sandwiched between them. The silicon oxide film 2 and the silicon nitride film 3 fill the concave portion 37. Each element isolation portion 6 also has a protruding portion 6a protruding from the upper surface of the semiconductor substrate 1 at the top, as shown in FIG.

  Next, as shown in FIGS. 9 and 10, a photoresist 101 is formed in the peripheral circuit region and the memory cell region to partially expose the upper surface of some of the device isolation portions 6 among the plurality of device isolation portions 6. Then, the exposed element isolation portion 6 is etched with hydrofluoric acid or the like using the photoresist 101 as a mask. Then, the photoresist 101 is removed. As a result, as shown in FIGS. 11 and 12, a recess 7 is formed in the upper surface of a part of the element isolation portion 6 so as to be surrounded by the protruding portion 6a. Here, when a semiconductor element such as a polysilicon diode or a resistance element is formed using the recess 7 as described later, the distance between the recess 7 and the active region of the semiconductor substrate 1 is at least about 0.3 μm, It is desirable that the distance between the recess 7 and the bottom surface of the trench 34 be at least about 100 nm. Thereby, for example, in the trench 34 having a width of several tens of μm and a depth of 300 nm, an element of about 5 μm in length × 10 μm in width × 100 nm in thickness is formed.

  Next, as shown in FIGS. 13 and 14, the silicon nitride film 3 is removed using, for example, hot phosphoric acid. Then, as shown in FIGS. 15 and 16, the silicon oxide film 2 is removed using, for example, hydrofluoric acid. At this time, the element isolation portions 6 and 36 are also slightly etched. As a result, the upper surface of the semiconductor substrate 1 between the adjacent element isolation portions 6 and the upper surface of the semiconductor substrate 1 between the protruding portions 36a of the adjacent element isolation portions 36 are exposed.

  Next, as shown in FIGS. 17 and 18, the upper surface of the semiconductor substrate 1 is thermally oxidized to form an insulating film 8 made of a silicon oxide film having a thickness of about 10 nm on the semiconductor substrate 1 in the peripheral circuit region and the memory cell region. To form. Thereby, in the memory cell region, the insulating film 8 is formed on the upper surface of the semiconductor substrate 1 exposed by the recess 37. This insulating film 8 becomes a tunnel insulating film of a memory cell transistor formed in the memory cell region.

  Next, as shown in FIGS. 19 and 20, a conductive film 9 made of a conductive material such as a polysilicon film is formed on the entire surface with a thickness of about 150 nm. Thereby, the recesses 7 and 37 are filled with the conductive film 9. The conductive film 9 serves as a floating gate electrode of a memory transistor formed in the memory cell region.

  Next, the conductive film 9 is polished and planarized from the upper surface by CMP using the element isolation portions 6 and 36 as stopper layers, and the conductive film 9 above the recesses 7 and 37 is removed. As a result, as shown in FIG. 21, the conductive film 9 remains in the recess 7 in the peripheral circuit region. At the same time, in the memory cell region, as shown in FIG. 22, the conductive films 9 filling the plurality of recesses 37 are separated from each other, and the plurality of conductive films 9 serving as the floating gate electrodes of the plurality of memory cell transistors Positioned in a self-aligned manner with respect to the separation portion 36. As described above, since the plurality of conductive films 9 to be the floating gate electrodes are formed in a self-aligned manner with respect to the element isolation portion 36, a photolithography process is not required. The conductive film 9 may be removed by an etch back method using dry etching, but the flatness is inferior to the CMP method.

  Next, as shown in FIGS. 23 and 24, the element isolation portions 6 and 36 are partially removed using hydrofluoric acid or the like to expose the side surfaces of the conductive film 9. As a result, in the memory cell region, the facing area between the floating gate electrode and the control gate electrode that will be formed later can be increased, and the coupling ratio between them can be improved. As a result, the value of the write voltage applied to the control gate electrode can be reduced.

  Here, in the peripheral circuit region, as shown in FIG. 23, the protruding portion 6a of the element isolation portion 6 is partially removed so that the side surface of the conductive film 9 is not completely exposed. As a result, the conductive film 9 is surrounded by the protruding portion 6 a and partially embedded in the element isolation portion 6. Also in the memory cell region, the protruding portion 36a of the element isolation portion 36 is partially removed so that the side surface of the conductive film 9 is not completely exposed. The side surface of the conductive film 9 is partially exposed in this way because the conductive film 9 is peeled off from the element isolation portion 6 and the semiconductor substrate 1 when completely exposed.

  Next, as shown in FIGS. 25 and 26, an ONO film 10 having a thickness of about 20 nm is formed on the entire surface. The ONO film 10 is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. 27 and 28, a photoresist 102 is formed on the ONO film 10 to cover the memory cell region and the conductive film 9 and the ONO film 10 on the element isolation portion 6. Then, the ONO film 10 and the conductive film 9 are sequentially dry-etched using the photoresist 102 as a mask, the insulating film 8 is removed with hydrofluoric acid, and then the photoresist 102 is removed. Thus, as shown in FIGS. 29 and 30, the ONO film 10, the conductive film 9, and the insulating film 8 are not removed in the memory cell region, and the semiconductor substrate 1 between the element isolation portions 6 is formed in the peripheral circuit region. The insulating film 8, the conductive film 9, and the ONO film 10 are removed, and the portion of the element isolation portion 6 where the conductive film 9 is not formed and the side of the conductive film 9 are exposed on the ONO film 10 thereon. It is partially removed so that there is no.

  Next, as shown in FIGS. 31 and 32, the upper surface of the semiconductor substrate 1 in the peripheral circuit region is thermally oxidized to form an insulating film 11 having a thickness of about 15 nm on the semiconductor substrate 1. Then, a polysilicon film 12, a tungsten silicide film (WSi) 13, and a silicon nitride film 14 are sequentially formed on the entire surface. Then, a photoresist 104 having a predetermined opening pattern is formed on the silicon nitride film 14 using photolithography.

  Next, using the photoresist 104 as a mask, the silicon nitride film 14 is partially removed by dry etching, and the photoresist 104 is removed. Then, using the patterned silicon nitride film 14 as a mask, the tungsten silicide film 13 and the polysilicon film 12 are partially removed by dry etching sequentially. Thus, as shown in FIGS. 33 and 34, the gate electrode 26 of the normal MOS transistor composed of the polysilicon film 12 and the tungsten silicide film 13 is completed in the peripheral circuit region, and the polysilicon film 12 and the tungsten silicide in the memory cell region. The control gate electrode 56 of the memory cell transistor made of the film 13 is completed. A silicon nitride film 14 is formed on the gate electrode 26 and the control gate electrode 56.

  Next, as shown in FIG. 35, the peripheral circuit region is covered with a photoresist 105 using photolithography. Then, as shown in FIG. 36, the ONO film 10 and the conductive film 9 are sequentially dry etched using the photoresist 105 and the silicon nitride film 14 in the memory cell region as a mask. As a result, the insulating film 8 is exposed and the floating gate electrode of the memory cell transistor made of the conductive film 9 is completed. Next, impurities are ion-implanted into the upper surface of the semiconductor substrate 1 in the memory cell region to form the source / drain regions 45 of the memory cell transistor, and then the photoresist 105 is removed.

  Next, as shown in FIGS. 37 and 38, a silicon nitride film 15 is formed on the entire surface. Then, the silicon nitride film 15 is dry etched using an anisotropic etching method having a high etching rate in the thickness direction of the semiconductor substrate 1. As a result, as shown in FIGS. 39 and 40, in the peripheral circuit region, the sidewall 16 made of the silicon nitride film 15 is formed on the side surfaces of the gate electrode 26 and the silicon nitride film 14, and in the memory cell region, silicon nitride is formed. A sidewall 46 made of the silicon nitride film 15 is formed on the side surfaces of the film 14, the control gate electrode 56, the ONO film 10, and the conductive film 9 that functions as the floating gate electrode.

  Thus, a gate structure 28 of a normal MOS transistor including the insulating film 11 functioning as a gate insulating film, the gate electrode 26, the silicon nitride film 14, and the sidewall 16 is completed in the peripheral circuit region. In the memory cell region, an insulating film 8 functioning as a tunnel insulating film, a conductive film 9 functioning as a floating gate electrode, an ONO film 10, a control gate electrode 56, a silicon nitride film 14, and a sidewall 46 are provided. The memory cell transistor gate structure 58 is completed.

  Next, a photoresist (not shown) covering the memory cell region is formed, and impurities are ion-implanted into the semiconductor substrate 1 in the peripheral circuit region, thereby forming the source / drain regions 25 of the normal MOS transistor. At this time, impurities are also ion-implanted into the conductive film 9 partially embedded in the element isolation portion 6, and the conductive film 9 is used as a resistance element having a predetermined electric resistance. Thereafter, the used photoresist is removed.

  When the conductive film 9 partially embedded in the element isolation portion 6 is used as a diode element, the photolithography process is performed twice, and p-type impurities and n-type impurities are added to the conductive film 9. Introduced to form a pn junction.

  Next, as shown in FIGS. 41 and 42, an interlayer insulating film 17 is formed on the entire surface so as to cover the gate structures 28 and 58. Then, a photoresist 106 having a predetermined opening pattern is formed on the interlayer insulating film 17 using photolithography. 42 and FIGS. 44, 46, 48, and 50, which will be described later, are sectional views taken along the line AA in FIG. 41, and the above-described FIGS. 2, 4 and the like are taken along the line BB in FIG. It is sectional drawing in the position corresponding.

  FIG. 42 shows the silicon nitride film 15 formed in the element isolation portion 36. When the above-described ONO film 10 is etched, the upper end portion of the element isolation portion 36 is also partially etched, and a silicon nitride film 15 serving as a sidewall is formed in a recess portion formed thereby. FIG. 42 shows this silicon nitride film 15.

  Next, the interlayer insulating film 17 and the insulating film 8 are dry-etched using the photoresist 106 as a mask, and the photoresist 106 is removed. As a result, as shown in FIGS. 43 and 44, in the interlayer insulating film 17 and the insulating film 8 in the memory cell region, a pair of source / drain regions 45 penetrating in the thickness direction and adjacent to each other are provided. A contact hole 48a reaching one side is formed.

  Next, a photoresist (not shown) having a predetermined opening pattern is formed on the interlayer insulating film 17, and the interlayer insulating film 17 and the insulating films 8 and 11 are dry-etched using the photoresist as a mask. Then, the used photoresist is removed. Thus, as shown in FIGS. 45 and 46, in the interlayer insulating film 17 and the insulating film 8 in the memory cell region, a pair of source / drain regions 45 penetrating in the thickness direction and adjacent to each other are provided. A contact hole 48a reaching the other is formed, and a contact hole 18a penetrating in the thickness direction and reaching each source / drain region 25 is formed in the interlayer insulating film 17 and the insulating film 11 in the peripheral circuit region. The

  The contact hole 48a according to the first embodiment is formed in the interlayer insulating film 17 between the gate structures 58 in a self-aligned manner with respect to the sidewall 46 made of a silicon nitride film. Therefore, even if the photoresist formation position is slightly shifted, the contact hole 18a reaching the source / drain region 45 can be reliably formed. Further, since the silicon nitride film 14 is formed on the control gate electrode 56, the control gate electrode 56 is not exposed even if the formation position of the contact hole 48a is slightly deviated from the design value.

  Next, a tungsten film filling the contact holes 18a and 48a is formed on the entire surface. Then, the tungsten film above the contact holes 18a and 48a is removed by CMP or the like. As a result, as shown in FIGS. 47 and 48, a contact plug 18 made of tungsten filling each contact hole 18a and a contact plug 48 made of tungsten filling each contact hole 48a are formed.

  Next, an interlayer insulating film 19 is formed on the upper surface of the interlayer insulating film 17 and the upper surfaces of the contact plugs 18 and 48. Then, a contact plug 20 reaching the contact plug 18 and a contact plug 50 reaching the contact plug 48 are formed in the interlayer insulating film 19. Thereafter, an aluminum wiring 21 connected to the contact plug 20 and an aluminum wiring 51 connected to the contact plug 50 are formed on the interlayer insulating film 19. As a result, a semiconductor device including a memory cell and its peripheral circuit as shown in FIGS. 49 to 51 is completed. 51 shows a cross-sectional structure of the peripheral circuit region shown in FIG. 49 and a cross-sectional structure at a position corresponding to the arrow BB in FIG. 41 in the memory cell region of FIG.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, the conductive film 9 above the recesses 7 and 37 is removed, and the conductive film 9 filling the plurality of recesses 37 is separated. The conductive film 9 is left in the recess 7. Since the conductive film 9 filling the plurality of recesses 37 is formed on the semiconductor substrate 1 via the insulating film 8, the conductive film 9 can be used as a floating gate electrode of the memory cell transistor. Therefore, according to the manufacturing method according to the first embodiment, a plurality of conductive films 9 that can be used as floating gate electrodes are formed in a self-aligned manner with respect to the element isolation portion 36, and at the same time on the element isolation portion 6. The conductive film 9 is formed. As a result, by forming a semiconductor element such as a diode element or a resistance element using the conductive film 9 on the element isolation portion 6, the influence of the potential in the active region of the semiconductor substrate 1 is not added so much. An element that is not easily affected can be formed. In addition, the element isolation region can be effectively used.

  Further, in the semiconductor device manufactured by the manufacturing method according to the first embodiment, as shown in FIGS. 40 and 49, a plurality of element isolation portions 6 provided apart from each other in the upper surface of the semiconductor substrate 1. As a result, element isolation portions 36 provided apart from each other are formed. In the plurality of element isolation portions 36, an insulating film 8 is formed on the semiconductor substrate 1 between adjacent element isolation portions 36, and a conductive film 9 is formed on the insulating film 8. .

  As described above, when the conductive film 9 filling the plurality of recesses 37 is polished from the upper surface by the CMP method when separating the conductive film 9 in the memory cell region in a self-aligned manner (see FIG. 22), The upper surface of the conductive film 9 after the separation is flat, and the upper surface of the conductive film 9 on the element isolation portion 6 in the peripheral circuit region and the upper surface of the conductive film 9 that can be used as the floating gate electrode in the memory cell region are on the same plane. Will come to be located. Accordingly, the flatness is improved as compared with the case where the etch back method is used, the focus margin in the photoengraving in the subsequent steps is improved, and a problem due to an unnecessary residue remaining in the step portion can be prevented. Note that although the film thickness of the conductive film 9 may vary by about 20% due to variations in the polishing amount due to the normal CMP process, the conductive film 9 and the element are preferably set to 10% or less, more preferably 5% or less. It is desirable to adjust the polishing conditions so that the selection ratio with the separation portions 6 and 36 is high.

  Further, as described above, since the side surface of the conductive film 9 can only be partially exposed in order to prevent the conductive film 9 from peeling off from the element isolation portion 6, the present embodiment shown in FIG. In the semiconductor device according to the first embodiment, the conductive film 9 in the peripheral circuit region is surrounded by the protruding portion 6 a at the lower end portion thereof and is partially embedded in the element isolation portion 6.

  As can be understood from the above description, in the semiconductor device according to the first embodiment, the conductive film of the same material as the conductive film 9 formed on the semiconductor substrate 1 between the element isolation portions 36 via the insulating film 8. 9 is partially embedded in the element isolation portion 6, so that the conductive film 9 that can be used as a floating gate electrode is formed on the element isolation portion 6 at the same time as the self-alignment with the element isolation portion 36. A conductive film 9 can be formed. As a result, by using the conductive film 9 on the element isolation portion 6 as a diode element or a resistance element, an element that is not easily affected by the potential in the active region of the semiconductor substrate 1 is formed without adding a large number of steps. be able to.

Embodiment 2. FIG.
52 to 63 are cross-sectional views showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. In the semiconductor device according to the first embodiment described above, as shown in FIG. 40, the floating gate electrode is separated between the plurality of memory cell transistors arranged along the gate length direction. In the semiconductor device according to the second embodiment, the floating gate electrodes are connected to each other in part of them. That is, the semiconductor device according to the second embodiment includes a plurality of memory cell transistors whose floating gate electrodes are separated from each other and a plurality of memory cell transistors whose floating gate electrodes are connected to each other.

  A plurality of memory cell transistors in which such floating gate electrodes are connected to each other can be used for managing the impurity concentration in the channel region. In a normal memory cell transistor, the floating gate electrode is isolated and insulated from the surroundings, so that a voltage cannot be directly applied to the floating gate electrode. Therefore, when a malfunction occurs in the memory cell transistor, it is determined whether the cause is the insulating film between the control gate electrode and the floating gate electrode, the floating gate electrode, or the impurity concentration of the channel region. Can not. Further, even if the floating gate electrode is pulled out to the outer periphery of the semiconductor chip so that a voltage can be directly applied, it is difficult to pull out the plurality of floating gate electrodes individually in terms of wiring layout, which is not practical.

  As in the semiconductor device according to the second embodiment, in the plurality of memory cell transistors, when the floating gate electrodes are connected to each other, only the floating gate electrodes of the memory cell transistors existing near the outer periphery of the semiconductor chip are extracted. Thus, a voltage can be applied directly to the floating gate electrodes of all the memory cell transistors simultaneously. Therefore, the impurity concentration in the channel region can be directly evaluated for a plurality of memory cell transistors, and device analysis is facilitated.

  A method for manufacturing the semiconductor device according to the second embodiment will be described below. 52 to 63, cross-sectional views along the gate width direction are shown in FIGS. 52 to 63, and the other views are cross-sectional views along the gate length direction. A cross-sectional view at a position corresponding to B is shown. A region where a plurality of memory cell transistors to which the floating gate electrode is connected is formed is called a “floating gate connection region”, and a region where a plurality of memory cell transistors from which the floating gate electrode is separated is formed is “ This is called “floating gate isolation region”.

  First, the structure shown in FIGS. 7 and 8 is manufactured using the manufacturing method according to the first embodiment. Then, as shown in FIGS. 52 and 53, a photo that partially exposes the upper surface of some of the element isolation portions 6 in the peripheral circuit region 6 and exposes the floating gate connection region. A resist 201 is formed in the peripheral circuit region and the memory cell region.

  Next, using the photoresist 201 as a mask, the exposed element isolation portion 6 and the element isolation portion 36 in the floating gate connection region are etched with hydrofluoric acid or the like. Then, the photoresist 201 is removed. As a result, as shown in FIG. 54, a recess 7 is formed in the upper surface of the element isolation portion 6. At the same time, as shown in FIG. 55, in the floating gate connection region, the protruding portions 36a of the plurality of element isolation portions 36 are mostly removed so that the side surfaces of the silicon nitride film 3 are not completely exposed. .

  Next, as shown in FIG. 56, the silicon nitride film 3 is removed using, for example, hot phosphoric acid, and then the silicon oxide film 2 is removed using, for example, hydrofluoric acid, as shown in FIG.

  Next, as shown in FIG. 58, the upper surface of the semiconductor substrate 1 is thermally oxidized to form an insulating film 8 made of a silicon oxide film having a thickness of about 10 nm on the semiconductor substrate 1 in the peripheral circuit region and the memory cell region. To do. Thereby, in the floating gate connection region, the insulating film 8 is formed on the semiconductor substrate 1 between the element isolation portions 36 adjacent to each other. At the same time, in the floating gate isolation region, the semiconductor substrate 1 exposed by the recess 37 is exposed. An insulating film 8 is formed on the upper surface.

  Next, as shown in FIG. 59, a conductive film 9 to be a floating gate electrode of the memory cell transistor is formed on the entire surface with a thickness of about 150 nm. As a result, the recess 7 is filled with the conductive film 9 and the recess 37 in the floating gate isolation region is also filled with the conductive film 9.

  Next, the CMP method using the element isolation portion 36 as a stopper layer is used to polish and planarize the conductive film 9 from above, and the conductive film 9 above the recesses 7 and 37 is removed. Thereby, as shown in FIG. 60, in the floating gate isolation region, the conductive films 9 filling the plurality of recesses 37 are separated from each other, and the plurality of conductive films 9 serving as the floating gate electrodes of the plurality of memory cell transistors It is formed in a self-aligned manner with respect to the separation portion 36. At this time, since the upper surface of the element isolation portion 36 in the floating gate connection region exists at a position lower than the upper surface of the element isolation portion 36 in the floating gate isolation region, the upper surface of the element isolation portion 36 in the floating gate connection region The conductive film 9 is not removed, and the conductive film 9 exists continuously on each element isolation portion 36 and on the insulating film 8. The conductive film 9 may be removed by an etch back method using dry etching, but the flatness is inferior to that of the CMP method.

  Next, as shown in FIG. 61, the protruding portion 6a of the element isolation portion 6 and the protruding portion 36a of the element isolation portion 36 in the floating gate isolation region are partially removed using hydrofluoric acid, etc. The side surfaces of the conductive film 9 in the circuit region and the floating gate isolation region are exposed. Then, as shown in FIG. 62, an ONO film 10 having a thickness of about 20 nm is formed on the entire surface.

  Thereafter, using the manufacturing method described with reference to FIGS. 27 to 51, aluminum wirings 21 and 51 are manufactured in the same manner as in the first embodiment. Thereby, the semiconductor device according to the second embodiment having the structure as shown in FIG. 63 as the structure below the upper surface of the gate structure 58 in the cross-sectional structure along the gate length direction in the memory cell region is completed. . Note that the cross-sectional structure along the gate width direction of the semiconductor device according to the second embodiment is the same as the structure shown in FIG.

  As described above, in the method of manufacturing a semiconductor device according to the second embodiment, the protruding portion 36a of the element isolation portion 36 in the floating gate connection region is removed, so that the upper surface of the element isolation portion 36 is the floating gate. It becomes lower than the upper surface of the element isolation portion 36 in the isolation region. Therefore, when the conductive film 9 above the recesses 7 and 37 is removed and a plurality of conductive films 9 are formed in a self-aligned manner with respect to the element isolation portion 36, the element isolation portion 36 in the floating gate connection region is formed. The conductive film 9 existing on the insulating film 8 between them is not removed. As a result, after the step of removing the conductive film 9 above the recesses 7 and 37 is executed, the conductive film 9 on the insulating film 8 adjacent via the element isolation portion 36 becomes conductive on the element isolation portion 36. The films 9 are connected to each other. Therefore, as in the second embodiment, by using these conductive films 9 as floating gate electrodes, a memory cell in which the floating gate electrodes are connected to each other among a plurality of memory cell transistors can be obtained.

  Furthermore, since the protruding portion 36a of the element isolation portion 36 in the floating gate connection region is removed together with the recess 7 in which the conductive film 9 that can be used as a diode element or a resistance element is formed, there is no need to add a special process. A memory cell in which floating gate electrodes are connected to each other between a plurality of memory cell transistors can be obtained.

  In the semiconductor device manufactured by the manufacturing method according to the second embodiment, as shown in FIG. 63, a plurality of elements provided apart from each other in the upper surface of the semiconductor substrate 1 in the floating gate connection region. A separation portion 36 is formed. An insulating film 8 is formed on the semiconductor substrate 1 between the element isolation portions 36 adjacent to each other in the floating gate connection region, and is separated on the insulating film 8 and each element isolation portion 36. No continuous conductive film 9 is formed.

  As described above, when separating the conductive film 9 in the floating gate isolation region in a self-aligned manner, when the conductive film 9 is polished from the upper surface by the CMP method (see FIG. 60), the conductivity in the floating gate isolation region is determined. Not only the film 9 but also the upper surface of the conductive film 9 in the floating gate connection region is flat, and both upper surfaces are located on the same plane. Accordingly, the flatness is improved as compared with the case where the etch back method is used, the focus margin in the photoengraving in the subsequent steps is improved, and a problem due to an unnecessary residue remaining in the step portion can be prevented. As in the first embodiment, the film thickness of the conductive film 9 may vary by about 20% due to variations in the polishing amount by a normal CMP process, but preferably settles to 10% or less, more preferably 5% or less. Thus, it is desirable to adjust the polishing conditions so that the selection ratio between the conductive film 9 and the element isolation portions 6 and 36 is high.

  As can be understood from the above description, in the semiconductor device according to the second embodiment, the conductive film 9 in the floating gate isolation region and the conductive film 9 in the floating gate connection region are made of the same material. When the plurality of conductive films 9 are formed in a self-aligning manner using the element isolation portion 36 in the region, the conductive film 9 in the floating gate connection region can be formed at the same time. Therefore, as in the second embodiment, by using the conductive film 9 in the floating gate connection region as the floating gate electrode, the floating gate electrodes are connected to each other between the plurality of memory cell transistors without adding a special process. A connected memory cell can be obtained.

  In the first and second embodiments, the case where the present invention is applied to a flash memory has been described. However, the present invention can also be applied to other memories and the like.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 4,34 trench, 5 silicon oxide film, 6,36 element isolation part, 7,37 recessed part, 8 insulating film, 9 electrically conductive film, 6a, 36a Projection part.

Claims (6)

A semiconductor substrate;
First to third separation grooves provided apart from each other in the upper surface of the semiconductor substrate;
First and second isolation insulating films filled in the first and second isolation trenches, the first and second isolation insulating films having a first projecting portion projecting from an upper surface of the semiconductor substrate at an upper portion;
A second insulating film sandwiched between the first projecting portions of the first and second isolation insulating films and formed on the upper surface of the semiconductor substrate;
A first conductive film made of a conductive material sandwiched between the first protruding portions of the first and second isolation insulating films and formed on the second insulating film;
A first insulating film filled in the third isolation trench and having a second projecting portion projecting from an upper surface of the semiconductor substrate on the upper surface, the upper surface being surrounded by the second projecting portion; A third isolation insulating film having a recess;
A second conductive film made of the conductive material at least partially embedded in the recess,
The first conductive film is a floating gate electrode formed in a memory cell region,
The semiconductor device, wherein the second conductive film is a semiconductor element formed in a peripheral circuit region. The semiconductor device according to claim 1,
A semiconductor device, wherein an upper surface of the first conductive film and an upper surface of the second conductive film are located on the same plane. The semiconductor device according to claim 1,
Fourth to sixth isolation insulating films provided apart from each other in the upper surface of the semiconductor substrate;
Third layers provided on the upper surface of the semiconductor substrate between the fourth and fifth isolation insulating films and on the upper surface of the semiconductor substrate between the fifth and sixth isolation insulating films, respectively. And a fourth insulating film;
A third conductive film made of the conductive material and continuously provided on the fourth to sixth isolation insulating films and the third and fourth insulating films;
The semiconductor device, wherein the third conductive film is a floating gate electrode formed in a memory cell region. The semiconductor device according to claim 3,
A semiconductor device, wherein upper surfaces of the first to third conductive films are located on the same plane. A semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the semiconductor element is a diode or a resistance element. A semiconductor device according to any one of claims 1 to 5,
The recess has a distance of 0.3 μm or more from the boundary between the third isolation insulating film and the upper surface of the semiconductor substrate,
The recess is a semiconductor device, wherein the distance from the bottom surface of the third separation groove is 100 nm or more.

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