JP2010177226A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010177226A
JP2010177226A JP2009014924A JP2009014924A JP2010177226A JP 2010177226 A JP2010177226 A JP 2010177226A JP 2009014924 A JP2009014924 A JP 2009014924A JP 2009014924 A JP2009014924 A JP 2009014924A JP 2010177226 A JP2010177226 A JP 2010177226A
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semiconductor device
electrode pad
connection region
resistance
region
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Takeshi Fukami
武志 深見
Tatsushi Kuno
達志 久納
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Toyota Motor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To make a semiconductor device, whose resistance value is adjustable, compact. <P>SOLUTION: A substrate connection region, an external wiring connection region, and a resistance adjusting region disposed between the substrate connection region and external wiring connection region are formed in one electrode pad to make the semiconductor device compact. The resistance adjusting region of the electrode pad is trimmed away to be able to adjust a resistance value between the substrate connection region and external wiring connection region of the electrode pad. Consequently, the semiconductor device whose resistance value is adjustable can be made compact. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体基板と外部配線とを導通させ、半導体基板に給電するための電極パッドを備えた半導体装置に関する。   The present invention relates to a semiconductor device including an electrode pad for conducting a semiconductor substrate and external wiring and supplying power to the semiconductor substrate.

半導体装置の特性を必要に応じて微調整したり、半導体素子の主セルに流れる電流を検知するセンスセルに流れる検知電流値を調整したりするために、半導体装置の電極の抵抗値等を調整する技術が開発されている。特許文献1には、半導体基板上に設置された電極層の抵抗値等を調整可能な半導体装置90が開示されている。半導体装置90は、図21に示すように、半導体基板91と、半導体基板の給電部分92と、シリコン酸化膜93と、シリコン酸化膜93の表面に形成されたワイヤボンディング用電極パッド94および抵抗調整電極層95と、半導体装置91の最表面を被覆する絶縁膜96とを備えている。絶縁膜96には、孔部961が設けられており、ワイヤボンディング用電極パッド94の一部が露出している。孔部961に露出したワイヤボンディング用電極パッド94に対してワイヤボンディングを行う。ワイヤボンディング用電極パッド94は、給電部分92と電気的に接続している。抵抗調整電極層95には、トリミング部951が設けられている。半導体装置90は、シリコン酸化膜93の表面にワイヤボンディング用電極パッド94および抵抗調整電極層95を形成した後、レーザトリミングを行って、抵抗調整電極層95にトリミング部951を形成する。トリミング部951を形成する際は、抵抗調整電極層95に、測定装置に接続された測定針を当て、抵抗値を測定しながらレーザトリミングを行い、半導体装置の抵抗値等を調整する。その後、図21のように抵抗調整電極層95の表面上を絶縁膜96によって被覆する。抵抗調整電極層95は、絶縁膜96によって保護する必要がある電極層の一部であり、ワイヤボンディング用電極パッド94とは別に設けられている。   In order to finely adjust the characteristics of the semiconductor device as necessary, or to adjust the detection current value flowing in the sense cell that detects the current flowing in the main cell of the semiconductor element, the resistance value of the electrode of the semiconductor device is adjusted. Technology has been developed. Patent Document 1 discloses a semiconductor device 90 capable of adjusting a resistance value and the like of an electrode layer installed on a semiconductor substrate. As shown in FIG. 21, the semiconductor device 90 includes a semiconductor substrate 91, a power feeding portion 92 of the semiconductor substrate, a silicon oxide film 93, a wire bonding electrode pad 94 formed on the surface of the silicon oxide film 93, and resistance adjustment. An electrode layer 95 and an insulating film 96 covering the outermost surface of the semiconductor device 91 are provided. A hole 961 is provided in the insulating film 96, and a part of the wire bonding electrode pad 94 is exposed. Wire bonding is performed on the electrode pad 94 for wire bonding exposed in the hole 961. The wire bonding electrode pad 94 is electrically connected to the power feeding portion 92. A trimming portion 951 is provided in the resistance adjustment electrode layer 95. In the semiconductor device 90, the wire bonding electrode pad 94 and the resistance adjustment electrode layer 95 are formed on the surface of the silicon oxide film 93, and then laser trimming is performed to form a trimming portion 951 in the resistance adjustment electrode layer 95. When forming the trimming portion 951, the resistance adjustment electrode layer 95 is applied with a measuring needle connected to the measuring device, and laser trimming is performed while measuring the resistance value, thereby adjusting the resistance value of the semiconductor device. Thereafter, the surface of the resistance adjustment electrode layer 95 is covered with an insulating film 96 as shown in FIG. The resistance adjustment electrode layer 95 is a part of an electrode layer that needs to be protected by the insulating film 96, and is provided separately from the wire bonding electrode pad 94.

特開昭63−293970号公報JP-A-63-293970

特許文献1では、半導体装置の給電部分と外部配線とを接続するための電極パッドと、トリミングによって抵抗を調整可能な電極層とをそれぞれ別々に設けている。抵抗を調整するために、抵抗調整用の電極層を追加する必要があるため、抵抗調整機能のない半導体装置と比較して、半導体装置のサイズが大きくなってしまっていた。   In Patent Document 1, an electrode pad for connecting a power feeding portion of a semiconductor device and an external wiring and an electrode layer whose resistance can be adjusted by trimming are separately provided. In order to adjust the resistance, it is necessary to add an electrode layer for resistance adjustment, so that the size of the semiconductor device has become larger than a semiconductor device without a resistance adjustment function.

そこで、本発明では、半導体基板と、半導体基板の表面に設けられた絶縁膜と、半導体基板および絶縁膜の表面に設けられた電極パッドとを備えた半導体装置であって、電極パッドは、絶縁膜を貫通して半導体基板と電気的に接続する基板接続領域と、外部配線がその表面に電気的に接続される外部配線接続領域と、基板接続領域と外部配線接続領域との間に設けられた抵抗調整領域とを備えている半導体装置を提供する。   Therefore, in the present invention, a semiconductor device comprising a semiconductor substrate, an insulating film provided on the surface of the semiconductor substrate, and an electrode pad provided on the surface of the semiconductor substrate and the insulating film, the electrode pad being insulated A substrate connection region that is electrically connected to the semiconductor substrate through the film, an external wiring connection region in which external wiring is electrically connected to the surface, and a substrate connection region and the external wiring connection region are provided. And a resistance adjustment region.

本発明では、基板接続領域と、抵抗調整領域と、外部配線接続領域とが、1つの電極パッドに形成されているため、従来のように、半導体基板と外部配線とを接続するための電極パッドと、トリミングによって抵抗を調整可能な電極層とをそれぞれ設ける必要がなく、半導体装置のコンパクト化に寄与できる。   In the present invention, since the substrate connection region, the resistance adjustment region, and the external wiring connection region are formed in one electrode pad, the electrode pad for connecting the semiconductor substrate and the external wiring as in the prior art. In addition, there is no need to provide an electrode layer whose resistance can be adjusted by trimming, which can contribute to a compact semiconductor device.

本発明の抵抗調整領域は、例えば、基板接続領域から外部配線接続領域に延びる複数の導電部を備えている。このような構成によれば、複数の導電部の少なくとも1つを切断することによって、抵抗調整領域の抵抗値を高くすることができる。   The resistance adjustment region of the present invention includes, for example, a plurality of conductive portions extending from the substrate connection region to the external wiring connection region. According to such a configuration, it is possible to increase the resistance value of the resistance adjustment region by cutting at least one of the plurality of conductive portions.

さらに、複数の導電部の少なくとも一つが、他の導電部とは抵抗が異なることが好ましい。調整したい抵抗値の大きさに応じて、抵抗の異なる導電部の中から適宜トリミングすべき導電部を選択することができるため、より適切に電極パッドの抵抗値を調整するができる。   Furthermore, it is preferable that at least one of the plurality of conductive portions has a resistance different from that of the other conductive portions. According to the magnitude of the resistance value to be adjusted, the conductive part to be trimmed can be appropriately selected from the conductive parts having different resistances, so that the resistance value of the electrode pad can be adjusted more appropriately.

また、抵抗調整領域は、基板接続領域と外部配線接続領域とを接続する主導電部と、主導電部を短絡させる複数の副導電部とを備えており、複数の副導電部は主導電部を異なる位置で短絡させる。そして、複数の副導電部のいずれかを適宜トリミングによって切断することによって、基板接続領域と外部配線接続領域との間の抵抗値を調整することができるようにしてもよい。このような抵抗調整領域としては、例えば、基板接続領域から外部配線接続領域に向けてサーペンタイン状に蛇行した主導電部と、蛇行する主導電部を短絡させる副導電部とを用いることができる。   The resistance adjustment region includes a main conductive portion that connects the substrate connection region and the external wiring connection region, and a plurality of sub conductive portions that short-circuit the main conductive portion, and the plurality of sub conductive portions are the main conductive portions. Are short-circuited at different positions. Then, the resistance value between the substrate connection region and the external wiring connection region may be adjusted by appropriately cutting any of the plurality of sub conductive portions by trimming. As such a resistance adjustment region, for example, a main conductive portion meandering in a serpentine shape from the substrate connection region to the external wiring connection region and a sub conductive portion that short-circuits the meandering main conductive portion can be used.

また、本発明の抵抗調整領域は、半導体装置の表面に露出していることが好ましい。半導体装置の表面に露出した抵抗調整領域に対してトリミングを行うことによって、電極パッドの基板接続領域と外部配線接続領域との間の抵抗値を調整することができるため、例えば、半導体装置の電気特性の検査工程など、完成した半導体装置の検査工程においてトリミングを行うことが可能となる。   Further, the resistance adjustment region of the present invention is preferably exposed on the surface of the semiconductor device. By trimming the resistance adjustment region exposed on the surface of the semiconductor device, the resistance value between the substrate connection region of the electrode pad and the external wiring connection region can be adjusted. Trimming can be performed in an inspection process for a completed semiconductor device, such as a characteristic inspection process.

本発明によれば、半導体基板と外部配線とを接続するための電極パッドに抵抗調整領域を設けているため、半導体装置の大型化を抑制することができる。   According to the present invention, since the resistance adjustment region is provided in the electrode pad for connecting the semiconductor substrate and the external wiring, an increase in the size of the semiconductor device can be suppressed.

本実施例の半導体装置(電極パッド)の平面図。The top view of the semiconductor device (electrode pad) of a present Example. 本実施例の半導体装置の断面図であり、図1のII−II線断面図。FIG. 2 is a cross-sectional view of the semiconductor device of the present embodiment, taken along the line II-II in FIG. 1. 図1の電極パッドの抵抗調整領域に設けられた導電部を切断した図。The figure which cut | disconnected the electroconductive part provided in the resistance adjustment area | region of the electrode pad of FIG. 本実施例の変形例に係る半導体装置の電極パッドの平面図。The top view of the electrode pad of the semiconductor device which concerns on the modification of a present Example. 本実施例の他の変形例に係る半導体装置の電極パッドの平面図。The top view of the electrode pad of the semiconductor device which concerns on the other modification of a present Example. 図5のVI−VI線断面から矢印方向に見た図。The figure seen in the arrow direction from the VI-VI line cross section of FIG. 本実施例の他の変形例に係る半導体装置の電極パッドの平面図。The top view of the electrode pad of the semiconductor device which concerns on the other modification of a present Example. 本実施例の他の変形例に係る半導体装置の電極パッドの平面図。The top view of the electrode pad of the semiconductor device which concerns on the other modification of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図であり、図12のXI−XI線断面図。FIG. 13 is a diagram showing a manufacturing process of the electrode pad of the semiconductor device of the example, and is a cross-sectional view taken along line XI-XI in FIG. 12. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図であり、図14のXIII−XIII線断面図。It is a figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example, and is the XIII-XIII sectional view taken on the line of FIG. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図であり、図18のXVII−XVII線断面図。FIG. 19 is a diagram showing a manufacturing process of the electrode pad of the semiconductor device of the example, and is a cross-sectional view taken along line XVII-XVII in FIG. 18. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の半導体装置の電極パッドの製造工程を示す図。The figure which shows the manufacturing process of the electrode pad of the semiconductor device of a present Example. 本実施例の他の変形例に係る半導体装置の電極パッドの平面図。The top view of the electrode pad of the semiconductor device which concerns on the other modification of a present Example. 従来例の半導体装置の断面図。Sectional drawing of the semiconductor device of a prior art example.

以下に説明する実施例の主要な特徴を以下に列記する。
(特徴1)半導体基板の表面に形成された絶縁膜は、絶縁膜の表面に形成された電極パッドの抵抗調整領域から基板接続領域まで延びている。
The main features of the embodiments described below are listed below.
(Feature 1) The insulating film formed on the surface of the semiconductor substrate extends from the resistance adjustment region of the electrode pad formed on the surface of the insulating film to the substrate connection region.

以下、本発明の実施例1について、図面を参照しながら説明する。図1は、本実施例に係る半導体装置10の平面図であり、図2は、図1のII−II線断面図である。ただし、図1及び図2では、電極パッドが形成された領域のみを図示している(図3〜20において同様)。半導体装置10は、半導体基板1と、半導体基板1に形成された給電部分2と、半導体基板1の表面を被覆する絶縁膜3と、半導体基板1および絶縁膜3の表面を被覆する電極パッド4とを備えている。半導体基板1の裏面には、電極6が形成されている。ここで、給電部分とは、半導体基板上において、電極パッドを通して、外部配線から給電が行われる部分を意味する。例えば、半導体素子の活性領域である主セルや、主セルの電流を検知するためのセンスセル等のコンタクト領域が、給電部分に該当する。   Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor device 10 according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line II-II in FIG. However, in FIG.1 and FIG.2, only the area | region in which the electrode pad was formed is shown in figure (similarly in FIGS. 3-20). The semiconductor device 10 includes a semiconductor substrate 1, a power feeding portion 2 formed on the semiconductor substrate 1, an insulating film 3 that covers the surface of the semiconductor substrate 1, and an electrode pad 4 that covers the surfaces of the semiconductor substrate 1 and the insulating film 3. And has. An electrode 6 is formed on the back surface of the semiconductor substrate 1. Here, the power supply portion means a portion where power is supplied from the external wiring through the electrode pad on the semiconductor substrate. For example, a contact region such as a main cell, which is an active region of a semiconductor element, or a sense cell for detecting a current in the main cell corresponds to the power feeding portion.

電極パッド4は、図1および図2に示すように、半導体装置10の最表面に露出している。電極パッド4は、絶縁膜3を貫通して給電部分2に電気的に接続している。電極パッド4は、給電部分2の上方に位置する基板接続領域41、外部配線(ワイヤ)と接続する外部配線接続領域43、基板接続領域41と外部配線接続領域43との間に設けられた抵抗調整領域45とを備えている。図2に示すように、抵抗調整領域45および外部配線接続領域43は、絶縁膜3の上方となる位置に設けられている。絶縁膜3は、抵抗調整領域45を越えて基板接続領域41の一部まで延びており、給電部分2に接していない。電極パッド4の材料としては、例えばアルミニウム(Al)や銅(Cu)等の導電材を用いることができる。   As shown in FIGS. 1 and 2, the electrode pad 4 is exposed on the outermost surface of the semiconductor device 10. The electrode pad 4 penetrates the insulating film 3 and is electrically connected to the power feeding portion 2. The electrode pad 4 includes a substrate connection region 41 located above the power feeding portion 2, an external wiring connection region 43 connected to an external wiring (wire), and a resistor provided between the substrate connection region 41 and the external wiring connection region 43. And an adjustment area 45. As shown in FIG. 2, the resistance adjustment region 45 and the external wiring connection region 43 are provided at a position above the insulating film 3. The insulating film 3 extends beyond the resistance adjustment region 45 to a part of the substrate connection region 41 and is not in contact with the power feeding portion 2. As a material of the electrode pad 4, for example, a conductive material such as aluminum (Al) or copper (Cu) can be used.

図1に示すように、本実施例の電極パッド4には、複数の導電部451からなる抵抗調整領域45が設けられている。複数の導電部451は、基板接続領域41から外部配線接続領域43に向けて延びている。隣接する複数の導電部451の間には、孔部452が設けられている。孔部452は、抵抗調整領域45の非導電部として機能する。なお、孔部452が設けられている位置には、非導電性の材料を充填してもよい。   As shown in FIG. 1, the electrode pad 4 of the present embodiment is provided with a resistance adjustment region 45 including a plurality of conductive portions 451. The plurality of conductive portions 451 extend from the substrate connection region 41 toward the external wiring connection region 43. A hole 452 is provided between a plurality of adjacent conductive portions 451. The hole 452 functions as a non-conductive part of the resistance adjustment region 45. Note that a position where the hole 452 is provided may be filled with a non-conductive material.

複数の導電部451は、図1および図2に示す長さL、幅W、厚さDが等しくなるように形成されている。複数の導電部451のうち、いくつかの導電部451をトリミングにより切断することによって、抵抗調整領域45の抵抗値を調整することができる。例えば、図1に示すように、6本の導電部451が設けられている場合には、そのうちの1本をトリミングによって図3に示すように切断すれば、抵抗調整領域45の抵抗値が20%大きくなる。   The plurality of conductive portions 451 are formed so that the length L, the width W, and the thickness D shown in FIGS. 1 and 2 are equal. The resistance value of the resistance adjustment region 45 can be adjusted by cutting some of the plurality of conductive portions 451 by trimming. For example, when six conductive portions 451 are provided as shown in FIG. 1, if one of them is cut as shown in FIG. 3 by trimming, the resistance value of the resistance adjustment region 45 is 20 %growing.

本実施例によれば、基板接続領域と、抵抗調整領域と、外部配線接続領域とが、1つの電極パッドに形成されている。このため、従来のように、半導体装置の給電部分と外部配線とを接続するための電極パッドと、トリミングによって抵抗を調整可能な電極パッドとをそれぞれ設ける必要がなく、抵抗調整領域を設置することによって半導体装置が大型化することを抑制できる。   According to this embodiment, the substrate connection region, the resistance adjustment region, and the external wiring connection region are formed on one electrode pad. Therefore, unlike the conventional case, there is no need to provide an electrode pad for connecting the power feeding portion of the semiconductor device and the external wiring, and an electrode pad capable of adjusting the resistance by trimming, and a resistance adjustment region is provided. As a result, an increase in size of the semiconductor device can be suppressed.

また、半導体装置の表面に露出した電極パッドに抵抗調整領域が設けられており、この抵抗調整領域に対してトリミングを行うことによって、電極パッドの基板接続領域と外部配線接続領域との間の抵抗値を調整することができる。このため、例えば半導体装置の電気特性の検査工程など、完成した半導体装置の検査工程においてトリミングを行うことが可能となる。半導体基板や電極層が絶縁膜で保護された状態になった後で、トリミングを行うことができるため、トリミングに起因する半導体装置の特性低下を防止することができる。トリミングを行う抵抗調整領域の下方となる位置には、絶縁膜が存在しており、絶縁膜は、抵抗調整領域を越えて基板接続領域の一部まで延びている。このため、抵抗調整領域に対してトリミングを行っても、その下方となる位置に設置された半導体基板等を損傷しにくい。   Further, a resistance adjustment region is provided in the electrode pad exposed on the surface of the semiconductor device, and the resistance between the substrate connection region of the electrode pad and the external wiring connection region is obtained by trimming the resistance adjustment region. The value can be adjusted. For this reason, for example, trimming can be performed in an inspection process of a completed semiconductor device such as an inspection process of electrical characteristics of the semiconductor device. Since the trimming can be performed after the semiconductor substrate and the electrode layer are protected by the insulating film, the characteristics of the semiconductor device due to the trimming can be prevented from being deteriorated. An insulating film exists at a position below the resistance adjustment region where trimming is performed, and the insulating film extends beyond the resistance adjustment region to a part of the substrate connection region. For this reason, even if trimming is performed on the resistance adjustment region, it is difficult to damage a semiconductor substrate or the like installed at a position below the trimming region.

上記の実施例では、電極パッド4の抵抗調整領域45に設けられた複数の導電部451は、全て同じ材料、同じ形状、同じ大きさであったが、材料、形状、大きさが異なる複数の導電部を組み合わせてもよい。これによって、抵抗値の異なる導電部の組合せを得ることができる。   In the above embodiment, the plurality of conductive portions 451 provided in the resistance adjustment region 45 of the electrode pad 4 are all the same material, the same shape, and the same size, but a plurality of materials, shapes, and sizes are different. You may combine an electroconductive part. Thereby, a combination of conductive parts having different resistance values can be obtained.

例えば、図4に示すように、長さおよび厚さは全て同じで、幅が異なる導電部453a〜導電部453dを組み合わせることができる。導電部453aの幅はWであり、導電部453bの幅はWであり、導電部453cの幅はWであり、導電部453dの幅はWであって、幅W〜Wの大きさは、W>W>W>Wである。図1と同様に、隣接する導電部の間には、孔部が設けられている。導電部453a〜導電部453dの厚さをDとすれば、導電部453a〜導電部453dを基板接続領域41から外部配線接続領域43に向かう方向に垂直な面で切断した断面積は、導電部453aではDW、導電部453bではDW、導電部453cではDW、導電部453dではDWとなり、DW>DW>DW>DWである。導電部453a〜導電部453dの長さは全てLであり、同一であるから、導電部453a〜導電部453dの抵抗値は、導電部453aが最も小さく、導電部453b、導電部453c、導電部453dの順に大きくなる。 For example, as shown in FIG. 4, conductive portions 453a to 453d having the same length and thickness but different widths can be combined. Width of the conductive portion 453a is W 1, the width of the conductive portion 453b is W 2, the width of the conductive portion 453c is W 3, the width of the conductive portion 453d is a W 4, the width W 1 to W- The size of 4 is W 1 > W 2 > W 3 > W 4 . As in FIG. 1, a hole is provided between adjacent conductive portions. If the thickness of the conductive portions 453a to 453d is D, the cross-sectional area obtained by cutting the conductive portions 453a to 453d along a plane perpendicular to the direction from the substrate connection region 41 to the external wiring connection region 43 is the conductive portion. DW 1 in 453a, DW 2 in the conductive portion 453b, DW 3 in the conductive portion 453c, and DW 4 in the conductive portion 453d, and DW 1 > DW 2 > DW 3 > DW 4 . Since the lengths of the conductive portions 453a to 453d are all L and are the same, the resistance values of the conductive portions 453a to 453d are the smallest in the conductive portion 453a, and the conductive portions 453b, 453c, and conductive portions. It becomes large in order of 453d.

このように、導電部453a〜導電部453dはそれぞれ抵抗値が異なっているから、トリミングを行う導電部によって、抵抗調整領域45の抵抗値の増加量が異なる。抵抗値の異なる導電部453a〜導電部453dのうちから、適宜選択し、トリミングを実施することによって、抵抗調整領域45の抵抗値の増加量を調整することができる。   In this way, since the conductive portions 453a to 453d have different resistance values, the amount of increase in the resistance value of the resistance adjustment region 45 differs depending on the conductive portion to be trimmed. By appropriately selecting and conducting trimming from the conductive portions 453a to 453d having different resistance values, the increase amount of the resistance value of the resistance adjustment region 45 can be adjusted.

同様に、導電部の長さおよび幅は全て同じで、厚さを変えることによっても、抵抗値の異なる導電部の組合せを得ることができる。図5は変形例に係る電極パッド4の平面図であり、図6は、図5のVI−VI線断面から矢印方向に見た図である。図5および図6に示すように、長さおよび幅は全て同じで、厚さが異なる導電部454a〜導電部454cを用いることによって、上記と同様に、基板接続領域41から外部配線接続領域43に向かう方向に垂直な面で切断した断面積がそれぞれ異なる導電部454a〜導電部454cを得ることができる。尚、図1と同様に、隣接する導電部の間には、孔部が設けられている。図5に示すように、導電部454aの厚さはDであり、導電部454bの厚さはDであり、導電部454cの厚さはDであって、厚さD〜Dの大きさは、D>D>Dである。基板接続領域41から外部配線接続領域43に向かう方向に垂直な面で切断した断面積は、導電部454aが最も大きく、導電部454b、導電部454cの順に小さくなる。このため、導電部454a〜導電部454cの抵抗値は、それぞれ異なり、導電部454aが最も小さく、導電部454b、導電部454cの順に大きくなる。抵抗値の異なる導電部454a〜導電部454cのうちから、適宜選択し、トリミングを実施することによって、抵抗調整領域45の抵抗値の増加量を調整することができる。 Similarly, the lengths and widths of the conductive portions are all the same, and combinations of conductive portions having different resistance values can be obtained by changing the thickness. FIG. 5 is a plan view of the electrode pad 4 according to the modified example, and FIG. 6 is a view as seen in the direction of the arrow from the VI-VI line cross section of FIG. As shown in FIGS. 5 and 6, by using the conductive portions 454a to 454c having the same length and width and different thicknesses, the substrate connection region 41 to the external wiring connection region 43 are used in the same manner as described above. It is possible to obtain the conductive portions 454a to 454c having different cross-sectional areas cut along a plane perpendicular to the direction toward. As in FIG. 1, a hole is provided between adjacent conductive portions. As shown in FIG. 5, the thickness of the conductive portion 454a is D 1, the thickness of the conductive portion 454b is D 2, the thickness of the conductive portion 454c is a D 3, the thickness D 1 to D The size of 3 is D 1 > D 2 > D 3 . The cross-sectional area cut along a plane perpendicular to the direction from the substrate connection region 41 to the external wiring connection region 43 is the largest in the conductive portion 454a, and decreases in the order of the conductive portion 454b and the conductive portion 454c. For this reason, the resistance values of the conductive portions 454a to 454c are different from each other, the conductive portion 454a is the smallest, and the conductive portions 454b and the conductive portion 454c increase in this order. The amount of increase in the resistance value of the resistance adjustment region 45 can be adjusted by appropriately selecting and conducting trimming from the conductive portions 454a to 454c having different resistance values.

導電部の幅Wおよび厚さDは全て同じで、長さを変えることによっても、抵抗値の異なる導電部の組合せを得ることができる。図7に示すように、幅および厚さは全て同じで、長さが異なる複数の導電部455a〜導電部455eと、複数の導電部455a〜455dのそれぞれが接続される定抵抗部47とを備えた抵抗調整領域45とすれば、導電部455a〜導電部455eの抵抗値をそれぞれ異ならせることができる。尚、図1と同様に、隣接する導電部の間には、孔部が設けられている。抵抗値の異なる導電部455a〜導電部455eのうちから、適宜選択し、トリミングを実施することによって、抵抗調整領域45の抵抗値の増加量を調整することができる。   The width W and thickness D of the conductive portions are all the same, and combinations of conductive portions having different resistance values can be obtained by changing the length. As shown in FIG. 7, a plurality of conductive portions 455a to 455e having the same width and thickness, and different lengths, and a constant resistance portion 47 to which each of the plurality of conductive portions 455a to 455d is connected. If the resistance adjustment region 45 is provided, the resistance values of the conductive portions 455a to 455e can be made different. As in FIG. 1, a hole is provided between adjacent conductive portions. By appropriately selecting from the conductive portions 455a to 455e having different resistance values and performing trimming, the increase amount of the resistance value of the resistance adjustment region 45 can be adjusted.

また、導電部の材質を変えることによって、抵抗値の異なる導電部の組合せを得ることもできる。図8に示す導電部456aは、比較的抵抗の低い材料によって形成されている。導電部456bは、比較的抵抗の高い材料によって形成されている。図1と同様に、隣接する導電部の間には、孔部が設けられている。表1に、電極材料として用いられる代表的な金属の比抵抗を示す。比較的抵抗の低い材料としては、例えば、Al、Cuなどを好適に用いることができる。比較的抵抗の高い材料としては、例えば、プラチナ(Pt)、鉄(Fe)、チタン(Ti)、クロム(Cr)などを好適に用いることができる。尚、図8においては、導電部456aと、電極パッド4の基板接続領域41および外部配線接続領域43は同じ材料を用いている。

Figure 2010177226
Moreover, the combination of the conductive parts having different resistance values can be obtained by changing the material of the conductive parts. The conductive portion 456a shown in FIG. 8 is formed of a material having a relatively low resistance. The conductive portion 456b is formed of a material having a relatively high resistance. As in FIG. 1, a hole is provided between adjacent conductive portions. Table 1 shows specific resistances of typical metals used as electrode materials. As a material having a relatively low resistance, for example, Al, Cu or the like can be suitably used. As a material having relatively high resistance, for example, platinum (Pt), iron (Fe), titanium (Ti), chromium (Cr), or the like can be preferably used. In FIG. 8, the same material is used for the conductive portion 456a, the substrate connection region 41 of the electrode pad 4 and the external wiring connection region 43.
Figure 2010177226

導電部456aと導電部456bは、図1に示す導電部451と同様に同じ大きさ、同じ形状であるから、抵抗の高い材料で形成された導電部456bの抵抗値は、抵抗の低い材料で形成された導電部456aよりも高い。抵抗値の異なる導電部456a、導電部456bのうちから、適宜選択し、トリミングを実施することによって、抵抗調整領域45の抵抗値の増加量を調整することができる。   Since the conductive portion 456a and the conductive portion 456b have the same size and the same shape as the conductive portion 451 shown in FIG. 1, the resistance value of the conductive portion 456b formed of a material with high resistance is a material with low resistance. It is higher than the formed conductive portion 456a. By appropriately selecting from the conductive portions 456a and 456b having different resistance values and performing trimming, the amount of increase in the resistance value of the resistance adjustment region 45 can be adjusted.

尚、導電部に用いる金属材料は、2種類以上選んでもよい。例えば、表2に示す全ての金属材料について、それぞれ1つずつ導電部を設けてもよい。また、導電部に用いる材料と電極パッドの基板接続領域および外部配線接続領域に用いる材料が異なっていてもよい。   Two or more kinds of metal materials used for the conductive portion may be selected. For example, one conductive portion may be provided for each of the metal materials shown in Table 2. Further, the material used for the conductive portion and the material used for the substrate connection region of the electrode pad and the external wiring connection region may be different.

次に、本実施例に係る半導体装置10の電極パッド4の製造工程について説明する。尚、半導体装置10のその他の製造工程(すなわち、電極パッド4以外の構造の製造工程)については、一般的な半導体装置の製造方法を利用することができるため、ここではその詳細な説明は省略する。本実施例に係る半導体装置10の電極パッド4は、レジストを用いた電極パターニング技術によって製造することができる。   Next, the manufacturing process of the electrode pad 4 of the semiconductor device 10 according to the present embodiment will be described. In addition, since the manufacturing method of a general semiconductor device can be utilized about the other manufacturing process (namely, manufacturing process of structures other than the electrode pad 4) of the semiconductor device 10, the detailed description is abbreviate | omitted here. To do. The electrode pad 4 of the semiconductor device 10 according to the present embodiment can be manufactured by an electrode patterning technique using a resist.

図1および図2に示す電極パッド4の製造工程の一例について説明する。まず、図9に示すように、半導体基板1上に、絶縁膜3を形成し、給電部分2の上方に位置する絶縁膜3をエッチングによって除去する。次に、図10に示すように、半導体基板1および絶縁膜3の表面に、電極パッド34を形成する。   An example of the manufacturing process of the electrode pad 4 shown in FIGS. 1 and 2 will be described. First, as shown in FIG. 9, the insulating film 3 is formed on the semiconductor substrate 1, and the insulating film 3 located above the power feeding portion 2 is removed by etching. Next, as shown in FIG. 10, electrode pads 34 are formed on the surfaces of the semiconductor substrate 1 and the insulating film 3.

次に、図11および図12に示すように、電極パッド34の表面にレジスト35を形成する。図11は図10に対してレジスト35を積層した状態を示す図であり、図12は図11の状態での平面図である。図11は図12のXI−XI線断面図に相当する。レジスト35は、図1に示す電極パッド4の形状に合わせてパターニングされている。すなわち、レジスト35には開口部351が設けられる。開口部351の位置は、図1に示す孔部452の位置に対応している。   Next, as shown in FIGS. 11 and 12, a resist 35 is formed on the surface of the electrode pad 34. FIG. 11 is a view showing a state in which a resist 35 is stacked with respect to FIG. 10, and FIG. 12 is a plan view in the state of FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG. The resist 35 is patterned in accordance with the shape of the electrode pad 4 shown in FIG. That is, the resist 35 is provided with an opening 351. The position of the opening 351 corresponds to the position of the hole 452 shown in FIG.

次に、RIE(Reactive Ion Etching)法等によって、レジスト35の開口部351に位置する電極パッド34の一部分をエッチングによって除去する。エッチング終了後、レジストを除去する。このように電極パッド34をパターニングすることによって、図1および図2に示す電極パッド4を製造することができる。   Next, a part of the electrode pad 34 located in the opening 351 of the resist 35 is removed by etching by RIE (Reactive Ion Etching) method or the like. After the etching is completed, the resist is removed. By patterning the electrode pad 34 in this way, the electrode pad 4 shown in FIGS. 1 and 2 can be manufactured.

図4〜図7に示す電極パッド4についても、上記の方法を用いて製造することができる。図4〜図7に示す電極パッド4は、図11および図12に示すレジスト35を図4〜図7に合わせてパターニングすることによって製造することができる。図5および図6に示す厚さの異なる導電部454a〜454cを有する電極パッド4は、例えば、適宜パターニングしたレジストを用いて図10〜図12に示す製造工程を3回繰返すことによって製造することができる。   The electrode pad 4 shown in FIGS. 4 to 7 can also be manufactured using the above method. The electrode pad 4 shown in FIGS. 4 to 7 can be manufactured by patterning the resist 35 shown in FIGS. 11 and 12 according to FIGS. The electrode pad 4 having the conductive portions 454a to 454c having different thicknesses shown in FIGS. 5 and 6 is manufactured by repeating the manufacturing process shown in FIGS. 10 to 12 three times using an appropriately patterned resist, for example. Can do.

また、図8に示すような異なる材料の導電部456aと導電部456bを備えた電極パッド4は、リフトオフ法によって製造することができる。リフトオフ法では、図9に示す状態(絶縁膜3の一部を除去した状態)とした後、図13および図14に示すように、半導体基板1および絶縁膜3の表面にレジスト36を形成する工程を行う。図13は図9に対してレジスト36を積層した状態を示す図であり、図14は図13の状態での平面図である。図13は図14のXIII−XIII線断面図に相当する。レジスト36には、開口部361が設けられている。開口部361の位置は、図8に示す比較的抵抗の高い材料を用いた導電部456bの位置に対応している。   Moreover, the electrode pad 4 provided with the conductive part 456a and the conductive part 456b of different materials as shown in FIG. 8 can be manufactured by a lift-off method. In the lift-off method, a resist 36 is formed on the surfaces of the semiconductor substrate 1 and the insulating film 3 as shown in FIGS. 13 and 14 after the state shown in FIG. 9 (a state in which a part of the insulating film 3 is removed) is obtained. Perform the process. 13 is a view showing a state in which a resist 36 is laminated with respect to FIG. 9, and FIG. 14 is a plan view in the state of FIG. 13 corresponds to a cross-sectional view taken along line XIII-XIII in FIG. The resist 36 has an opening 361. The position of the opening 361 corresponds to the position of the conductive portion 456b using a relatively high resistance material shown in FIG.

次に、図15に示すように、導電部456bに用いる材料によって導電膜38を形成し、その後、レジスト36を除去する。これにより、図16に示すように、導電部456bの位置の導電膜38のみが残る。次に、図17および図18に示すように、レジスト37を形成する。図17は図16に対してレジスト37を積層した状態を示す図であり、図18は図17の状態での平面図である。図17は図18のXVII−XVII線断面図に相当する。レジスト37は、図8に示す比較的抵抗の低い材料を用いた導電部456aと、電極パッド4の基板接続領域41と、外部配線接続領域43の位置を除いた部分に形成する。次に、図19に示すように、導電部456a等に用いる材料によって導電膜39を形成し、その後、レジストを除去する。このように電極パッド34をパターニングすることによって、図8に示す電極パッド4を製造することができる。   Next, as illustrated in FIG. 15, the conductive film 38 is formed using a material used for the conductive portion 456 b, and then the resist 36 is removed. Thereby, as shown in FIG. 16, only the conductive film 38 at the position of the conductive portion 456b remains. Next, as shown in FIGS. 17 and 18, a resist 37 is formed. FIG. 17 is a view showing a state in which a resist 37 is laminated with respect to FIG. 16, and FIG. 18 is a plan view in the state of FIG. FIG. 17 corresponds to a cross-sectional view taken along line XVII-XVII in FIG. The resist 37 is formed in a portion excluding the positions of the conductive portion 456a using the material having a relatively low resistance shown in FIG. Next, as illustrated in FIG. 19, a conductive film 39 is formed using a material used for the conductive portion 456a and the like, and then the resist is removed. The electrode pad 4 shown in FIG. 8 can be manufactured by patterning the electrode pad 34 in this way.

上記のとおり、本実施例に係る電極パッドは、従来の半導体装置の製造工程に用いられている技術を応用して製造することができる。従来の半導体装置の製造工程を大幅に変更することなく製造できるため、製造工程での手間やコスト、時間を大幅に増大させることなく、製造することが可能である。   As described above, the electrode pad according to the present embodiment can be manufactured by applying the technique used in the manufacturing process of the conventional semiconductor device. Since it can be manufactured without significantly changing the manufacturing process of the conventional semiconductor device, it can be manufactured without significantly increasing the labor, cost, and time in the manufacturing process.

また、本実施例では、トリミングによって抵抗を調整した後に、絶縁膜を形成する工程などを行う必要がないため、抵抗を調整した後に行う工程によって半導体装置の特性が再びばらついてしまうこともない。完成した半導体装置の特性に応じて抵抗値を調整できるため、半導体装置の特性をより適切に調整することができる。   Further, in this embodiment, it is not necessary to perform a step of forming an insulating film after adjusting the resistance by trimming, and thus the characteristics of the semiconductor device are not varied again by the step performed after adjusting the resistance. Since the resistance value can be adjusted according to the characteristics of the completed semiconductor device, the characteristics of the semiconductor device can be adjusted more appropriately.

実施例2に係る半導体装置20では、図20に示すように、電極パッド24は、基板接続領域41と外部配線接続領域43との間に設けられた抵抗調整領域55を備えている。なお、実施例1と共通の部分については重複説明を省略する。   In the semiconductor device 20 according to the second embodiment, as shown in FIG. 20, the electrode pad 24 includes a resistance adjustment region 55 provided between the substrate connection region 41 and the external wiring connection region 43. In addition, duplication description is abbreviate | omitted about the part which is common in Example 1. FIG.

抵抗調整領域55は、基板接続領域41から外部配線接続領域43に向けてサーペンタイン状に蛇行した主導電部551と、主導電部551を短絡させる副導電部553aおよび副導電部553bとを備えている。   The resistance adjustment region 55 includes a main conductive portion 551 meandering in a serpentine shape from the substrate connection region 41 toward the external wiring connection region 43, and a sub conductive portion 553a and a sub conductive portion 553b that short-circuit the main conductive portion 551. Yes.

副導電部553a、副導電部553bの少なくとも1つを切断することによって、抵抗調整領域55を流れる電流の経路が長くなるため、抵抗調整領域55の抵抗値を高くすることができる。   By cutting at least one of the sub-conductive portion 553a and the sub-conductive portion 553b, the path of the current flowing through the resistance adjustment region 55 becomes longer, so that the resistance value of the resistance adjustment region 55 can be increased.

尚、実施例2に係る半導体装置20の電極パッド24についても、実施例1において説明した電極パッド4の製造方法と同様の方法によって製造することができる。例えば、図11および図12に示すレジスト35を図20に合わせてパターニングすることによって製造することが可能である。   The electrode pad 24 of the semiconductor device 20 according to the second embodiment can be manufactured by the same method as the manufacturing method of the electrode pad 4 described in the first embodiment. For example, the resist 35 shown in FIGS. 11 and 12 can be manufactured by patterning according to FIG.

上記のとおり、本発明に係る実施例1および実施例2によれば、基板接続領域と、抵抗調整領域と、外部配線接続領域とが、1つの電極パッドに形成されている。このため、従来のように、半導体装置の給電部分と外部配線とを接続するための電極パッドと、トリミングによって抵抗を調整可能な電極パッドとをそれぞれ設ける必要がなく、抵抗調整領域を設置することによって半導体装置が大型化することを抑制できる。   As described above, according to the first and second embodiments of the present invention, the substrate connection region, the resistance adjustment region, and the external wiring connection region are formed on one electrode pad. Therefore, unlike the conventional case, there is no need to provide an electrode pad for connecting the power feeding portion of the semiconductor device and the external wiring, and an electrode pad capable of adjusting the resistance by trimming, and a resistance adjustment region is provided. As a result, an increase in size of the semiconductor device can be suppressed.

また、上記の実施例1および実施例2によれば、半導体装置の表面に露出した電極パッドに抵抗調整領域が設けられており、この抵抗調整領域に対してトリミングを行うことによって、電極パッドの基板接続領域と外部配線接続領域との間の抵抗値を調整することができる。このため、例えば半導体装置の電気特性の検査工程など、完成した半導体装置の検査工程においてトリミングを行うことが可能となる。半導体基板や電極層が絶縁膜で保護された状態になった後で、トリミングを行うことができるため、トリミングに起因する半導体装置の特性低下を防止することができる。すなわち、トリミングを行う抵抗調整領域の下方となる位置には、絶縁膜が存在しており、絶縁膜は、抵抗調整領域から基板接続領域まで延びている。このため、抵抗調整領域に対してトリミングを行っても、その下方となる位置に設置された半導体基板等を損傷しにくい。   Further, according to the first and second embodiments described above, the resistance adjustment region is provided on the electrode pad exposed on the surface of the semiconductor device, and trimming is performed on the resistance adjustment region, so that the electrode pad The resistance value between the substrate connection region and the external wiring connection region can be adjusted. For this reason, for example, trimming can be performed in an inspection process of a completed semiconductor device such as an inspection process of electrical characteristics of the semiconductor device. Since the trimming can be performed after the semiconductor substrate and the electrode layer are protected by the insulating film, the characteristics of the semiconductor device due to the trimming can be prevented from being deteriorated. That is, the insulating film exists at a position below the resistance adjustment region where trimming is performed, and the insulating film extends from the resistance adjustment region to the substrate connection region. For this reason, even if trimming is performed on the resistance adjustment region, it is difficult to damage a semiconductor substrate or the like installed at a position below the trimming region.

また、トリミングによって抵抗を調整した後に、絶縁膜を形成する工程などを行う必要がないため、抵抗を調整した後に行う工程によって半導体装置の特性が再びばらついてしまうこともない。完成した半導体装置の特性に応じて抵抗値を調整できるため、半導体装置の特性をより適切に調整することができる。   Further, it is not necessary to perform a step of forming an insulating film after adjusting the resistance by trimming. Therefore, the characteristics of the semiconductor device are not varied again by the step performed after adjusting the resistance. Since the resistance value can be adjusted according to the characteristics of the completed semiconductor device, the characteristics of the semiconductor device can be adjusted more appropriately.

以上、本発明の実施例について詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。   As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 半導体基板
2 給電部分
3 絶縁膜
4、24、34 電極パッド
6 電極層
10、20 半導体装置
35、36、37 レジスト
38、39 導電膜
41 基板接続領域
43 外部配線接続領域
45、55 抵抗調整領域
47 定抵抗部
351、361 開口部
451 導電部
452 孔部
453a〜453d 導電部
454a〜454c 導電部
455a〜455e 導電部
456a、457b 導電部
551 主導電部
553a、553b 副導電部
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electric power feeding part 3 Insulating film 4, 24, 34 Electrode pad 6 Electrode layer 10, 20 Semiconductor device 35, 36, 37 Resist 38, 39 Conductive film 41 Substrate connection area 43 External wiring connection area 45, 55 Resistance adjustment area 47 constant resistance parts 351 and 361 opening 451 conductive part 452 holes 453a to 453d conductive parts 454a to 454c conductive parts 455a to 455e conductive parts 456a and 457b conductive parts 551 main conductive parts 553a and 553b sub conductive parts

Claims (6)

半導体基板と、前記半導体基板の表面に設けられた絶縁膜と、前記半導体基板および前記絶縁膜の表面に設けられた電極パッドとを備えた半導体装置であって、
前記電極パッドは、前記絶縁膜を貫通して前記半導体基板と電気的に接続する基板接続領域と、外部配線がその表面に電気的に接続される外部配線接続領域と、前記基板接続領域と前記外部配線接続領域との間に設けられた抵抗調整領域とを備えていることを特徴とする半導体装置。
A semiconductor device comprising: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; and an electrode pad provided on the surface of the semiconductor substrate and the insulating film,
The electrode pad includes a substrate connection region that is electrically connected to the semiconductor substrate through the insulating film, an external wiring connection region in which external wiring is electrically connected to the surface, the substrate connection region, and the A semiconductor device comprising: a resistance adjustment region provided between the external wiring connection region and the semiconductor device.
前記抵抗調整領域は、前記基板接続領域から前記外部配線接続領域に延びる複数の導電部を備えており、
前記複数の導電部の少なくとも1つが切断可能となっていることを特徴とする請求項1に記載の半導体装置。
The resistance adjustment region includes a plurality of conductive portions extending from the substrate connection region to the external wiring connection region,
The semiconductor device according to claim 1, wherein at least one of the plurality of conductive portions is cuttable.
前記複数の導電部の少なくとも一つが、他の導電部とは抵抗が異なることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein at least one of the plurality of conductive portions has a resistance different from that of the other conductive portions. 前記抵抗調整領域は、前記基板接続領域と前記外部配線接続領域とを接続する主導電部と、前記主導電部を短絡させる複数の副導電部とを備えており、
前記複数の副導電部は、主導電部を異なる位置で短絡させるものであり、それら複数の副導電部の少なくとも1つが切断可能となっていることを特徴とする請求項1に記載の半導体装置。
The resistance adjustment region includes a main conductive portion that connects the substrate connection region and the external wiring connection region, and a plurality of sub conductive portions that short-circuit the main conductive portion.
2. The semiconductor device according to claim 1, wherein the plurality of sub-conductive portions short-circuit the main conductive portion at different positions, and at least one of the plurality of sub-conductive portions can be cut. .
前記主導電部は、サーペンタイン状に蛇行した導電部であることを特徴とする請求項4に記載の半導体装置。   The semiconductor device according to claim 4, wherein the main conductive portion is a conductive portion meandering in a serpentine shape. 前記抵抗調整領域が半導体装置の表面に露出していることを特徴とする請求項1ないし5のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the resistance adjustment region is exposed on a surface of the semiconductor device.
JP2009014924A 2009-01-27 2009-01-27 Semiconductor device Pending JP2010177226A (en)

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