JP2010176702A5

JP2010176702A5 -

Info

Publication number: JP2010176702A5
Application number: JP2010102697A
Authority: JP
Filing date: 2010-04-27
Publication date: 2011-05-06
Anticipated expiration: 2028-03-12

Claims

A plurality of blocks that are data erasing units, each of the blocks including a plurality of pages that are data writing and reading units;
A plurality of blocks included in the nonvolatile semiconductor memory, a first storage area in which data is managed in a first management unit that is a natural number multiple of a sector unit, and two or more natural numbers in the first management unit A controller that allocates data to a second storage area in which data is managed in a second management unit that is doubled ,
The controller is
First means for expelling valid data of the first management unit from the first storage area, integrating the valid data with data of the second management unit, and storing the data in the second storage area; ,
A second means for selecting a plurality of valid data of the first management unit in the first storage area and rewriting to a new block in the first storage area;
The memory system , wherein the first means is executed at least once before the second means is executed .

The controller executes the second means after executing the first means when the number of blocks allocated to the first storage area exceeds an upper limit value. Item 4. The memory system according to Item 1.

After executing the first means, the controller executes the first means again when the total capacity of valid data of the first management unit in the first storage area is equal to or greater than a predetermined value. The memory system according to claim 2, wherein:

After executing the first means, the controller executes the second means when the total capacity of valid data of the first management unit in the first storage area is less than a predetermined value. The memory system according to claim 2.

The memory system according to claim 3, wherein the predetermined value is equal to a storage capacity for one block.

The controller, when executing the first means, selects the address range of the second management unit corresponding to the storage capacity of a plurality of blocks, and within the address range of the selected second management unit The memory system according to claim 1, wherein valid data of the first management unit included is expelled.

The controller, when executing the second means, selects blocks in order from the smallest number of valid data in the first management unit, and validates the first management unit included in the selected block. The memory system according to claim 1, wherein data is rewritten.

When the controller executes the first means, the controller reads from the first storage area based on the number of valid data of the first management unit included in the address range of the second management unit. 2. The memory system according to claim 1, wherein valid data to be expelled to the second storage area is selected.

The controller, when executing the first means, selects the address range of the second management unit in order from the largest number of valid data, and the address range of the selected second management unit 9. The memory system according to claim 8, wherein valid data of the first management unit included in the memory is expelled.

When the controller executes the first means, the second storage unit corresponding to the address range of the second management unit including valid data of the first management unit in the first storage area. Based on whether valid data of the management unit is stored in the block including invalid data of the second management unit in the second storage area, the second data from the first storage area 9. The memory system according to claim 8, wherein data to be pushed out to a storage area is selected.

The controller, when executing the first means, sets an address range of the second management unit corresponding to valid data of the second management unit stored in a block having a large number of invalid data. 11. The memory system according to claim 10, wherein the memory system is selected preferentially and valid data of the first management unit included in an address range of the selected second management unit is expelled.

When the controller executes the first means, the controller invalidates the valid data of the first management unit expelled to the second storage area in the first storage area, and there is valid data. The memory system according to claim 1, wherein a block that is not to be released is released from the first storage area.

The controller invalidates the valid data of the first management unit rewritten in a new block in the first storage area in the first storage area when executing the second means, 2. The memory system according to claim 1, wherein a block having no valid data is released from the first storage area.

The controller, when executing the first means, valid data of the first management unit evicted from the first storage area, at least one of the first storage area and the second storage area 2. The memory system according to claim 1, wherein data read from one side is integrated into data of the second management unit.

A semiconductor memory capable of holding data to be transferred to the nonvolatile semiconductor memory;
The controller is
A third means for storing the sector unit data in the semiconductor memory;
Fourth means for integrating the data evicted from the semiconductor memory into the first storage area by integrating the data into the data of the first management unit;
Fifth means for integrating the data evicted from the semiconductor memory with the data of the second management unit and storing it in the second storage area;
The memory system according to claim 1, further comprising:

The memory system according to claim 15, wherein the semiconductor memory is a volatile random access memory.

The memory system according to claim 15, wherein the semiconductor memory is a nonvolatile random access memory.

The memory system according to claim 1, wherein the page unit is a natural number multiple of 2 or more of the first management unit, and the first management unit is smaller than the block unit. .

2. The memory system according to claim 1, wherein the block unit is a natural number multiple of 2 or more of the second management unit, and the second management unit is larger than the page unit. .

The memory system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.