JP2010171043A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that mounts thereon a capacitance element, whose capacitance per unit area is increased compared with a semiconductor device mounted with a conventional capacitance element, and a method for manufacturing the same. <P>SOLUTION: The method for manufacturing the semiconductor device includes the following steps. A step of forming an element isolation film 2, a gate insulating film, a first poly-silicon film 4a, and an anti-oxidation film on a semiconductor film 1 and implanting impurity ions into the first poly-silicon film 4a. Subsequently, a step of applying thermal oxidation treatment to the first poly-silicon film so as to form a porous silicon film 8a, having voids penetrating through the first poly-silicon film or voids not penetrating through the first poly-silicon film, on the element isolation film. Further, a step of forming a capacitance insulating film 12 on the surface of the porous silicon film 8a so as to form a second poly-silicon film 13 on the first poly-silicon film, on the capacitance insulating film, and in each void respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and the like, and more particularly, to a semiconductor device capable of mounting a capacitor element having a capacity per unit area increased as compared with a conventional semiconductor device mounting a capacitor element, and a manufacturing method thereof. Etc.

  FIG. 10 is a plan view showing a conventional semiconductor device. FIGS. 8A to 8D and FIGS. 9A to 9D are cross-sectional views corresponding to the CC ′ portion shown in FIG. 10 for explaining a conventional method for manufacturing a semiconductor device. FIG. In addition, the semiconductor device illustrated in FIG. 10 is a mixed product of a capacitor (PIP capacitor) and a transistor.

  First, as shown in FIG. 8A, an STI film 52 that is an element isolation film is embedded in a silicon substrate 51. Next, a gate insulating film 53 is formed on the silicon substrate 51 in the transistor formation region 71.

  Next, as shown in FIG. 8B, a first polysilicon film 54 to be a capacitor lower electrode and a gate electrode is formed on the STI film 52 and the gate insulating film 53. Thereafter, as shown in FIG. 8C, high concentration phosphorus ions 57 are ion-implanted into the first polysilicon film 54 and activated.

  Next, as shown in FIG. 8D, the silicon substrate 51 is thermally oxidized to form a capacitive insulating film 62 on the surface of the first polysilicon film 54. Thereafter, a second polysilicon film 63 to be a capacitor upper electrode is formed.

  Next, as shown in FIG. 9A, high-concentration phosphorus ions 64 are ion-implanted into the second polysilicon film 63. Thereafter, as shown in FIG. 9B, a cap film 65 is formed on the second polysilicon film 63. Next, the second polysilicon film 63 is ion-activated by performing a heat treatment on the silicon substrate 51.

  Next, as shown in FIG. 9C, a first resist pattern 66 is formed on the cap film 65 by a photolithography method, and the cap film 65 and the first resist pattern 66 are formed by an etching method using the first resist pattern 66 as a mask. The second polysilicon film 63 is processed. As a result, a capacitor upper electrode 63a is formed in the capacitor formation region 72. Thereafter, the first resist pattern 66 is peeled off.

  Next, as shown in FIG. 9D, the capacitive insulating film 62 and the first polysilicon film 54 are processed on the entire surface including the capacitive insulating film 62 and the cap film 65 by photolithography and etching. Thus, the gate electrode 54b and the capacitor lower electrode 54a are simultaneously formed in the transistor formation region 71 and the capacitor formation region 72, respectively.

  Next, an interlayer insulating film 68 is formed on the gate electrode 54b and the capacitor lower electrode 54a. Next, contact holes are formed in the interlayer insulating film 68 by photolithography and etching. W plugs 67a, 67b, 67c, and 67d are buried in the contact holes, and a wiring layer (not shown) is formed on the W plugs 67a, 67b, 67c, and 67d and the interlayer insulating film 68. Thereby, in the transistor formation region 71 and the capacitor formation region 72, the wiring layer is electrically connected to the gate electrode 54b and the capacitor lower electrode 54a (see, for example, Patent Document 1).

JP-A-6-13547 (paragraphs 0002-0017)

  Conventionally, in order to improve the capacity per unit area in a capacitive element, changing the capacitive insulating film by reducing the thickness of the capacitive insulating film or changing the capacitive element shape by making the shape of the capacitive element three-dimensional, etc. Can be considered as a practical method. However, in order to reduce the cost by reducing the chip size of the semiconductor device, it is necessary to reduce the capacity element occupation region by increasing the capacity per unit area. At this time, since the change of the capacitance insulating film described above is limited to the inter-electrode breakdown voltage, a sufficient improvement in capacitance cannot be expected. In addition, the change in the shape of the capacitive element greatly increases the number of masks due to the additional three-dimensional structure processing. Thus, it is difficult to improve the capacitance per unit area without increasing the number of masks in the capacitive element.

  The present invention has been made in view of the above, and an aspect according to the present invention is equipped with a capacitive element having an increased capacity per unit area compared to a semiconductor device equipped with a conventional capacitive element. A semiconductor device that can be manufactured and a method for manufacturing the same.

In order to solve the above problems, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming an element isolation film over a semiconductor substrate;
Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a first polysilicon film on the gate insulating film and the element isolation film;
Forming an antioxidant film on the first polysilicon film;
Removing the antioxidant film located above the element isolation film;
Implanting impurity ions into the first polysilicon film located on the element isolation film;
By subjecting the first polysilicon film to a thermal oxidation process, a first oxide film is formed on the surface of the first polysilicon film located on the element isolation film, and the first polysilicon film is formed. Forming a grain in which atoms of impurities exceeding the solid solubility limit are deposited on the film;
Removing the grains and the first oxide film to form a porous silicon film having a gap penetrating or not penetrating the first polysilicon film on the element isolation film;
Forming a capacitive insulating film on the surface of the porous silicon film including the surface in the void by a thermal oxidation method using the antioxidant film as a mask;
Exposing the first polysilicon film located on the gate insulating film by removing the antioxidant film;
Forming a second polysilicon film on the first polysilicon film, on the capacitive insulating film, and in the gap;
By removing the second polysilicon film by a CMP method or an etch back method, the first polysilicon film located above the gate insulating film is exposed and the second polysilicon film located on the capacitor insulating film is exposed. A step of leaving the polysilicon film of
It is characterized by comprising.

  According to the method for manufacturing a semiconductor device, a porous silicon film having a gap penetrating or not penetrating the first polysilicon film is formed on the element isolation film. Thereby, the surface area of the porous silicon film can be greatly increased. Since a capacitive insulating film is formed on the surface of the porous silicon film, the capacity per unit area can be increased as compared with a conventional capacitive element using the same capacitive insulating film as the capacitive insulating film. .

In the method of manufacturing a semiconductor device according to the present invention, after the step of removing the second polysilicon film by a CMP method or an etch back method,
Ion-implanting impurity ions into the first and second polysilicon films;
Forming a second oxide film on the surfaces of the first and second polysilicon films by a thermal oxidation method;
A gate electrode made of the first polysilicon film is formed on the gate insulating film by processing the second oxide film and the first polysilicon film, and a capacitive element is formed on the element isolation film. Forming a step;
Comprising
The capacitive element preferably includes a lower electrode including the porous silicon film, an upper electrode including the capacitive insulating film and the second polysilicon film.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a polysilicon film on an insulating film,
Implanting impurity ions into the polysilicon film;
Performing a thermal oxidation process on the polysilicon film to form an oxide film on the surface of the polysilicon film and forming grains in which impurities atoms exceeding a solid solubility limit are deposited on the polysilicon film; ,
Removing the grains and the oxide film to form a porous silicon film having a void penetrating or not penetrating the polysilicon film on the insulating film;
Forming a capacitive insulating film on the surface of the porous silicon film including the surface in the void;
Forming a conductive film on the capacitive insulating film and in the gap;
It is characterized by comprising.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the impurity ions are phosphorus ions, and the atoms of the impurities are phosphorus atoms.

A semiconductor device according to the present invention includes an element isolation film formed on a semiconductor substrate,
A gate insulating film formed on the surface of the semiconductor substrate;
A gate electrode made of a first polysilicon film formed on the gate insulating film;
A capacitive element formed on the element isolation film;
Comprising
The capacitive element is
A lower electrode including a porous silicon film formed on the element isolation film and having a void penetrating or not penetrating the first polysilicon film, and the first polysilicon film;
A capacitive insulating film formed on the surface of the porous silicon film including the surface in the void;
An upper electrode made of a second polysilicon film formed on the capacitive insulating film and in the gap;
It is characterized by having.

A semiconductor device according to the present invention is formed on an insulating film, a porous silicon film having a gap that penetrates or does not penetrate a polysilicon film,
A capacitive insulating film formed on the surface of the porous silicon film including the surface in the void;
A conductive film formed on the capacitive insulating film and in the gap;
It is characterized by comprising.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 7 is a plan view showing a semiconductor device according to the embodiment of the present invention. 1 (a) to (d), FIGS. 2 (a) to (d), FIGS. 3 (a) to (d), and FIGS. FIG. 6 is a cross-sectional view corresponding to, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 5A to 5D and FIGS. 6A to 6C are cross-sectional views corresponding to cross-sectional views illustrating the manufacturing process of the semiconductor device. The semiconductor device shown in FIG. 7 is a product in which a capacitor element (PIP capacitor) formation region 22 and a transistor formation region 21 are mixedly mounted.

  First, as shown in FIG. 1A, an STI film 2 which is an element isolation film is embedded in a silicon substrate 1. Next, in the transistor formation region 21, the gate insulating film 3 is formed on the silicon substrate 1 by a thermal oxidation method.

  Next, as shown in FIG. 1B, a first polysilicon film to be a capacitor lower electrode and a gate electrode is formed on the entire surface of the substrate including the STI film 2 and the gate insulating film 3 by a CVD (Chemical Vapor Deposition) method. 4a is formed.

  Next, as shown in FIG. 1C, an antioxidant film 5 is formed on the first polysilicon film 4a by the CVD method. The antioxidant film 5 may be an insulating film, and for example, a silicon nitride film or a silicon carbide film is used.

  Next, as shown in FIG. 1D, a first resist pattern 6 is formed on the antioxidant film 5 by photolithography. The first resist pattern 6 is patterned so as to open the capacitor element formation region 22.

  Next, as shown in FIG. 2A, the antioxidant film 5 is processed by an etching method using the first resist pattern 6 as a mask. Thereby, the antioxidant film 5 is removed and the first polysilicon film 4a is exposed in the capacitive element formation region 22.

  Next, as shown in FIG. 2B, high dose phosphorus ions 7 are ion-implanted into the first polysilicon film 4a using the first resist pattern 6 as a mask. At this time, phosphorus ions 7 having a high dose amount are ion-implanted only in the exposed first polysilicon film 4a in the capacitor element formation region 22. Therefore, the first polysilicon film 4a in the ion-implanted capacitive element forming region 22 is in a state where the phosphorus concentration is considerably high or is close to the solid solution limit. In addition, since the first polysilicon film 4a in the transistor formation region 21 is covered with the first resist pattern 6 and the antioxidant film 5 during the ion implantation, phosphorus ions 7 are not ion-implanted. It can be used as a normal polysilicon film for a gate electrode.

FIG. 5A is a view in which the cross-sectional view shown in FIG. 2C is cut along A1-A1 ′ and the cut surface is shown from the top.
Next, as shown in FIGS. 2C and 5A, the first resist pattern 6 is peeled off. Next, the silicon substrate 1 is subjected to a thermal oxidation process to activate the ion-implanted first polysilicon film 4a, thereby forming a first activated silicon film 8 and an antioxidant film. A thermal oxide film 10 is formed on the first activated silicon film 8 not covered with 5. Further, the first activated silicon film 8 in the capacitor element formation region 22 becomes a part of the capacitor lower electrode. At this time, phosphorus atoms in the vicinity of the upper surface in the oxidized first activated silicon film 8 are dispersed and moved to the lower layer portion of the first activated silicon film 8 that is not oxidized. As a result, phosphorus atoms exceeding the solid solubility limit are precipitated, and abnormally grown grains 9 are formed.

The formation density of the abnormally grown grains 9 described above can be controlled by the dose amount of ion implantation into the first polysilicon film 4a. For example, a first polysilicon film 4a having a thickness of 0.2 μm is formed, and ions 9 are implanted at a dose of 4 × 10 ¹⁶ ions / cm ² to form grains 9. At this time, the shape of the formed grain 9 is often cylindrical, but assuming that it is a quadrangular prism, the average grain precipitation size (vertical length of the top surface of the quadrangular prism × horizontal length) and When the average grain precipitation frequency (average number of grains deposited per unit area) is calculated, the average grain precipitation size is 0.5 × 0.1 μm, and the average grain precipitation frequency is 2 / μm ² .

FIG. 5B is a view in which the cross-sectional view shown in FIG.
Next, as shown in FIGS. 2D and 5B, the silicon oxide film 10 and the grains 9 are removed by performing a chemical treatment on the silicon substrate 1. As a result, a void 11 penetrating the first activated silicon film 8 is formed in the first activated silicon film 8 to become porous silicon 8a. At this time, for example, ammonia overwater (APM) is used for the chemical solution in the chemical solution treatment.

Due to the formation of the void 11 described above, the surface area exposed in the porous silicon film 8a is greatly increased. The increase rate of the surface area of the porous silicon film 8a will be described in the case of the above-described grain 9 formation density. First, according to the formation density of the grains 9 described above, ^two grains 9 are deposited per 1 μm ² , and the area [μm ² ] of the upper surface portion of the grains 9 is 0.5 μm × 0.1 μm. Further, since the first polysilicon film 4a is formed with a thickness of 0.2 μm, the height of the gap 11 is also 0.2 μm. The surface area [μm ² ] inside the void 11 formed in the unit area (1 μm ² ) is (0.5 μm + 0.1 μm) × 2 × 0.2 μm × 2. The area [μm ² ] of the upper surface of the porous silicon film 8a formed in the unit area (1 μm ² ) is calculated by subtracting the area of the hole due to the void 11 from the area 1 μm ² of the conventional upper surface without the void 11. 1 μm ² −0.5 μm × 0.1 μm × 2 pieces. From this, the total surface area is 1.38 μm ^{2 when} the surface area inside the void 11 and the area of the upper surface of the porous silicon film 8 a are added, which is compared with the conventional upper area 1 μm ² without the void 11. Thus, the formation of the void 11 increases the overall surface area by 38%.

FIG.5 (c) is the figure which cut | disconnected sectional drawing shown to Fig.3 (a) by A3-A3 'part, and represented the cut surface from the upper surface.
Next, as shown in FIGS. 3A and 5C, by subjecting the silicon substrate 1 to thermal oxidation, capacitive insulation is provided on the surface of the porous silicon film 8a exposed in the capacitive element formation region 22. A film 12 is formed. Further, since the antioxidant film 5 is formed outside the capacitor element formation region 22, the capacitor insulating film 12 is not formed.

  Next, as shown in FIG. 3B, the antioxidant film 5 is removed by performing chemical treatment on the silicon substrate 1.

FIG.5 (d) is the figure which cut | disconnected sectional drawing shown in FIG.3 (c) by A4-A4 'part, and represented the cut surface from the upper surface.
Next, as shown in FIG. 3C and FIG. 5D, a second polysilicon film that becomes a capacitor upper electrode is formed on the entire surface of the substrate including the first polysilicon film 4a and the capacitor insulating film 12 by the CVD method. A silicon film 13 is formed. The second polysilicon film 13 is also embedded in the gap portion 11.

  Next, as shown in FIG. 3D, the second polysilicon film 13 is removed by a CMP method or an etch back method. As a result, the first polysilicon film 4a located above the gate insulating film 3 is exposed and the second polysilicon film 13 located on the capacitor insulating film 12 is left.

  Next, as shown in FIG. 4A, impurity ions 14 are ion-implanted into the first polysilicon film 4 a and the second polysilicon film 13.

Fig.6 (a) is the figure which cut | disconnected the cross section shown in FIG.4 (b) by A5-A5 'part, and represented the cut surface from the upper surface.
Next, as shown in FIGS. 4B and 6A, the first polysilicon film 4a and the second polysilicon film 13 are ion-activated by subjecting the silicon substrate 1 to thermal oxidation. . As a result, the capacitor upper electrode 13a made of the second polysilicon film is formed, the second activated silicon film 4b in which the impurity ions of the first polysilicon film are activated is formed, and the capacitor upper electrode An oxide film 15 is formed on 13a and the second activated silicon film 4b. As a result, the capacitor upper electrode 13a is covered with the capacitive insulating film 12 and the oxide film 15, and is completely separated from the second activated silicon film 4b and the porous silicon film 8a.

FIG. 6B is a view in which the cross-sectional view shown in FIG.
Next, as shown in FIGS. 4C and 6B, a second resist pattern 16 is formed on the oxide film 15 by photolithography. The oxide film 15 and the second activated silicon film 4b are processed by an etching method using the second resist pattern 16 as a mask. As a result, the capacitor lower electrode 4 c including the porous silicon film 8 is formed in the capacitive element formation region 22, and the gate electrode 4 d is formed in the transistor formation region 21. Thereafter, the second resist pattern 16 is peeled off.

FIG. 6C is a diagram in which the cross-sectional view shown in FIG. 4D is cut along A7-A7 ′ and the cut surface is shown from the top.
Next, as shown in FIGS. 4D and 6C, an interlayer insulating film 18 is formed on the entire surface of the substrate including the oxide film 15 by the CVD method. Next, contact holes are formed in the interlayer insulating film 18 and the oxide film 15 by photolithography and etching. By burying a W film in this contact hole, W plugs 17a, 17b, 17c and 17d are formed. Thereafter, a wiring layer (not shown) is formed on the W plugs 17 a, 17 b, 17 c, 17 d and the interlayer insulating film 18. As a result, the capacitor upper electrode 13a and the capacitor lower electrode 4c are electrically connected to the wiring layer in the capacitive element formation region 22, and the wiring layer and the gate electrode 4d are electrically connected in the transistor formation region 21.

As described above, according to the embodiment of the present invention, the first activated silicon film is formed by ion-implanting and performing thermal oxidation on the first polysilicon film 4a serving as the capacitor lower electrode in the capacitor element forming region 22. 8 and the grain 9 is generated. Thereafter, the grains 9 are removed by chemical treatment to form the voids 11 to form the porous silicon film 8a. Thereby, the surface area of the porous silicon film 8a can be greatly increased. For example, when the first polysilicon film 4a is formed with a thickness of 0.2 μm and ion implantation is performed at a dose amount of 4 × 10 ¹⁶ ions / cm ² , the entire surface area of the porous silicon film 8a is increased by 38%. Can be made. Since the capacitive insulating film 12 is formed on the surface of the porous silicon film 8a, the capacity increase of about 38% is achieved as compared with the conventional capacitive element using the same capacitive insulating film as the capacitive insulating film 12. Will be. As a result, the capacity per unit area can be improved without increasing the number of masks.

  Further, the capacitor upper electrode 13a is within the film thickness of the capacitor lower electrode 4c, and is substantially equal to the film thickness of the gate electrode 4d. That is, it is possible to eliminate the film thickness difference of the capacitor upper electrode 13a as compared with the conventional capacitor structure. Thereby, the film thickness difference between the second resist pattern 16 formed for processing the gate electrode 4d and the capacitor lower electrode 4c can be reduced in the transistor formation region 21 and the capacitor element formation region 22. As a result, it is possible to suppress the dimensional variation of the gate electrode 4d in the vicinity of the capacitive element formation region 22. Further, in the conventional capacitor structure, there was a risk of contact penetration when forming the contact hole due to the film thickness difference of the capacitor upper electrode. .

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the capacitor upper electrode is formed by the second polysilicon film 13, but the capacitor upper electrode can also be formed by another conductive film.

  Further, in the above embodiment, the high dose phosphorus ions 7 are implanted into the first polysilicon film 4a using the first resist pattern 6 as a mask with the antioxidant film 5 removed. It is also possible to implant a high dose of phosphorus ions into the first polysilicon film 4a through the antioxidant film 5 using the first resist pattern 6 as a mask without removing 5. However, in this case, before forming the thermal oxide film 10, it is necessary to remove the antioxidant film 5 in the region where the thermal oxide film 10 is to be formed.

  Moreover, in the said embodiment, although it is set as the porous silicon 8a in which the cavity part 11 which penetrates the 1st activated silicon film 8 was formed, this invention is not limited to this, All the cavity parts 11 are used. May not penetrate through the first activated silicon film 8, part of the gap 11 may not penetrate and the other part may not penetrate, and all the gaps 11 may not pass through the first activated silicon film 8. The activated silicon film 8 may not be penetrated.

(A)-(d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is a figure which shows the cut surface corresponding to sectional drawing explaining the manufacturing process of a semiconductor device. (A)-(d) is a figure which shows the cut surface corresponding to sectional drawing explaining the manufacturing process of a semiconductor device. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. (A)-(d) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. (A)-(d) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. The top view which shows the conventional semiconductor device.

  21, 71 ... transistor formation region, 22, 72 ... capacitor formation region, 1, 51 ... silicon substrate, 2, 52 ... STI film, 3, 53 ... gate insulating film, 4a, 54 ... 1st polysilicon film, 4b ... 2nd activated silicon film, 4c, 54a ... Capacitor lower electrode, 4d, 54b ... Gate electrode, 5 ... Antioxidation film, 6, 66 ... first resist pattern, 7, 57 ... phosphorus ions, 8 ... first activated silicon film, 8a ... porous silicon film, 9 ... grain, 10 ... · Thermal oxide film, 11 ··· gap, 12, 62 ··· capacitance insulating film, 13, 63 ··· second polysilicon film, 13a, 63a · · · capacitor upper electrode, 14, 64 ··· Impurity ions, 15 ... oxide film, 16 ... second layer Strike pattern, 18, 68 ... interlayer insulating film, 17a, 17b, 17c, 17d, 67a, 67b, 67c, 67d ··· W plug, 65 ... cap film

Claims (6)

Forming an element isolation film on a semiconductor substrate;
Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a first polysilicon film on the gate insulating film and the element isolation film;
Forming an antioxidant film on the first polysilicon film;
Removing the antioxidant film located above the element isolation film;
Implanting impurity ions into the first polysilicon film located on the element isolation film;
By subjecting the first polysilicon film to a thermal oxidation process, a first oxide film is formed on the surface of the first polysilicon film located on the element isolation film, and the first polysilicon film is formed. Forming a grain in which atoms of impurities exceeding the solid solubility limit are deposited on the film;
Removing the grains and the first oxide film to form a porous silicon film having a gap penetrating or not penetrating the first polysilicon film on the element isolation film;
Forming a capacitive insulating film on the surface of the porous silicon film including the surface in the void by a thermal oxidation method using the antioxidant film as a mask;
Exposing the first polysilicon film located on the gate insulating film by removing the antioxidant film;
Forming a second polysilicon film on the first polysilicon film, on the capacitive insulating film, and in the gap;
By removing the second polysilicon film by a CMP method or an etch back method, the first polysilicon film located above the gate insulating film is exposed and the second polysilicon film located on the capacitor insulating film is exposed. A step of leaving the polysilicon film of
A method for manufacturing a semiconductor device, comprising: 2. The method of claim 1, wherein the second polysilicon film is removed by a CMP method or an etch back method.
Ion-implanting impurity ions into the first and second polysilicon films;
Forming a second oxide film on the surfaces of the first and second polysilicon films by a thermal oxidation method;
A gate electrode made of the first polysilicon film is formed on the gate insulating film by processing the second oxide film and the first polysilicon film, and a capacitive element is formed on the element isolation film. Forming a step;
Comprising
The method of manufacturing a semiconductor device, wherein the capacitor element includes a lower electrode including the porous silicon film, an upper electrode including the capacitor insulating film and the second polysilicon film. Forming a polysilicon film on the insulating film;
Implanting impurity ions into the polysilicon film;
Performing a thermal oxidation process on the polysilicon film to form an oxide film on the surface of the polysilicon film and forming grains in which impurities atoms exceeding a solid solubility limit are deposited on the polysilicon film; ,
Removing the grains and the oxide film to form a porous silicon film having a void penetrating or not penetrating the polysilicon film on the insulating film;
Forming a capacitive insulating film on the surface of the porous silicon film including the surface in the void;
Forming a conductive film on the capacitive insulating film and in the gap;
A method for manufacturing a semiconductor device, comprising:   4. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity ions are phosphorus ions, and the atoms of the impurities are phosphorus atoms. 5. An element isolation film formed on a semiconductor substrate;
A gate insulating film formed on the surface of the semiconductor substrate;
A gate electrode made of a first polysilicon film formed on the gate insulating film;
A capacitive element formed on the element isolation film;
Comprising
The capacitive element is
A lower electrode including a porous silicon film formed on the element isolation film and having a void penetrating or not penetrating the first polysilicon film, and the first polysilicon film;
A capacitive insulating film formed on the surface of the porous silicon film including the surface in the void;
An upper electrode made of a second polysilicon film formed on the capacitive insulating film and in the gap;
A semiconductor device comprising: A porous silicon film formed on the insulating film and having a void penetrating or not penetrating the polysilicon film;
A capacitive insulating film formed on the surface of the porous silicon film including the surface in the void;
A conductive film formed on the capacitive insulating film and in the gap;
A semiconductor device comprising:

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