JP2010170409A - Arithmetic control unit, microprocessor and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the waste of power and arithmetic capacity in the waiting time of a plurality of processor-built-in arithmetic units, which is increasingly evident with new memory emergence, and reduce a context switch load on the arithmetic units. <P>SOLUTION: An arithmetic control unit is for use in an apparatus including a microprocessor and a memory connected to the microprocessor. The microprocessor includes a plurality of arithmetic parts, and the memory includes a shared storage area that the plurality of arithmetic parts can read from/write to. The arithmetic control unit includes a writing detection part for detecting whether or not writing to the shared storage area is allowed. If the arithmetic part cannot write to the shared storage area, the shared storage area is monitored and the operation of the arithmetic part is stopped. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a parallel processing execution method in a microprocessor, and more particularly to a microprocessor with low power consumption in a process switching time and a waiting time for parallel processing.

  Microprocessors are also incorporated into home appliances, and in general, a microprocessor incorporates a plurality of arithmetic units in order to reduce the power consumption of home appliances as described above. In the future, the number of arithmetic devices mounted on the microprocessor is expected to increase.

  The aforementioned microprocessor is required to simultaneously execute a plurality of arithmetic processes such as Internet communication and digital media processing. For this reason, in order to simultaneously execute a plurality of arithmetic processes as described above, the microprocessor is managed using software having a scheduler function that allocates an execution time of a plurality of processes, such as an OS (Operating System) or a hypervisor. Has been.

  As processing executed by the above-described software, there are control processing for operations executed exclusively and control processing for executing a plurality of operations in parallel (see, for example, Non-Patent Document 1).

  Control processing of operations executed exclusively is performed using a lock variable that is a management variable for managing operations executed exclusively. Specifically, the arithmetic device acquires a lock variable on the memory. Arithmetic operations executed by the arithmetic unit are executed exclusively until the lock variable is released. That is, the resource used by the operation is monopolized. The acquisition of the lock variable will be described later with reference to FIG.

In addition, the control processing for executing a plurality of operations in parallel causes the arithmetic device to execute the arithmetic operation based on the arithmetic operation that the above-described software causes each arithmetic device to execute and the execution time of the arithmetic operation. At this time, when executing another calculation from the currently performed calculation, the calculation device executes initialization and then executes a process for switching to the next calculation to be executed.
David A. Patterson, John L. Hennessy, "Computer Configuration and Design: Hardware and Software Interfaces, Third Edition", 2006

  However, the above-described operation control process executed exclusively has the following problems.

  In other words, when the processor includes the first arithmetic device and the second arithmetic device, and the first arithmetic device is executing an exclusive operation, the second arithmetic device will execute the exclusive operation. Then, since the first arithmetic unit has already acquired the lock variable, the second arithmetic unit cannot acquire the lock variable. At this time, the second arithmetic unit continues to access the memory until the lock variable is acquired. As a result, the second arithmetic unit performs an extra operation, and thus has a problem of consuming extra power.

  Further, the control processing for executing the above-described plurality of operations in parallel has the following problems.

  That is, when the arithmetic device executes the first operation and switches to the second operation, the arithmetic device needs to execute the management process when switching from the first operation to the second operation. There is a problem that the load on the arithmetic unit becomes large.

  In particular, the problem described above becomes more serious as the number of arithmetic units built in the microprocessor increases. In addition, in a memory that has been speeded up and nonvolatileized, response time and power saving are important, and the above-described problems become serious.

  The present invention has been made in view of such problems.

  A typical example of the present invention is as follows. That is, an arithmetic control device provided in a device including a microprocessor and a memory connected to the microprocessor, wherein the microprocessor includes a plurality of arithmetic units, and the memory is read and written by the plurality of arithmetic units. Including a possible shared storage area, the arithmetic control device includes a write detection unit that detects whether or not writing to the shared storage area is possible, and when the arithmetic unit is unable to write to the shared storage area, The shared storage area is monitored, and the operation of the arithmetic unit is stopped.

  According to the present invention, it is possible to reduce the power consumed by the processor by the synchronization waiting loop, and to speed up the switching of the calculation of the calculation device.

[First Embodiment]
In the first embodiment of the present invention, an invention relating to the above-described work control process executed exclusively will be described.

  First, the prior art will be described.

  FIG. 11 is a block diagram showing a device configuration of a device including a conventional microprocessor.

  The device 101 includes a microprocessor 102 and a memory 103.

  The microprocessor 102 and the memory 103 are connected via a memory access bus 107.

  The microprocessor 102 includes an arithmetic device 1 (105), an arithmetic device 2 (106), and a clock 112.

  The clock 112 is a circuit that generates a clock necessary for the operation of the synchronization circuit, and includes a crystal oscillator or the like.

  The arithmetic device 1 (105) and the arithmetic device 2 (106) are logic circuits that execute arithmetic operations based on the clock supplied from the clock 112. The arithmetic device 1 (105) and the arithmetic device 2 (106) manage the progress of the operation being executed as context information 1108 and context information 1110, respectively. Hereinafter, when the computing device 1 (105) and the computing device 2 (106) are not distinguished, they are referred to as computing devices 1 (105) and 2 (106).

  The memory access bus 107 is a bus that mediates access between the arithmetic devices 1 (105) and 2 (106) and the memory 103.

  The memory 103 is a storage area for storing all data necessary for the microprocessor 102 to execute an operation. The memory 103 includes, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash (Flash Memory), or an HDD (Hard Disk Drive). The memory 103 includes a main storage area 1126.

  The main storage area 1126 stores data necessary for the microprocessor 102 to execute operations.

  The main storage area 1126 includes a process information storage area 1118, a work queue 1122, a process memory area 1128, and a kernel memory area 1130.

  The process memory area 1128 is a memory area required for processing executed by the arithmetic devices 1 (105) and 2 (106), and is managed for each area divided into each arithmetic processing (process).

  The kernel memory area 1130 is a memory area necessary for managing the device 101 and controlling the operation of the microprocessor 102. The kernel memory area 1130 includes a scheduler 1101 and a lock variable 116.

  The scheduler 1101 is software for managing calculations executed by the calculation devices 1 (105) and 2 (106). The scheduler 1101 updates the process information storage area 1118 and the work queue 1122 and manages the order of operations.

  The lock variable 116 is a management for managing a portion that must be exclusively executed among the operations executed by the arithmetic devices 1 (105) and 2 (106) so that the operation is executed correctly and exclusively. Is a variable. Specifically, when the value of the lock variable 116 is “0x1”, the lock variable 116 indicates a state that is not locked. That is, it indicates that exclusive processing is not executed. When the value of the lock variable 116 is “0x0”, it indicates a locked state and cannot be locked until the lock is released. That is, it indicates that exclusive processing is being executed.

  The process information storage area 1118 is an area for storing the results of calculations executed by the calculation devices 1 (105) and 2 (106). Specifically, when more operations than the number of arithmetic devices included in the device 101 are executed in parallel, the arithmetic devices 1 (105) and 2 (106) execute processing according to instructions of the scheduler 1101, The context information 1108 and 1110 in which the results are stored are stored as context information 1124 in the process information storage area 1118, and the operations instructed by the scheduler 1101 are executed in order.

  The work queue 1122 is an area for storing a list of operations executed by the arithmetic devices 1 (105) and 2 (106). The scheduler 1101 refers to the process to be executed next.

  FIG. 12 is a sequence diagram for explaining a process when an exclusive operation is executed in the prior art.

  The sequence when the computing device 1 (105) and the computing device 2 (106) execute exclusive processing simultaneously is shown.

  First, the value of the lock variable 116 is “0x1”, and the lock variable 116 is not locked (state 1201).

  The arithmetic device 2 (106) executes lock acquisition for the lock variable 116 in order to execute exclusive operation, and succeeds in acquiring the lock (step 1205). In this case, since the lock variable 116 is not locked, the computing device 2 (106) succeeds in acquiring the lock. As a result, the value of the lock variable 116 becomes “0x0”, and the lock variable 116 is locked (state 1202).

  Here, as a method for acquiring the lock, for example, a method using a swap instruction can be considered. Specifically, by replacing the variable “1” held by the arithmetic device 2 (106) with the variable “0” held by the lock variable 116, the arithmetic device 2 (106) acquires the lock. That is, the value of the lock variable 116 is changed from “0x0” to “0x1”. In the method using the swap instruction, lock acquisition and lock acquisition detection can be performed simultaneously. The lock acquisition method is not limited to the above-described method, and may be another method.

  In the state described above, since the arithmetic device 1 (105) executes exclusive operation, when the lock acquisition is executed for the lock variable 116, the value of the lock variable 116 is already “0x0”. Acquisition fails (step 1206). That is, in the method using the swap instruction described above, the variable held by the arithmetic unit 1 (105) and the variable held by the lock variable 116 are both “0x0”. The retained variables are not changed. Therefore, it can be seen that the arithmetic device 1 (105) failed to acquire the lock. The arithmetic device 1 (105) executes a lock acquisition process until the lock acquisition is successful.

  In the example shown in FIG. 12, the arithmetic device 1 (105) actually refers to the cache memory included in the arithmetic device 1 (105) without accessing the lock variable 116 many times, It is monitored via the memory access bus 107 whether or not the cache of the lock variable 116 read out in (1) and the lock variable 116 on the memory 103 are different. In other words, the arithmetic device 1 (105) executes the monitoring process of the memory access bus 107.

  The computing device 2 (106) ends the computation protected by the lock variable 116, and releases the lock variable 116 (step 1207). As a result, the value of the lock variable 116 is rewritten to “0x1”, and the lock variable 116 is not locked (state 1203).

  The arithmetic unit 1 (105) detects that the value of the lock variable 116 has become “0x1” (step 1208), and invalidates the cache. Then, the arithmetic device 1 (105) executes the lock acquisition, and the lock acquisition is successful (step 1209).

  As a result, the value of the lock variable 116 becomes “0x0”, and the lock variable 116 is locked again (state 1204).

  Next, the 1st Embodiment of this invention is described using FIGS. 1-3.

  FIG. 1 is a block diagram illustrating an example of a device configuration of a device 101 including a microprocessor according to the first embodiment of this invention. Hereinafter, the difference from the apparatus configuration of the conventional device in FIG. 11 will be mainly described.

  Compared with the device 101 of FIG. 11, in the device 101 according to the present invention, the arithmetic device 1 (105) and the arithmetic device 2 (106) include the clock 112 and the clock 113, respectively.

  In addition, the device 101 according to the present invention newly includes an arithmetic device processing control unit 114.

  The arithmetic device processing control unit 114 includes a change monitoring command receiving unit 104, a write memory monitoring unit 115, a clock control unit 132, and a memory (not shown). The change monitoring command receiving unit 104, the write memory monitoring unit 115, and the clock control unit 132 are connected to a memory (not shown) via a bus (not shown). The memory (not shown) includes a monitoring information table 131.

  The change monitoring command receiving unit 104 is connected to the arithmetic devices 1 (105) and 2 (106). The change monitoring command receiving unit 104 receives a change monitoring command issued from the arithmetic device 1 (105) or the arithmetic device 2 (106), and updates the monitoring information table 131 based on the received change monitoring command.

  The clock control unit 132 is connected to the clocks 112 and 113. The clock control unit 132 periodically acquires information from the monitoring information table 131, and transmits an operation clock control instruction to the clocks 112 and 113 according to the acquired information.

  Note that the timing at which the clock control unit 132 periodically acquires information from the monitoring information table 131 may be, for example, when synchronized with the clock of the memory access bus or when synchronized with the clocks 112 and 113. Alternatively, the clock control unit 132 may be synchronized with another device, and the information in the monitoring information table 131 may be acquired at the operation timing of the other device.

  As a result, the clocks 112 and 113 in the present invention supply the clock to the arithmetic device 1 (105) or the arithmetic device 2 (106) based on the control instruction transmitted from the clock control unit 132, or interrupt the supply. can do. The clocks 112 and 113 may be constituted by crystal oscillators that generate clocks, but clocks supplied from crystal oscillators arranged outside the microprocessor 102 are supplied to the arithmetic units 1 (105) and 2 (106). A logic circuit having a function of adjusting to an appropriate frequency may be used.

  The write memory monitoring unit 115 is connected to the memory access bus 107 and monitors an access signal transmitted from the arithmetic device to the memory 103 flowing on the memory access bus 107, and the arithmetic device according to the contents of the monitoring information table 131. 1 (105) or the arithmetic unit 2 (106) detects rewriting of information stored in the memory 103, and updates the monitoring information table 131.

  The monitoring information table 131 stores information necessary for controlling the arithmetic devices 1 (105) and 2 (106). Details will be described later with reference to FIG.

  FIG. 2 is an explanatory diagram illustrating an example of the monitoring information table 131 according to the first embodiment of this invention.

  The monitoring information table 131 stores information necessary for the clock control unit 132 to control the clocks 112 and 113, and is updated by the change monitoring command receiving unit 104 and the write memory monitoring unit 115. An entry in the monitoring information table 131 is created when an instruction is received from the arithmetic device.

  The monitoring information table 131 includes a monitoring space 201, a monitoring address 202, a value 203, a call calculation device 204, and a clock state 205.

  The monitoring space 201 stores information indicating the address space of the memory address to which the address being monitored belongs. In the example shown in FIG. 2, it can be seen that the monitoring space 201 of the entry 206 is a kernel address space.

  The monitoring address 202 stores an address on the memory 103 monitored by the write memory monitoring unit 115. Specifically, the address on the memory where the lock variable 116 is arranged is stored.

  A value 203 stores a value to be monitored. Thereby, the write memory monitoring unit 115 determines whether or not the data stored at the address corresponding to the monitoring address 202 is the value stored in the value 203. Specifically, the write memory monitoring unit 115 monitors whether or not the lock variable 116 is “1”. Note that, in the device 101 that can simultaneously perform exclusive operations, for example, a value 203 such as “2” may be monitored.

  In the example illustrated in FIG. 2, the monitoring address 202 of the entry 206 is “0xAAAAAAAA”, and the value 203 is “1”. In this case, the write memory monitoring unit 115 monitors whether or not the data stored in the monitoring address 202 at “0xAAAAAAAA” is “1”.

  The call computing device 204 stores information for identifying the computing device that has instructed monitoring. In the example shown in FIG. 2, it can be seen that “arithmetic unit 1” is stored in the call arithmetic unit 204 of the entry 206.

  The clock state 205 stores information indicating the current operation state of the arithmetic device that has instructed monitoring. In the example shown in FIG. 2, it can be seen that the clock state 205 of the entry 206 is “clock stopped”.

  FIG. 3 is a sequence diagram illustrating processing when the computing devices 1 (105) and 2 (106) execute exclusive computations in the first embodiment of the present invention.

  First, since the value of the lock variable 116 is “0x1”, the lock variable 116 is not locked (state 301).

  Since the arithmetic device 2 (106) executes the operation protected by the lock variable 116, the lock acquisition is executed for the lock variable 116, and the lock acquisition is successful (step 306). As a result, the value of the lock variable 116 becomes “0x0”, and the lock variable 116 is locked (state 302).

  In the state described above, the arithmetic device 1 (105) executes lock acquisition for the lock variable 116 in order to execute the operation protected by the lock variable 116, but the value of the lock variable 116 is “0x0”. Therefore, the lock acquisition fails (step 307).

  The arithmetic device 1 (105) that has failed to acquire the lock transmits a change monitoring instruction that instructs the arithmetic device processing control unit 114 to monitor the value of the lock variable 116 without executing lock acquisition again ( Step 308).

  Receiving the change monitoring command, the arithmetic device processing control unit 114 creates an entry in the monitoring information table 131 and stores necessary information in the created entry. At this time, the monitoring information table 131 stores all the information of the monitoring space 201, the monitoring address 202, the value 203, the call calculation device 204, and the clock state 205. However, “clock supply” is stored in the clock state 205. The arithmetic device processing control unit 114 starts monitoring the memory access bus 107 based on the monitoring information table 131, and further issues a clock supply stop instruction to stop the clock supply to the arithmetic device 1 (105). It transmits to 113 (step 309).

  The clock 113 that has received the clock supply stop instruction stops the supply of the clock to the arithmetic unit 1 (105) (step 310). As a result, the arithmetic device 1 (105) enters a power saving state (state 305). Here, in consideration of recovery by restarting the clock supply, the supply of power to the arithmetic device 1 (105) is not stopped.

  The computing device 2 (106) finishes the computation protected by the lock variable 116, and releases the lock variable 116 (step 311). As a result, the value of the lock variable 116 becomes “0x1”, and the lock variable 116 is not locked (state 303).

  The arithmetic device processing control unit 114 detects that the lock has been released, that is, the value of the lock variable 116 has become “0x1” (step 312).

  In the unlock detection method, the write memory monitoring unit 115 monitors the address set in the access signal transmitted from the arithmetic unit 2 (106) to the memory 103, which flows through the memory access bus, and the address is the monitored address. If the address matches the monitoring address 202, it is possible to further determine whether or not the data corresponding to the address matches the value 203. If the data corresponding to the address matches the value 203, the arithmetic device processing control unit 114 determines that the lock has been released.

  Next, the write memory monitoring unit 115 that detects unlocking changes the clock state 205 of the monitoring information table 131 to “clock supply”, and based on the change, the clock control unit 132 starts clock supply to the clock 113. The time instruction is transmitted, and then the corresponding entry in the monitoring information table 131 is deleted (step 313).

  The clock 113 that has received the clock supply restart instruction restarts clock supply to the arithmetic unit 1 (105) (step 314). Thereby, the arithmetic device 1 (105) ends the power saving state and starts the operation again.

  The computing device 1 (105) that has resumed computation executes lock acquisition for the lock variable 116 and succeeds in obtaining the lock (step 315). As a result, the value of the lock variable 116 becomes “0x0”, and the lock variable 116 is locked again (state 304).

  As described above, according to the first embodiment, when the arithmetic device 1 (105) fails to acquire the lock, the arithmetic device 1 (105) transmits a monitoring command to the arithmetic device processing control unit 114 and releases the lock. Since the computing device 1 (105) is in the power saving state as in the state 305 until power is detected, the power consumption until the lock is released can be suppressed.

  It goes without saying that the first embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, in step 309, the arithmetic device processing control unit 114 has transmitted a clock supply stop instruction to the clock 113, but after the arithmetic device 1 (105) has transmitted a change monitoring instruction to the arithmetic device processing control unit 114, It may be a form in which the supply of the clock is stopped. Thus, the arithmetic device processing control unit 114 can be made simpler.

  In the first embodiment, the power saving state 305 is realized by stopping the clock supply. However, the clock speed is reduced, or the power supply of the arithmetic device 1 (105) is stopped. It may be a form to do. In the form of stopping the power supply, the arithmetic device processing control unit 114 includes a power control unit that controls the supply of power to the arithmetic devices 1 (105) and 2 (106) instead of the clock control unit 132.

  FIG. 4 is a block diagram illustrating a modification of the device configuration of the device including the microprocessor according to the first embodiment of this invention.

  In the example illustrated in FIG. 1, the microprocessor 102 including one arithmetic device processing control unit 114 has been described. However, as illustrated in FIG. 4, the arithmetic devices 1 (105) and 2 (106) perform arithmetic device processing control, respectively. The microprocessor 102 including the unit 114 may be used. Further, the arithmetic device may include the arithmetic device processing control unit 114. This facilitates modularization of the arithmetic device 1 (105) and the arithmetic device 2 (106). The connection and processing of the arithmetic device processing control unit 114, the arithmetic devices 1 (105) and 2 (106), and the clocks 112 and 113 in the device 101 as described above are those shown in FIGS. Is the same.

[Second Embodiment]
In the second embodiment of the present invention, an invention related to the above-described work control process executed exclusively will be described.

  A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 5 is a block diagram illustrating an example of a device configuration of a device including the microprocessor according to the second embodiment of this invention. Hereinafter, the difference from the first embodiment will be mainly described.

  In the device 101 shown in FIG. 5, an arithmetic device processing control unit 514 is connected to each of the arithmetic device 1 (105) and the arithmetic device 2 (106).

  The arithmetic device processing control unit 514 includes an execution calculation monitoring unit 503, a write memory monitoring unit 115, a monitoring information table 131, and a clock control unit 132. The write memory monitoring unit 115, the monitoring information table 131, and the clock control unit 132 have the same configuration as in the first embodiment.

  The execution calculation monitoring unit 503 reads the contents of the calculation executed by the calculation device 1 (105) and the calculation device 2 (106) connected to the calculation device processing control unit 514, and the calculation device The operations of 1 (105) and 2 (106) are monitored.

  In addition, the execution calculation monitoring unit 503 determines whether or not the contents of the calculations executed by the calculation devices 1 (105) and 2 (106) are in a certain pattern, so that the clocks 112 and 113 are clocked. Instruct the supply to stop.

  Here, for example, a waiting process of the arithmetic device 1 (105) in a state where the arithmetic device 2 (106) has succeeded in acquiring the lock can be considered as the fixed pattern. In the wait process, when the arithmetic device 2 (106) succeeds in acquiring the lock and the arithmetic device 1 (105) fails to acquire the lock, the arithmetic device 1 (105) monitors the memory access bus 107, A loop process that waits until the value of the lock variable 116 in the memory 103 reaches a specific value (in this case, “1”) is shown. The execution calculation monitoring unit 503 can determine whether or not the pattern is a fixed pattern by detecting the loop process.

  Compared to the first embodiment, the arithmetic device processing control unit 514 monitors the arithmetic devices 1 (105) and 2 (106) and detects that the operation being performed is a fixed pattern. The difference is that the clocks 112 and 113 are instructed to stop the clock supply.

  FIG. 6 is a sequence diagram illustrating a process when the arithmetic device executes an exclusive operation in the second embodiment of the present invention. Hereinafter, the difference from the first embodiment will be mainly described.

  When the arithmetic device 2 (106) succeeds in acquiring the lock (step 606), the arithmetic device 1 (105) fails to acquire the lock for the lock variable 116, and the value of the lock variable 116 is changed to “1”. A process of waiting for the process is executed (step 607).

  The arithmetic device processing control unit 514 that monitors the arithmetic device 1 (105) detects that the arithmetic device 1 (105) is executing the waiting process (step 608). The arithmetic device processing control unit 514 that has detected the waiting process creates an entry in the monitoring information table 131, stores information in the created entry, and the clock control unit 132 clocks the clock 113 based on the monitoring information table 131. A supply stop instruction is transmitted (step 609).

  Steps 610 to 615 and states 601 to 604 are the same as those in the first embodiment.

  Note that, in step 602, the arithmetic device processing control unit 514 may transmit a clock supply stop instruction to the clock 113 when it is detected that the loop processing surely occurs.

  As described above, according to the second embodiment of the present invention, the arithmetic device 1 (105) enters the power saving state as indicated by the state 605 according to the instruction from the arithmetic device processing control unit 514 that has detected the waiting process. , Can reduce power consumption. Further, it is not necessary for the arithmetic devices 1 (105) and 2 (106) to instruct a special command, and power consumption can be suppressed. Further, like the first embodiment of the present invention, the second embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof.

[Third Embodiment]
In the third embodiment of the present invention, an invention related to control processing for executing the above-described plurality of operations in parallel will be described.

  First, the prior art will be described.

  FIG. 13 is a sequence diagram for explaining processing of a microprocessor that executes a plurality of operations in parallel in the prior art.

  The device configuration of the device 101 is the same as that in FIG. Here, “U 1”, “U 2”, “U 3”, and “U 4” indicate types of operations, and “K” indicates initialization processing and operation switching processing. However, the operations “U1”, “U2”, “U3”, and “U4” are each divided into predetermined execution units, and the arithmetic devices 1 (105) and 2 (106) perform operations for each execution unit. Execute. As the predetermined execution unit, various execution units such as threads or tasks can be considered. A state 1301 to a state 1311 indicate states in which each calculation is executed in units of execution.

  In the following description, a case where an operation is performed in units of tasks will be described.

  First, the arithmetic device 1 (105) and the arithmetic device 2 (106) are initialized, and the scheduler 1101 is executed on the arithmetic device 1 (105). The scheduler 1101 executed on the arithmetic device 1 (105) initializes the arithmetic device 2 (106), and the scheduler 1101 is executed on the arithmetic device 2 (106). The scheduler 1101 executed on the arithmetic device 2 (106) refers to the work queue 122 and searches for an operation to be executed (step 1312).

Next, the scheduler 1101 executed on the computing device 1 (105) registers the computation “U1” in the work queue 122 (step 1313).
The scheduler 1101 executed on the arithmetic device 2 (106) acquires information related to the operation “U1” from the work queue 1122, and starts executing the operation “U1” (step 1314).

  The scheduler 1101 executed on the computing device 1 (105) registers the computations “U2”, “U3”, and “U4” in the work queue 1122 (step 1315).

  Next, the scheduler 1101 executed on the arithmetic device 1 (105) acquires information related to the operation “U2” from the work queue 1122, and starts executing the operation “U2” (step 1316).

  The scheduler 1101 executed on the arithmetic devices 1 (105) and 2 (106) pre-allocates the execution time of each acquired operation, and the arithmetic devices 1 (105) and 2 (106) When the assigned execution time has passed or the operation is paused or terminated, the execution of the operation is interrupted and the scheduler 1101 is called.

  The arithmetic device 2 (106) executing the operation “U1” interrupts the operation “U1” being executed and calls the scheduler 1101. The called scheduler 1101 stores the context information 1110 stored in the process information storage area 1118 of the memory 103 as the context information 1124 and stores the context information 1110 stored in the arithmetic unit 2 (106), which stores the verification result of the operation “U1”. The context information 1124 for “K” is read (step 1317). Furthermore, the scheduler 1101 executes initialization processing, saves the result of the operation “K” as the context information 1124 in the process information storage area 1118, acquires information about the operation “U3” from the work queue 1122, and executes the operation “U3”. "Is started (step 1318).

  Thereafter, the same processing is executed in steps 1319 to 1324.

  In the conventional processing, since the scheduler 1101 is read whenever the operation is switched, the arithmetic devices 1 (105) and 2 (106) execute the initialization process and the context information 1108 stores the result of the initialization process. There is a problem that the load of the saving process and the acquisition process of 1110 is large.

  Further, since exclusive control is required when the scheduler 1101 executed on each of the arithmetic devices 1 (105) and 2 (106) accesses the work queue 1122, there is a problem that overhead is increased. Further, although the sizes of the context information 1124 required by the operations “U1” to “U4” are different, there is a problem that all information must be saved and acquired in the conventional method.

  Next, a third embodiment of the present invention will be described with reference to FIGS.

  FIG. 7 is a block diagram illustrating an example of a device configuration of a device including the microprocessor according to the third embodiment of this invention. Hereinafter, the difference from the apparatus configuration of the conventional device in FIG. 11 will be mainly described.

  Compared with the device 101 of FIG. 11, in the device 101 according to the present invention, the arithmetic device 1 (105) and the arithmetic device 2 (106) include the clock 112 and the clock 113, respectively.

  In addition, the device 101 according to the present invention newly includes an arithmetic device processing control unit 714.

  The arithmetic device processing control unit 714 includes a write memory monitoring / scheduler unit 723, a clock control unit 732, and a memory (not shown). The write memory monitoring / scheduler unit 723 and the clock control unit 732 are connected to a memory (not shown) via a bus (not shown). The memory (not shown) includes an arithmetic device management table 716.

  The write memory monitoring / scheduler unit 723 monitors the writing to the memory 103 based on the arithmetic device management table 716 and the process management area 715 and performs arithmetic operations on the arithmetic devices 1 (105) and 2 (206). Allocation and calculation switching, process information, and work queue 722 are managed.

  The arithmetic device management table 716 stores information necessary for controlling the clocks of the arithmetic devices 1 (105) and 2 (106). The arithmetic device management table 716 is updated by the write memory monitoring / scheduler unit 723 and the clock control unit 732. The arithmetic device management table 716 is a fixed-length storage area having entries equal to the number of arithmetic devices provided in the microprocessor 102. Details will be described later with reference to FIG.

  The clock control unit 732 is the same as that in the first embodiment.

  Further, the device 101 according to the present invention includes a process management area 715 in the memory 103 separately from the main storage area 1126. The process management area 715 is an area for storing information on the operations executed by the arithmetic devices 1 (105) and 2 (106) and the results of the operations.

  The process management area 715 is referred to and updated by the write memory monitoring / scheduler unit 723. 11 and 13, the kernel memory area 1130 (OS) manages the process information storage area 1118 and the work queue 1122, but in the third embodiment, the arithmetic device processing control unit 714 includes: A process information storage area 1118 and a work queue 1122 are managed.

  Accordingly, the arithmetic device processing control unit 714 can manage each process, and the load on the arithmetic devices 1 (105) and 2 (106) can be reduced.

  The process management area 715 includes a process information storage area 1118 and a work queue 722.

  The process information storage area 1118 is the same as that shown in FIG.

  The work queue 722 is an area for storing a list of operations executed by the arithmetic devices 1 (105) and 2 (106). Details will be described later with reference to FIG.

  FIG. 8 is an explanatory diagram illustrating an example of the work queue 722 according to the third embodiment of this invention.

  The work queue 722 includes a process ID 801, a state 802, and an allocation calculation device 803. When the arithmetic devices 1 (105) and 2 (106) newly register the arithmetic in the arithmetic device processing control unit 714, an entry of the work queue 722 is created, and when the arithmetic operation of the corresponding entry is completed, The entry is deleted. In the example shown in FIG. 8, entries 806 to 809 are created.

  The process ID 801 stores an identifier for identifying an operation to be executed. In the example illustrated in FIG. 8, the process ID 801 of the entry 806 is “U1”, the process ID 801 of the entry 807 is “U2”, the process ID 801 of the entry 808 is “U3”, and the process of the entry 809 The ID 801 is “U4”.

  The state 802 stores information related to the state of calculation corresponding to the process ID 801. For example, the state 802 of the entry 806 stores “executed” indicating that the process has been executed. As described above, one operation is divided into predetermined execution units. When the state 802 is “executed”, this indicates that one of the execution units has been executed. Similarly, the state 802 of the entry 807 is “executing” and indicates that the operation is currently being executed. The state 802 of the entry 808 and the entry 809 is “waiting for execution” and indicates that it will be executed from now.

  Note that an operation whose state 802 is “executed” has one more execution than the “executing” entry in the state 802, and an operation whose state 802 is “waiting for execution” The number of executions of the operation is one less than that of the entry.

  FIG. 9 is an explanatory diagram illustrating an example of the arithmetic device management table 716 according to the third embodiment of this invention.

  The arithmetic device management table 716 includes an arithmetic device 901, a monitoring space 902, a monitoring address 903, a value 904, an execution task 905, an execution interruption time 906, and a clock state 907.

  The monitoring space 902, the monitoring address 903, the value 904, and the clock state 907 are the same as the monitoring address 202, the monitoring space 201, the value 203, and the clock state 205 of FIG.

The arithmetic device 901 stores an identifier for identifying the arithmetic device included in the device 101.
In the example illustrated in FIG. 9, the arithmetic device 901 of the entry 908 is “arithmetic device 1”, and the arithmetic device 901 of the entry 909 is “arithmetic device 2”.

  The execution task 905 stores information for identifying an operation being executed by an arithmetic device corresponding to the arithmetic device 901. Specifically, a process ID 801 indicating the operation being performed is stored. In the example illustrated in FIG. 9, the execution task 905 of the entry 908 is “U2”, and the execution task 905 of the entry 909 is “U1”.

  The execution interruption time 906 stores the end time of the execution time of the operation corresponding to the execution task 905. When the time has passed, arithmetic switching processing is executed in arithmetic devices 1 (105) and 2 (106). In the example illustrated in FIG. 9, the execution suspension time 906 of the entry 908 is “0x12345678”, and the execution suspension time 906 of the entry 909 is “0x1224567”. The time here is the time in the device. However, the present invention is not limited to this, and the time may be a time outside the device.

  FIG. 10 is a sequence diagram illustrating the processing of the microprocessor that executes a plurality of operations in parallel according to the third embodiment of the present invention. Hereinafter, the difference from FIG. 13 will be mainly described.

  First, the arithmetic device 1 (105) and the arithmetic device 2 (106) are initialized. The arithmetic device 1 (105) initializes the arithmetic device processing control unit 714 (step 1009), registers the operation “U1” in the initialized arithmetic device processing control unit 714, and the arithmetic device processing control unit 714 The registered operation “U1” is registered in the work queue 722 (step 1010). At this time, an entry is created in the arithmetic device management table 716. Specifically, “U1” is stored in the process ID 801, “waiting to execute” is stored in the state 802, and “unassigned” is stored in the assignment arithmetic device 803.

  Next, when the arithmetic device processing control unit 714 confirms that the execution task 905 of the arithmetic device management table 716 is not specified, and confirms that the arithmetic device 2 (106) is not performing an arithmetic operation, The computing device 2 (106) is initialized, and an execution instruction for the computation “U1” is transmitted to the initialized computing device 2 (106) (step 1012).

  Receiving the execution instruction, the arithmetic device 2 (106) executes the operation “U1” (state 1005). At this time, “in execution” is stored in the state 802 of the entry whose process ID 801 is “U1”, and “arithmetic unit 2” is stored in the allocation arithmetic unit 803.

  The arithmetic device 1 (105) registers the arithmetic operations “U2”, “U3”, and “U4” in the arithmetic device processing control unit 714 (step 1013).

  Arithmetic device 1 (105) that has registered all the arithmetic operations transmits a notification of completion of initialization processing and an instruction to start arithmetic processing to arithmetic device processing control unit 714 (step 1014).

  The arithmetic device processing control unit 714 transmits an execution instruction for the operation “U2” to the arithmetic device 1 (105) (step 1015), and the arithmetic device 1 (105) that has received the execution instruction performs an operation for the operation “U2”. Execute (state 1002).

  The arithmetic device processing control unit 714 refers to the execution interruption time 906 in the work queue 722 and transmits an execution instruction for the operation “U3” to cause the arithmetic device 2 to execute the next operation (step 1016). Receiving the execution instruction, the arithmetic device 2 (106) stores the operation result of the operation “U1” in the process management area 715 as context information 1124, and then acquires the information of the operation “U3” from the process management area 715. Then, the calculation “U3” is executed (state 1006).

  The arithmetic device processing control unit 714 refers to the execution interruption time 906 in the work queue 722 and transmits an execution instruction for the operation “U4” to cause the arithmetic device 1 to execute the next operation (step 1017). Receiving the execution instruction, the arithmetic device 2 (106) stores the operation result of the operation “U2” in the process management area 715 as context information 1124, and then acquires the information of the operation “U4” from the process management area 715. Then, the calculation “U4” is executed (state 1003).

  Thereafter, the same processing is executed in steps 1018 to 1020. That is, the arithmetic device processing control unit 714 refers to the arithmetic device management table 716 and the work queue 722 and transmits an operation execution instruction to the arithmetic devices 1 (105) and 2 (106). Receiving the operation execution instruction, the arithmetic devices 1 (105) and 2 (106) store the result of the operation executed before receiving the execution instruction as the context information 1124 in the process management area 715 and follow the execution instruction. Then, the information of the next calculation is acquired from the process management area 715, and the calculation is executed.

  As described above, according to the third embodiment of the present invention, when the operation to be executed is switched, the arithmetic devices 1 (105) and 2 (106) perform the initialization process and the operation to be executed next. It is not necessary to execute an operation such as determining the above, and the operation to be executed can be switched immediately. Further, since it is not necessary to perform the operation “K”, it is not necessary to read out and write out the context information 1124 related to the operation “K”, so that the operation efficiency of the operation devices 1 (105) and 2 (106) is improved. In addition, power consumption can be reduced.

  Note that the third embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, the arithmetic device processing control unit 714 may restore a part of context information necessary for the switching and execute the arithmetic operation when the arithmetic devices 1 (105) and 2 (106) perform the arithmetic operation. it can. The remaining context information that has not been restored can be restored by the arithmetic device processing control unit 714 in parallel with the execution of the arithmetic device. Also, when the arithmetic devices 1 (105) and 2 (106) require context information that has not been restored during the context information restoration process, the context information is restored or the context switch Until the operation is completed, the execution of the operation can be temporarily stopped, and the clock supply to the operation devices 1 (105) and 2 (106) can be stopped.

  Also, the arithmetic device processing control unit 714 can monitor the cotext information used by the arithmetic devices 1 (105) and 2 (106), and can save and restore only the context information being used.

It is a block diagram which shows an example of the apparatus structure of an apparatus provided with the microprocessor of the 1st Embodiment of this invention. It is explanatory drawing which shows an example of the monitoring information table of the 1st Embodiment of this invention. It is a sequence diagram explaining a process when the arithmetic devices 1 (105) and 2 (106) perform exclusive calculation in the 1st Embodiment of this invention. It is a block diagram which shows the modification of the apparatus structure of an apparatus provided with the microprocessor of the 1st Embodiment of this invention. It is a block diagram which shows an example of the apparatus structure of an apparatus provided with the microprocessor of the 2nd Embodiment of this invention. It is a sequence diagram explaining a process when a calculating device performs exclusive calculation in the 2nd Embodiment of this invention. It is a block diagram which shows an example of the apparatus structure of an apparatus provided with the microprocessor of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the work queue in the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the arithmetic unit management table of the 3rd Embodiment of this invention. It is a sequence diagram explaining the process of the microprocessor which performs several calculation in parallel in the 3rd Embodiment of this invention. It is a block diagram which shows the apparatus structure of the apparatus provided with the conventional microprocessor. It is a sequence diagram explaining a process when an exclusive calculation is performed in a prior art. It is a sequence diagram explaining the process of the microprocessor which performs several calculations in parallel in a prior art.

101 Device 102 Microprocessor 103 Memory 104 Change Monitoring Command Receiving Unit 105 Arithmetic Device 1
106 Arithmetic unit 2
107 memory access bus 112 clock 113 clock 114 arithmetic device processing control unit 115 write memory monitoring unit 116 lock variable 131 monitoring information table 132 clock control unit 305 power saving state 503 execution arithmetic monitoring unit 514 arithmetic device processing control unit 605 power saving state 714 Processing unit processing control unit 715 Processing management area 716 Processing unit management table 722 Work queue 723 Write memory monitoring / scheduler unit 1001 Initialization execution time 1002 to 1008 Operation “U2” to “U4” execution time 1101 Scheduler 1108 Context information 1110 Context information 1118 Process information storage area 1122 Work queue 1124 Context information 1126 Main storage area 1128 Process memory area 1130 Kernel memory areas 1301 and 13 03, 1305, 1306, 1308, 1310 Scheduler execution time 1302, 1304, 1307, 1309, 1311 Operation “U2” to “U4” execution time

Claims (24)

An arithmetic control device provided in a device including a microprocessor and a memory connected to the microprocessor,
The microprocessor includes a plurality of arithmetic units,
The memory includes a shared storage area that can be read and written by the plurality of arithmetic units,
The arithmetic and control unit is
A write detection unit for detecting whether or not writing to the shared storage area is possible;
An arithmetic control apparatus, wherein when the arithmetic unit cannot write in the shared storage area, the arithmetic unit monitors the shared storage area and stops the operation of the arithmetic unit. A receiving unit for receiving a command transmitted from the arithmetic unit;
The arithmetic control device according to claim 1, wherein monitoring of the shared storage area is started based on a monitoring instruction that requests monitoring of the shared storage area transmitted from the arithmetic unit. An execution calculation detection unit for detecting a calculation executed by the calculation unit;
When the execution calculation detection unit of the calculation control device detects that the calculation unit has failed to write to the shared storage area, the calculation control device starts monitoring the shared storage area. The arithmetic and control unit according to claim 1. A clock control unit for controlling supply of a clock to the arithmetic unit;
4. The arithmetic control device according to claim 2, wherein the operation of the arithmetic unit is stopped by stopping supply of a clock to the arithmetic unit. 5. A power control unit that controls supply of power to the arithmetic unit;
The arithmetic control device according to claim 2, wherein the operation of the arithmetic unit is stopped by stopping the supply of power to the arithmetic unit. An arithmetic control device provided in a device including a microprocessor and a memory connected to the microprocessor,
The microprocessor includes a plurality of arithmetic units,
The memory includes a process management area for storing information on processing executed by the arithmetic unit and a result of the processing.
In the process management area, context information including a result of the processing is stored,
The arithmetic and control unit is
A scheduler unit that sets the allocation of the process to be executed by the arithmetic unit and the execution time of the process;
Transmitting an execution instruction of the first process to the arithmetic unit;
An arithmetic control apparatus, wherein an execution command for a second process to be executed next is transmitted to the arithmetic unit before the end of the first process. When the calculation unit switches from the first process to the second process, the calculation unit reads partial context information that is part of the context information related to the second process,
The calculation according to claim 6, wherein when the calculation unit is executing the second calculation based on the read partial context information, the calculation unit reads the remaining context information. Control device. An access detection unit that detects that the calculation unit has accessed uncompleted context information, which is the context information that has not been read to the calculation unit;
When the operation unit detects that the incomplete context information has been accessed, the operation of the operation unit is stopped,
The arithmetic control device according to claim 7, wherein after the arithmetic unit reads all the incomplete context information, the operation of the arithmetic unit is resumed. A clock control unit for controlling supply of a clock to the arithmetic unit;
The arithmetic control device according to claim 8, wherein the operation of the arithmetic unit is stopped by stopping the supply of a clock to the arithmetic unit. A power control unit that controls supply of power to the arithmetic unit;
The calculation control device according to claim 8, wherein the operation of the calculation unit is stopped by stopping the supply of power to the calculation unit. Of the context information, comprising an access information extraction unit that extracts information that the operation unit is actually accessing,
When the arithmetic unit switches from the first process to the second process, only the context information that is actually accessed among the context information related to the first process is stored in the process management area,
When the context information related to the first process is read from the process management area in order for the calculation unit to execute the first process, the calculation unit reads the actually accessed context information.
The arithmetic control device according to claim 6, wherein the arithmetic unit executes initialization when there is access to the context information that is not actually read. A microprocessor that is connected to a memory and performs arithmetic processing,
The microprocessor includes a plurality of calculation units and a calculation control unit,
The memory includes a shared storage area that can be read and written by the plurality of arithmetic units,
The arithmetic control unit includes a writing detection means for detecting whether or not writing to the shared storage area is possible,
The microprocessor is characterized in that, when the arithmetic unit cannot write to the shared storage area, the arithmetic control unit monitors the shared storage area and stops the operation of the arithmetic unit. The arithmetic control unit is
Comprising command receiving means for receiving a command transmitted from the arithmetic unit;
The microprocessor according to claim 12, wherein monitoring of the shared storage area is started based on a monitoring instruction that requests monitoring of the shared storage area transmitted from the arithmetic unit. The arithmetic control unit is
An execution calculation detecting means for detecting a calculation executed by the calculation unit;
When the execution calculation detection unit of the calculation control unit detects that the calculation unit has failed to write to the shared storage area, the calculation control unit starts monitoring the shared storage area. The microprocessor according to claim 12. The arithmetic control unit is
Clock control means for controlling the supply of the clock to the arithmetic unit;
15. The microprocessor according to claim 13, wherein the operation of the arithmetic unit is stopped by stopping the supply of the clock to the arithmetic unit. The arithmetic control unit is
Power control means for controlling the supply of power to the arithmetic unit,
15. The microprocessor according to claim 13, wherein the operation of the arithmetic unit is stopped by stopping the supply of power to the arithmetic unit. A microprocessor that is connected to a memory and performs arithmetic processing,
The microprocessor includes at least one calculation unit and a calculation control unit,
The memory includes a process management area for storing information on processing executed by the arithmetic unit and a result of the processing.
In the process management area, context information including a result of the processing is stored,
The arithmetic control unit is
Scheduler means for setting the allocation of the process to be executed by the arithmetic unit and the execution time of the process;
Transmitting an execution instruction of the first process to the arithmetic unit;
A microprocessor that transmits an execution instruction of a second process to be executed next before the end of the first process to the arithmetic unit. The arithmetic control unit is
When the calculation unit switches from the first process to the second process, the calculation unit reads partial context information that is part of the context information related to the second process,
18. The microprocessor according to claim 17, wherein when the calculation unit is executing the second calculation based on the read partial context information, the calculation unit reads the remaining context information. . The arithmetic control unit is
An access detecting means for detecting that the computing unit has accessed uncompleted context information, which is the context information that has not been read to the computing unit;
When the operation unit detects that the incomplete context information has been accessed, the operation of the operation unit is stopped,
19. The microprocessor according to claim 18, wherein after the arithmetic unit reads all the incomplete context information, operation of the arithmetic unit is resumed. The arithmetic control unit is
Clock control means for controlling the supply of the clock to the arithmetic unit;
The microprocessor according to claim 19, wherein the operation of the arithmetic unit is stopped by stopping the supply of a clock to the arithmetic unit. The arithmetic control unit is
Power control means for controlling the supply of power to the arithmetic unit,
The microprocessor according to claim 19, wherein the operation of the arithmetic unit is stopped by stopping the supply of power to the arithmetic unit. The calculation control unit includes an access information extraction unit that extracts information that the calculation unit actually accesses from the context information,
The microprocessor is
When the arithmetic unit switches from the first process to the second process, only the context information that is actually accessed among the context information related to the first process is stored in the process management area,
When the context information related to the first process is read from the process management area in order for the calculation unit to execute the first process, the calculation unit reads the actually accessed context information.
18. The microprocessor according to claim 17, wherein initialization is performed when there is access to the context information that has not been actually read. A device comprising a microprocessor and a memory connected to the microprocessor,
An apparatus comprising the arithmetic and control unit according to claim 1. A device comprising a microprocessor and a memory connected to the microprocessor,
The said microprocessor is provided with the calculation control part as described in any one of Claim 12 to 22. The apparatus characterized by the above-mentioned.

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