JP2010170206A - Information processor, initialization request mechanism, and television set - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an initialization request mechanism for notifying a nonvolatile circuit about presence of a volatile circuit needing initialization, in a system with the nonvolatile circuit and volatile circuit coexisting. <P>SOLUTION: This initialization request mechanism includes a power detection part and a register. When the power detection part detects that a power supply driving a peripheral circuit comprising the volatile circuit turns off, the power detection part records a register value indicating that the power supply turns off into the register. When the register value indicating that at least one power supply turns off is recorded in the register, the initialization request mechanism transmits an initialization request interrupt indicating that the initialization of the peripheral circuit is needed to a processor configured by the nonvolatile circuit. When the processor receives the initialization request interrupt, the processor starts the peripheral circuit in accordance with an execution state of a process held by the processor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an initialization request mechanism, and a television receiver, and more particularly to an information processing apparatus, an initialization request mechanism, and a television receiver in which a nonvolatile circuit and a volatile circuit are mixed.

  There are DRAM, SRAM, and flash memory as memory constituting the storage device, but these memories have advantages and disadvantages, respectively. That is, DRAM has a large capacity but is volatile. SRAM has high speed and low power consumption but small capacity. Flash memory is non-volatile but slow. In recent years, universal memories having the advantages of these memories have been devised. The universal memory has a large capacity of DRAM, a high speed power saving performance of SRAM, and a non-volatile property of flash memory.

  By applying this universal memory to the main storage device of the computer system, the main storage device can maintain the execution state of the process even when the power is turned off, and after the power is turned on, The operation can be resumed based on the execution state of the retained process. Therefore, the power source that drives the main storage device may be turned on and off at short intervals. As a result, the computer system can significantly reduce power consumption by turning off the power supply while the main storage device does not need to operate.

  Furthermore, when the universal memory is applied to the internal register of the computer system, the internal register can hold the process execution state even when the power is turned off. In addition, after the power is turned on again, the internal register can resume its operation from the held execution state of the process. Hereinafter, a circuit in which such an internal register is nonvolatile is referred to as a nonvolatile circuit. A circuit in which the internal register is volatile is called a volatile circuit.

There is also a computer that initializes only peripheral circuits by a program without initializing data stored in an internal register of the CPU (see, for example, Patent Document 1).
JP-A-9-311849

  In a system in which a CPU composed of a nonvolatile circuit and a peripheral circuit composed of a volatile circuit coexist, when the system is turned off and then turned on again, the CPU that is a nonvolatile circuit Without recognizing that the power has been turned off, the operation is resumed from the process execution state held when the power was turned off. On the other hand, the peripheral circuit, which is a volatile circuit, loses the execution state of the process when the power is turned off when the power is turned on again after the power is turned off. Resume operation.

  Therefore, there is a mismatch between the execution state of the CPU process and the execution state of the peripheral circuit process, and there is a problem that the CPU cannot operate the peripheral circuit appropriately. In order to match the execution state of the process of the CPU and the execution state of the process of the peripheral circuit, when the power is turned on, the CPU properly initializes the peripheral circuit and changes the execution state of the process of the peripheral circuit. It must be set to suit the execution state of the process held by the CPU.

  Depending on the technique described in Patent Document 1, the CPU cannot properly initialize the peripheral circuit, which is a volatile circuit, when the power is turned on.

  The present invention has been made in view of the above-described problems, and an information processing apparatus capable of matching process execution states in a nonvolatile circuit and a volatile circuit when the nonvolatile circuit and the volatile circuit coexist, and initialization An object is to provide a request mechanism and a television receiver.

  A typical example of the present invention is as follows. That is, an information processing apparatus including a nonvolatile circuit in which an internal register is nonvolatile, one or more volatile circuits in which an internal register is volatile, and an initialization request mechanism, wherein the initialization request mechanism includes: One or more power detection units that detect that the power source that drives the volatile circuit is turned off, and an initialization request register that records that the power source is turned off. When detecting that the power is turned off, the first information indicating that the power is turned off is recorded in the initialization request register, and the initialization request mechanism stores at least one or more in the initial request register. When the first information is recorded, the nonvolatile circuit notifies the nonvolatile circuit that the volatile circuit needs to be initialized. When the nonvolatile circuit receives the notification from the initialization request mechanism, In accordance with the execution state internal registers of the outgoing circuits it is holding, setting the internal registers of the volatile circuit, characterized in that activating the volatile circuit.

  According to an embodiment of the present invention, when a nonvolatile circuit and a volatile circuit are mixed, the execution states of processes in the nonvolatile circuit and the volatile circuit can be matched.

<Embodiment 1>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The first embodiment described below is one of the embodiments of the present invention and does not limit the present invention.

  FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to the first embodiment of this invention.

  The information processing apparatus 100 according to the first embodiment includes a CPU 110, an initialization request mechanism 120, a peripheral circuit 130, and a memory 140.

  The CPU 110 is a processor whose internal register is configured by a nonvolatile memory. Here, the non-volatile memory is, for example, an MRAM (Magnetorative Random Access Memory). The CPU 110 is a processor that reads various programs stored in the memory 140 and executes the read programs. The memory 140 stores an initialization request interrupt handler 141 in addition to various programs executed by the CPU 110.

  The CPU 110 receives the initialization request interrupt 123 from the initialization request mechanism 120. Further, the CPU 110 receives the initialization request register value 124 from the initialization request mechanism 120. Further, the CPU 110 transmits initialization control information 111 to the peripheral circuit 130.

  When the CPU 110 receives the initialization request interrupt 123, the CPU 110 reads the initialization request interrupt handler 141 stored in the memory 140, and executes the read initialization request interrupt handler 141. The initialization request interrupt handler 141 is a program executed by the CPU 110 and initializes the peripheral circuit 130 based on the initialization control information 111. Further, the initialization request interrupt handler 141 resets the bit register 129 (FIG. 3 described later) of the power supply detection unit 122 by a reset input.

  The initialization request mechanism 120 includes an initialization request register 121 including a plurality of bit registers, and a power supply detection unit 122. When the information processing apparatus 100 includes a plurality of peripheral circuits (peripheral devices) 130 and each peripheral circuit 130 is driven by a plurality of power supplies, the initialization request mechanism 120 detects the states of the plurality of power supplies. In order to do so, a plurality of power source detection units 122 may be provided.

  Each bit register 125 (FIG. 2 described later) of the initialization request register 121 is associated with a peripheral circuit 130 connected thereto. Each bit register 125 may be associated with a power source (detected power source) 101 that drives the peripheral circuit 130. The initialization request register 121 receives the initialization request register value 132 output from the power supply detection unit 122 and records the received register value in the corresponding bit register 125.

  When the peripheral circuit 130 includes the power supply detection unit 122, the peripheral circuit 130 may transmit the initialization request register value 131 to the initialization request register 121. In this case, the initialization request register 121 may receive the initialization request register value 131 output from the peripheral circuit 130 and record the received register value in the bit register 125 corresponding to the peripheral circuit 130.

  The initialization request register 121 outputs an initialization request interrupt 123 and an initialization request register value 124 to the CPU 110.

  Details of the initialization request register 121 will be described later with reference to FIG.

  When detecting that the detected power source 101 (FIG. 3 described later) is turned off, the power source detection unit 122 outputs an initialization request register value 132. The initialization request register 121 records the received initialization request register value 132 in the corresponding bit register 125. The detailed description of the power supply detection unit 122 will be described later with reference to FIG.

  The peripheral circuit 130 is driven by the detected power source 101. When the CPU 110 receives the initialization request interrupt 123 output from the initialization request register 121, the CPU 110 executes the initialization request interrupt handler 141 and transmits the initialization control information 111 to the peripheral circuit 130. Based on the initialization control information 111, the CPU 110 initializes the peripheral circuit 130 so as to match the process execution state of the CPU 110.

  The peripheral circuit 130 is a volatile circuit included in the information processing apparatus 100 and includes a CPU (not shown). The peripheral circuit 130 is, for example, a graphics circuit having a display function.

  As a modification of the first embodiment, the CPU 110 may include an initialization request mechanism 120. Further, the CPU 110 that is a non-volatile circuit may initialize a CPU that is a volatile circuit different from the CPU 110.

  The configuration of the initialization request mechanism 120 will be described below. The initialization request mechanism 120 includes an initialization request register 121 and a power supply detection unit 122. The initialization request register 121 and the power supply detection unit 122 will be described with reference to FIGS. 2 and 3, respectively.

  FIG. 2 is a block diagram showing the configuration of the initialization request register according to the first embodiment of the present invention.

  The initialization request register 121 according to the first embodiment includes a plurality of bit registers 125, a mask register 126, and an initialization request interrupt output unit 127. The bit register 125 and the mask register 126 are nonvolatile memories.

  The initialization request register 121 includes, for example, 32 bit registers 125-1 to 125-32. Each bit register 125 records a 1-bit value. Each bit register 125 is connected to each power supply (detected power supply) 101 for driving each peripheral circuit 130 connected to the initialization request mechanism 120 or a plurality of peripheral circuits 130 connected to the initialization request mechanism 120. It is associated.

  Each bit register 125 transmits the register value recorded for each clock to the CPU 110 as the initialization request register value 124. Each bit register 125 outputs the register value recorded for each clock to the corresponding mask register 126.

  The mask register 126 includes, for example, 32 mask registers 126-1 to 126-32 respectively corresponding to the 32 bit registers 125-1 to 125-32 described above. The mask register 126 is a register for identifying the peripheral circuit 130 connected to the initialization request mechanism 120 or the power source (detected power source) 101 that drives the peripheral circuit 130.

  For example, when the two connected peripheral circuits 130-1 and 130-2 are associated with the bit registers 125-1 and 125-2, respectively, the mask registers 126-1 and 126-2 have “1”. Is set. Even when the peripheral circuits 130-1 and 130-2 are driven by the same power supply 101, the initialization request register value 132 output by the power supply detection unit 122 is stored in the bit registers 125-1 and 125-2. Recorded in each. Thereby, the CPU 110 can recognize that the peripheral circuits 130-1 and 130-2 need to be initialized.

  If the connected peripheral circuit 130 is not changed, the manufacturer or the like may set the register value of the mask register 126 at the time of system setting. When the connected peripheral circuit 130 is dynamically changed, the CPU 110 may recognize the connection of the peripheral circuit 130 and set the register value of the mask register 126 when the system is activated.

  The mask register 126 calculates a logical product of the register value recorded in each bit register of the mask register 126 and the register value recorded in each corresponding bit register 125, and initializes each calculated logical value. The request is output to the request interrupt output unit 127. The initialization request interrupt output unit 127 calculates a logical sum of the 32 register values input from the mask register 126, and transmits an initialization request interrupt 123 to the CPU 110 based on the calculated logic value.

  For example, when the register value of the bit register 125-N is “1” and the register value of the corresponding mask register 126-N is “1”, the mask register 126-N sets the initialization request allocation. “1” is output to the embedded output unit 127. When at least one of the bit register 125-N and the mask register 126-N is “0”, the mask register 126-N outputs “0”.

  When all the logical values input to the initialization request interrupt output unit 127 are “0”, the initialization request register 121 does not transmit the initialization request interrupt 123 to the CPU 110. On the other hand, when at least one of the logical values input to the initialization request interrupt output unit 127 is “1”, that is, when at least one power supply 101 is turned off, initialization is performed. The request register 121 transmits an initialization request interrupt 123 to the CPU 110.

  FIG. 3 is a block diagram illustrating a logical configuration of the power supply detection unit according to the first embodiment of this invention.

  The power supply detection unit 122 detects the power supply state of the power supply (detected power supply) 101 that drives the peripheral circuit 130.

  The power supply detection unit 122 rewrites the value of the internal bit register 129 according to the detected power supply state. When the detected power supply 101 is turned off, the power detection unit 122 records “1” in the bit register 129 and records “1” until the reset input becomes active. Further, the power supply detection unit 122 records “0” in the bit register 125 when the reset input becomes active.

  For example, a resistor R3 (for example, 80 kΩ) and a resistor R4 (for example, 250 kΩ) are connected between the detected power supply 101 and the ground, and the potential between the resistor R3 and the resistor R4 is a power supply state to the power supply detection unit 122. In the case of an input, if the detected power supply 101 is turned on at 3.3V, the power supply state input potential when the detected power supply 101 is turned on is 2.5V.

  Hereinafter, the operation of the power supply detection unit 122 will be described. When the detected potential is 2.5 V, the power supply detection unit 122 sets the power supply state input to “1”. When the detected potential is 0 V, that is, when the detected power supply 101 is off, the power supply detection unit 122 sets the power supply state input to “0”.

  The power detection unit 122 calculates a logical sum of the logical negation of the power state input and the output of the bit register 129, and inputs the logical value of the calculated logical sum 128 to the bit register 129.

  That is, when the detected power supply 101 is turned off and the power supply state input is changed from “1” to “0”, the power supply detection unit 122 performs a logical negation “1” of the power supply state input “0” and the bit. The logical sum with the value (“1” or “0”) output from the register 129 is calculated, and the calculated logical value, that is, “1” is input to the bit register 129. Therefore, the bit register 129 of the power supply detection unit 122 outputs “1”. Note that after the detected power supply 101 is turned off, the register value of the bit register 129 does not become “0” unless a reset input is input to the bit register 129 by the initialization request interrupt handler 141.

  Therefore, even when the detected power supply 101 is turned on again after the detected power supply 101 is turned off and the power supply state input is changed from “0” to “1”, the logical negation of the power supply state input “1” Since the logical sum of “0” and “1” recorded in the bit register 129 is calculated, the logical value recorded in the bit register 129 remains “1”.

  That is, once the power supply detection unit 122 detects that the detected power supply 101 is turned off, “1” is set as the initialization request register value 132 until the value of the bit register 129 is reset to “0” by the reset input. Continue to output.

  After the detected power supply 101 is turned off, the detected power supply 101 is turned on again, and the power supply state input is changed from “0” to “1”, that is, the logical negation of the power supply state input is changed from “1” to “0”. When the bit register 129 becomes “0” by reset input, the power supply detection unit 122 outputs the register value “0”.

  The power supply detection unit 122 records the logical value input at the clock timing in the bit register 129 and outputs the recorded register value until the next clock timing.

  FIG. 4 is a sequence diagram illustrating processing of the initialization request according to the first embodiment of this invention.

  When detecting that the detected power supply 101 is turned off, the power supply detection unit 122 outputs the register value “1” of the bit register 129 as the initialization request register value 132. The initialization request register 121 receives the initialization request register value 132 from the power supply detection unit 122. The initialization request register 121 records the register value “1” output by the power supply detection unit 122 in the corresponding bit register 125.

  When the detected power supply 101 is turned on, the CPU 110, the peripheral circuit 130 (and the initialization request mechanism 120) driven by the detected power supply 101 resume operation. Note that the nonvolatile CPU 110 holds the process execution state when the power is turned off when the power is turned on again. On the other hand, the volatile peripheral circuit 130 does not hold the process execution state when the power is turned off.

  After the detected power source 101 is turned on, the initialization request register 121 determines that the initialization request interrupt 123 and the initialization request are based on the fact that “1” is recorded in at least one bit register 125. The register value 124 is transmitted to the CPU 110.

  When the CPU 110 receives the initialization request interrupt 123, the CPU 110 executes the initialization request interrupt handler 141 and transmits the initialization control information 111 to the peripheral circuit 130. The CPU 110 identifies the peripheral circuit 130 that is the transmission destination of the initialization control information 111 based on the initialization request register value 124.

  The peripheral circuit 130 receives the initialization control information 111 from the CPU 110. The CPU 110 initializes the internal register of the peripheral circuit 130 based on the initialization control information 111. Here, the initialization means that the CPU 110 sets the internal register of the peripheral circuit 130 so that the peripheral circuit 130 resumes the operation based on the process execution state held when the power is turned off. It is. By this initialization, the CPU 110 can match the sequence of program execution between the CPU 110 and the peripheral circuit 130.

  After the initialization process is completed, the peripheral circuit 130 notifies the CPU 110 that the initialization is complete. When the CPU 110 receives the notification of initialization completion, the CPU 110 resets the corresponding bit register 125 to “0” and ends the execution of the initialization request interrupt handler 141. The CPU 110 activates a reset input to the power supply detection unit 122 when resetting the bit register 125. When the power detection unit 122 receives a reset input from the CPU 110, the power detection unit 122 resets the bit register 129 to “0”.

  As described above, according to the first embodiment, in a system in which nonvolatile circuits and volatile circuits are mixed, the initialization request mechanism needs to be initialized when the power is turned off and turned on again. It is possible to notify the nonvolatile circuit that there is a volatile circuit.

<Embodiment 2>
Hereinafter, a second embodiment of the present invention will be described with reference to FIG.

  FIG. 5 is a block diagram showing the configuration of the power supply detection unit according to the second embodiment of the present invention.

  The power detection unit 122 of the second embodiment is different from the power detection unit 122 of the first embodiment shown in FIG. 2 in that it includes a capacitor C1 and a diode D1. The power source detection unit driving power source 102 may be the same as the power source (detected power source) 101 that drives the peripheral circuit 130.

  The power supply detection unit 122 can continue the operation for a certain period of time by the electric charge accumulated in the capacitor C1 even when the power supply detection unit drive power supply 102 is turned off. The diode D1 prevents the electric charge accumulated by the capacitor C1 from flowing to the power source detection unit driving power source 102 side.

  For example, when the detected power source 101 is the same as the power source detection unit driving power source 102, the detected power source 101 is turned off simultaneously with the power source detection unit driving power source 102. When the detected power source 101 is turned off, the power source detection unit 122 records “1” in the bit register 129 and outputs the recorded register value as the initialization request register value 132. In this case, the power source detection unit driving power source 102 is also turned off at the same time, but the power source detection unit 122 is driven by the charge accumulated in the capacitor C1.

  In addition, although the power supply detection part 122 of 1st Embodiment is also provided with the power supply detection part drive power supply 102, the power supply detection part drive power supply 102 is abbreviate | omitted in FIG.

  As described above, according to the second embodiment, the power supply detection unit can continue to operate for a certain period of time due to the charge accumulated in the capacitor even when the power supply detection unit drive power supply is turned off. it can. Further, similar to the effect of the first embodiment, the initialization request mechanism may notify the nonvolatile circuit that there is a volatile circuit that needs to be initialized when the drive power is turned off and turned on again. it can.

<Embodiment 3>
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, the initialization request mechanism of the first embodiment is applied to a television receiver. The television receiver of the third embodiment realizes power saving operation.

  FIG. 6 is a block diagram showing a configuration of a television receiver according to the third embodiment of the present invention.

  The television receiver 600 includes an antenna 610, a tuner 601, a network interface 605, a decoder 602, a panel 604, a video output unit 603, a memory 606, a CPU 110, an initialization request mechanism 120, and a timer 607. Each part is connected by an internal signal line.

  The antenna 610 receives broadcast radio waves. The tuner 601 receives the encoded video data via the antenna 610. The decoder 602 decodes the encoded video data output from the tuner 601 or the network interface 605 and outputs the video data. The video output unit 603 receives the video data output from the decoder 602 and outputs the video data to the panel 604. The panel 604 is a display unit using a liquid crystal or the like that displays the video data output from the video output unit 603.

  The network interface 605 receives the encoded video data via the network 620. The memory 606 records the encoded video data output from the tuner 601 or the network interface 605. The CPU 110 reads the encoded video data from the memory 606 and outputs the read video data to the decoder 602. When detecting that the decoder 602 is powered off, the initialization request mechanism 120 notifies the CPU 110 of an initialization request interrupt 123. The timer 607 turns on the power of the CPU 110 and the decoder 602 when a set time has elapsed.

  In the third embodiment, the CPU 110 and the initialization request mechanism 120 are nonvolatile circuits, and the decoder 602 is a volatile circuit. The decoder 602 is initialized by the CPU 110 in the peripheral circuit 130 in the first embodiment.

  FIG. 7 is a flowchart showing the power saving operation of the television receiver according to the third embodiment of the present invention.

  The CPU 110 reads the video data stored in the memory 606 and outputs the read video data to the decoder 602. Here, for example, when the video data format is MPEG-2, the decoder 602 decodes the video data read from the memory 606 by the CPU 110 in GOP (Group Of Picture) units. One GOP includes 15 frames.

  Conventionally, the CPU 110 reads out one frame of video data from the memory 606 every 1/30 seconds and outputs the read video data to the decoder 602. In the third embodiment, since the CPU 110 is a non-volatile circuit, the CPU 110 can resume operation from the process execution state when the power is turned off even after the power is turned off. Therefore, the power may be turned off while the CPU 110 does not execute the video data input / output process. For example, the CPU 110 may not operate until video data for 1 GOP sufficient for decoding is stored in the memory 606 (for example, 0.5 seconds). That is, for example, the CPU 110 may execute the video data input / output process only once every 0.5 seconds. Thereby, the television receiver 600 can reduce the power consumed by the CPU 110. Note that since the decoder 602 which is a peripheral circuit is a volatile circuit, the operation starts from the initial state when the power is turned on after the power is turned off. Therefore, the CPU 110 initializes the decoder 602 based on the initialization request interrupt from the initialization request mechanism 120.

  The power saving operation of the television receiver 600 will be described below.

  In the power saving operation of the television receiver 600, the initialization request mechanism 120 monitors the power supply of the decoder 602, and when detecting the power off (711), notifies the CPU 110 of the initialization request interrupt 123 (712).

  The CPU 110 is activated after the power is turned on (721). Next, the CPU 110 determines whether or not the initialization request interrupt 123 has been notified from the initialization request mechanism 120 (722).

  If it is determined in step 722 that the initialization request interrupt 123 has been notified, the CPU 110 initializes the decoder 602 that is a peripheral circuit (723). After step 723, the CPU 110 proceeds to step 724.

  On the other hand, if it is determined in step 722 that the initialization request interrupt 123 has not been notified, the CPU 110 next determines whether video data having a size sufficient for decoding is stored in the memory 606. Is determined (724). Here, the video data having a size sufficient for decoding is, for example, video data for 1 GOP.

  If it is determined in step 724 that video data of sufficient size is stored, the CPU 110 reads the video data from the memory 606 (725). Next, the CPU 110 decodes the read video data by the decoder 602 (726), inputs the decoded video data to the video output unit 603, and displays the video data on the panel 604 (727). The CPU 110 repeats the processing from step 724 to step 727 until the video data stored in the memory 606 is encoded.

  On the other hand, if it is determined in step 724 that video data of sufficient size is not stored, the CPU 110 sets a standby time in the timer 730 (728). After setting the standby time, the CPU 110 turns off the power of the CPU 110 and the decoder 602 (729).

  The timer 607 waits until the standby time is set by the CPU 110 (731). When the standby time is set by the CPU 110, the timer 607 measures the time and determines whether or not the set standby time has elapsed (732). Here, the waiting time set in the timer 607 is, for example, the time until video data (1 GOP, 15 frames) of a size sufficient for decoding is stored in the memory 606 (ie, 0.5 seconds). It is.

  If it is determined in step 732 that the standby time has elapsed, the timer 607 turns on the power source for driving the CPU 110 and the decoder 602 (733). After step 733, the timer 607 returns to the process of step 731 and waits until the standby time is set by the CPU 110.

  As described above, according to the third embodiment, similar to the effect of the first embodiment, the initialization request mechanism needs to be initialized when the drive power supply is turned off and turned on again. The non-volatile circuit (CPU) can be notified that there is a volatile circuit (decoder). As a result, the television receiver can turn off the power until the necessary video data is received, and the power consumed by the CPU can be reduced.

It is a block diagram which shows the structure of the information processing apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the initialization request register of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the power supply detection part of the 1st Embodiment of this invention. It is a sequence diagram which shows the process of the initialization request | requirement of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the power supply detection part of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the television receiver of the 3rd Embodiment of this invention. It is a flowchart which shows the power saving operation | movement of the television receiver of the 3rd Embodiment of this invention.

100 Information processing apparatus 101 Power supply 110 CPU
111 Initialization Control Information 120 Initialization Request Mechanism 121 Initialization Request Register 122 Power Supply Detection Unit 123 Initialization Request Interrupt 124 Initialization Request Register Value 125 Bit Register 126 Mask Register 127 Initialization Request Interrupt Output Unit 128 OR 129 Bit Register 130 Peripheral circuit 131 Initialization request register value 132 Initialization request register value 140 Memory 141 Initialization request interrupt handler 600 Television receiver 601 Tuner 602 Decoder 603 Video output unit 604 Panel 605 Network interface 606 Memory 607 Timer 610 Antenna 620 Network

Claims (12)

An information processing apparatus including a nonvolatile circuit in which an internal register is nonvolatile, one or more volatile circuits in which the internal register is volatile, and an initialization request mechanism,
The initialization request mechanism includes one or more power detection units that detect that a power source that drives the volatile circuit is turned off, and an initialization request register that records that the power source is turned off. ,
The power detection unit, when detecting that the power is turned off, records first information indicating that the power is turned off in the initialization request register,
The initialization request mechanism notifies the nonvolatile circuit that the volatile circuit needs to be initialized when at least one or more pieces of the first information are recorded in the initial request register.
The nonvolatile circuit is
When the notification is received from the initialization request mechanism, the internal register of the volatile circuit is set according to the execution state of the process held in the internal register of the nonvolatile circuit,
An information processing apparatus, wherein the volatile circuit is activated after the internal register is set. The initialization request register includes one or more first bit registers.
Each first bit register is associated with the volatile circuit;
The power detection unit is
Monitoring the state of the power supply;
If it is detected that the power supply is turned off, the first information is recorded in the first bit register associated with the volatile circuit driven by the power supply,
The initialization request mechanism notifies the nonvolatile circuit that the peripheral circuit needs to be initialized when at least one or more pieces of the first information are recorded in the initialization request register. The information processing apparatus according to claim 1. The initialization request register further includes one or more second bit registers respectively corresponding to the one or more first bit registers;
Each second bit register stores second information indicating the volatile circuit,
The initialization request mechanism includes:
When the first information is recorded in the first bit register and the second information is recorded in the second bit register, it is necessary to initialize the volatile circuit indicated by the second information. The information processing apparatus according to claim 2, wherein the information processing apparatus notifies the nonvolatile circuit. The initialization request mechanism includes:
In addition, with a capacitor,
The information processing apparatus according to claim 1, wherein the first information is recorded in the initialization request register while being driven by the capacitor after the power is turned off. The nonvolatile circuit is a processor;
The information processing apparatus according to claim 1, wherein the volatile circuit is a peripheral circuit connected to the processor. An initialization request mechanism that is connected to a nonvolatile circuit in which the internal register is nonvolatile and one or more volatile circuits in which the internal register is volatile, and notifies the nonvolatile circuit that the power source for driving the volatile circuit has been turned off. Because
One or more power detection units that detect that the power is turned off, and an initialization request register that records that the power is turned off.
The initialization request register includes one or more first bit registers.
Each first bit register is associated with the volatile circuit;
The power detection unit is
Monitoring the state of the power supply;
When detecting that the power supply is turned off, first information indicating that the power supply is turned off is recorded in the first bit register associated with the volatile circuit driven by the power supply. ,
The initialization request mechanism notifies the nonvolatile circuit that the volatile circuit needs to be initialized when at least one or more pieces of the first information are recorded in the initialization request register. Initialization request mechanism to perform. The initialization request register further includes one or more second bit registers respectively corresponding to the one or more first bit registers;
Each second bit register stores second information indicating the volatile circuit,
The initialization request mechanism includes:
When the first information is recorded in the first bit register and the second information is recorded in the second bit register, it is necessary to initialize the volatile circuit indicated by the second information. The initialization request mechanism according to claim 6, wherein the initialization request is notified to the nonvolatile circuit. The initialization request mechanism includes:
In addition, with a capacitor,
The initialization request mechanism according to claim 6, wherein the first information is recorded in the initialization request register while being driven by the capacitor after the power is turned off. The nonvolatile circuit is a processor;
The initialization request mechanism according to claim 6, wherein the volatile circuit is a peripheral circuit connected to the processor. A processor configured by a non-volatile circuit that maintains an execution state when the power is turned off and starts operation from the execution state when the power is turned on, and holds an execution state when the power is turned off The decoder configured by a volatile circuit that starts operation from an initial state when the power is turned on, a memory for storing received video data, and a notification that the power is turned off to the processor A television receiver comprising: an initialization request mechanism that performs a timer for turning on the power;
The initialization request mechanism includes a power detection unit that detects that the power is turned off, and an initialization request register that records that the power is turned off.
The processor is
Determine whether video data necessary for decoding is stored in the memory,
When video data necessary for decoding is not stored in the memory, after setting a waiting time until the power is turned on in the timer, the power is turned off,
The power detection unit, when detecting that the power is turned off, records information indicating that the power is turned off in the initialization request register,
The timer turns on the power when the set standby time has elapsed,
The initialization request mechanism notifies the processor that the decoder needs to be initialized based on information indicating that the recorded power is turned off.
When receiving a notification from the initialization request mechanism, the processor activates the decoder in accordance with the execution state of a process held by the processor. An information processing apparatus comprising a nonvolatile circuit whose internal register is nonvolatile and a volatile circuit whose internal register is volatile,
When the power source for driving the volatile circuit is turned on again after being turned on, the internal register of the volatile circuit is set according to the execution state of the process held in the internal register of the nonvolatile circuit, An information processing apparatus that starts a volatile circuit. A storage unit for storing information indicating that the power is turned off;
An initialization request for outputting information indicating that the volatile circuit needs to be initialized to the nonvolatile circuit when the information is stored in the storage unit when the power is turned off and then turned on again. A mechanism,
The nonvolatile circuit starts the volatile circuit after setting the internal register of the volatile circuit in accordance with an execution state of a process held in the internal register of the nonvolatile circuit. Information processing device.

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