JP2010166403A - Pulse separation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse separation circuit, capable of avoiding complexity in regulation by dynamically regulating a threshold voltage for separating a clock pulse or a synchronization pulse which is superimposed on a serial signal from an input signal. <P>SOLUTION: A pulse separation circuit includes a comparator 2 which compares an input signal Sig1, which is obtained by superimposing a clock pulse 80 on a serial signal 81, with a threshold voltage Vth and outputs the result of the comparison; and a threshold voltage regulating circuit 3, which outputs as the threshold voltage Vth, a voltage of such a voltage value as to separate the clock pulse or a synchronization pulse from the input signal Sig1. The threshold voltage regulating circuit 3 is configured to increase/decrease the threshold voltage Vth, according to the output of the comparator 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pulse separation circuit that separates a clock pulse, a synchronization pulse, and the like superimposed on a serial signal from an input signal.

  Conventionally, a transmission method is known in which a pulse such as a clock pulse or a synchronization pulse is superimposed on a serial signal for transmission (see Patent Document 1, for example, a Sync on Video signal in which a synchronization pulse is superimposed on a serial video signal (FIG. 10). (A) and an AiPi serial signal in which a clock pulse is superimposed on a serial video signal (see FIG. 10B).

  In such a transmission system, a clock pulse and a synchronization pulse are separated from a signal input on the receiving side (hereinafter referred to as “input signal”) by a pulse separation circuit, and a serial signal is derived from the input signal based on the separated pulse. Processing such as extraction is performed.

  In this pulse separation circuit, a fixed threshold voltage and an input signal are compared by a comparator to separate clock pulses and synchronization pulses.

  FIG. 11 shows a configuration of a conventional pulse separation circuit 100 that separates clock pulses from an AiPi serial signal that is an input signal.

  The pulse separation circuit 100 includes a comparator 101, a reference voltage generation circuit 102 including a voltage source and a voltage follower, a resistor 103, and a variable current source 104.

  The AiPi serial signal is input to the positive input terminal (+) of the comparator 101, and the threshold voltage Vth is input to the negative input terminal (-). The threshold voltage Vth is obtained by adding a voltage (= I × R) generated in the resistor 103 (resistance value R) by the current (current value I) of the variable current source 104 to the reference voltage Vref output from the reference voltage generation circuit 102. Voltage (= I × R + Vref).

  In the pulse separation circuit 100, the user can set the current value of the variable current source 104 according to the state of the clock pulse in the AiPi serial signal, the amplitude level, Tr (rise time) / Tf (fall time), and the like. The threshold voltage Vth is adjusted to an optimum value.

Japanese Patent Application Laid-Open No. 2007-300490

  In the pulse separation circuit described above, when the width, amplitude level, and Tr / Tf of the pulse superimposed on the serial signal change, the width and phase of the pulse after separation change. Therefore, the threshold voltage Vth can be adjusted from the outside in accordance with the width, amplitude level, and Tr / Tf state of the pulse superimposed on the serial signal.

  However, the adjustment of the threshold voltage Vth cannot be easily performed because it requires expertise. In addition, in an electronic device such as a liquid crystal display device that requires a large number of pulse separation circuits, the adjustment of the threshold voltage Vth becomes complicated, and the number of control lines for adjusting the threshold voltage Vth from the outside increases. There arises a problem that the area increases.

  Therefore, the present invention provides a pulse separation circuit that can avoid the complexity of adjustment by dynamically adjusting a threshold voltage for separating a clock pulse and a synchronization pulse superimposed on a serial signal from an input signal. The purpose is to provide.

  Therefore, in order to solve the above-described problem, the invention according to claim 1 compares a threshold voltage with an input signal in which a clock pulse or a synchronization pulse is superimposed on a serial signal, and outputs a comparison result. A threshold voltage adjusting circuit that outputs a voltage having a voltage value capable of separating the clock pulse or the synchronization pulse from the input signal as the threshold voltage, the threshold voltage adjusting circuit according to an output of the comparator A pulse separation circuit for raising and lowering the threshold voltage is provided.

  According to a second aspect of the present invention, in the pulse separation circuit according to the first aspect, the threshold voltage adjustment circuit includes a charge / discharge circuit that charges and discharges an internal capacitor in accordance with an output level of the comparator. And a threshold voltage generation circuit that generates the threshold voltage according to the voltage value of the capacitor.

  The invention according to claim 3 is the pulse separation circuit according to claim 2, wherein the charge / discharge circuit includes the capacitor, a charging current source having a first current value connected to the capacitor, A discharge current source having a second current value n times the first current value, a switch connecting the discharge current source and the capacitor, and controlling the switch according to the output of the comparator.

  According to a fourth aspect of the present invention, in the pulse separation circuit according to the second aspect, the charge / discharge circuit includes the capacitor, a charging current source having a first current value, and an n of the first current value. A discharge current source having a doubled second current value, a first switch connecting the charging current source and the capacitor, a second switch connecting the discharge current source and the capacitor, and an output of the comparator Accordingly, the first switch and the second switch are controlled.

  According to a fifth aspect of the present invention, in the pulse separation circuit according to any one of the first to fourth aspects, the threshold voltage adjusting circuit includes a resistor having one end connected to a predetermined potential, and a capacitor. A transistor having an input node connected and an output node connected to the other end of the resistor, and outputting the threshold voltage from the output node of the transistor.

  According to the present invention, the threshold voltage adjustment circuit that raises and lowers the threshold voltage in accordance with the output of the comparator that compares the input signal in which the clock pulse or the synchronization pulse is superimposed on the serial signal and the threshold voltage is provided. Can be avoided. Moreover, the problem that the control area for adjusting the threshold voltage from the outside is not necessary and the mounting area is increased can be avoided.

It is a figure which shows the structure of the pulse separation circuit of 1st Embodiment. It is a figure which shows the waveform of the AiPi serial signal as an input signal. It is a figure for demonstrating operation | movement of the pulse separation circuit of 1st Embodiment. It is a figure which shows the transition of the voltage of each site | part when the signal by which the clock pulse was superimposed on the serial signal was input into the pulse separation circuit of 1st Embodiment. It is a figure which shows the transition of the voltage of each site | part when the signal by which the clock pulse was superimposed on the serial signal was input into the pulse separation circuit of 1st Embodiment. It is a figure which shows the transition of the voltage of each site | part when the signal by which the clock pulse was superimposed on the serial signal was input into the pulse separation circuit of 1st Embodiment. It is a figure which shows the structure of the other pulse separation circuit of 1st Embodiment. It is a figure which shows the structure of the pulse separation circuit of 2nd Embodiment. It is a figure which shows the structure of another pulse separation circuit. It is a figure which shows the example of the signal which superimposed pulses, such as a clock pulse and a synchronous pulse number. It is a figure which shows the structure of the conventional pulse separation circuit.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described. The description will be given in the following order.
1. 1. Pulse separation circuit according to the first embodiment 2. Pulse separation circuit according to the second embodiment Other pulse separation circuits

[1. Pulse Separation Circuit of First Embodiment]
First, the pulse separation circuit of the first embodiment will be specifically described with reference to the drawings. In the following description, a pulse separation circuit that separates a clock pulse from an input signal in which a clock pulse is superimposed on a serial signal will be described. The same applies to the circuit.

  FIG. 1 is a diagram showing the configuration of the pulse separation circuit of the first embodiment, FIG. 2 is a diagram showing the waveform of an AiPi serial signal as an input signal, and FIG. 3 is for explaining the operation of the pulse separation circuit of the first embodiment. FIG. FIG. 4 to FIG. 6 are diagrams showing voltage transition of each part when an AiPi serial signal in which a clock pulse is superimposed on a serial signal is input to the pulse separation circuit of the first embodiment.

  As shown in FIG. 1, the pulse separation circuit 1 includes a comparator 2 having hysteresis and a threshold voltage adjustment circuit 3, and separates and outputs a clock pulse 80 from an input signal Sig1. As will be described later, the threshold voltage adjustment circuit 3 functions as a circuit that detects the duty ratio of the output signal of the comparator 2 and generates the threshold voltage Vth.

  As shown in FIG. 2, the input signal Sig1 is an AiPi serial signal in which a clock pulse 80 having a duty ratio of 1:17 is superimposed on the serial signal 81. The amplitude of the input signal Sig1 is that of the serial signal 81 itself at the superimposed position of the clock pulse 80. The amplitude is higher than the amplitude by a predetermined value or more. Therefore, in the pulse separation circuit 1, the input signal Sig1 is input to the positive input terminal (+) of the comparator 2, and the threshold voltage Vth higher than the amplitude of the serial signal 81 itself is input to the negative input terminal (−) of the comparator 2. Thus, the clock pulse 80 is separated and output.

  In the conventional pulse separation circuit 100, the threshold voltage Vth is adjusted by the user. However, in the pulse separation circuit 1 of this embodiment, the threshold voltage adjustment circuit 3 is used to automatically adjust the threshold voltage Vth. That is, the threshold voltage adjustment circuit 3 generates a voltage having a voltage value that enables the clock pulse 80 to be separated from the input signal Sig1, and outputs the voltage as the threshold voltage Vth.

  In this way, the complexity of adjusting the threshold voltage Vth can be avoided. In addition, there is no need for a control line for adjusting the threshold voltage Vth from the outside, and an increase in mounting area can be suppressed.

  As shown in FIG. 1, the threshold voltage adjusting circuit 3 includes a charge / discharge circuit 10 that charges and discharges an internal capacitor C1 in accordance with the output level of the comparator 2, and a threshold voltage Vth in accordance with the voltage value of the capacitor C1. And a threshold voltage generation circuit 11 for generating.

  The charging / discharging circuit 10 includes a capacitor C1, a charging current source I1 for charging the capacitor C1 with a current value Ic, a discharging current source I2 for discharging the capacitor C1 with a current value Id, and a switch SW1. It has. Note that the switch SW1 is composed of, for example, a MOS transistor.

  When the output of the comparator 2 is at a low level, charging is performed from the charging current source I1 to the capacitor C1 with the current value Ic, and the voltage of the capacitor C1 rises. The threshold voltage generation circuit 11 decreases the threshold voltage Vth when the voltage of the capacitor C1 increases.

  The threshold voltage generation circuit 11 includes a PMOS transistor 21 whose source is grounded, a resistor 22, a reference power source that outputs a reference voltage Vref to an input node, a voltage follower 23 that amplifies and outputs the reference voltage Vref, have. The PMOS transistor 21 forms a variable current source together with the charge / discharge circuit 10.

  The output node (drain) of the PMOS transistor 21 is connected to the output node of the voltage follower 23 via the resistor 22, and the negative input terminal (−) of the comparator 2 is connected to the input node (gate). Is connected to a capacitor C1. Therefore, when the voltage of the capacitor C1 increases, the voltage at the input node of the PMOS transistor 21 increases, the current flowing through the resistor 22 decreases, and the threshold voltage Vth, which is the voltage at the negative input terminal (−) of the comparator 2, decreases. Will do. The other output node (source) of the PMOS transistor 21 is connected to a predetermined voltage Vd.

  On the other hand, when the output of the comparator 2 is at a high level, the switch SW1 is short-circuited and the discharge current source I2 is connected to the capacitor C1.

  At this time, the charging current source I1 and the discharging current source I2 are connected to the capacitor C1. Since the current value Id of the discharge current source I2 is set larger than the current value Ic of the charge current source I1, the discharge current of the current value It (= Id−Ic) from the capacitor C1 to the discharge current source I2 is set. Flows, and the voltage of the capacitor C1 drops.

  When the voltage of the capacitor C1 falls, the voltage at the input node of the PMOS transistor 21 falls, the current flowing through the resistor 22 increases, and the threshold voltage Vth, which is the voltage at the negative input terminal of the comparator 2, rises.

  Thus, the threshold voltage adjusting circuit 3 increases or decreases the threshold voltage Vth according to the output of the comparator 2.

  Further, in this threshold voltage adjusting circuit 3, in order to set the threshold voltage Vth to an appropriate value, the current value Ic of the charging current source I1 and the current value Id of the discharging current source I2 are set to the duty ratio of the clock pulse 80. It is set according to.

  In the present embodiment, the duty ratio of the clock pulse 80 in the input signal Sig1 is 1:17 as shown in FIG. 2, and the current value Id of the discharging current source I2 is equal to the current value Ic of the charging current source I1. It is set to 18 times. That is, the ratio of the value of the charging current to the capacitor C1 and the value of the discharging current from the capacitor C1 is set to 1:17, which is the same as the duty ratio of the clock pulse 80 in the input signal Sig1.

  By setting the current value Id of the discharge current source I2 in this way, the voltage of the capacitor C1 can be kept substantially constant when the input signal Sig1 is being input, and the clock pulse 80 output from the comparator 2 can be maintained. The duty ratio can be 1:17. Note that, if the charge / discharge current values Ic and Id are larger than the capacitance value of the capacitor C1, the threshold voltage Vth varies greatly. preferable. However, it is necessary to set the charging / discharging current values Ic and Id to such an extent that the time until the charging / discharging circuit 10 is stabilized becomes long and does not affect the reception of the input signal Sig1.

  Since the pulse separation circuit 1 has such a configuration, the clock pulse 80 is accurately separated and output even when the width, amplitude level, or Tr / Tf of the clock pulse 80 included in the input signal Sig1 fluctuates. be able to.

  That is, as shown in FIG. 3A, when the width of the clock pulse 80 included in the input signal Sig1 becomes narrower, in the conventional pulse separation circuit 100, the pulse width of the clock pulse 80 to be separated becomes narrower. The pulse separation circuit 1 can keep constant. Similarly, when the width of the clock pulse 80 included in the input signal Sig1 is widened, the pulse separation circuit 1 can keep it constant.

  FIG. 4 shows the output of the comparator 2 when the pulse width of the clock pulse 80 included in the input signal Sig1 is widened due to power supply fluctuation or temperature fluctuation (state 2) from when the input signal Sig1 is in a predetermined state (state 1). The state of the gate voltage of the PMOS transistor 21 is shown.

  As shown in the figure, when the state 1 is shifted to the state 2, the ratio between the high level and the low level of the clock pulse 80 output from the comparator 2 is (1 + Δ: 17−Δ). Therefore, the discharging time of the capacitor C1 by the discharging current source I2 becomes longer than the charging time of the capacitor C1 by the charging current source I1, the voltage of the capacitor C1 decreases, and the gate voltage of the PMOS transistor 21 decreases. As a result, the threshold voltage Vth increases, and as a result, the period of the high level of the clock pulse 80 output from the comparator 2 is shortened, and is stabilized when the ratio of the high level to the low level becomes 1:17. . Further, when the width of the clock pulse 80 included in the input signal Sig1 becomes narrow, the reverse operation is performed.

  Further, as shown in FIG. 3B, when the amplitude level of the clock pulse 80 included in the input signal Sig1 drops, the pulse width of the clock pulse 80 to be separated becomes narrow in the conventional pulse separation circuit 100. The pulse separation circuit 1 can keep constant. Similarly, when the amplitude level of the clock pulse 80 included in the input signal Sig1 rises, the pulse separation circuit 1 can keep it constant.

  FIG. 5 shows the output of the comparator 2 and the PMOS when the amplitude level of the clock pulse 80 included in the input signal Sig1 rises due to power supply fluctuation or temperature fluctuation (state 2) from when the input signal Sig1 is in a predetermined state (state 1). The state of the gate voltage of the transistor 21 is shown.

  As shown in the figure, when the state 1 is shifted to the state 2, the ratio between the high level and the low level of the clock pulse 80 output from the comparator 2 is (1 + Δ: 17−Δ). Therefore, the discharging time of the capacitor C1 by the discharging current source I2 becomes longer than the charging time of the capacitor C1 by the charging current source I1, the voltage of the capacitor C1 decreases, and the gate voltage of the PMOS transistor 21 decreases. As a result, the threshold voltage Vth increases, and as a result, the period of the high level of the clock pulse 80 output from the comparator 2 is shortened, and is stabilized when the ratio of the high level to the low level becomes 1:17. . Further, when the amplitude level of the clock pulse 80 included in the input signal Sig1 decreases, the reverse operation is performed.

  Further, as shown in FIG. 3C, when Tr / Tf of the clock pulse 80 included in the input signal Sig1 becomes short, the pulse width of the clock pulse 80 to be separated becomes narrow in the conventional pulse separation circuit 100. However, the pulse separation circuit 1 can keep it constant. Similarly, when the Tr / Tf of the clock pulse 80 included in the input signal Sig1 becomes longer, the pulse separation circuit 1 can keep it constant.

  FIG. 6 shows the output of the comparator 2 when the Tr / Tf of the clock pulse 80 included in the input signal Sig1 becomes longer (state 2) due to power supply fluctuation or temperature fluctuation from when the input signal Sig1 is in a predetermined state (state 1). The state of the gate voltage of the PMOS transistor 21 is shown.

  As shown in the figure, when the state 1 is shifted to the state 2, the ratio between the high level and the low level of the clock pulse 80 output from the comparator 2 is (1 + Δ: 17−Δ). Therefore, the discharging time of the capacitor C1 by the discharging current source I2 becomes longer than the charging time of the capacitor C1 by the charging current source I1, the voltage of the capacitor C1 decreases, and the gate voltage of the PMOS transistor 21 decreases. As a result, the threshold voltage Vth increases, and as a result, the period of the high level of the clock pulse 80 output from the comparator 2 is shortened, and is stabilized when the ratio of the high level to the low level becomes 1:17. . Further, when Tr / Tf of the clock pulse 80 included in the input signal Sig1 becomes short, the reverse operation is performed.

  As described above, in the pulse separation circuit 1 of the present embodiment, even when the width, amplitude level, or Tr / Tf of the clock pulse 80 included in the input signal Sig1 changes due to power supply fluctuation or temperature fluctuation, The pulse 80 can be separated and output with high accuracy.

  Therefore, in the receiver that latches the serial signal 81 based on the clock pulse 80 separated and output by the pulse separation circuit 1, the latch timing margin is increased, and the transmission speed of the corresponding input signal Sig1 can be improved. .

  Similarly, the sync pulse can be separated from the input signal in which the sync pulse is superimposed on the serial signal, such as the Sync on Video signal shown in FIG. As described above, by using the pulse separation circuit 1 as a circuit for separating the synchronization pulse from the input signal in which the synchronization pulse is superimposed on the serial signal, the sag tolerance is increased.

  Since the minimum voltage of the threshold voltage Vth is the reference voltage Vref, by appropriately setting the reference voltage Vref, it is possible to shorten the time until the input signal Sig1 reaches the appropriate threshold voltage Vth. It becomes possible.

  In particular, in the circuit shown in FIG. 1, when the input signal Sig1 is not input to the comparator 2, since the capacitor C1 is charged from the charging current source I1, the voltage of the capacitor C1 rises and the PMOS transistor 21 is turned off. Therefore, no current flows from the PMOS transistor 21 to the resistor 22, and the threshold voltage Vth becomes the reference voltage Vref before the input signal Sig1 starts to be received, and it is easy to shorten the time until the threshold voltage Vth is reached. be able to.

  Further, as shown in FIG. 7, the output node (drain-source) of the NMOS transistor 30 is connected between the capacitor C1 and a predetermined voltage (here, the ground voltage GND), and the input node (gate) of the NMOS transistor 30 is connected. Can be controlled externally. Then, by setting the input node (control terminal Cont) of the NMOS transistor 30 to the High level until the input signal Sig1 starts to be received, the voltage of the capacitor C1 becomes 0V and the PMOS transistor 21 is turned on. Therefore, before the reception of the input signal Sig1, the threshold voltage Vth becomes the set potential Vd which is the maximum voltage, and by appropriately setting this set potential Vd, until the threshold voltage Vth appropriate for the input signal Sig1 is reached. It becomes possible to shorten the time.

[2. Pulse Separation Circuit of Second Embodiment]
Next, a pulse separation circuit according to a second embodiment will be described with reference to the drawings. The pulse separation circuit according to the second embodiment is obtained by changing the charge / discharge circuit 10 of the pulse separation circuit according to the first embodiment. Since the rest of the circuit configuration is the same, the description of the same parts is omitted.

  FIG. 8 is a diagram showing the configuration of the pulse separation circuit of the second embodiment. As shown in the figure, the charge / discharge circuit 10 ′ of the pulse separation circuit 1 ′ of the second embodiment includes a capacitor C10, a charging current source I11, a discharging current source I12, switches SW11 and SW12, and an inverter. Circuit INV.

  The charging current source I11 is a current source for charging the capacitor C10 with the current value Ic, and the discharging current source I12 is a current source for discharging the capacitor C10 with the current value Id. The first switch SW11 is a switch provided between the charging current source I11 and the capacitor C10, and the second switch SW12 is a switch provided between the discharging current source I12 and the capacitor C10. These are composed of MOS transistors or the like. The current value of the discharging current source I12 is set to a current value Id (= Ic × 17) that is 17 times the duty ratio of the clock pulse 80 with respect to the current value Ic of the charging current source I11. .

  When the output of the comparator 2 is at a low level, the output of the inverter circuit INV is at a high level, the first switch SW11 is short-circuited, and the charging current source I11 and the capacitor C10 are connected. As a result, charging from the charging current source I11 to the capacitor C10 is performed at the current value Ic, the voltage of the capacitor C10 increases, and the threshold voltage generation circuit 11 decreases the threshold voltage Vth.

  On the other hand, when the output of the comparator 2 is at a high level, the second switch SW12 is short-circuited and the discharge current source I12 is connected to the capacitor C10. At this time, the output of the inverter circuit INV becomes low level, the first switch SW11 is opened, and charging from the charging current source I11 to the capacitor C10 is stopped. As a result, the discharge current source I12 discharges from the capacitor C10 with the current value Id, the voltage of the capacitor C10 decreases, and the threshold voltage generation circuit 11 increases the threshold voltage Vth.

  As described above, in the pulse separation circuit 1 ′ of the second embodiment, the threshold voltage Vth can be adjusted according to the output of the comparator 2, similarly to the pulse separation circuit 1 of the first embodiment. Therefore, even when the width, amplitude level, or Tr / Tf of the clock pulse 80 included in the input signal Sig1 fluctuates (eg, fluctuates due to power supply fluctuation or temperature fluctuation), the clock pulse 80 is accurately separated. Can be output.

  In the pulse separation circuit 1 of the first embodiment, only the switch SW1 is necessary, whereas in the pulse separation circuit 1 of the second embodiment, two switches, the first switch SW11 and the second switch SW12, are provided. In addition, an inverter circuit INV is required. Therefore, in the mounting area, the pulse separation circuit 1 of the first embodiment can be made smaller.

  However, in the pulse separation circuit 1 ′ of the second embodiment, the current value Ic of the charging current source I11 and the current value Id of the discharging current source I12 (=) at the same ratio as the duty ratio (1:17) of the clock pulse 80. Ic × 17), the circuit design can be easily performed.

[3. Other pulse separation circuit]
Instead of the threshold voltage adjusting circuit 3 as in the above-described embodiment, a threshold voltage adjusting circuit 53 as shown in FIG. 9 may be used. Note that the comparator 52 is a comparator having hysteresis similar to the comparator 2 of the above embodiment.

  As shown in FIG. 9, the pulse separation circuit 51 generates a charge / discharge circuit 60 that charges and discharges the internal capacitor C20 according to the output level of the comparator 52, and generates a threshold voltage Vth according to the voltage value of the capacitor C20. And a threshold voltage generation circuit 61 for performing the above operation. The threshold voltage generation circuit 61 is configured by a voltage follower, and amplifies the voltage of the capacitor C20 and outputs it as a threshold voltage Vth.

  The charging / discharging circuit 60 includes a capacitor C20, a charging current source I21 for charging the capacitor C20 with a current value Ic ′, a discharging current source I22 for discharging the capacitor C20 with a current value Id ′, and a switch. SW21 and SW22 are provided. The switches SW21 and SW22 are composed of, for example, MOS transistors.

  Before the input signal Sig1 is input, the output of the comparator 52 is low level. At this time, the output of the inverter circuit INV becomes high level, the switch SW22 is short-circuited, and the discharge current source I22 is connected to the capacitor C20. The On the other hand, since the switch SW21 is in an open state, the capacitor C20 is discharged at the current value Id ′ by the discharge current source I22, the voltage of the capacitor C20 decreases, and the threshold voltage Vth output from the threshold voltage generation circuit 61 decreases. To do.

  On the other hand, when the input signal Sig1 is input and the output of the comparator 2 becomes High level, the switch SW21 is short-circuited and the switch SW22 is open. Therefore, the capacitor C20 is charged with the current value Ic ′ by the charging current source I21, the voltage of the capacitor C20 increases, and the threshold voltage Vth output from the threshold voltage generation circuit 61 increases.

  When the duty ratio of the clock pulse 80 in the input signal Sig1 is 1:17 as shown in FIG. 2, the current value Ic ′ of the charging current source I21 is 17 times the current value Id ′ of the discharging current source I22. Set to. That is, the ratio of the value of the discharge current from the capacitor C20 and the value of the charge current to the capacitor C20 is set to 1:17, which is the same as the duty ratio of the clock pulse 80 in the input signal Sig1.

  As described above, the threshold voltage adjustment circuit 53 increases or decreases the threshold voltage Vth according to the output of the comparator 52. As a result, as in the case of the pulse separation circuit 1, 1 ′, the clock pulse 80 is accurately separated even when the width, amplitude level, or Tr / Tf of the clock pulse 80 included in the input signal Sig1 changes. Can be output.

  The output node of the PMOS transistor is connected between the capacitor C20 and the predetermined voltage Vd, and the threshold voltage Vth is started from the predetermined voltage Vd by turning on the PMOS transistor before the input signal Sig1 is input. be able to.

  The pulse separation circuit described above can be used, for example, in a source driver IC (semiconductor integrated circuit including a liquid crystal driving circuit) that supplies a video signal to a liquid crystal panel. The larger the liquid crystal panel, the greater the number of source driver ICs. Accordingly, the wiring used for supplying video data from the timing generator IC (semiconductor integrated circuit including a signal processing circuit) to the source driver IC also has a different length for each source driver IC. Will also be different. However, by applying the above-described pulse separation circuit to the source driver IC, it is not necessary to consider the influence of wiring, and the complexity of adjusting the threshold voltage Vth can be avoided.

  Note that video data for each column group is transmitted from the timing generator to each source driver IC as a signal in which a clock pulse is superimposed on a serial signal. Each source driver IC separates a clock pulse from a signal received from the timing generator IC by a pulse separation circuit, and receives a serial signal from the signal received from the timing generator IC at a timing based on the clock pulse. The received serial signal is subjected to predetermined processing and output to the liquid crystal panel.

  Although one embodiment according to the present invention has been specifically described, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible.

1, 1 ', 51 Pulse separation circuit 2, 52 Comparator 3, 53 Threshold voltage adjustment circuit 10, 10', 60 Charge / discharge circuit 11, 61 Threshold voltage generation circuit 21 PMOS transistor 22 Resistor 23 Voltage follower 30 NMOS transistor SW1 Switch SW11 , SW21 First switch SW12, SW22 Second switch C1, C10, C20 Capacitors I1, I11, I21 Charging current sources I2, I12, I22 Discharging current sources

Claims (5)

A comparator that compares a threshold voltage with an input signal in which a clock pulse or a synchronization pulse is superimposed on a serial signal; and
A threshold voltage adjustment circuit that outputs, as the threshold voltage, a voltage value that enables separation of the clock pulse or the synchronization pulse from the input signal,
The threshold voltage adjustment circuit is a pulse separation circuit that raises and lowers the threshold voltage according to the output of the comparator. The threshold voltage adjustment circuit includes:
A charge / discharge circuit that charges and discharges an internal capacitor according to the output level of the comparator;
The pulse separation circuit according to claim 1, further comprising a threshold voltage generation circuit that generates the threshold voltage according to a voltage value of the capacitor. The charge / discharge circuit is
The capacitor;
A charging current source having a first current value connected to the capacitor;
A discharging current source having a second current value n times the first current value;
A switch connecting the current source for discharge and the capacitor;
The pulse separation circuit according to claim 2, wherein the switch is controlled in accordance with an output of the comparator. The charge / discharge circuit is
The capacitor;
A charging current source having a first current value;
A discharging current source having a second current value n times the first current value;
A first switch connecting the charging current source and the capacitor;
A second switch connecting the discharge current source and the capacitor;
The pulse separation circuit according to claim 2, wherein the first switch and the second switch are controlled in accordance with an output of the comparator. The threshold voltage adjustment circuit includes:
A resistor having one end connected to a predetermined potential;
A transistor having an input node connected to the capacitor and an output node connected to the other end of the resistor;
The pulse separation circuit according to claim 1, wherein the threshold voltage is output from an output node of the transistor.

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