JP2010166300A - High-speed level shifting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To communicate variation in a gate potential to a substrate potential without attenuation and delay to enable a high-speed operation, and to reduce a parasitic diode leakage current in the case where the gate potential does not change. <P>SOLUTION: In a substrate potential control circuit 101, a SW1 connects a gate terminal of an MN1 with a substrate terminal. A SW2 connects the substrate terminal to 0V. A switching control circuit 102 controls to set the SW1 in a conductive state and set the SW2 in a non-conductive state during the gate terminal is 0V and for a predetermined time period after the gate terminal is changed from 0V to Vdd. In addition, the circuit 102 controls to set the SW1 in the non-conductive state and set the SW2 in the conductive state after a lapse of the predetermined time period. The circuit 102 controls to set the SW1 in the non-conductive state and set the SW2 in the conductive state at least during the potential of the gate terminal is Vdd. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The disclosed technology relates to a level shift circuit in a semiconductor integrated circuit.

  The level shift circuit is an interface circuit that transmits a pulse signal from a circuit that operates at a low voltage to a circuit that operates at a high voltage in a mixed signal circuit such as an ADC (analog-digital converter) circuit or a PLL (phase-locked loop) circuit. Widely used.

  FIG. 11A shows a general level shift circuit. The circuit of FIG. 11A converts a pulse signal having a 1.2V (volt) amplitude (see FIG. 11B) into a pulse signal having a 3.3V amplitude (see FIG. 11C). In FIG. 11A, MN1 and MN2 are NMOS transistors, MP1 and MP2 are PMOS transistors, and INV1 to INV4 are inverter circuits.

  In a level shift circuit as shown in FIG. 11A, it is a general problem to reduce the propagation delay (that is, speed up) from the input voltage to the output voltage. The critical path is as follows.

  When the input voltage Vi changes from 0V to Vdd (1.2V in FIG. 11), that is, when the gate voltage Vg1 of MN1 changes from 0V to Vdd, MN1 changes from the off state to the on state and the potential of the node a Is changed from Vddh (3.3V in FIG. 11) to 0V. As a result, MP2 changes from the off state to the on state to charge the node b, and the output voltage Vo finally changes from 0V to Vddh.

  Conversely, when the input voltage Vi changes from Vdd to 0V, that is, when the gate voltage Vg1 of MN2 supplied via INV1 changes from 0V to Vdd, MN2 transitions from the off state to the on state and becomes a node. The potential of b is changed from Vddh to 0V. In addition, MP1 changes from the OFF state to the ON state, charges the node a, and causes MP2 to transition from the ON state to the OFF state. As a result, the output voltage Vo output via INV3 and INV4 changes from Vddh to 0V.

  In the above operation, when the output voltage Vo changes from 0V to Vddh in response to the input voltage Vi changing from 0V to Vdd, and in response to the input voltage Vi changing from Vdd to 0V. Propagation delay when the voltage Vo changes from Vddh to 0 V becomes a critical path.

  Factors that cause the above-described problems include the magnitude of the load capacity of the node a or b and the lack of driving power of MP1 and MP2. The main factor is that high voltage transistors must be used as MN1 and MN2. Although the high breakdown voltage transistor generally has a higher threshold value than the core transistor, it can supply only the power supply voltage Vdd having the lowest gate voltage, so obviously the driving power of MN1 and MN2 is low. This is most noticeable when the threshold values of MN1 and MN2 are high (slow process or low temperature condition) and Vdd is the minimum condition.

Various conventional techniques have been proposed for speeding up the level shift circuit. Among such conventional techniques, there is also a conventional technique in which a circuit that senses a change in an output terminal (nodes a and b) and supplies an auxiliary charging current is added. However, such a conventional technique cannot fundamentally solve the deficiency of driving force of MN1 and MN2, and increases the load capacity of the output terminal, so that the influence on the propagation delay remains as described above.

  Therefore, as a technique for improving the driving power of MN1 and MN2, as shown in FIG. 12A, a so-called DTMOS (Dynamic Threshold voltage MOS) in which the gate (G) terminal and the substrate (B) terminal of the transistor are connected to each other. ) Based speedup methods have been proposed. The details of DTMOS are described in Non-Patent Document 1 below. The DTMOS has a feature that, when the gate potential Vg changes from 0 V to Vdd, the substrate potential also rises and is forward-biased, so that the threshold value of the NMOS transistor decreases and as a result, the driving force increases. On the other hand, when the gate potential is fixed at Vdd (for example, the high level period of the pulse), as shown in FIG. 12B, the parasitic diode Dp formed by the PN junction between the substrate and the source is in order. There is a problem that a current (hereinafter referred to as a parasitic diode leakage current) flows from the power source to the ground by being directionally biased, and power consumption increases. In particular, this current is likely to be a problem at low speed operation.

The following conventional techniques have been proposed as a technique for reducing parasitic diode leakage current based on DTMOS.
FIG. 13 is a configuration diagram of the first conventional technique described in Patent Document 1 below. The gate terminal of the transistor TN1 and the substrate terminal are connected by the capacitive element C1. Signal transmission from the gate potential to the substrate potential is attenuated by the ratio between C1 and the parasitic capacitance (for example, Pwell and DeepNwelll) on the substrate terminal. As a result, even if the gate potential of TN1 becomes Vdd, the substrate potential does not rise to Vdd. For this reason, the parasitic diode leakage current can be reduced.

  FIG. 14 is a configuration diagram of a second prior art described in Patent Document 2 below. The gate terminal of the transistor 33 and the substrate terminal are connected by a trigger circuit. The trigger circuit is a circuit that detects when the gate potential changes from 0 V to Vdd and generates a short Hi-width pulse signal. The potential of the substrate terminal rises only during the short Hi width period of this pulse signal. For this reason, the parasitic diode leakage current can be reduced.

  FIG. 15 is a configuration diagram of a third conventional technique described in Patent Document 3 below. The gate terminal and the substrate terminal of the transistor 24 are connected only by the NMOS transistor 26. When the threshold value of the NMOS transistor 26 is Vth, this transistor can transmit only to the potential of Vdd-Vth. For this reason, an increase in the substrate potential of the transistor 24 is suppressed by Vth, and the parasitic diode leakage current can be reduced.

JP 2006-287309 A Japanese Patent No. 3962383 JP 2003-273723 A

“A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage”, F.A. Assaderahi et. al, Electron Device Letters, IEEE, Dec. 1994

However, in the first prior art described above, signal transmission from the gate potential to the substrate potential is attenuated by the capacitance ratio. For this reason, compared with the case where attenuation is not performed, there is a problem that the effect of reducing the threshold value is weakened and the high speed is also reduced. Moreover, the addition of the capacitive element is disadvantageous in that it leads to an increase in circuit area and process cost.

  In the second prior art described above, the timing at which the OUT signal of the trigger circuit shown in FIG. 14 changes from 0 V to Vdd is greater than the delay of the logic gate 33 than the timing at which the IN signal changes from 0 V to Vdd. Only sure will be slow. For this reason, there is a problem that the high-speed performance is reduced accordingly.

  Further, in the third prior art described above, the amount of suppression of the increase in the substrate potential is small under the condition that the threshold value of the NMOS transistor 26 shown in FIG. For this reason, there is a problem that the effect of reducing the parasitic diode leakage current is reduced.

  A problem to be solved by the disclosed technology is that a parasitic diode is used when a gate potential fluctuation is transmitted to a substrate potential “without attenuation” and “without delay” to enable high-speed operation and there is no gate potential fluctuation. It is to reduce the leakage current.

  In the disclosed technique, an inversion and non-inversion signal of a pulse signal having a low voltage amplitude is supplied to each gate terminal, and a potential difference between each drain terminal of the two NMOS transistors is operated. In order to amplify, a level shift circuit including a positive feedback circuit having a cross-coupled configuration of PMOS transistors is assumed.

The following configuration is provided for at least one NMOS transistor.
The first switch circuit makes the gate terminal of the NMOS transistor and the substrate terminal conductive.

The second switch circuit conducts the substrate terminal to a low level potential.
The switch control circuit turns on the first switch circuit and turns off the second switch circuit during a period when the gate terminal is at the low level potential and for a predetermined period after the low level potential is changed to the high level potential. Control to the conduction state. In addition, the switch control circuit sets the first switch circuit in a non-conductive state and controls the second switch circuit in a conductive state after a predetermined period. The switch control circuit sets the first switch circuit to a non-conductive state and controls the second switch circuit to a conductive state at least during a period when the potential of the gate terminal is at a high level potential.

According to the disclosed technique, it is possible to reduce the parasitic diode leakage current while speeding up the level shift circuit.
According to the disclosed technique, the gate terminal and the substrate terminal are connected via the CMOS switch for a while for a while even when the gate potential is the low level potential and even when the gate potential changes from the low level potential to the high level potential. As a result, it becomes possible to transmit the fluctuation of the gate potential to the substrate potential without being attenuated as in the first prior art or the delay of the logic gate as in the second prior art. Operation is realized.

  According to the disclosed technique, the gate potential is changed from the low level potential to the high level potential, and the substrate potential is connected to the low level potential after a while. For this reason, it is possible to stably reduce the parasitic diode leakage current under all PVT (process, power supply voltage, temperature) conditions as compared with the third conventional technique using the threshold value of the switch transistor. Further, since the additional circuit does not include a capacitive element, it is advantageous in terms of circuit area and process cost as compared with the first prior art.

It is a block diagram of embodiment of a level shift circuit. 2 is a configuration diagram of a first embodiment of a detailed circuit of a switch control circuit 102. FIG. 3 is an operation timing chart showing the operation of the detailed circuit of the switch control circuit 102 according to the first embodiment. 5 is a configuration diagram of a second embodiment of a detailed circuit of a switch control circuit 102. FIG. 6 is an operation timing chart showing the operation of the detailed circuit of the switch control circuit 102 in the second and third embodiments. 6 is a configuration diagram of a third embodiment of a detailed circuit of a switch control circuit 102. FIG. It is a figure which shows the simulation result which shows the comparison of high speed of embodiment and a prior art. It is a figure which shows the simulation result which shows the comparison of the parasitic diode leakage current of embodiment and a prior art. It is a figure which shows the structural example of the circuit which applied embodiment to the A / D converter. It is a figure which shows the structural example of the radio | wireless communication apparatus containing the A / D converter to which embodiment is applied. FIG. 2 is a configuration diagram and an operation waveform diagram of a general level shift circuit. It is explanatory drawing of the structure of the prior art which used DTMOS, and its subject. It is a block diagram of the 1st prior art. It is a block diagram of the 2nd prior art. It is a block diagram of the 3rd prior art.

Hereinafter, embodiments will be described in detail.
FIG. 1 is a configuration diagram of an embodiment of a level shift circuit.
In FIG. 1, MN1 and MN2 are NMOS transistors, and MP1 and MP2 are PMOS transistors. INV1 to INV4 are inverter circuits.

  The cores of the level shift circuit are MN1, MN2, MP1, and MP2, and high voltage transistors are used. The portion configured by MN1, MN2, MP1, MP2, and INV1 to INV4 is the same as the general configuration shown in FIG.

  The gate terminals of MN1 and MN2 are supplied with non-inverted and inverted signals of a low-voltage amplitude pulse signal, which is the input voltage Vi, respectively. The magnitude relationship changes depending on the input voltage Vi. The magnitude relationship (that is, the potential difference between the drains) is amplified to a logic level (0 / Vddh) by a positive feedback circuit (cross-coupled configuration) composed of MP1 and MP2.

A substrate potential control circuit 101 (# 1 or # 2) is inserted between the gate terminal and the substrate terminal of at least one of the above-described level shift circuits MN1 and MN2.
For example, when the substrate potential control circuit 101 is connected to MN1 (101 (# 1) in the figure), the circuit 101 first includes a CMOS switch SW1 that connects the gate terminal and the substrate terminal. SW1 continues to conduct for a certain time Td not only when the gate potential Vg1 = 0 V (volt) but also after Vg1 changes from 0 V to Vdd. Thereby, the fluctuation of the gate terminal is transmitted to the substrate terminal without delay.

The substrate potential control circuit 101 also includes a switch SW2 that makes the substrate terminal conductive to 0V. SW2 conducts only when SW1 is in the off state. By SW1 and SW2, the substrate potential of MN1 is always 0V except for the time Td immediately after the change from 0V to Vdd.

  Further, the substrate potential control circuit 101 includes a switch control circuit 102 that controls SW1 and SW2. This switch control circuit 102 controls SW1 to be in an on state and SW2 to be in an off state only during a predetermined period Td before and after the gate potential Vg1 changes from 0V to Vdd. Further, the switch control circuit 102 controls SW1 to be in an OFF state and SW2 to be in an ON state after a lapse of a predetermined period Td, and at least as long as Vg1 is in a Vdd state, the SW1 OFF state and the SW2 ON state are maintained. To control.

  As described above, when the gate potential Vg1 is 0V and even when the gate potential Vg1 changes from 0V to Vdd, the gate terminal and the substrate terminal are connected via the CMOS switch SW1 for a while period Td, and the substrate quickly changes due to the change of the gate terminal. Follow. As a result, the fluctuation of the gate potential can be transmitted to the substrate potential without being attenuated as in the first prior art and without the delay of the logic gate as in the second prior art. As a result, a high-speed level shift circuit is realized.

  Further, the gate potential Vg1 changes from 0V to Vdd, and after a period of time Td, the substrate potential is connected to 0V. Even when Vg1 = Vdd, the current from Vb to the ground, that is, the parasitic diode leakage current does not flow. As a result, the parasitic diode leakage current can be stably reduced under all PVT (process, power supply voltage, temperature) conditions as compared with the third conventional technique using the threshold value of the switch transistor. Further, the additional circuit is advantageous in terms of circuit area and process cost compared to the first prior art in that it does not include a capacitive element.

2 is a first detailed circuit configuration diagram of the switch control circuit 102 of FIG. 1, and FIG. 3 is an operation timing chart showing the operation timing thereof.
The switch control circuit 102 shown in FIG. 2 includes a delay circuit 201 and inverter circuits 202 and 203. The operation of this configuration is as follows.

  The delay circuit 201 delays the gate potential Vg1 shown in FIG. 3A by a predetermined period Td and outputs a voltage value Vd shown in FIG. 3B. The inverter circuit 202 inverts the voltage value Vd shown in FIG. 3B and outputs the voltage value Vc1 shown in FIG. The inverter circuit 203 inverts the voltage value Vc1 shown in FIG. 3C and outputs the voltage value Vc2 shown in FIG. The voltage values Vc1 and Vc2 control ON / OFF of SW1 and SW2, respectively.

  Before and after time t1 when Vg1 changes from 0V to Vdd and until time t2 when Td elapses and Vd rises to Vdd (FIGS. 3A and 3B), Vc1 which is the inverted output of Vd maintains Vdd. (FIG. 3C), SW1 is turned on (FIG. 3F). During this time, Vc2, which is the inverted output of Vc1, is maintained at 0V (FIG. 3 (d)), and SW2 is turned off (FIG. 3 (g)).

  From time t2 when Vd rises to Vdd until time t4 when Vg1 falls to 0V and Td elapses and Vd falls to 0V at time t3 (FIGS. 3A and 3B), Vc1 is the inverted output of Vd. Is maintained at 0 V (FIG. 3C), SW1 is turned off (FIG. 3F). During this time, Vc2 shown in FIG. 3D, which is an inverted output of Vc1, maintains Vdd (FIG. 3D), and SW2 is turned on (FIG. 3G).

After time t4 when Vd falls to 0V (FIG. 3 (b)), Vc1, which is the inverted output of Vd, maintains Vdd (FIG. 3 (c)), and SW1 is turned on (FIG. 3 (f)). )). During this time, Vc2, which is the inverted output of Vc1, is maintained at 0V (FIG. 3 (d)), and SW2 is turned off (FIG. 3 (g)).

  As a result, from the time t1 when the gate potential Vg1 changes from 0V to Vdd to the time t2 when the predetermined period Td elapses, the substrate potential Vb becomes Vdd as shown in FIG. Terminal is connected. Thereby, the fluctuation of the gate potential is quickly transmitted to the substrate potential.

  Also, after time t2 when the gate potential Vg1 changes from 0V to Vdd and after a period of time Td, the substrate potential Vb is connected to 0V as shown in FIG. As a result, even if Vg1 = Vdd, a current from Vb to the ground, that is, a parasitic diode leakage current does not flow.

4A and 4B are second detailed circuit configuration diagrams of the switch control circuit 102 of FIG. 1, and FIG. 5 is an operation timing chart showing the operation timing thereof.
The switch control circuit 102 shown in FIG. 4A includes a delay circuit 401, a NAND circuit 402, and an inverter circuit 403. The switch control circuit 102 shown in FIG. 4B includes a delay circuit 404, an AND circuit 405, and an inverter circuit 406. The operation of these configurations is as follows.

  The delay circuit 401 or 404 delays the gate potential Vg1 shown in FIG. 5A by a predetermined period Td and outputs the voltage value Vd shown in FIG. 5B. As in the case of FIG. 2, the voltage value Vc1 for controlling on / off of SW1 inverts the output of the NAND circuit 402 in the case of FIG. 4A and the output of the AND circuit 405 in the case of FIG. 4B. This is the output of the inverter circuit 406. Similarly to the case of FIG. 2, the voltage value Vc2 for controlling the on / off of SW2 is the output of the inverter circuit 403 that inverts the output of the NAND circuit 402 in the case of FIG. The case is the output of the AND circuit 405.

  Vc1 becomes Vdd and turns on SW1 in a period other than the period in which both potentials Vg1 and Vd are Vdd. That is, before and after time t1 when Vg1 changes from 0V to Vdd, and after time Td elapses and until time t2 when Vd rises to Vdd (FIGS. 3A and 3B), and Vg1 falls to 0V. In a period after time t3 (FIG. 3B), Vc1 becomes Vdd and SW1 is turned on. Since Vc2 is an inverted output of Vc1 as shown in FIG. 4A or 4B, it becomes 0V during these periods and turns off SW2.

  Vc1 becomes 0V and turns off SW1 during a period when both potentials Vg1 and Vd are Vdd. That is, during a period from time t2 when Vd rises to Vdd to time t3 when Vg1 falls to 0V (FIGS. 3A and 3B), Vc1 becomes 0V and SW1 is turned off. Since Vc2 is an inverted output of Vc1, as shown in FIG. 4A or 4B, it becomes Vdd during this period and turns on SW2.

  As a result, as in FIGS. 2 and 3, as shown in FIG. 5E, the substrate potential Vb becomes Vdd and the gate terminal and the substrate terminal only during a predetermined period Td from time t1 to time t2. Are connected, and the fluctuation of the gate potential is quickly transmitted to the substrate potential. Similarly, after time t2, as shown in FIG. 5E, the substrate potential Vb is connected to 0 V, and even if Vg1 = Vdd, the parasitic diode leakage current from Vb to the ground does not flow. Become.

6A and 6B are third detailed circuit configuration diagrams of the switch control circuit 102 of FIG.
The switch control circuit 102 in FIG. 6A includes an inverter circuit 601 that inverts Vg1,
A delay circuit 602 that delays the output, an NOR circuit 603 that receives the output and the output of the inverter circuit 601, and an inverter circuit 604 that inverts the output and controls SW1 are provided. The output of the NOR circuit 603 controls SW2.

  The circuit group including the inverter circuit 601, the delay circuit 602, and the NOR circuit 603 illustrated in FIG. 6A is equivalent to the circuit group including the delay circuit 404 and the AND circuit 405 illustrated in FIG.

  The switch control circuit 102 in FIG. 6B includes an inverter circuit 605 that inverts Vg1, a delay circuit 606 that delays its output, an OR circuit 607 that receives the output and the output of the inverter circuit 601, and its output. And an inverter circuit 608 for controlling SW2. The output of the OR circuit 607 controls SW1.

  The circuit group including the inverter circuit 605, the delay circuit 606, and the OR circuit 607 illustrated in FIG. 6B is equivalent to the circuit group including the delay circuit 401 and the NAND circuit 402 illustrated in FIG.

Therefore, the circuit shown in FIG. 6 (a) or (b) realizes the same operation as the control operation shown in the operation timing chart of FIG. 5 by the circuit shown in FIG. 4 (a) or (b).
Simulation results showing a comparison between the embodiment having the above-described configuration and operation and the prior art are shown in FIGS.

  In these simulations, all the 3.3V transistors have the same size, and the additional circuits (the switch size, the number of logic gates, etc.) in the first to third prior arts described above are set to have substantially the same parameters. ing.

  FIG. 7 shows simulation results comparing high speed. FIGS. 7A, 7B, and 7C show comparison results with the first, second, and third prior arts, respectively. These simulation conditions are slow process conditions, high temperature conditions, and power supply voltage = minimum conditions. In the above description of the prior art, the low temperature condition is shown as the condition for maximizing the threshold values of the NMOS transistors MN1 and MN2, but the propagation delay is the largest in the entire level shift circuit because the β of the transistor is small. The simulation was performed under a high temperature condition. From these results, it can be seen that the waveform change is steeper in the present embodiment than any of the first, second, and third prior arts, and is excellent in high speed.

  FIG. 8 is a simulation result comparing the parasitic diode leakage current with the third prior art. The simulation conditions are fast process conditions, high temperature conditions, and power supply voltage = maximum conditions. As a result, the average value of the parasitic diode leakage current of this embodiment is about 1/20 of that of the third prior art.

FIG. 9 is a diagram illustrating a configuration example of a circuit in which the embodiment using the configuration of FIG. 1 and FIG. 2, FIG. 4, or FIG. 6 is applied to an A / D converter.
The analog circuit 902 that is a part of the A / D converter operates at a high voltage of 3.3 V (volt), for example, and is compared with the analog signal processing circuit 902-1 that processes the analog input and the threshold voltage. This is realized by a comparator 902-2 that outputs a logical value. On the other hand, the digital circuit 903 which is a part of the A / D converter operates with a low voltage of 1.2 V, for example, and encodes the output of the comparator 902-2 to output a digital output. , A clock buffer 903-2, a switch control signal generation circuit 903-3, and the like.

  In such an A / D converter configuration, the level shift circuit 901 that can be realized by the embodiment is output from the low-voltage clock signal output from the clock buffer 903-2 or the switch control signal generation circuit 903-3. The low voltage switch control signal is level-shifted to generate a high voltage clock and switch control signal, which are supplied to the analog signal processing circuit 902-1 and the comparator 902-2 in the analog circuit 902.

FIG. 10 is a diagram illustrating a configuration example of a wireless communication device including the A / D converter illustrated in FIG.
The reception signal input from the antenna 1002 is received and processed by an RF front end circuit 1003 including an LNA (low noise amplifier) 1003-1, a filter 1003-2, a frequency conversion circuit 1003-3, and the like. Next, for example, an A / D converter 1001 having the configuration of FIG. 9 converts an analog reception signal output from the RF front-end circuit 1003 into a digital reception signal. Then, the digital baseband signal processing circuit 1004 converts the digital reception signal output from the A / D converter 1001 into a baseband reception signal and outputs the baseband reception signal to a signal processing unit (not shown) in the subsequent stage.

The wireless communication device having the above configuration can be realized as a receiver for terrestrial digital television, for example.
With the above configuration example, it is possible to realize a high-performance A / D converter capable of high-speed operation and reducing parasitic diode leakage current and a wireless communication device using the A / D converter.

In relation to the above embodiment, the following additional notes are disclosed.
(Appendix 1)
Two NMOS transistors that supply inverted and non-inverted signals of low voltage amplitude pulse signals to each gate terminal and operate in opposite phases to each other, and a PMOS for amplifying the potential difference between the drain terminals of the two NMOS transistors In a level shift circuit including a positive feedback circuit having a cross-coupled configuration of transistors,
Provided for at least one of the NMOS transistors,
A first switch circuit for conducting a gate terminal and a substrate terminal of the NMOS transistor;
A second switch circuit for conducting the substrate terminal to a low level potential;
The first switch circuit is turned on and the second switch circuit is turned off for a period during which the gate terminal is at the low level potential and for a predetermined period after the low level potential is changed to the high level potential. A period in which the first switch circuit is turned off and the second switch circuit is turned on after the predetermined period, and at least the potential of the gate terminal is the high-level potential. Is a switch control circuit for setting the first switch circuit to a non-conductive state and controlling the second switch circuit to a conductive state;
A level shift circuit comprising:
(Appendix 2)
The switch control circuit includes:
A delay circuit for delaying the potential of the gate terminal;
A first inverter circuit that inverts the output potential of the delay circuit, and the resulting output potential controls the first switch circuit;
A second inverter circuit that further inverts the output potential of the first inverter circuit, and the resulting output potential controls the second switch circuit;
The level shift circuit according to appendix 1, characterized by comprising:
(Appendix 3)
The switch control circuit includes:
A delay circuit for delaying the potential of the gate terminal;
A NAND circuit that inputs an output potential of the delay circuit and a potential of the gate terminal to perform a NAND operation, and an output potential obtained as a result controls the first switch circuit;
An inverter circuit that inverts an output of the NAND circuit, and an output potential obtained as a result controls the second switch circuit;
The level shift circuit according to appendix 1, characterized by comprising:
(Appendix 4)
The switch control circuit includes:
A delay circuit for delaying the potential of the gate terminal;
An AND circuit that inputs an output potential of the delay circuit and a potential of the gate terminal to perform an AND operation, and an output potential obtained as a result controls the second switch circuit;
An inverter circuit that inverts the output of the AND equivalent circuit, and the resulting output potential controls the first switch circuit;
The level shift circuit according to appendix 1, characterized by comprising:
(Appendix 5)
The switch control circuit includes:
A first inverter circuit for inverting the potential of the gate terminal;
A delay circuit for delaying the output of the first inverter circuit;
A NOR circuit that inputs an output potential of the delay circuit and an output potential of the first inverter circuit to perform a NOR operation, and an output potential obtained as a result controls the second switch circuit;
A second inverter circuit that inverts the output of the NOR circuit, and the resulting output potential controls the first switch circuit;
The level shift circuit according to appendix 1, which includes:
(Appendix 6)
The switch control circuit includes:
A first inverter circuit for inverting the potential of the gate terminal;
A delay circuit for delaying the output of the first inverter circuit;
An OR circuit that inputs an output potential of the delay circuit and an output potential of the first inverter circuit to perform an OR operation, and an output potential obtained as a result controls the first switch circuit;
A second inverter circuit that inverts the output of the OR circuit, and the resulting output potential controls the second switch circuit;
The level shift circuit according to appendix 1, which includes:
(Appendix 7)
An A / D converter equipped with the level shift circuit according to any one of appendices 1 to 6.
(Appendix 8)
A wireless communication device equipped with the level shift circuit according to any one of appendices 1 to 6.

  The disclosed technology is an interface circuit for transmitting a pulse signal from a circuit operating at a low voltage to a circuit operating at a high voltage in a mixed signal circuit such as an ADC (analog-digital converter) circuit or a PLL (phase-locked loop) circuit. Can be used as

101 Substrate Potential Control Circuit 102 Switch Control Circuit 201, 401, 404, 602, 606 Delay Circuit 202, 203, 403, 406, 601, 604, 605, 608, INV1-4 Inverter Circuit 402 NAND Circuit 405 AND Circuit 603 NOR Circuit 607 OR circuit 901 level shift circuit 902 analog circuit 902-1 analog signal processing circuit 902-2 comparator 903 digital circuit 903-1 encoder logic 903-2 clock buffer 903-3 switch control signal generation circuit 1001 A / D converter 1002 Antenna 1003 RF front-end circuit 1003-1 LNA (low noise amplifier)
1003-2 filter 1003-3 frequency conversion circuit 1004 digital baseband signal processing circuit MN1, MN2 NMOS transistor MP1, MP2 PMOS transistor SW1, SW2 switch

Claims (5)

Two NMOS transistors that supply inverted and non-inverted signals of low voltage amplitude pulse signals to each gate terminal and operate in opposite phases to each other, and a PMOS for amplifying the potential difference between the drain terminals of the two NMOS transistors In a level shift circuit including a positive feedback circuit having a cross-coupled configuration of transistors,
Provided for at least one of the NMOS transistors,
A first switch circuit for conducting a gate terminal and a substrate terminal of the NMOS transistor;
A second switch circuit for conducting the substrate terminal to a low level potential;
The first switch circuit is turned on and the second switch circuit is turned off for a period when the gate terminal is at the low level potential and for a predetermined period after the low level potential is changed to the high level potential. A period in which the first switch circuit is turned off and the second switch circuit is turned on after the predetermined period, and at least the potential of the gate terminal is the high-level potential. Is a switch control circuit for setting the first switch circuit to a non-conductive state and controlling the second switch circuit to a conductive state;
A level shift circuit comprising: The switch control circuit includes:
A delay circuit for delaying the potential of the gate terminal;
A first inverter circuit that inverts the output potential of the delay circuit, and the resulting output potential controls the first switch circuit;
A second inverter circuit that further inverts the output potential of the first inverter circuit, and the resulting output potential controls the second switch circuit;
The level shift circuit according to claim 1, comprising: The switch control circuit includes:
A delay circuit for delaying the potential of the gate terminal;
A NAND circuit that inputs an output potential of the delay circuit and a potential of the gate terminal to perform a NAND operation, and an output potential obtained as a result controls the first switch circuit;
An inverter circuit that inverts an output of the NAND circuit, and an output potential obtained as a result controls the second switch circuit;
The level shift circuit according to claim 1, comprising:   An A / D conversion device on which the level shift circuit according to any one of claims 1 to 3 is mounted.   A wireless communication device equipped with the level shift circuit according to any one of claims 1 to 3.