JP2010165334A - High-level synthesis apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically execute latency adjustment between modules when the latency of a certain module is changed when constituting a plurality of modules. <P>SOLUTION: A high-level synthesis apparatus 1 performs high-level synthesis processing by inputting behavioral description to output HDL description. The high-level synthesis apparatus is provided with: a latency adjustment path specification part 201 which specifies a latency adjustment part in the behavioral description; a latency adjustment path extraction part 202 which extracts a connection relation between an input and an output from the specified latency adjustment part to input and the modules; a behavioral synthesis part 203 which executes the behavior synthesis of the extracted modules; a latency information extraction part 204 which extracts latency information about each module according to results of the behavior synthesis part 203; a latency calculation part 205 which calculates a latency value inserted into the specified latency adjustment part on the basis of the extracted latency information; and a latency insertion part 206 which inserts the calculated latency value into the HDL description. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a high-level synthesis apparatus, method, and program, and in particular, a technique for analyzing module latency in a behavioral description during high-level synthesis and automatically adjusting the latency method between modules and optimizing module throughput. About.

  High-level synthesis is a C-based circuit design technique. C language-based design has higher description abstraction than conventional HDL (Hardware Description Language) such as Verilog / VHDL, and is expected to improve design efficiency. In high-level synthesis design, module latency (delay from input to output) can be designed by directives (specified in the source code). When reusing with frequency up, a module that satisfies the target specification (latency) can be automatically generated without much effort. However, reuse by frequency up may not meet the target specifications due to the influence of the gate size / timing of the module. If the target specification cannot be met, redesign of the latency (directive redesignation) is required.

  Japanese Patent Application Laid-Open No. H10-228561 describes that the latency is adjusted between threads in a module “in” and the throughput is optimized. However, it is not disclosed to adjust the latency between modules “between” and optimize the throughput.

  Latency redesign affects the latency adjustment between modules when a plurality of modules are configured. (See FIG. 48) In high-level synthesis design, when modules A, B, and C are separately high-level synthesized, arrival times (X ′, Y ′) from inputs X and Y to D must be aligned by hand design. When the latency of a module is changed at the time of reuse, it is necessary to manually adjust the latency between modules, which is troublesome.

  In view of the above circumstances, the present invention provides a high-level synthesis apparatus, method, and program capable of automatically performing latency adjustment between modules when the latency of a certain module is changed when a plurality of modules are configured. The purpose is to do.

  In order to achieve the above object, a high-level synthesis apparatus, method, and program characterized by the following configurations are provided.

  A high-level synthesis apparatus according to the present invention is a high-level synthesis apparatus that inputs a behavioral description, performs high-level synthesis processing, and outputs an HDL description, and is designated with latency adjustment path designation means for designating a latency adjustment location in the behavioral description. Based on the results of the behavioral synthesis means, the latency adjustment path extraction means for extracting the input / output connection relationship from the latency adjustment location to the input and the module, the behavioral synthesis means for performing behavioral synthesis of the extracted module Latency information extraction means for extracting module latency information, latency calculation means for calculating a latency value to be inserted into the designated latency adjustment location based on the extracted latency information, and the calculated latency value in HDL description And a latency insertion means for inserting into the.

  The high-level synthesis method according to the present invention is a high-level synthesis method using a computer that inputs a behavioral description, performs high-level synthesis processing, and outputs an HDL description, and specifies a latency adjustment path designation that specifies a latency adjustment location in the behavioral description. A latency adjustment path extraction step for extracting a module, a connection relationship of input / output from a specified latency adjustment location to an input, a behavior synthesis step for performing behavior synthesis of the extracted module, and the behavior synthesis step A latency information extracting step for extracting latency information of each module based on the result, a latency calculating step for calculating a latency value to be inserted into the designated latency adjustment location based on the extracted latency information, and a calculated A latency insertion step of inserting a latency value into the HDL description, and That.

  The high-level synthesis program according to the present invention is a latency adjustment path that extracts a latency adjustment path designation means for designating a latency adjustment location in a behavioral description, and an input / output connection relationship and module from the designated latency adjustment location to an input. Path extraction means, behavior synthesis means for performing behavioral synthesis of the extracted modules, latency information extraction means for extracting latency information of each module based on the result of the behavioral synthesis means, and based on the extracted latency information The latency calculation means for calculating the latency value to be inserted into the designated latency adjustment location and the latency insertion means for inserting the calculated latency value into the HDL description, and the behavioral description is input to perform high-level synthesis processing. To function as a high-level synthesis device that outputs HDL descriptions And wherein the door.

  According to the present invention, it is possible to provide a high-level synthesis apparatus, method, and program capable of automatically performing latency adjustment between modules when the latency of a certain module is changed when a plurality of modules are configured. It becomes possible.

It is a figure which shows the example of an external appearance of the high level synthesis | combination apparatus which concerns on each embodiment of this invention. It is a block diagram which shows the structural example of the high level synthesis | combination apparatus which concerns on each embodiment of this invention. It is a figure which shows the concept of the circuit to which Embodiment 1 of this invention is applied. It is a block diagram which shows the function structure of Embodiment 1 of this invention. FIG. 5 is a block diagram illustrating a functional configuration of a latency calculation unit 205 in FIG. 4. FIG. 6 is a diagram (part 1) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. FIG. 6 is a diagram (part 2) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. FIG. 6 is a diagram (part 1) illustrating a high-level synthesis result example (corresponding to the HDL description in FIG. 4) according to the first embodiment of the present invention; FIG. 6 is a diagram (part 2) illustrating a high-level synthesis result example (corresponding to the HDL description in FIG. 4) according to the first embodiment of the present invention; It is a flowchart which shows the procedure of the high level synthesis process of Embodiment 1 of this invention. It is a figure which shows the example which designates a delay adjustment point in Embodiment 1 of this invention. It is a figure which shows the example of the log result which the behavioral synthesis part 203 of Embodiment 1 of this invention produced | generated. It is a figure which shows the example of the latency information extracted by the latency information extraction part 204 of Embodiment 1 of this invention linked | related with the circuit conceptual diagram of FIG. It is a flowchart which shows the detailed procedure (equivalent to step S5 of FIG. 10) of the latency calculation process of Embodiment 1 of this invention. It is a figure which shows the example of the result of the latency calculation process of Embodiment 1 of this invention linked | related with the circuit conceptual diagram of FIG. It is a figure which shows the concept of the circuit obtained as a result of the high-level synthesis process by Embodiment 1 of this invention. It is a figure for demonstrating the deformation | transformation embodiment of Embodiment 1 of this invention. It is a figure which shows the concept of the circuit to which Embodiment 2 of this invention is applied. FIG. 19 is a diagram (part 1) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. 18 is behaviorally described; FIG. 19 is a diagram (part 2) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. 18 is behaviorally described. It is a figure which shows the example of a high level synthesis result (equivalent to the HDL description of FIG. 4) by Embodiment 2 of this invention. It is a flowchart which shows the procedure of the high level synthetic | combination process of Embodiment 2 of this invention. It is a figure which shows the example which designates a delay adjustment point in Embodiment 2 of this invention. It is a flowchart which shows the detailed procedure (equivalent to step S2a of FIG. 22) of the extraction process of the latency adjustment path of Embodiment 2 of this invention. It is a figure for demonstrating the example of an extraction result of the extraction process of the latency adjustment path | pass of Embodiment 2 of this invention. It is a figure which shows the example of the log result which the behavioral synthesis part 203 of Embodiment 2 of this invention produced | generated. It is a figure which shows the example of the latency information extracted by the latency information extraction part 204 of Embodiment 2 of this invention linked | related with the circuit conceptual diagram of FIG. It is a flowchart which shows the detailed procedure (equivalent to step S5a of FIG. 22) of the latency calculation process of Embodiment 2 of this invention. FIG. 19 is a diagram (part 1) illustrating an example of a result of latency calculation processing according to the second embodiment of the present invention in association with the circuit conceptual diagram of FIG. 18; FIG. 19 is a diagram (part 2) illustrating an example of a result of latency calculation processing according to the second embodiment of the present invention in association with the circuit conceptual diagram of FIG. 18; It is a figure which shows the concept of the circuit obtained as a result of the high-level synthesis process by Embodiment 2 of this invention. It is a figure which shows the concept of the circuit to which Embodiment 3 of this invention is applied. FIG. 33 is a diagram (part 1) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. 32 is behaviorally described; FIG. 33 is a diagram (part 2) illustrating an example (corresponding to the behavioral description of FIG. 4) in which the circuit concept of FIG. 32 is behaviorally described. It is a figure which shows the example of a high level synthesis result (equivalent to the HDL description of FIG. 4) by Embodiment 3 of this invention. It is a flowchart which shows the procedure of the high level synthetic | combination process of Embodiment 3 of this invention. It is a figure which shows the example which designates a delay adjustment point in Embodiment 3 of this invention. It is a flowchart which shows the detailed procedure (equivalent to step S2b of FIG. 36) of the extraction process of the latency adjustment path | pass of Embodiment 3 of this invention. It is a figure for demonstrating the example of an extraction result of the extraction process of the latency adjustment path | pass of Embodiment 3 of this invention. It is a figure which shows the example of the log result which the behavioral synthesis part 203 of Embodiment 3 of this invention produced | generated. It is a figure which shows the example of the latency information extracted by the latency information extraction part 204 of Embodiment 3 of this invention linked | related with the circuit conceptual diagram of FIG. It is a flowchart which shows the detailed procedure (equivalent to step S5b of FIG. 36) of the latency calculation process of Embodiment 3 of this invention. (Equivalent to FIG. 28) It is a figure which shows a part of result of the latency calculation process of Embodiment 3 of this invention linked | related with the circuit conceptual diagram of FIG. It is a flowchart which shows the detailed procedure (equivalent to step S6b of FIG. 36) of the latency insertion process of Embodiment 3 of this invention. It is a figure which shows the example of the result of the latency calculation process of Embodiment 3 of this invention linked | related with the circuit conceptual diagram of FIG. It is a figure which shows the concept of the circuit obtained as a result of the high-level synthesis process by Embodiment 3 of this invention. It is a figure which shows the example of the result of the latency insertion when not implementing Embodiment 3 of this invention linked with the circuit conceptual diagram of FIG. It is a figure for demonstrating the conventional high level synthetic | combination process.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an external appearance example of a high-level synthesis apparatus according to each embodiment of the present invention. The high-level synthesis device includes a computer main body, a graphic display device, a keyboard, a mouse, a CD-ROM device to which a CD-ROM (Compact Disc-Read Only Memory) is mounted, and a network. The high-level synthesis program is supplied by a storage medium such as a CD-ROM. The high-level synthesis program is executed by the computer main body, and the operator performs high-level synthesis by operating the keyboard or mouse while looking at the graphic display device. Further, the high-level synthesis program may be supplied to the computer main body via a network from another computer via a communication line.

  FIG. 2 is a block diagram illustrating a configuration example of the high-level synthesis apparatus according to each embodiment of the present invention. The computer main body shown in FIG. 2 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and a hard disk. The CPU performs processing while inputting / outputting data to / from a graphic display device, keyboard, mouse, CD-ROM device, network device, ROM, RAM, or hard disk. The high-level synthesis program recorded on the CD-ROM is temporarily stored in the hard disk by the CPU via the CD-ROM device. The CPU performs high-level synthesis by appropriately loading a high-level synthesis program from the hard disk into the RAM and executing it.

  The high level synthesis apparatus in each embodiment will be described below, but the appearance of the high level synthesis apparatus shown in FIG. 1 and the configuration of the high level synthesis apparatus shown in FIG. 2 are common to each embodiment.

(Embodiment 1)
In the first embodiment, the circuit (concept) shown in FIG. 3 is taken as an example, and it is assumed that the latency of each module is changed by reusing the modules A, B, C, and D by increasing the frequency, and the latency adjustment between modules is adjusted This is an example in which (the delay adjustment of outB and outC) is performed by the above-described high-level synthesis apparatus.

  FIG. 4 is a functional block diagram showing a schematic configuration of the high-level synthesis apparatus according to Embodiment 1 of the present invention. As illustrated, the high-level synthesis apparatus 1 includes a latency adjustment path designation unit 201, a latency path extraction unit 202, a behavior synthesis unit 203, a latency information extraction unit 204, a latency calculation unit 205, and a latency insertion unit 206. Hereinafter, each part will be described.

The latency adjustment path designation unit 201 designates a latency adjustment location in the behavioral description.
The latency adjustment path extraction unit 202 extracts input / output connection relationships and modules from the latency adjustment location to the input.
The behavioral synthesis unit 203 performs behavioral synthesis of each connection module.

The latency information extraction unit 204 extracts the latency information of each module from the result of the behavioral synthesis unit 203.
The latency calculation unit 205 calculates the latency to be inserted into the adjustment point based on the result of the latency information extraction unit 204.

The latency insertion unit 206 inserts the latency value calculated by the latency calculation unit 205 into the HDL description. Note that the following three methods are effective as an insertion mode. First, a method of inserting an FF corresponding to the delay adjustment value between modules, second, a method of inserting a delay corresponding to the delay adjustment value to the output of the preceding module, and third, an amount corresponding to the delay adjustment value to each input port of the subsequent module This is a method of inserting a delay.
Next, the latency calculation unit 205 will be described in more detail with reference to the detailed functional block of FIG.

  FIG. 5 is a functional block diagram of the latency calculation unit 205. The “latency total calculation unit” 205 a totals the latencies of the modules on each pass extracted by the latency adjustment path extraction unit 204. The maximum latency calculation unit 205b calculates the maximum value of each path calculated by the “total latency calculation unit for each path” 205a. The latency insertion value calculation unit 205c calculates a latency value to be inserted into each path based on the maximum latency calculated by the maximum latency calculation unit 205b.

FIGS. 6 and 7 are examples in which the circuit concept of FIG. 3 is described by system C (corresponding to “operation description” in FIG. 4).
module_top.h / .cc describes I / O definitions (IN1, IN2, OUT) of modules and connections between modules.
module _ *. h / .cc (* indicates A, B, C, D) describes the I / O definition of modules A, B, C, D and the operation of each module.
“META” described in the operation description is a declaration that summarizes the data and multiple I / F control signals (META is a SysemC description method that allows user-defined control signals including names).
Note that descriptions relating to descriptions not related to the present invention are omitted.

FIGS. 8 and 9 are examples of results obtained by high-level synthesis of the behavioral descriptions of FIGS. 6 and 7 by the high-level synthesis apparatus 1 of this embodiment (corresponding to “HDL description” in FIG. 4). In the high-level synthesis apparatus 1 of the present embodiment, the example is generated by Verilog-HDL.
module_top.v describes module I / O (IN1, IN2, OUT) and describes connections between modules.
module_A to Dv describe the operation of each module in HDL.
According to this embodiment, “module_2delay C_delay” described in module_top.v is automatically inserted.
Also, module_2delay.v is automatically generated (conventionally, it is analyzed by analyzing the delay between modules and manually inserting it).
Note that descriptions relating to descriptions not related to the present invention are omitted.

  Next, the processing procedure of the high-level synthesis apparatus 1 of this embodiment will be described using the flowchart of FIG.

  S1: A delay adjustment point (ADJUST (...)) is specified in module_top.h (an example in which a delay adjustment point is specified is shown in FIG. 11. The following description is based on the example shown in FIG. 11). In this embodiment, the latency adjustment point is designated by the latency adjustment path designation means as a manually selected point. The argument describes the signal whose latency is to be adjusted. Any number can be described, but in this explanation example, it is assumed to be 2 (outB, outC).

S2: The latency adjustment path extraction unit 202 extracts the input / output connection relationship from the signals outB, outC to the inputs (IN1, IN2) and modules described in the argument of ADJUST.
In the case of this example,
PassE: outB ← (moduleB) ← outA ← (moduleA) ← IN1
PassF: outC ← (moduleC) ← IN2
Is extracted.

  S3: The behavioral synthesis unit 203 performs behavioral synthesis of modules A to D. Verilog-HDL is generated. FIG. 12 shows an example of the generated Verilog-HDL.

S4: The latency information extraction unit 204 extracts the latency information from the log result of the behavioral synthesis unit 203 (see FIG. 13). In FIG. 13, the circuit conceptual diagram of FIG. Attached).
moduleA_Latency = 1
moduleB_Latency = 3
moduleC_Latency = 2
moduleD_Latency = 1

S5: The latency value to be inserted into PassE and PassF is calculated based on the latency information extracted in S4. This will be described with reference to FIG. FIG. 14 is a detailed flow of S5.
S5-1: Sum the latency of modules on each pass
Pass_E Latency = moduleA Latency + moduleB Latency = 1 + 3 = 4
Pass_F Latency = moduleC_Latency = 2
S5-2: Calculate the maximum latency for each pass
Max_Latency = (Pass_E Latency, Pass_F Latency) = 4
S5-3: Calculate the latency insertion value of each pass from the maximum latency value.
Adjust_E_Latency = Max_Latency-Pass_E_Latency = 4-4 = 0
Adjust_F_Latency = Max_Latency-Pass_F_Latency = 4-2 = 2
By S5, 2CLK Delay is inserted into Pass_F (see FIG. 15).

S6: The latency value calculated in S5-3 is inserted into the HDL of FIG. 12 (see FIGS. 8 and 9).
A 2CLK delay is inserted into Pass_F.
The module “module_2delay” generated by the high-level synthesizer is inserted after the output of module C in module_top.v (outC). The output (outC_2d) of “module_2delay” is connected to the input of module D.
FIG. 16 shows a circuit generated based on the processing result (see FIGS. 8 and 9) according to the present embodiment. The circuit shown in FIG. 16 is mounted on the device.

  According to the embodiment, it is possible to calculate a latency adjustment value between modules from the behavioral synthesis results (latency information) of the modules A, B, C, and D and insert them into HDL without human intervention. .

  In the above embodiment, the extraction of latency information is extracted from the behavioral synthesis log result, but it is also possible to extract latency information from directive information specified on the source code at the time of design. FIG. 17 shows an example in which a directive (LATENCY (3): latency 3) is inserted into module B.

(Embodiment 2)
In the second embodiment, the circuit (concept) shown in FIG. 18 is taken as an example, and latency adjustment between modules (delay adjustment of outB and outE) when there is a branch between the latency adjustment paths is shown in FIGS. This is an example implemented in the high-level synthesis apparatus 1. Note that the schematic configuration of the high-level synthesis apparatus 1 according to the second embodiment is the same as that of the first embodiment (FIGS. 4 and 5), and is omitted.

FIGS. 19 and 20 are examples in which the circuit concept of FIG. 18 is described in systemC (corresponding to “operation description” in FIG. 4).
module_top.h / .cc describes I / O definitions (IN1, IN2, OUT) of modules and connections between modules.
module _ *. h / .cc (* indicates A, B, C, D, E, F) describes the I / O definition of modules A, B, C, D, E and the operation of each module It is.
“META” described in the operation description is a declaration that summarizes the data and multiple I / F control signals (META is a SysemC description method that allows user-defined control signals including names).
There are two module_D outputs in module_top.h (outD1, outD2), but this is a restriction on SystemC description.
outD1 and outD2 are outputs of the same value at the same timing.
Note that descriptions relating to descriptions not related to the present invention are omitted.

FIG. 21 is an example of the high-level synthesis result by the high-level synthesis apparatus 1 of the present embodiment for the behavioral descriptions of FIGS. 19 and 20 (corresponding to “HDL description” in FIG. 4). In the high-level synthesis apparatus 1 of the present embodiment, the example is generated by Verilog-HDL.
module_top.v describes module I / O (IN1, IN2, OUT) and describes connections between modules.
module_A to Fv describe the operation of each module in HDL.
According to this embodiment, “module_3delay A_delay” and “module_2delay B_delay” described in module_top.v are automatically inserted.
Also, module_2delay.v and module_3delay.v are automatically generated (conventionally, the delay between modules is analyzed and manually inserted)
Note that descriptions relating to descriptions not related to the present invention are omitted.

  The processing procedure of the high-level synthesis apparatus of the present invention will be described using the functional flowchart of FIG. Although the processing procedure of the first embodiment shown in FIG. 10 is almost the same, the latency adjustment path extraction processing and the latency calculation processing are different.

  S1: A delay adjustment point (ADJUST (...)) is specified in module_top.cc (an example in which a delay adjustment point is specified is shown in FIG. 23. The following description is based on the example shown in FIG. 23). In this embodiment, the latency adjustment point is designated by the latency adjustment path designation means as a manually selected point. The argument describes the signal whose latency is to be adjusted. Any number can be described, but in this embodiment, two (outB, outE).

S2a: The functional flow of the latency adjustment path extraction unit 202 is shown in FIG. If there is a path branch in the path extraction process, the latency of the branch point is adjusted.
S2a-1: Extracts input / output connection relations and modules from signals outB and outE to inputs (IN1 and IN2) described in the argument of ADJUST. In this case, connection relationships and modules as shown in FIG. 25 are extracted.
S2a-2: It is determined whether there is a branch path in the path. In this illustrative example based on FIG. 23, since there is a branch path in module_B of PassE, the process proceeds to S2a-3 and the module_B branch path latency adjustment priority flag is asserted (module_B_pri_adjust = 1).

  S3: The behavioral synthesis unit 203 performs behavioral synthesis of modules A to F. Verilog-HDL is generated. FIG. 26 shows an example of the generated Verilog-HDL.

S4: The latency information extraction unit 204 extracts the latency information from the log result of the behavioral synthesis unit 203 (see FIG. 27. In FIG. 27, the circuit conceptual diagram of FIG. Attached).
moduleA_Latency = 1
moduleB_Latency = 2
moduleC_Latency = 3
moduleD_Latency = 1
moduleE_Latency = 4
moduleF_Latency = 2

S5a: The functional flow of the latency path calculation unit 205 is shown in FIG.
S5a-1: If the branch path flag indicating that there is a path branch in the extraction process is asserted, the latency of the branch point is adjusted. In this illustrative example based on FIG. 23, since the module_B branch path latency adjustment priority flag of PassE is asserted in S2a-2 (module_B_pri_adjust = 1), the latency adjustment of the module_B input point is performed. Proceed to S5a-2.

S5a-2: Calculate the total latency from the branch path (module_B) to the input.
Pass_B_IN1 Latency = moduleA Latency = 1
Pass_B_IN2 Latency = moduleD_Latency + moduleC_Latency = 1 + 3 = 4

S5a-3: Calculate the maximum latency of the branch pass.
Max_Latency = (Pass_B_IN1 Latency, Pass_B_IN2 Latency) = 4

S5a-4: Calculate the latency value of the branch pass.
Adjust_B_IN1 Latency = Max_Latency-Pass_B_IN1 Latency = 4-1 = 3
Adjust_B_IN2 Latency = Max_Latency-Pass_B_IN2 Latency = 4-4 = 0
Return to S5a-1.
From S5a-4, 3CLK Delay is inserted into Pass_B_IN1 (see FIG. 29).

S5a-5: Clear the branch path flag. (module_B_pri_adjust = 0)
Return to S5a-1.
S5a-1: Since the branch path flag is not asserted, the process proceeds to S5a-6.

S5a-6: Sum the latency of modules on each pass. At this time, the latency value (Adjust_B_IN1 Latency) calculated in S5a-3 is also included.
Pass_E Latency = moduleA Latency + moduleB Latency + Adjust_B_IN1 Latency = 1 + 2 + 3 = 6
Pass_F Latency = moduleC_Latency + moduleD_Latency + moduleE_Latency = 3 + 1 + 4 = 8

S5a-7: Calculate the maximum latency for each pass.
Max_Latency = (Pass_E Latency, Pass_F Latency) = 8

S5a-8: The latency insertion value of each pass is calculated from the maximum latency value.
Adjust_E_Latency = Max_Latency-Pass_E_Latency = 8-6 = 2
Adjust_F_Latency = Max_Latency-Pass_F_Latency = 8-8 = 0
With S5a-8, 2CLK Delay is inserted into Pass_E (see FIG. 30).

S6: The latency value calculated in S5a-4 / S5a-8 is inserted into the HDL in FIG. 26 (see FIG. 21).
The module “module_3delay” generated by the high-level synthesis apparatus 1 is inserted after the module A output (outA) of module_top.v.
The output (outA_3d) of “module_3delay” is connected to the input of module B.
In addition, “module_2delay” is inserted after the output (outB) of module B of module_top.v.
The output (outB_2d) of “module_2delay” is connected to the input of module F.
FIG. 31 shows a circuit generated based on the processing result (see FIG. 21) according to the present embodiment. The circuit shown in FIG. 31 is mounted on the device.

  According to the above embodiment, latency adjustment between modules constituted by modules having a plurality of inputs can be automated.

  In the above-described embodiment, the extraction of latency information is extracted from the behavioral synthesis log result. However, the latency information can be extracted from directive information specified on the source code at the time of design.

(Embodiment 3)
In the third embodiment, taking the circuit (concept) shown in FIG. 32 as an example, latency adjustment between modules (delay adjustment of outA and outB) when there is a branch (x) in the final module output of the latency adjustment point is shown in FIG. This is an example implemented by the high-level synthesis apparatus 1 shown in FIG. Note that the schematic configuration of the high-level synthesis apparatus 1 according to the third embodiment is the same as that of the first embodiment (FIGS. 4 and 5), and is omitted.

FIGS. 33 and 34 are examples in which the circuit concept of FIG. 32 is described by systemC. (Corresponds to the “behavior description” in FIG. 4).
module_top.h / .cc describes I / O definitions (IN1, IN2, OUT) of modules and connections between modules.
module _ *. h / .cc (* indicates A, B, and C) describes the I / O definitions of modules A, B, and C, and the operation of each module.
“META” described in the operation description is a declaration that summarizes the data and multiple I / F control signals (META is a SysemC description method that allows user-defined control signals including names).
There are two outputs of module_B in module_top.h (outD1, outD2), but this is a restriction on SystemC description. outB1 and outB2 are outputs of the same value at the same timing.
Note that descriptions relating to descriptions not related to the present invention are omitted.

FIG. 35 is an example of the result of high-level synthesis by the high-level synthesis apparatus 1 of the present embodiment for the behavioral descriptions of FIGS. 33 and 34 (corresponding to “HDL description” in FIG. 4). In the high-level synthesis apparatus 1 of the present embodiment, the example is generated by Verilog-HDL.
module_top.v describes module I / O (IN1, IN2, OUT) and describes connections between modules.
module_A to Cv describe the operation of each module in HDL.
According to this embodiment, `` module_2delay IN1_delay '' and `` module_3delay B_delay '' described in module_top.v are automatically inserted and module_2delay.v and module_3delay.v are automatically generated. (It will be implemented by insertion.)
Further, a branch signal “branch_B” of module_B output is automatically generated (circled number 1 in FIG. 35), and “branch_B” is automatically connected to din2 of module_A (circled number 2 in FIG. 35). The module_A input latency adjustment is guaranteed by connecting the module_B output branch_B (= out_B) without connecting the module_3delay B_delay output (outB_3d) to module_B.
Note that descriptions relating to descriptions not related to the present invention are omitted.

  The processing procedure of the high-level synthesis apparatus of this embodiment will be described with reference to the function flowchart of FIG. Although the processing procedure of the second embodiment shown in FIG. 22 is almost the same, the latency adjustment path extraction processing (step S2b) is different from the latency insertion processing (step S6b).

  S1: A delay adjustment point (ADJUST (...)) is specified in module_top.cc (an example in which a delay adjustment point is specified is shown in FIG. 37. The following description is based on the example shown in FIG. 37). In this embodiment, the latency adjustment point is designated by the latency adjustment path designation means as a manually selected point. The argument describes the signal whose latency is to be adjusted. Any number can be described, but in this embodiment, two (outA, outB).

S2b: The functional flow of the latency adjustment path extraction unit 202 is shown in FIG. If there is a path branch in the path extraction process, the latency of the branch point is adjusted. Furthermore, the presence or absence of a branch path is found in the final output module of the latency adjustment point.
S2b-1: (The mechanism is the same as in the second embodiment.) The input / output connection relationship and the module from the signals outA, outB to the input (IN1, IN2) described in the argument of ADJUST are extracted. In this case, connection relationships and modules as shown in FIG. 39 are extracted.
S2b-2: (The mechanism is the same as in the second embodiment.) It is determined whether there is a branch path in the path. In this illustrative example based on FIG. 36, since there is a branch path in module_A of PassE, the process proceeds to S2a-3 and the module_A branch path latency adjustment priority flag is asserted (module_A_pri_adjust = 1).
S2b-4: It is determined whether the branch path does not walk to the final output module of the latency adjustment point (outA, outB). In the present explanation example based on FIG. 36, since there is a branch path at the adjustment point outB of PassF, the process proceeds to S2a-5 and the outB branch path flag is asserted (out_B_branch = 1).

  S3: The behavioral synthesis unit 203 performs behavioral synthesis of modules A to C. Verilog-HDL is generated. FIG. 40 shows an example of the generated Verilog-HDL.

S4: The latency information extraction unit 204 extracts latency information from the log result of the behavioral synthesis unit 203 (see FIG. 41. Note that in FIG. 41, the circuit conceptual diagram of FIG. 32 and the log result are linked for easy understanding. Attached).
moduleA_Latency = 3
moduleB_Latency = 2
moduleC_Latency = 3

S5: The functional flow of the latency path calculation unit 205 is shown in FIG. (Same as FIG. 28 in the second embodiment)
S5-1: If the branch path flag indicating that there is a path branch in the extraction process is asserted, the branch point latency is adjusted. In this illustrative example based on FIG. 32, since the module_A branch path latency adjustment priority flag of PassE is asserted in S2a-2 (module_A_pri_adjust = 1), the latency adjustment of the module_A input point is performed. Proceed to S5-2.

S5a-2: Calculate the total latency from the branch path (module_A) to the input.
Pass_A_IN1 Latency = 0
Pass_A_IN2 Latency = moduleB_Latency = 2

S5a-3: Calculate the maximum latency of the branch pass.
Max_Latency = (Pass_A_IN1 Latency, Pass_A_IN2 Latency) = 2

S5-4: Calculate the latency value of the branch pass.
Adjust_A_IN1 Latency = Max_Latency-Pass_A_IN1 Latency = 2-0 = 2
Adjust_A_IN2 Latency = Max_Latency-Pass_A_IN2 Latency = 2-2 = 0
Return to S5-1.
From S5-4, 2CLK Delay is inserted into Pass_A_IN1 (see FIG. 43).

S5a-5: Clear the branch path flag. (module_A_pri_adjust = 0)
Return to S5a-1.
S5-1: Since the branch path flag is not asserted, the process proceeds to S5-6.

S5a-6: Sum the latency of modules on each pass. At this time, the latency value (Adjust_A_IN1 Latency) calculated in S5-3 is also included.
Pass_E Latency = moduleA Latency + Adjust_B_IN1 Latency = 3 + 2 = 5
Pass_F Latency = moduleB_Latency = 2

S5-7: Calculate the maximum latency for each pass.
Max_Latency = (Pass_E Latency, Pass_F Latency) = 5

S5-8: The latency insertion value of each pass is calculated from the maximum latency value.
Adjust_E_Latency = Max_Latency-Pass_E_Latency = 5-5 = 0
Adjust_F_Latency = Max_Latency-Pass_F_Latency = 5-2 = 3
With S5-8, 3CLK Delay is inserted into Pass_F (the insertion position will be described later).

S6b: The functional flow of the latency insertion unit 206 is shown in FIG.
In this embodiment, the latency value calculated in S5-4 / S5-8 is inserted into the HDL in FIG.
If the final output branch path flag is asserted, a branch path path is generated from the final module output path, and the branch path path is connected to the branch destination module. The latency value calculated in S5-4 is asserted by the final output branch path flag. FIG. 45 shows a state in which the latency calculated in S5-4 and S5-8 in the circuit (concept) shown in FIG. 32 is inserted.
The latency insertion flow calculated in S5-4 is shown below.

S6b-1: Since the latency final output branch path flag calculated in S5-8 is asserted, the process proceeds to S6b-2.
S6b-3: A branch path path (branch_B) is generated from the last module (module_B) output (outB) path at the latency insertion position to be inserted in S5-8. (Refer to the circled number 1 in Fig. 35 for the generated state)
S6b-4: Connect the branch path (branch_B) to the branch destination module (module_A) for connection. (Refer to circled number 2 in Fig. 35 for connection)
S6b-5: Latency “module_3delay B_delay” is inserted after the final module (module_B) output (outB) (see circled numeral 3 in FIG. 35).
The output (outB_3d) of “module_3delay B_delay” is connected to the input of module_C.

  Note that the latency calculated in S5-8 is inserted into the insertion path because the final output branch path flag is not asserted (transition to S6b-2 in S6b-1). (See module_2delay IN1_delay in Figure 35)

  FIG. 46 shows a circuit generated based on the result of the processing according to this embodiment (see FIG. 35). The circuit shown in FIG. 46 is mounted on the device.

  According to the above embodiment, even when there is a branch path to another module (module A) at the adjustment point (outB of module B) of the adjustment path, the latency can be automatically inserted at an appropriate position. (Inappropriate latency insertion example: see Figure 47)

  In the above-described embodiment, the extraction of latency information is extracted from the behavioral synthesis log result. However, the latency information can be extracted from directive information specified on the source code at the time of design.

  According to each embodiment described above, it is possible to automate the redesign of the latency in the high-level synthesis design, particularly when the frequency is reused. That is, it becomes possible to adjust the latency between modules and optimize the throughput.

  Further, according to each of the above embodiments, the latency adjustment path extraction unit 202 extracts a path from the latency adjustment point to the input point, so that it is possible to adjust the latency of an arbitrary point.

  Further, according to each of the above embodiments, latency extraction information is extracted based on at least one of high-level synthesis log results and directive information (specified on the source code at the time of design) when extracting latency information. Therefore, there is an effect that latency information can be obtained from information that can be easily understood by the user.

  Further, according to each of the above embodiments, the latency calculation algorithm becomes easy and the PC load is reduced.

  In addition, according to each of the above embodiments, it is possible to insert latency without human intervention. There is no human connection error.

  Further, according to the second embodiment, it is possible to automate latency adjustment between modules configured by modules having a plurality of inputs. In addition, it is possible to automate latency adjustment between modules configured by modules having a plurality of inputs.

  Further, according to the third embodiment, even when there is a branch path to another module at the adjustment point of the adjustment path, the latency adjustment can be performed while maintaining the input timing of the module connected to the branch path.

DESCRIPTION OF SYMBOLS 1 High level synthetic | combination apparatus 110 Computer main body 120 Network 201 Latency adjustment path designation | designated part 202 Latency adjustment path extraction part 203 Behavior synthesis part 204 Latency information extraction part 205 Latency calculation part 205a Latency total calculation part 205b Maximum latency calculation part 205c Latency Insertion value calculation unit 206 Latency insertion unit

Japanese Patent No. 3763700

Claims (12)

A high-level synthesis device that inputs a behavior description, performs high-level synthesis processing, and outputs an HDL description,
A latency adjustment path designating means for designating a latency adjustment location in the behavioral description;
Latency adjustment path extraction means for extracting input / output connection relationships and modules from the specified latency adjustment location to the input;
Behavioral synthesis means for performing behavioral synthesis of the extracted modules;
Latency information extraction means for extracting latency information of each module based on the result of the behavioral synthesis means;
Latency calculating means for calculating a latency value to be inserted into the designated latency adjustment location based on the extracted latency information;
Latency insertion means for inserting the calculated latency value into the HDL description;
A high-level synthesis apparatus comprising:   The high-level synthesis apparatus according to claim 1, wherein the latency information extraction unit extracts latency information based on at least one of a high-level synthesis log result and directive information. The latency calculation means includes:
Means for calculating the total latency of each path;
Maximum latency calculation means,
Latency insertion value calculation means,
The high-level synthesis apparatus according to claim 1, wherein the high-level synthesis apparatus includes: The means for calculating the total latency of each path is:
4. The high-level synthesis apparatus according to claim 3, wherein a total of module latencies on each path extracted by the latency adjustment path extraction unit is calculated. The means for calculating the total latency of each path is:
5. The high-level synthesis apparatus according to claim 4, wherein, when there is a latency insertion value to be inserted on the path, the total including the latency insertion value is calculated for calculation. The maximum latency calculating means includes:
6. The high-level synthesis apparatus according to claim 3, wherein a maximum value of the latency calculated by the latency total calculation unit of each path is calculated. 7. The latency insertion value calculation means includes:
7. The high level synthesis apparatus according to claim 3, wherein a latency insertion value to be inserted is calculated by subtracting each latency value from the maximum value calculated by the maximum latency calculating means.   8. The multi-input point latency adjustment is preferentially performed when it is determined that there is a multi-input module in the extraction process by the latency adjustment path extracting unit. 9. The high-level synthesizer described. The latency calculation means includes:
9. The latency value is calculated for each branch path when it is determined in the extraction process by the latency adjustment path extraction means that there is a branch path in the output of the last module of the latency adjustment point. The high level synthesis apparatus according to any one of the above. The latency insertion means includes:
If it is determined in the extraction process by the latency adjustment path extraction means that there is a branch path in the output of the final module of the latency adjustment point, a branch path path is generated from the final module output path, and the branch path path is changed to the branch destination module. The high-level synthesis apparatus according to claim 9, wherein the high-level synthesis apparatus is connected. A high-level synthesis method using a computer that inputs a behavior description, performs high-level synthesis processing, and outputs an HDL description.
A latency adjustment pass designating process for designating a latency adjustment location in the behavior description;
Latency adjustment path extraction process for extracting input / output connection relationship and module from specified latency adjustment location to input,
A behavioral synthesis process for performing behavioral synthesis of the extracted modules;
Latency information extraction step of extracting latency information of each module based on the result of the behavioral synthesis step;
A latency calculating step of calculating a latency value to be inserted into the designated latency adjustment location based on the extracted latency information;
A latency insertion step of inserting the calculated latency value into the HDL description;
A high-level synthesis method comprising: Computer
A latency adjustment path designating means for designating a latency adjustment location in the behavioral description;
Latency adjustment path extraction means for extracting input / output connection relationships and modules from the specified latency adjustment location to the input;
Behavioral synthesis means for performing behavioral synthesis of the extracted modules;
Latency information extraction means for extracting latency information of each module based on the result of the behavioral synthesis means;
Latency calculating means for calculating a latency value to be inserted into the designated latency adjustment location based on the extracted latency information;
Function as a latency insertion means for inserting the calculated latency value into the HDL description;
A high-level synthesis program that functions as a high-level synthesis device that inputs an operation description, performs high-level synthesis processing, and outputs an HDL description.

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