JP2010161400A - Semiconductor device and production method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of high performance and low threshold voltage, and its manufacturing method. <P>SOLUTION: The device has: an isolation region which is formed on a substrate and insulates and isolates an NMOS formation region wherein an NMOS transistor is formed and a PMOS formation region wherein a PMOS transistor is formed; a gate insulating film of NMOS and PMOS formed of a High-k material formed on the substrate; an NMOS gate electrode formed on the gate insulating film of the NMOS; a PMOS gate electrode which has a first nickel silicide layer formed on the PMOS gate insulating film and a second nickel silicide layer which is formed on the first nickel silicide layer and is thicker than the first nickel silicide layer and has a larger nickel density than the first nickel silicide layer; and a sidewall spacer which is formed in a sidewall of the NMOS gate electrode and the PMOS gate electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a CMOS type semiconductor device and a manufacturing method thereof.

  In a CMOS type semiconductor device, it is common to use silicon oxide (SiO2) for the gate insulating film, but for high performance, the gate insulating film SiO2 is made thin or the gate insulating film is It is necessary to change to a high dielectric constant material called a so-called High-k material (see the following non-patent document). However, if the SiO2 film, which is a conventional gate insulating film, is made thin, the leakage current through the gate insulating film becomes too large because the film thickness is about 2 nm or less, and there is a limit to using the SiO2 film. .

  On the other hand, dual polysilicon gates have been generally used so far for high integration, low voltage, and high speed operation (see the following patent document). However, the polysilicon gate has a problem of depletion of the gate electrode, and the problem becomes more serious as the gate insulating film becomes thinner. Especially in PMOS, it is especially serious. That is, for the gate electrode, polysilicon doped with boron as an impurity is used, but in addition to the problem that boron is not sufficiently activated, boron diffuses and penetrates through the thin gate insulating film to form a silicon substrate. There arises a problem of being doped to a maximum.

JP 2002-359295 A

2003 Symposium on VLSI Technology Digest of Technical Papers: Fermi Level Pinning at the PolySi / Metal Oxide Interface

  The limit of the thinning of the SiO2 gate insulating film has begun to appear, and attempts have been made to use a high-k material. In this case, however, there is a problem that it is difficult to form a dual polysilicon gate. In other words, this phenomenon is called FermiLevel Pinning.For example, when HfO2 is used as the high-k material, the work function of the N + doped polysilicon gate electrode for NMOS is also the work function of the P + doped polysilicon gate electrode for PMOS. The function also has a value close to the conduction band of silicon, and the difference between the two becomes small. For NMOS, a polysilicon gate electrode is suitable. However, in the case of PMOS, in this case, the threshold value becomes too large and the drive current becomes small.

  Therefore, an object of the present invention is to provide a semiconductor device having high performance (high integration, low voltage, high speed operation) and a low threshold voltage, and a method for manufacturing the same.

  A semiconductor device according to the present invention includes a substrate, an element isolation region formed on the substrate for insulatingly isolating the NMOS formation region where the NMOS transistor is formed and the PMOS formation region where the PMOS transistor is formed, and the substrate. NMOS and PMOS gate insulating films made of a high-k material formed on the NMOS, an NMOS gate electrode made of polysilicon formed on the gate insulating film of the NMOS, and a first gate formed on the PMOS gate insulating film. A first nickel silicide layer, and a second nickel silicide layer formed on the first nickel silicide layer, having a larger film thickness than the first nickel silicide layer, and having a nickel density greater than that of the first nickel silicide layer A PMOS gate electrode, and the NMOS gate electrode and the PMOS gate electrode Characterized in that a sidewall spacer formed on the wall.

  According to a method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation portion on a substrate for insulating and separating an NMOS formation region where an NMOS transistor is formed and a PMOS formation region where a PMOS transistor is formed; A step of forming an insulating film and a polysilicon film thereon, a photoresist is formed on the polysilicon film, patterning is performed, and then anisotropic etching is performed to form gate electrodes and gate insulation of the NMOS and PMOS. Forming a film, forming a silicon oxide film and sidewall spacers on sidewalls of the NMOS and PMOS gate electrodes, and selectively etching the PMOS polysilicon gate electrode to form the PMOS polysilicon gate The film thickness of the electrode is made smaller than that of the NMOS polysilicon gate electrode. And a step of depositing a multilayer film containing Ni on the entire surface of the substrate, silicidizing the upper portion of the polysilicon gate electrode of the NMOS, and silicidizing the entire polysilicon gate electrode of the PMOS. It is characterized by.

  According to the semiconductor device and the manufacturing method thereof of the present invention, an increase in gate leakage current due to the thinning of the gate insulating film is suppressed by using a so-called High-k material for the gate insulating film, and the threshold voltage is increased for both NMOS and PMOS. A PMOS can be set to a low value, and in PMOS, the current drive capability is improved by eliminating the depletion of the gate electrode, and at the same time, the resistance of the source / drain and gate is reduced by silicide, which enables high performance semiconductor devices. realizable.

It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention. It is a manufacturing process figure of the CMOS type semiconductor device concerning the present invention.

  Hereinafter, the best mode of the present invention will be described with reference to the drawings.

  In this embodiment, a hafnium (Hf) or zirconium (Zr) oxide film or a silicate film is used as a gate insulating film formed on a silicon substrate. By using polysilicon for the gate electrode of NMOS, the work function is located close to the conduction band of silicon, and the threshold can be set low. In order to prevent mobility degradation, a silicon oxide (SiO 2) film having a thickness of 2 nm or less may be formed below the Hf or Zr oxide film or the silicate film.

  In the NMOS, polysilicon is used for the gate electrode immediately above the gate insulating film. However, in order to reduce the gate resistance, a silicide layer may be formed on the polysilicon.

  In the PMOS, Ni or Ni silicide is used for the gate electrode immediately above the gate insulating film. The work function of the gate electrode according to the present invention is located near the valence band of silicon, and the threshold value can be set low.

  The manufacturing process will be described below. First, as shown in FIG. 1, after an element isolation region 11 is formed in a silicon substrate 10, a P well 12 is formed in the NMOS region, and an N well 13 is formed in the PMOS region.

  Next, as shown in FIG. 2, an impurity for adjusting a threshold voltage is introduced into each of the P well 12 and the N well 13, and then a gate insulating film 14 is formed. The gate insulating film 14 is made of, for example, a material containing Hf or Zr, HfO2 or ZrO2 formed by MOCVD, or HfSiO4 or ZrSiO4 formed by adding a material containing Si to the material. Can be used. The film thickness is 1.0 to 4.0 nm.

  When these gate insulating films 14 are used, polysilicon having a work function close to the conduction band of silicon can be used as a gate electrode for NMOS. A SiO2 film of 2 nm or less may be formed by thermal oxidation below the HfO2, ZrO2, HfSiO4 or ZrSiO4. Next, the polysilicon 15 is formed on the gate insulating film 14 to a thickness of 100 to 200 nm by LPCVD using SiH4 or SiD4 as a raw material.

  Next, in FIG. 3, gate electrodes 16 and 17 are formed in the PMOS region and the NMOS region, respectively, by patterning the photoresist and anisotropic etching. At that time, the gate insulating film is left only immediately below the gate electrodes 16 and 17.

  Next, as shown in FIG. 4, a silicon oxide film 18 is formed on the entire surface. The silicon oxide film 18 is formed by LPCVD using TEOS as a raw material. The film thickness is 1.0 to 5.0 nm.

  Next, as shown in FIG. 5, an NMOS LDD region 19 and a PMOS LDD region 20 are respectively formed by ion implantation.

  Next, as shown in FIG. 6, after a silicon nitride film is formed by LPCVD, sidewall spacers 21 are formed by etch back.

  Next, as shown in FIG. 7, an NMOS source / drain region 22 and a PMOS source / drain region 23 are formed by ion implantation.

  Next, as shown in FIG. 8, the thickness of the polysilicon of the PMOS gate electrode 24 is made thinner than the thickness of Ni to be formed in a later step by etching.

  Next, after depositing a TiN / Ni laminated film on the entire surface by sputtering, Ni is annealed in a nitrogen atmosphere at 400 to 550 ° C. for several seconds to several tens of minutes, so that Ni is the silicon or gate of the substrate. Ni silicide (NiSi) is formed between the polysilicon of the electrode. At this time, the thickness of Ni to be sputtered is 5 to 20 nm, which is larger than the thickness of the PMOS gate polysilicon.

  Thereafter, the unreacted TiN / Ni remaining is removed with a solution obtained by adding hydrogen peroxide to sulfuric acid or the like. The results are shown in FIG. Ni silicides 25, 26, and 27 are formed in the source / drain regions, the PMOS gate electrode, and the NMOS gate electrode, respectively. In the silicide reaction between Ni and Si, since Ni is a movable atom, excess nickel 28 diffuses to a position just above the gate insulating film in the PMOS gate electrode.

  After this, although not shown in the figure, an insulating film is formed on the entire surface, planarized by CMP treatment, contacts are opened to the source, drain and gate, tungsten is buried, and finally wiring is performed. The CMOS type semiconductor device is completed.

  10 ... silicon substrate, 11 ... element isolation region, 12 ... P well, 13 ... N well, 14 ... gate insulating film, 15 ... polysilicon, 16 ... NMOS gate electrode, 17 ... PMOS gate electrode, 18 ... silicon oxide film , 19 ... NMOS LDD region, 20 ... PMOS LDD region, 21 ... Side wall spacer, 22 ... NMOS source / drain region, 23 ... PMOS source / drain region, 24 ... PMOS gate electrode, 25, 26, 27 ... Nickel silicide (NiSi), 28 ... Nickel (Ni)

Claims (11)

A substrate,
An element isolation region formed on the substrate for insulatingly isolating the NMOS formation region where the NMOS transistor is formed and the PMOS formation region where the PMOS transistor is formed;
NMOS and PMOS gate insulating films made of a High-k material formed on the substrate;
An NMOS gate electrode made of polysilicon formed on the gate insulating film of the NMOS;
A first nickel silicide layer formed on the PMOS gate insulating film; and a first nickel silicide layer formed on the first nickel silicide layer and having a thickness greater than that of the first nickel silicide layer. A PMOS gate electrode having a second nickel silicide layer having a nickel density greater than the layer;
A semiconductor device comprising: a sidewall spacer formed on a sidewall of the NMOS gate electrode and the PMOS gate electrode.   The semiconductor device according to claim 1, wherein a thickness of the PMOS gate electrode is smaller than a thickness of the sidewall spacer.   3. The semiconductor device according to claim 1, wherein a silicon oxide film is formed between the substrate and the gate insulating films of the NMOS and PMOS.   4. The semiconductor device according to claim 1, wherein a silicide layer is formed on the NMOS polysilicon gate electrode.   5. The semiconductor device according to claim 1, wherein the NMOS and PMOS gate insulating films are made of an oxide film or a silicate film of hafnium or zirconium. Forming, on the substrate, an element isolation part for insulating and separating an NMOS formation region in which an NMOS transistor is formed and a PMOS formation region in which a PMOS transistor is formed;
Forming an insulating film and a polysilicon film on the substrate;
Forming a photoresist on the polysilicon film and performing patterning, and then performing anisotropic etching to form the gate electrode and gate insulating film of the NMOS and PMOS; and
Forming a silicon oxide film and sidewall spacers on the sidewalls of the NMOS and PMOS gate electrodes;
Selectively etching the PMOS polysilicon gate electrode to make the thickness of the PMOS polysilicon gate electrode smaller than the thickness of the NMOS polysilicon gate electrode;
Depositing a multilayer film containing Ni on the entire surface of the substrate, silicidizing the upper portion of the NMOS polysilicon gate electrode, and silicidating the entire polysilicon gate electrode of the PMOS. A method of manufacturing a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the thickness of the laminated film is made larger than the thickness of the polysilicon gate electrode in which the thickness of the PMOS is reduced.   The sum of the thickness of the laminated film and the thickness of the polysilicon gate electrode in which the thickness of the PMOS is reduced is smaller than the thickness of the sidewall spacer. A method for manufacturing a semiconductor device according to claim 1.   9. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating film is made of a silicon oxide film and a high-k insulating film.   The method for manufacturing a semiconductor device according to claim 6, wherein the laminated film is a laminated film made of titanium nitride and nickel.   11. The semiconductor according to claim 6, wherein the silicidation process of the NMOS and PMOS polysilicon gate electrodes further includes an annealing process, and the annealing process is performed in a nitrogen atmosphere. Device manufacturing method.

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