JP2010160588A - Semiconductor integrated circuit, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of outputting a signal reduced in the influence of spread spectrum while suppressing the increase of an asynchronous circuit in the case of using a spread spectrum clock signal as an operation signal, and to provide an image forming apparatus. <P>SOLUTION: When the spread spectrum clock signal is used as an operation signal, a correction signal for correcting the influence of spread spectrum is generated from the spread spectrum clock signal and the non-spread spectrum clock signal, and the count value of a counter having a circuit block to which the spread spectrum clock signal is supplied is corrected based on the correction signal so that it is possible to output a signal by reducing the influence of spread spectrum while suppressing the increase of an asynchronous circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit to which a first clock signal that has been spread spectrum and a second clock signal that has not been spread spectrum are supplied, and an image forming apparatus having the semiconductor integrated circuit.

  Conventionally, a spread spectrum clock generator (Spread Spectrum Clock Generator) that spreads the spectrum of the operating clock signal by minutely changing the operating clock signal of the semiconductor integrated circuit to reduce the radiation of the electromagnetic wave and suppress the influence of the radiated electromagnetic field. )It has been known. In a semiconductor integrated circuit having a spread spectrum clock generation circuit, a spread spectrum clock signal is supplied as an operation signal.

  For example, Patent Documents 1 and 2 disclose a technique using a spread spectrum clock signal.

JP 2006-180260 A JP 2008-90774 A

  In the conventional technique, when a circuit block for each function is provided in a semiconductor integrated circuit, a spectrum-spread clock signal is supplied as an operation clock signal to all the circuit blocks. For this reason, the spread spectrum clock signal is also supplied to the circuit block to which the spread spectrum clock signal is not applied, and the output signal of this circuit block is a signal affected by the spread spectrum. The circuit blocks that do not want to apply the spread spectrum clock signal are, for example, an input system circuit block and a circuit block that requires accuracy in output.

  As a means for solving the above problem, there is a method of using a clock signal that is spread spectrum according to the function of the circuit block and a clock signal that is not spread spectrum. However, this method is not preferable because a large number of asynchronous circuits exist in the semiconductor integrated circuit, which increases design, verification man-hours, and circuit scale.

  The present invention has been made in view of the above circumstances, and in the case where a spread spectrum clock signal is used as an operation signal, a signal in which the influence of spread spectrum is reduced while suppressing an increase in asynchronous circuits. An object of the present invention is to provide a semiconductor integrated circuit and an image forming apparatus capable of outputting the above.

  The present invention employs the following configuration in order to achieve the above object.

  The present invention is a semiconductor integrated circuit to which a first clock signal that has been spread spectrum and a second clock signal that has not been spread spectrum are supplied, wherein the first clock signal and the second clock signal Correction signal generation means for generating a correction signal for correcting the influence of the spread spectrum from the phase difference between the first clock signal and a process execution means for operating the first clock signal as an operation clock to execute a predetermined process. The processing execution unit includes a counter that operates in synchronization with the first clock signal and a counter correction unit that corrects the count value of the counter using the correction signal.

  In the semiconductor integrated circuit of the present invention, the counter correction means may be configured to transition the counter value of the counter according to the correction signal.

  In the semiconductor integrated circuit of the present invention, the counter correction means may be configured to advance the counter value of the counter by one during a period when the correction signal is valid.

  In the semiconductor integrated circuit of the present invention, the counter correction means may stop the transition of the count value of the counter during a period when the correction signal is valid.

  In the semiconductor integrated circuit of the present invention, the first clock signal is a signal that is delayed with respect to the second clock signal, and the correction signal generating means is configured such that the first clock signal is the second clock signal. It is also possible to generate a correction signal that is valid for one cycle of the first clock signal in synchronization with the first clock signal when delayed by one cycle from the signal.

  Also, in the semiconductor integrated circuit of the present invention, the first clock signal is a spectrum-spread signal centered on the number of periods of the second clock signal, and the correction signal generating means includes the first clock signal. Generates a correction signal that is valid for one cycle of the first clock signal in synchronization with the first clock signal when the first clock signal is delayed by one cycle from the second clock signal. A configuration may be adopted in which a correction signal that is valid for one cycle of the first clock signal is generated in synchronization with the first clock signal when the cycle proceeds from the second clock signal.

  In the semiconductor integrated circuit of the present invention, the processing execution unit may be configured to set whether or not to correct the counter value by the counter correction unit.

  The present invention is an image forming apparatus that includes a recording head that discharges ink and forms an image by discharging ink from the recording head and attaching the ink to a recording medium. A clock signal and a second clock signal that is not spread spectrum are supplied, and a correction signal that corrects the influence of the spread spectrum is generated from the phase difference between the first clock signal and the second clock signal. Correction signal generating means, and processing execution means for operating the first clock signal as an operation clock and executing predetermined processing, wherein the processing execution means is synchronized with the first clock signal. The counter includes an operating counter, and counter correction means for correcting the count value of the counter with the correction signal.

  According to the present invention, when a spread spectrum clock signal is used as an operation signal, it is possible to output a signal that is not affected by spread spectrum while suppressing an increase in the number of asynchronous circuits.

1 is a diagram illustrating a semiconductor integrated circuit 100 according to a first embodiment. It is a timing chart explaining the correction signal output from the correction signal generation part 120 of 1st embodiment. It is a 1st figure explaining the production | generation of the correction signal by the correction signal generation part 120 of 1st embodiment. It is a 2nd figure explaining the production | generation of the correction signal by the correction signal generation part 120 of 1st embodiment. It is a 3rd figure explaining the production | generation of the correction signal by the correction signal generation part 120 of 1st embodiment. It is a figure explaining the correction | amendment in the circuit block 130 of 1st embodiment. FIG. 6 is a schematic side view of an image forming apparatus 200 according to a second embodiment. It is a top view explaining the principal part of the image forming apparatus 200 of 2nd embodiment. 3 is a diagram for explaining a head configuration of a recording head 34. FIG. 1 is a diagram illustrating a semiconductor integrated circuit 100A included in an image forming apparatus 200. FIG. FIG. 4 is a diagram illustrating a positional relationship between a carriage 33 and an encoder sensor 91. 3 is a diagram schematically illustrating the principle of an encoder sensor 91. FIG. FIG. 6 is a diagram illustrating the timing of driving waveform output to the recording head. It is a figure for demonstrating the bad influence which spread spectrum has on a drive waveform.

  The present invention generates a correction signal for correcting the effect of spread spectrum from a spread spectrum clock signal and a non-spread spectrum clock signal. Then, in the circuit block to which the spread spectrum clock signal is supplied, the counter value of the counter of the circuit block is corrected based on the correction signal, so that the signal whose influence of the spread spectrum is reduced while suppressing the increase of the asynchronous circuit. Can output.

(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a semiconductor integrated circuit 100 according to the first embodiment of the present invention.

  The semiconductor integrated circuit 100 of this embodiment includes a clock signal supply unit 110, a correction signal generation unit 120, and a circuit block 130. The correction signal generation unit 120 and the circuit block 130 are connected by an internal bus B or the like. Note that the semiconductor integrated circuit 100 shown in FIG. 1 describes only the configuration necessary for explaining the characteristic part of the present invention. In the semiconductor integrated circuit 100 of the present embodiment, a plurality of circuit blocks other than the circuit block 130 may be provided.

  The clock signal supply unit 110 supplies a clock signal (hereinafter referred to as an operation clock signal) that has been spectrum-spread from a clock signal (hereinafter referred to as a reference clock signal) that has not been spread spectrum to the correction signal generation unit 120. The clock signal supply unit 110 supplies an operation clock signal to the circuit block 130.

  The clock signal supply unit 110 of this embodiment supplies a reference clock signal and an operation clock signal supplied from an SSCG provided outside the semiconductor integrated circuit 100 to the correction signal generation unit 120 and the circuit block 130. There may be. Further, the clock signal supply unit 110 of this embodiment includes an SSCG, and the reference clock signal and the operation clock signal generated in the clock signal supply unit 110 are transferred to the correction signal generation unit 120 and the circuit block 130. You may supply.

  The correction signal generation unit 120 is an asynchronous circuit with the circuit block 130 and generates a correction signal from the reference clock signal and the operation clock signal supplied from the clock signal supply unit 110. The correction signal generation unit 120 includes a first counter 121, a second counter 122, and a signal generation unit 123. The correction signal generator 120 detects the phase difference between the reference clock signal and the operation clock signal using the first counter 121 and the second counter 122. Then, the correction signal generation unit 120 generates a correction signal based on the phase difference detected by the signal generation unit 123. Details of the generation of the correction signal will be described later.

  The circuit block 130 is a circuit that operates according to an operation clock signal and executes predetermined processing. The circuit block 130 of the present embodiment performs a process of generating a pulse signal using the operation clock signal.

  The circuit block 130 includes a counter 131 and a counter correction unit 132. The counter 131 is a counter for dividing the operation clock signal. The counter correction unit 132 corrects the counter value of the counter 131 using the correction signal supplied from the correction signal generation unit 120. Details of the correction of the counter value will be described later.

  Hereinafter, generation of a correction signal by the correction signal generation unit 120 of the present embodiment will be described with reference to FIGS. 2 to 5. FIG. 2 is a timing chart illustrating a correction signal output from the correction signal generation unit 120 of the first embodiment.

  The correction signal generator 120 of this embodiment generates the correction signal P so that the correction signal P is generated every time the operation clock signal is delayed by one cycle with respect to the reference clock signal. The correction signal P is a signal that is valid for one cycle in synchronization with the operation clock signal.

  As shown in FIG. 2, the cycle of the reference clock signal between the time point T1 and the time point T2 is 9 cycles, and the cycle of the operation clock signal is 8 cycles. Therefore, the correction signal P becomes valid for one cycle in synchronization with the operation clock signal from time T2.

  The example in FIG. 2 is an example of a downsplet that is clock-modulated so that the operation clock signal is equal to or lower than the frequency of the reference clock signal that is not spread spectrum. In the present embodiment, when the spread spectrum is center spread, the operation clock signal may be delayed or advanced with respect to the reference clock signal. Therefore, two correction signals P and P1 are used. The correction signal P1 is generated so as to be valid for one cycle in synchronization with the operation clock signal every time the operation clock signal advances by one cycle with respect to the reference clock signal. The center spread means that the spectrum is spread (clock modulated) around the number of periods of the original clock signal (reference clock signal) that has not been spread.

  Next, generation of a correction signal by the correction signal generation unit 120 of the present embodiment will be described with reference to FIG. FIG. 3 is a first diagram illustrating generation of a correction signal by the correction signal generation unit 120 of the first embodiment. FIG. 3A is a timing chart for explaining generation of the correction signal, and FIG. 3B is a diagram showing state transition of the counter and the pulse signal when the correction signal is generated. In the example of FIG. 3, the operation clock signal is a clock signal obtained by applying a down spread to the reference clock signal.

  The first counter 121 included in the correction signal generation unit 120 of the present embodiment operates in synchronization with the reference clock signal to generate a first pulse signal. In the present embodiment, the initial value of the first counter 121 is 1. The first counter 121 counts down, and when the counter value reaches 0, switches the state of the first pulse signal and returns the count value to the initial value of 1. In the example of FIG. 3, when the count value becomes 0, the state of the first pulse signal is switched from a high level (hereinafter, H level) to a low level (hereinafter, L level).

  The second pulse signal is obtained by replacing the value of the first pulse signal with the operation clock signal. Although an asynchronous absorption circuit is required here, it is not necessary to limit the asynchronous absorption circuit to a specific asynchronous absorption circuit in the present embodiment, and thus illustration is omitted. Since the operation clock signal of the present embodiment has a slightly longer cycle than the reference clock signal, the state of the second pulse signal may be switched between two cycles of the operation clock signal and one cycle.

  The second counter 122 counts a period during which the second pulse signal is at the H level and a period at which the second pulse signal is at the L level. When the state of the second pulse signal is switched, the second counter 122 has a count value of 1 (same as the initial value of the first counter 121) and starts counting down.

  In the correction signal generation unit 120 of this embodiment, the signal generation unit 123 performs only one cycle in synchronization with the operation clock signal when the state of the second pulse signal is switched before the count value of the second counter 122 becomes zero. An effective correction signal P is generated. The generated correction signal P is supplied to the circuit block 130 and used for correction for reducing the influence of spread spectrum.

  In the example of FIG. 3, the initial value of the first counter 121 is set to 1. However, the present invention is not limited to this. The initial value of the first counter 121 may be another value as long as the number of state transitions of the first pulse signal is the same as the number of state transitions of the second pulse signal.

  FIG. 4 is a second diagram illustrating generation of a correction signal by the correction signal generation unit 120 of the first embodiment. FIG. 4A is a timing chart for explaining the generation of the correction signal, and FIG. 4B is a diagram showing the state transition of the counter and the pulse signal when the correction signal is generated.

  FIG. 4 shows an example in which the number of cycles of the reference clock signal is different from the frequency of the non-spread spectrum clock signal that is the source of the operation clock signal. The reference clock signal in FIG. 4 has a frequency of 48 MHz. The reference clock signal is supplied separately from the operation clock signal, for example, for a module (not shown) such as a USB (Universal Serial Bus) interface built in the semiconductor integrated circuit 100.

  The operation clock signal in FIG. 4 is a signal obtained by performing spread spectrum (down spread) on a 66 MHz clock signal. The operation clock signal is generated by, for example, SSCG provided outside the semiconductor integrated circuit 100 and supplied to the semiconductor integrated circuit 100.

  In the example of FIG. 4, the cycle of the first pulse signal is set to 6 MHz in order to set the timing at which the state of the first pulse signal is switched to a timing that can be generated by dividing 48 MHz and 66 MHz. In FIG. 4, since the first counter 121 generates 6 MHz from 48 MHz, the initial value of the first counter 121 is set to 7 (divided by 1/8). Further, since the second counter 122 counts 6 MHz at 66 MHz, the initial value of the second counter is set to 10 (frequency division to 1/11).

  The generation procedure of the first pulse signal and the second pulse signal in FIG. 4 is as described in FIG. The signal generator 123 generates a correction signal P that is valid for only one cycle in synchronization with the operation clock signal when the state of the second pulse signal is switched before the count value of the second counter 122 becomes zero. Therefore, also in FIG. 4, the correction signal P becomes effective every time it is delayed by one cycle with respect to the clock signal having a period of 66 MHz before the operation clock signal is spread spectrum. The correction signal P is supplied to the circuit block 130 and used for correction to reduce the influence of spread spectrum.

  FIG. 5 is a third diagram for explaining the generation of the correction signal by the correction signal generation unit 120 of the first embodiment. FIG. 5A is a timing chart for explaining the generation of the correction signal, and FIG. 5B is a diagram showing the state transition of the counter and the pulse signal when the correction signal is generated.

  The operation clock signal shown in FIG. 5 is a signal obtained by spectrum spreading (center spread) of the reference clock signal. In the case of center spread, the operation clock signal may be delayed or advanced with respect to the reference clock signal, so that two correction signals P and P1 are generated.

  The correction signal P is a correction signal that is effective when the operation clock signal is delayed by one cycle compared to the reference clock signal, and is generated in the same manner as the procedure described in FIG.

  The correction signal P1 is a correction signal that is effective when the operation clock signal has advanced one cycle compared to the reference clock signal. The generation of the correction signal P1 will be described below.

  The process up to the generation of the second pulse signal is as described in FIG. When the second pulse signal is generated, the signal generation unit 123 of the correction signal generation unit 120 generates an operation clock signal when the state of the second pulse signal is not switched even when the count value of the second counter 122 becomes zero. A correction signal P1 that is effective for only one cycle is generated in synchronization. At this time, the count value of the second counter 122 remains 0, and the counter value does not transition until the state of the second pulse signal is switched. The correction signals P and P1 generated in FIG. 5 are supplied to the circuit block 130 and used for correction for reducing the influence of spread spectrum.

  Next, correction using the correction signal P in the circuit block 130 of the present embodiment will be described. The circuit block 130 according to the present embodiment generates and outputs a pulse signal at a timing obtained by dividing the operation clock signal by four by the counter 131. The count value of the counter 131 is corrected by the counter correction unit 132 using the correction signal P.

  FIG. 6 is a diagram for explaining correction in the circuit block 130 of the first embodiment. FIG. 6A shows an example in which an ideal clock signal is supplied to the circuit block 130 and an ideal output signal (pulse signal) is output. An ideal clock signal is a clock signal before spectrum spread, and corresponds to, for example, a reference clock signal shown in FIG.

  In FIG. 6A, the circuit block 130 divides the 100 MHz reference clock signal by 4 and outputs a pulse signal at a timing of 25 MHz.

  The counter 131 of the circuit block 130 of this embodiment counts down the count value from 3 → 2 → 1 → 0, and outputs an H level output signal only during the period when the count value is 0. The pulse signal output from the circuit block 130 in the state of FIG. 6A is an ideal pulse signal.

  FIG. 6B shows an example in which the operation clock signal obtained by spectrum-spreading the reference clock signal and the correction signal P are supplied to the circuit block 130. In the circuit block 130 of this embodiment, when the operation clock signal and the correction signal P are supplied, the counter correction unit 132 corrects the count value of the counter 131.

  When the counter 131 counts down the count value from 3 → 2 → 1 → 0, the counter correction unit 132 advances the count value of the counter 131 one more during the period when the correction signal P is valid. However, the counter correction unit 132 does not advance the count value excessively at the timing when the count value becomes 0, and starts the next count value from 2.

  As a result, the period of the pulse signal output from the circuit block 130 is not constant, but the number of pulses in a certain period is the same as the ideal pulse signal.

  In FIG. 6, the operation clock signal is a clock signal obtained by applying a down spread to the reference clock signal. However, when the spread spectrum is center spread and correction is performed using the correction signal P (see FIG. 5), the correction is performed. Correction opposite to the correction using the signal P is performed. In other words, the counter correction unit 132 stops the transition of the count value of the counter 131 and delays the generation timing by one cycle during the period when the correction signal P1 is valid.

  In the present embodiment, the processing performed in the circuit block 130 has been described as processing for generating and outputting a pulse signal. However, the present invention is not limited to this. The present embodiment can be applied to any process as long as the process executed in the circuit block 130 is a process using a counter that counts up (or counts down) the operation clock signal.

  Further, in the circuit block 130 of the present embodiment, it may be possible to select whether or not to correct the counter value by the counter correction unit 132. For example, in this embodiment, whether or not to correct the counter value is set in the circuit block 130, and the counter correction unit 132 may select whether or not to correct the counter value by this setting. According to this configuration, it is possible to determine whether or not to correct the counter value in consideration of the influence of spread spectrum and the load generated by the process of correcting the counter value.

  As described above, in this embodiment, by performing correction using the correction signal, the output signal of the circuit block 130 can be brought close to the output signal when operating with an ideal clock signal (reference clock signal). The effect of spread spectrum can be reduced. In the present embodiment, the circuit asynchronous with the circuit block 130 is only the correction signal generation unit 120. Therefore, according to the present embodiment, when the spread spectrum clock signal is used as an operation signal, the semiconductor integrated circuit 100 can output a signal in which the influence of spread spectrum is reduced while suppressing an increase in the number of asynchronous circuits. .

(Second embodiment)
A second embodiment of the present invention will be described below with reference to the drawings. The second embodiment of the present invention is an image forming apparatus on which the semiconductor integrated circuit 100 described in the first embodiment is mounted. In the following second embodiment, those having the same functional configuration as those of the first embodiment are given the same reference numerals as those used in the description of the first embodiment, and the description thereof is omitted.

  The image forming apparatus according to the present embodiment will be described below with reference to FIGS.

  FIG. 7 is a schematic side view of the image forming apparatus 200 according to the second embodiment, and FIG. 8 is a plan view for explaining a main part of the image forming apparatus 200. The image forming apparatus 200 according to this embodiment includes a droplet discharge head, and forms an image on a recording sheet with ink droplets discharged from the droplet discharge head.

  The image forming apparatus 200 according to the present embodiment holds a carriage 33 slidably in a main scanning direction by a guide rod 31 and a stay 32 which are guide members horizontally mounted on left and right side plates 21A and 21B constituting the frame 21. The main scanning motor (not shown) moves and scans in the carriage main scanning direction via a timing belt (not shown) (see FIG. 8).

  The carriage 33 has a recording head 34 including four droplet discharge heads that discharge ink droplets of each color of yellow (Y), cyan (C), magenta (M), and black (Bk). The ink jet head constituting the recording head 34 includes a piezoelectric actuator such as a piezoelectric element, a thermal actuator that uses a phase change due to liquid film boiling using an electrothermal transducer such as a heating resistor, and a metal phase change due to a temperature change. There are a shape memory alloy actuator to be used, an electrostatic actuator using an electrostatic force, and the like provided as pressure generating means for generating a pressure for discharging a droplet.

  In the image forming apparatus 200 of the present embodiment, all the ink discharge ports of the recording head 34 can be driven simultaneously. In the present embodiment, all the ink discharge ports of the recording head 34 can be driven by being divided in time. Driving all the ink outlets at the same time causes disadvantages such as a decrease in recording quality due to the crosstalk between all the ink outlets and an increase in the capacity of the power supply due to the temporarily required large current. In some cases, these disadvantages can be avoided by time-division driving.

  The recording head 34 includes a driver IC and is connected to a control unit (not shown) via a harness (flexible print cable) 22.

  In addition, the carriage 33 is equipped with a sub tank 35 for each color for supplying each color ink to the recording head 34. Each color sub-tank 35 is supplementarily supplied with ink of each color from the ink cartridge 10 of each color mounted in the cartridge loading unit 4 via the ink supply tube 36 of each color. The cartridge loading 4 is provided with a supply pump unit for feeding ink in the ink cartridge 10. The ink supply tube 36 is held and held by the locking member 25 on the rear plate 21 </ b> C constituting the frame 21 in the middle of scooping.

  The image forming apparatus 200 according to the present embodiment also includes a half-moon roller (sheet feeding roller) 43 that separates and feeds sheets 42 as recording media one by one from a sheet stacking unit (pressure plate) 41 as a sheet feeding unit, and the sheet feeding. A separation pad 44 made of a material having a large friction coefficient is provided facing the roller 43. The separation pad 44 is urged toward the paper feed roller 43 side.

  The paper 42 fed from the paper feeding unit is fed to the recording head 34 by a guide member 45 that guides the paper 42, a counter roller 46, a conveyance guide member 47, and a pressing member 48 having a tip pressure roller 49. It is sent to the lower side. The fed paper 42 is transported to a position facing the recording head 34 by the transport belt 51.

  The conveyor belt 51 is an endless belt, and is provided between the conveyor roller 52 and the tension roller 53 so as to circulate in the belt conveyance direction (sub-scanning direction). The transport belt 51 is, for example, a resin layer having a pure thickness of about 40 μm that is not subjected to resistance control, a surface layer that becomes a sheet suction surface formed of ETFE pure material, and a back layer that is made of the same material as the surface layer and is subjected to resistance control by carbon ( Medium resistance layer, earth layer).

  The charging roller 56 charges the surface of the transport belt 51. The charging roller 56 is disposed so as to contact the surface layer of the conveyor belt 51 and rotate following the rotation of the conveyor belt 51, and applies a predetermined pressing force to both ends of the shaft as a pressing force. The conveyance roller 52 also serves as an earth roller, and is in contact with the middle resistance layer (back layer) of the conveyance belt 51 and is grounded.

  A guide member 57 is disposed on the back side of the conveyor belt 51 so as to correspond to a printing area by the recording head 34. The guide member 57 maintains the high-precision flatness of the conveyor belt 51 by causing the upper surface to protrude toward the recording head 34 from the tangent line of the two rollers (the conveyor roller 52 and the tension roller 53) that support the conveyor belt 51. ing.

  The conveyance belt 51 rotates in the belt conveyance direction (sub-scanning direction) shown in FIG. 8 when the conveyance roller 52 is rotationally driven by a sub-scanning motor (not shown).

  The image forming apparatus 200 according to this embodiment includes a separation claw 61 for separating the paper 42 from the conveyance belt 51, a paper discharge roller 62, and a paper discharge roller in order to discharge the paper 42 recorded by the recording head 34. 63. Further, the image forming apparatus 200 includes a paper discharge tray 3 below the paper discharge roller 62. The height from between the discharge roller 62 and the discharge roller 63 to the discharge tray 3 is increased to some extent in order to increase the amount that can be stocked in the discharge tray 3.

  A double-sided unit 71 is detachably attached to the back surface of the image forming apparatus 200. The duplex unit 71 takes in the paper 42 returned by the reverse rotation of the transport belt 51, reverses it, and feeds it again between the counter roller 46 and the transport belt 51. The upper surface of the duplex unit 71 is a manual feed tray 72.

  As shown in FIG. 8, a maintenance / recovery mechanism 81 including a recovery means for maintaining and recovering the nozzle state of the recording head 34 is disposed in the non-printing area on one side of the carriage 33 in the scanning direction. The maintenance / recovery mechanism 81 wipes the nozzle surfaces and cap members (hereinafter referred to as “caps”) 82a to 82d (hereinafter referred to as “caps 82” when not distinguished from each other) for capping the nozzle surfaces of the recording head 34. A wiper blade 83 which is a blade member for the purpose, and an empty discharge receiver 84 which receives a droplet when performing an empty discharge for discharging a droplet which does not contribute to recording in order to discharge the thickened recording liquid. In this embodiment, the cap 82a is a suction and moisture retention cap, and the other caps 82b to 82d are moisture retention caps.

  The recording liquid waste generated by the maintenance and recovery operation by the maintenance and recovery mechanism 81, the ink discharged to the cap 82, the ink adhered to the wiper blade 83 and removed by the wiper cleaner, and the ink ejected to the idle ejection receiver 84 are The liquid is discharged and stored in a waste liquid tank (not shown).

  In the non-printing area on the other side of the carriage 33 in the scanning direction, as shown in FIG. 8, when the idle ejection is performed to eject the liquid droplets that do not contribute to the recording in order to discharge the recording liquid thickened during the recording or the like. An empty discharge receiver 88 for receiving droplets is disposed, and the empty discharge receiver 88 is provided with an opening 89 along the nozzle row direction of the recording head 34.

  A communication circuit unit (interface) such as a USB for transmitting / receiving data to / from the host is provided on the inner rear side of the image forming apparatus 200. A control circuit board constituting a control unit that controls the entire image forming apparatus 200 is provided on the inner rear side of the image forming apparatus 100. A semiconductor integrated circuit for controlling only image formation is mounted on the control circuit board. The semiconductor integrated circuit 100 described in the first embodiment is applied to a semiconductor integrated circuit that performs image processing. Details of the semiconductor integrated circuit that performs image processing will be described later.

  In the image forming apparatus 200 having the above configuration, the sheets 42 separated and fed one by one from the sheet feeding tray 2 are guided substantially vertically upward by the guide 45 and sandwiched between the transport belt 51 and the counter roller 46. Is transported. The paper 42 is further guided at the front end by the transport guide 47 and pressed against the transport belt 51 by the front end pressure roller 49, and the transport direction is changed by approximately 90 °.

  At this time, an alternating voltage is applied to the charging roller 56 so that a positive output and a negative output are alternately repeated from the AC bias supply unit by a control circuit (not shown). Therefore, the conveying belt 51 is alternately charged in a strip shape with a predetermined width in the sub-scanning direction that is the rotating direction, that is, plus and minus in an alternating charging voltage pattern. When the paper 42 is fed onto the transport belt 51 in this state, the paper 42 is attracted to the transport belt 51, and the paper 42 is transported in the sub-scanning direction by the circular movement of the transport belt 51.

  Here, the image forming apparatus 200 drives the recording head 34 according to the image signal while moving the carriage 33. Then, the image forming apparatus 200 ejects ink droplets onto the stopped paper 42 to record one line, and after the paper 42 is conveyed by a predetermined amount, the next line is recorded. The image forming apparatus 200 ends the recording operation upon receiving a recording end signal or a signal that the trailing edge of the paper 42 has reached the recording area, and discharges the paper 42 to the paper discharge tray 3.

  In the image forming apparatus 200 of the present embodiment, the carriage 33 waiting for printing (recording) is moved to the maintenance / recovery mechanism 81 side, the recording head 34 is capped by the cap 82, and the nozzles are kept in a wet state. Prevents ejection failures due to drying. In the image forming apparatus 200, the recording liquid is sucked from the nozzle by a suction pump (not shown) with the recording head 34 capped by the cap 82 (referred to as “nozzle suction” or “head suction”), Perform recovery action to discharge bubbles. Further, the image forming apparatus 200 performs an idle ejection operation for ejecting ink not related to the recording before the start of recording or during the recording. The image forming apparatus 200 of the present embodiment maintains the stable ejection performance of the recording head 34 with the above configuration.

  Next, an example of the head configuration of the recording head 34 will be described with reference to FIG. FIG. 9 is a diagram for explaining the head configuration of the recording head 34. The recording head 34 includes four nozzle rows 34k, 34c, 34m, 34y (for ejecting droplets of each color of black (K) ink, cyan (C) ink, magenta (M) ink, and yellow (Y) ink. Hereinafter, when not distinguished, it is referred to as “nozzle row 34N”. The nozzle row 34N is formed by a plurality of nozzles 34n.

  In the image forming apparatus 200 of the present embodiment, the first embodiment is applied to a semiconductor integrated circuit that controls the movement of the carriage 33 and the ejection of ink droplets from the recording head 34 described above.

  The image forming apparatus 200 of the present embodiment includes a control circuit board that constitutes a control unit that controls the entire image forming apparatus 200. An application specific integrated circuit (ASIC) 100A that controls only image formation is mounted on the control circuit board.

  In the image forming apparatus 200 of the present embodiment, by mounting the semiconductor integrated circuit 100A, it is possible to accurately control the movement of the carriage 33, the ejection of ink droplets from the recording head 34, and the like. Hereinafter, the semiconductor integrated circuit 100A mounted on the control circuit board of the image forming apparatus 200 of the present embodiment will be described.

  FIG. 10 is a diagram illustrating a semiconductor integrated circuit 100A included in the image forming apparatus 200. The semiconductor integrated circuit 100A of this embodiment includes a clock signal supply unit 110, a correction signal generation unit 120, and circuit blocks 130A to 130H. The clock signal supply unit 110 and the correction signal generation unit 120 are as described in the first embodiment. The clock signal supply unit 110 supplies a reference clock signal and an operation clock signal. The correction signal generation unit 120 generates a correction signal for reducing the influence of spread spectrum from the phase difference between the reference clock signal and the operation clock signal.

  The circuit blocks 130A to 130H of the present embodiment are circuit blocks corresponding to functions, and operate by being supplied with an operation clock signal.

  The circuit block 130A is a timer unit. The circuit block 130 </ b> B is a motor control unit that controls a motor or the like that moves the carriage 33. The circuit block 130C is a sensor analysis unit that analyzes a signal from a sensor for detecting the position, moving direction, moving speed, and the like of the carriage 33. The circuit block 130 </ b> D is a drive waveform output unit that outputs a drive waveform that drives the recording head 34 to eject ink droplets from the recording head 34.

  The circuit block 130E is a data input unit to which input data to be an image is input. The circuit block 130F is a CPU (Central Processing Unit) that controls the operation of the semiconductor integrated circuit 100A. The circuit block 130G is an image processing unit that performs image processing for forming an image from input data. The circuit block 130H is an image data output unit that outputs the formed image data.

  In the semiconductor integrated circuit 100A of this embodiment, in particular, in the circuit block 130A that is a timer unit, the circuit block 130B that is a motor control unit, the circuit block 130C that is a sensor analysis unit, and the circuit block 130D that is a drive waveform output unit, spread spectrum It is preferable to reduce the influence of.

  For example, in the timer unit, the effect of spread spectrum is not preferable when it is desired to measure a precise time in a short time. In the motor control unit, the duty ratio of a PWM (Pulse Width Modulation) signal for controlling the motor is influenced by spread spectrum, which is not preferable. The sensor analysis unit is not preferable because spectrum spreading affects when the period of the input signal from the sensor is counted. The drive waveform output unit is not preferable because it affects the output drive waveform by spectrum spreading.

  Therefore, each of the circuit blocks 130A to 130D of the semiconductor integrated circuit 100A of the present embodiment has a counter (not shown) corresponding to the counter 131 and counter correction means (corresponding to the counter correction unit 132) for correcting the counter value. ing. The correction signals generated by the correction signal generation unit 120 are supplied to the circuit blocks 130A to 130D, and the counter value is corrected by the counter correction unit. The count value correction method for each circuit block is as described in the first embodiment.

  An example of correction in the semiconductor integrated circuit 100A of the present embodiment will be described below. First, correction in the circuit block 130C, which is a sensor analysis unit, will be described.

  FIG. 11 is a diagram illustrating the positional relationship between the carriage and the encoder sensor. FIG. 11A is a diagram showing a positional relationship between the carriage and the encoder sensor, and FIG. 11B is a partially enlarged view of FIG. 11A. FIG. 12 is a diagram schematically illustrating the principle of the encoder sensor 91.

  The encoder sensor 91 has a light source 94 and two light receiving elements A and B. The two light receiving elements A and B are spaced apart by a quarter encoder period. The circuit block 130 </ b> C of the present embodiment can detect the position, moving direction, and moving speed of the carriage 33 from the outputs of the respective light receiving elements A and B.

  In the circuit block 130C, for example, when obtaining the moving speed of the carriage 33, it is necessary to measure the encoder cycle. The circuit block 130C of this embodiment has an encoder cycle measurement counter (not shown) that measures the encoder cycle, and the number of clocks (operation clock signal or operation) during one encoder cycle using the encoder cycle measurement counter. Measure the clock signal). In the circuit block 130C of the present embodiment, the encoder cycle measurement counter is a counter corresponding to the counter 131 described in the first embodiment.

  The circuit block 130C calculates the carriage speed based on the measured encoder period, and performs control to bring the carriage speed closer to the target value by servo control. For this reason, if an error occurs in the measured encoder cycle, an error also occurs in the control content, and speed fluctuation occurs even when constant speed control is performed in the movement of the carriage 33.

  Therefore, in the circuit block 130C of this embodiment, the encoder cycle can be correctly detected by correcting the count value described in FIG. 6 of the first embodiment for the encoder cycle measurement counter. Thus, speed control with higher accuracy becomes possible. Here, in the circuit block 130C of the present embodiment, the encoder cycle can be correctly detected by performing the correction described in the first embodiment on the encoder cycle measurement counter.

  The encoder cycle detection error is maximized when the encoder cycle is ½ of the modulation cycle of the operation clock signal. In this case, the present embodiment is more effective. To do.

  Next, correction in the circuit block 130D that is the drive waveform output unit will be described. FIG. 13 is a diagram showing the timing of driving waveform output to the recording head 34.

  In the example of FIG. 13, the landing position (white circle in FIG. 13) of the ejected ink droplets is the same as the main scanning position in the forward path and the backward path when the carriage 33 is guided by the guide rod 31 to reciprocate. Then, the output of the drive waveform is started with a delay of the delay time Td from the switching position of the output pulse of the encoder (see FIG. 12). Although not shown, the drive waveform is also delayed for printing while the carriage 33 is accelerating and for correcting the assembly error for each head. The delay time Td is a value determined by an ink droplet ejection speed, a carriage moving speed, a nozzle-paper surface distance, ink viscosity, and the like, and is set in advance in the circuit block 130D.

  The circuit block 130D includes a delay generation unit (not shown) and a delay generation counter. This delay generation means generates a delay corresponding to a set delay time Td by counting the operation clock signal by a delay generation counter, for example. Here, when the operation clock signal is spread spectrum, an error occurs in the delay time Td.

  The error is maximized when the set value of the delay time Td is ½ of the spread spectrum modulation period. This error leads to deterioration in accuracy of the landing position.

  The moving speed of the carriage 33 needs to be set in consideration of the speed fluctuation of the moving speed and the accuracy of the encoder sensor 91. In the drive waveform for driving the recording head 34, the NNth drive waveform and the (N + 1) th drive waveform must not overlap. There may be a case where a certain period is required from the completion of the output of the Nth drive waveform to the start of the output of the (N + 1) th drive waveform. Therefore, for example, if an error occurs between the set value of the delay time Td and the actual value, the carriage speed must be reduced in accordance with the worst value of the miscalculation.

  In the circuit block 130D of the present embodiment, the delay time measurement counter corresponds to the counter 131 described in the first embodiment. Therefore, the timing at which the delay time is generated can be corrected by correcting the count value described in the first embodiment for the delay time measurement counter included in the circuit block 130D. For this reason, in the circuit block 130D of the present embodiment, an error between the set value of the delay time Td and the actual value can be reduced.

  In some cases, the value of the (N−1) -th encoder cycle is used as the value of the N-th delay time Td. In this case, the set value of the delay time Td is obtained by performing correction when detecting the encoder cycle. And the actual value can be reduced.

  In addition, in the circuit block 130D that is the drive waveform output unit, spread spectrum may adversely affect the drive waveform. FIG. 14 is a diagram for explaining an adverse effect of spread spectrum on the drive waveform.

  The example of FIG. 14 shows a case where the ejection period of ink droplets from the recording head 34 is ½ of the modulation period of the reference clock signal by SSCG. In this case, ink droplets are ejected twice during one cycle of the change (fast / slow) in the diffusion of the operation clock signal. Under this condition, image quality degradation is maximized.

  Hereinafter, an adverse effect of the diffusion of the operation clock signal on the drive waveform will be described.

  The start of driving waveform output is controlled by an encoder signal. Therefore, the output of the drive waveform is coarse and dense, and a period in which the drive waveform is not output occurs. This period becomes a useless period and becomes a factor for reducing the moving speed of the carriage 33. In addition, the density of the output of the drive waveform affects the ink discharge position (□ portion in the figure) and degrades the image quality. Furthermore, the steep change in the drive waveform increases the speed of the ink droplet, and therefore the landing position (circled portion in the figure) further deteriorates.

  In the present embodiment, the above-described adverse effect can be improved by configuring the circuit block 130D with a DA converter.

  Since the cycle of the DA converter is usually slower than the cycle of the operation clock signal, the operation clock signal is divided by a DA cycle generation counter (not shown) to generate the DA cycle. In the circuit block 130D of the present embodiment, the DA cycle generation counter corresponds to the counter 131 described in the first embodiment. Therefore, by correcting the count value described in the first embodiment for the DA cycle generation counter included in the circuit block 130D, it is possible to reduce the density in the output of the drive waveform, and the above-described adverse effect is improved.

  As described above, also in the image forming apparatus 200 of the present embodiment, when the spread spectrum clock signal is used as an operation signal, a signal in which the influence of spread spectrum is reduced while suppressing an increase in asynchronous circuits is output. can do.

  As mentioned above, although this invention has been demonstrated based on each embodiment, this invention is not limited to the requirements shown in the said embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.

DESCRIPTION OF SYMBOLS 100, 100A Semiconductor integrated circuit 110 Clock signal supply part 120 Correction signal generation part 130, 130A-130H Circuit block 200 Image forming apparatus

Claims (8)

A semiconductor integrated circuit to which a first clock signal that is spread spectrum and a second clock signal that is not spread spectrum are supplied,
A correction signal generating means for generating a correction signal for correcting the influence of the spread spectrum from the phase difference between the first clock signal and the second clock signal;
Processing execution means for operating the first clock signal as an operation clock and executing predetermined processing;
The process execution means includes
A counter that operates in synchronization with the first clock signal;
Counter correction means for correcting the count value of the counter by the correction signal. The counter correction means includes
The semiconductor integrated circuit according to claim 1, wherein the counter value of the counter is shifted according to the correction signal. The counter correction means includes
3. The semiconductor integrated circuit according to claim 2, wherein the counter value of the counter is advanced by one during a period in which the correction signal is valid. The counter correction means includes
3. The semiconductor integrated circuit according to claim 2, wherein transition of the count value of the counter is stopped during a period in which the correction signal is valid. The first clock signal is a signal delayed with respect to the second clock signal;
The correction signal generating means includes
A correction signal that is valid for one cycle of the first clock signal is generated in synchronization with the first clock signal when the first clock signal is delayed by one cycle from the second clock signal. The semiconductor integrated circuit according to any one of 1 to 4. The first clock signal is a spectrum-spread signal around the number of periods of the second clock signal,
The correction signal generating means includes
When the first clock signal is delayed by one cycle from the second clock signal, a correction signal that is effective for one cycle of the first clock signal is generated in synchronization with the first clock signal;
A correction signal that is valid for one cycle of the first clock signal is generated in synchronization with the first clock signal when the first clock signal advances from the second clock signal by one cycle. The semiconductor integrated circuit according to any one of 1 to 5. The process execution means includes
7. The semiconductor integrated circuit according to claim 1, wherein whether or not to correct the counter value by the counter correction unit is set. An image forming apparatus that includes a recording head that discharges ink and forms an image by discharging ink from the recording head and attaching the ink to a recording medium,
A first spread spectrum clock signal and a second non spread spectrum clock signal are supplied, and the influence of the spread spectrum is determined from the phase difference between the first clock signal and the second clock signal. Correction signal generation means for generating a correction signal to be corrected;
Processing execution means for operating the first clock signal as an operation clock and executing predetermined processing;
The process execution means includes
A counter that operates in synchronization with the first clock signal;
An image forming apparatus on which a semiconductor integrated circuit having counter correction means for correcting the count value of the counter with the correction signal is mounted.

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