JP2010157311A - Pseudo-static dynamic bit line circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip including an improved register file (RF) which holds sufficient noise immunity and avoids contention even when an active minimum operating voltage (VccMin) is reduced. <P>SOLUTION: There are provided a method and a circuit for achieving a dynamic RF column including a pseudo-static dynamic bit lines in, for example, a register file circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a quasi-static dynamic bit line circuit and method.

  A dynamic register file (RF) is commonly used to store and read an array of data, for example in a microprocessor. They are particularly useful in areas where processing power (throughput) is important. Reading data from RF is typically performed using dynamic selection and evaluation where evaluation performance (eg, speed) is important. Accordingly, improved circuits and methods would be desired.

  With respect to FIG. 1, a conventional RF column (in this example a 64-bit column) is shown. (For simplicity and ease of understanding, a single 64-bit RF column is shown, but in many applications there are multiple such columns, for example, 32 columns in one RF array configuration, The result is 32 64-bit registers or RF words.) The illustrated RF is organized from eight groups 102, each group having eight cell stacks, and thus a 64-bit column. A 64 cell stack is formed for this purpose.

  A read word line (Wl) is provided to each cell stack to evaluate (or “read”) the cell stack when the word line is asserted (declared true). Each word line (Wl) is driven by a decoder driver, typically formed of a NAND gate, followed by an inverter to achieve the required active high input line (both devices) Not shown here). Thus, with such a configuration, one word line is asserted simultaneously (eg, every read cycle).

  Each cell stack group 102 shares a common local bit line (LBL) to evaluate a cell stack selected from the cell stacks shared within the group. The local bit line is precharged high and depending on the logic value stored in the cell to be read, the bit line remains high based on the evaluation, or Discharge to low level.

  There are four gates 104 (here NAND gates) for coupling the eight local bit lines to the four pre-global bit lines (PG). In this arrangement, each of the gates 104 receives two local bit lines and outputs a pre-global bit line to evaluate the two local bit lines. Thus, four PG lines represent 64 cell stack columns. Each of them is routed into a dynamic NOR gate 106, which in addition has a global bit line (GBL) output and is routed into an output driver 108, which in this description is a set • Dominant latch (SDL).

  The dynamic NOR gate 106 is clocked (precharged / evaluated) by the GBL precharge clock signal (GPCH Clk), for example as occurs when both GBL precharge and GBL pulldown consume DC power simultaneously. To avoid power contention, it may be delayed with respect to the LBL precharge clock. The global precharge clock is further used to clock the SDL 108. The state of the GBL line is captured by the latch 108 at the end of the evaluation phase (in this description GPCHClk is high), but it is also a set dominant latch, so it is also delayed assertion (here from high level). Capture low level) on the GBL. Thus, the latched global bit line (GBL) value is provided as an output (Rd Out) in latch 108 and corresponds to the value read from the selected word line cell in the column.

FIG. 2 shows a conventional circuit for the cell stack group 102. The circuit has 8 cells, each of which is a memory cell (not shown), a cell access stack transistor (N _S2 ), a local bit line (which is the evaluation node of the dynamic circuit). Formed from a word line access stack transistor (N _S1 ). The circuit further includes a precharge transistor (P _LClk ) and a keeper circuit 202 formed from a P-type transistor and an inverter, as shown. The Wl signal is coupled to the gate of the stack transistor (N _S1 ), which is placed between the local bit line (LBL) and the associated cell access stack transistor (N _S2 ). . A memory cell (not shown) is coupled to a cell access transistor (N _S2 ) to control its gate with stored data (data i).

During the precharge phase, all word line (Wl) signals are de-asserted (low level), which turns off the word line access stack transistor (N _S1 ). And the precharge transistor (P _LClk ) is asserted via the local bit line clock (LBL PCH Clk) and the local bit line (LBL) is charged high. During the subsequent evaluation phase, the precharge transistor is turned off and its word line (Wl) is asserted (goes high) when one of the cell stacks is read. (Note that the cell stacks in a group may or may not be read during a read cycle, eg, a word line in a different group may be selected.) The local bit line is coupled to its associated memory cell through its cell transistor (N _S2 ). Thus, depending on the state stored in that memory cell, the cell transistor is turned on, thereby “pulling” the local bit line through the stack transistor, or locally. • Keep the bit line high. As is well known, if keeper circuit 202 assumes that it evaluates to a high level, that is, if the selected memory cell applies a low level to its associated cell transistor (N _S2 ), then LBL is Plays a role of maintaining a high level.

FIG. 3 shows a conventional dynamic NOR circuit 106 for the RF column of FIG. It has four pull-down stack transistors (N _G0 to N _G3 ), a precharge transistor (P _GClk ) and a keeper circuit 302, as shown, all of which, as shown, Coupled to a global bit line (GBL) evaluation node. In addition, an SDL 108 is shown for latching data from the GBL and providing its inverted form at the Rd Out output. Each of the stack transistors (N _G0 to N _G3 ) receives one of the precharge signals and if the PGBL signal is asserted (high), that is, when the gate evaluates, ie, P _GClk Functions to pull down the GBL node after is turned off.

  Unfortunately, as the active minimum operating voltage (VccMin) decreases, typical device parameters vary in most manufacturing processes, making it more difficult to meet operational goals. In particular, dynamic register file circuits, for example, are sensitive to VccMin reduction due to contention between local and global bit line pull-down stacks and their associated keeper devices. . In addition, ambitious frequency targets at low voltage can limit the actual available read time. Some of the existing techniques for reducing the allowable active VccMin level are to increase the size of the bit line pull-down device, reduce the size of the keeper device, and optimize or reduce the capacitance on the bit line. Including. However, these approaches are relatively less profitable at the expense of area, power, noise, and / or significant design effort, respectively. Although miniaturization of the keeper is not very expensive, it generally impairs noise immunity, and as a result, the robustness of the circuit is impaired.

  Thus, the invention disclosed herein is a different approach to improving dynamic bit line circuits, thereby allowing, for example, reducing their active VccMin levels. In some embodiments, a pseudo-static bit line with a controllable pull-up is used as an alternative to a keeper, for example, to reduce contention while maintaining sufficient noise immunity. Associated with some of the new approaches are increased layout and increased power, but more important than these are a reduction in Vcc_min and an overall reduction in average power consumption.

Embodiments of the invention are shown for purposes of illustration and not limitation, and like reference numerals in the figures of the accompanying drawings refer to like elements.
It is a figure which shows the conventional RF column. FIG. 2 shows a conventional cell stack group for the column of FIG. FIG. 2 shows a conventional dynamic NOR gate with a set dominant latch for the column of FIG. FIG. 3 is a diagram of a dynamic RF column with pseudo-static bit lines, according to some embodiments. FIG. 5 is a diagram of a cell stack group with pseudo-static bit lines for the RF column of FIG. 4 according to some embodiments. FIG. 5 is a diagram of a dynamic NAND gate with pseudo-static circuitry for the column of FIG. 4 according to some embodiments. FIG. 6 is a diagram of a set dominant latch, according to some embodiments. FIG. 3 is a diagram of a dynamic RF column with pseudo-static bit lines, according to some embodiments. FIG. 2 is a diagram of a computer system having a processor with at least one register file circuit, in accordance with some embodiments.

  FIG. 4 illustrates a dynamic comprising at least some pseudo-static bit lines implemented, for example, in a local bit line, a global bit line, and / or an output latch, according to one embodiment of the present invention. The RF column is shown. In the illustrated embodiment, it has a cell stack group 402, a combining logic 404, a dynamic NOR gate 406, and an SDL 408, all of which are coupled together. Combination logic 404 combines a group of local bit lines (LBL [0] to LBL [M-1]) and a group of pre-global bit lines (PG [0] to PG [N-1]). They function to couple to each other and are fed to a dynamic NOR gate 406. The dynamic NOR gate 406 has a global bit line (GBL) that evaluates for the LBL associated with a selected one of the word lines (WL). The GBL value is then latched by SDL 408.

  Cell stack group 402 operates in the same manner as a conventional group including multiple cell stacks, evaluating a bit line when the word line (WL) for the cell stack is asserted. To read data from the memory cell. In some embodiments, a separate local bit line precharge clock (not shown) is used for each group so that only the LBLs of the selected group can be evaluated. Although not required, lines may be utilized to implement pseudo static global bit lines in dynamic NOR gates if possible. In some embodiments, each of the cell stack groups 402 is implemented by a pseudo static LBL node. Similarly, dynamic NOR gate 406 is also implemented with a pseudo-static global bit line (although not required) to reduce contention.

  As used herein, a pseudo-static dynamic bit line is any dynamic bit line (precharged and evaluated) that is selected to keep the keeper and bit line pull down Omit or disable the keeper (or hold) circuit, or at least to reduce (if not eliminate) contention that would otherwise occur with the stack (one or more pull-down devices) The strength is sufficiently reduced. (A “keeper” circuit is a pull-up device that is controlled directly or indirectly by a bit line to “keep” it.) To make up for the lack of a keeper circuit, One or more controlled pull-up devices are included and used in place of the keeper. In this context, the controlled pull-up device is not activated based on the state of the bit line itself, but is controlled by the state of an alternative source (any source other than the bit line). . Such alternative sources include memory cells to be read, different bit lines such as upstream bit lines (possibly through logic gates such as combinational gates), decode logic, signal lines, or the like Including, but not limited to. The controlled pull-up device is typically placed and / or controlled so that it does not turn on when the bit line is discharged (evaluation is low), thereby causing the line to Can be discharged without competing with the pull-up device, but is turned on when the line is evaluated high (maintaining charge). It may or may not be turned on during the precharge phase. The controlled pull-up device is relatively small in size because it normally only needs to support the line in a charged state if the line is rated high, ie it was used for a keeper pull-up device It approximates the thing.

  Combination logic 404 is implemented with any suitable logic circuit to combine individual LBL groups so that their corresponding PG lines assert when any of their constituent LBL lines assert. To do. In some embodiments, NAND gates are used to perform this task. In some embodiments, other gates are used to control the precharge transistors in the dynamic NOR gate 406 based on the clock used to drive the LBL precharge device. This will be further described below.

  (It should be understood that any suitable logic implementation can be used depending on the particular design. For example, although a dynamic NOR gate 406 is shown, other logic implementations, dynamic NAND, XOR, etc. can also be used to achieve the required logic, but the invention is not so limited, similarly, although SDL is illustrated in this example, it is not necessary. In other implementations, other types of latches or non-clock devices such as inverters or the like may be used.)

FIG. 5 illustrates a cell stack group with dynamic pseudo-static bit lines according to some embodiments. The illustrated group 402 has a cell stack (pull-down stack 503) and a precharge device _PLClk coupled to a bit line (LBL). In the illustrated embodiment, the stack includes P-type pass (access) transistor (P _S1 ) and pull-up P-type transistor (P _S1 ) in addition to including stack devices N _S1 , N _S2 arranged conventionally. P _S2 ). The pull-up device (P _S2 ) is a controlled pull-up device and is arranged to supply charge to the bit line when it remains high during the evaluation phase. In the illustrated configuration, its gate is coupled to the gate of the pull-down transistor (N _S2 ) and its drain is coupled to the source of the pass transistor (P _S1 ). The gate of the P-type pass transistor (P _S1 ) is coupled to the word line (WL) of the stack so that when the stack is selected, the pull-up device (P _S2 ) has LBL high. (Ie, in this figure, when the data applied to _NS2 is at a low level during the evaluation), it is coupled through the LBL to keep it at a high level. As a result of the use of a P-type pass transistor (P _S1 ), a high voltage level (eg, Vcc) can be supplied to the LBL more efficiently, ie, a high level requires N-type reduction. Passing through a P-type FET is more efficient than passing through an FET (field effect transistor). Thus, the circuit does not have a keeper circuit coupled to the bit line, but instead the circuit keeps the bit line fully charged when the bit line appears to remain high. Has a pull-up device P _S2 to do so, at the same time, the pull-up device (P _S2 ) does not compete with the pull-down device when the bit line is discharged during evaluation because it is turned off.

FIG. 6 illustrates a dynamic NOR gate 601 with a pseudo static bit line (GBL), according to some embodiments. It consists of a pair of N-type and P-type transistors (P _G00 / N _G00 to P _G30 / N _G30 ), an inverter (I _G00 to I _G30 ), a precharge device (P _GClk ), and a P-type access transistor with a _{(P GA3} from _{P GA0).} In this embodiment, the P-type transistor in the inverter serves as a controlled pull-up device. As shown, the data inputs (PG [0] to PG [3]) are coupled to the inverter input and the inverter output is coupled to the bit line (GBL). In this description, the data inputs (PG [i]) are derived from the output from combinational logic 404 corresponding to the evaluated local bit lines from the RF column, but in other embodiments they are It may come from other sources such as cells or other data output.

Access transistors (P _GA0 to P _GA3 ) are each arranged to controllably supply power to the associated inverter. The access transistors (P _GA0 to P _GA3 ) are controlled by access signals (AL0 to AL3), so that one inverter is enabled at a time. In some embodiments, the access signal corresponds to a signal from a preceding cell stack group section, thereby enabling the inverter coupled to the active PG line.

In operation, during the precharge phase, the precharge device (P _GClk ) is turned on and the access transistors (P _GA0 to P _GA3 ) are turned off, so that the GBL node is charged high. During the evaluation phase, a selected one of the access transistors is asserted. The selected access transistor is the transistor corresponding to the PG line associated with the selected word line. This activates the inverter for this PG line so that it is “evaluated”. Thus, as in the example of FIG. 5, a suppressed pull-up circuit (P _G00 to P _G30 ) is provided to keep the bit line sufficiently high during the evaluation without the need for a keeper circuit. It will be understood that

  FIG. 7 shows an SDL circuit 701 according to some embodiments. 3 except that it includes a transistor (PL6) for controllably disabling the keeper pull-up transistor (PL2) when the SDL is in the pass-through (or transmission) phase. Is similar to many conventional SDL circuits. This occurs when the GPCH Clk input is high. When the SDL input (GBL) comes from a bit line, such as the GBL line from FIG. 6, this will typically correspond to an evaluation phase for the bit line.

P _L6 serves to disable the keeper formed by PL2 and inverter U1 during that time in order not to bias the SDL output (Out) upward. Thus, without PL6, PL2 will act like the same keeper transistor on LBL and GBL. PL6 helps to eliminate this contention and reduce VccMin.

  FIG. 8 illustrates one embodiment of the RF bit column of FIG. It has cell stack group 402, dynamic NOR circuit 601, and SDL 701 with combinational logic 404 as described above, all coupled together as shown. Combinatorial logic 404 combines cell stack groups 402 together and provides them to global bit line NAND circuit 601. Cell stack group 402 (including their local bit lines) and global bit line circuits formed from NAND gate 601 have dynamic pseudo-static bit lines, which are evaluated. Contention can be reduced in the meantime. Meanwhile, the SDL incorporates a keeper circuit, which is disabled (disengaged) during the evaluation phase and recombined for the precharge phase.

  The illustrated example is a 64-bit RF column with 8 cell stack groups, each having 8 stacks (stack 0 to stack 7). (In this figure, only two cell stack groups (corresponding to LB [6] and LB [7] are shown).) The local bit line (LBL [i]) is connected to the precharge clock ( LPCH [i]) and from the cell stack group 402 to the combinational logic 404.

  Combination logic 404 includes a NOR gate 702 and a NAND gate 704. NOR gate 702 combines local precharge clocks (LPCH [i]) from two separate cell stack groups, while NAND gate 704 combines local bit lines (LBL from the same two groups). [I]). NOR gate 702 generates an access signal (ALi) from the applied precharge clock, and each NAND gate 704, for its two applied local bit lines, has a pre-global bit line. (PG [i]) is generated. In the illustrated example having a 64-bit cell and an eight cell stack group, four NOR gates 702 (four access signals, generating AL0 through AL3) and four NAND gates 704 (four preglobal Line signal, PG [0] is generated from PG [0]. (For simplicity and ease of understanding, only one of the four NAND and NOR gates is shown with their generated signals.)

Each access signal (ALi) is coupled to the gate of an associated access transistor (PGAi) in NOR circuit 601 and each pre-global bit line (PG [i]) is associated with an associated inverter in NOR circuit 601. To (I _Gi ). In this embodiment, each cell stack group is clocked by a separate precharge clock (LPCH [i]), it is (here a high level to turn off the P _Clk) shifts to evaluate state. Accordingly, NOR gate 702 for each set of two cell stack groups (or local bit lines) asserts (low level). Turns on the access transistor (PGAi) in the dynamic NOR circuit 601 and enables its associated inverter (I _Gi ), which is the pre-global bit line (PG [i]) from the associated NAND gate 704 ) At the input. Note that each word line WL typically drives multiple bits, for example 64 registers of 32 bits. In this example, a single WL drives 32 output bits. The combination of P _Lclk transistor and NOR can occur at once for all 32 bits, but the NAND gate should be repeated bit by bit. For example, four pre-global line signals per bit may be appropriate, and one or more NOR signals may be appropriate per bit. )

NAND gate 704 is coupled to its local bit line at its input, so if either goes low during the evaluation, its PG goes high, which causes the inverter to go low on the GBL line. Driven by level. During this time, the other access transistors (P _GAi ) are controlled to turn off, disabling their associated inverters so that they do not conflict with the evaluation of the selected inverter on that PG line. This value (high level or low level) is then latched by the SDL at its output (Out) after the GBL evaluation phase, since GPCH Clk goes low. However, during the evaluation time, GPCH_Clk also turns off PL6 in SDL 701, which disables its keeper during evaluation.

  With reference to FIG. 9, an example of a portion of a computer platform (eg, a mobile personal computer, PDA, cell phone, or similar computing system) is shown. The portion shown includes one or more processors 902, interface control functions 904, memory 906, wireless network interface 908, and antenna 909. Processor 902 is coupled to memory 906 and wireless network interface 908 through control function 904. The processor includes a register file 903 having one or more pseudo-static dynamic bit lines in accordance with the embodiments described herein. The control functions include one or more circuit blocks for performing various interface control functions (eg, memory control, graphics control, I / O interface control, etc.). These circuits may be implemented on one or more separate chips and / or may be implemented in part or in whole within processor 902.

  Memory 906 includes one or more memory blocks for providing additional random access memory to processor 902. It is implemented using any suitable memory, including but not limited to dynamic random access memory, static random access memory, flash memory, or the like. Wireless network interface 908 is coupled to antenna 909 for wirelessly coupling processor 902 to a wireless network (not shown), such as a wireless local area network or a cellular network.

  A computer platform implements a variety of different computing devices or other devices with computing capabilities. Such devices include, but are not limited to, laptop computers, notebook computers, personal digital assistants (PDAs), cell phones, audio and / or video media players, and the like. Never happen. It can constitute one or more complete computing systems, or it can consist of one or more components useful in a computing system.

  In the description above, a number of specific details have been described. However, it will be appreciated that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques may not be described in detail so as not to obscure the understanding of the description. With respect to “one embodiment”, “one embodiment”, “example”, “various embodiments”, etc., the embodiments of the invention so described are intended to include specific shapes, structures or characteristics. Although shown, it should be noted that not all embodiments include a particular shape, structure or characteristic. Further, some embodiments may have some, all, or none of the features described for other embodiments.

  In the foregoing description and the following claims, the following terms should be interpreted as follows. That is, the terms “coupled” and “connected” may be used with their derivatives. These terms should not be construed as synonyms for each other. Rather, in particular embodiments, “connected” is used to indicate that two or more elements are in direct physical and electrical contact with each other. “Coupled” is used to indicate that two or more elements cooperate or interact with each other, but they may also be in direct physical and electrical contact; It may not be.

  The term “P-type transistor” or “PMOS transistor” means a P-type metal oxide semiconductor field effect transistor. Similarly, “N-type transistor” or “NMOS transistor” means an N-type metal oxide semiconductor field effect transistor. Where the terms “MOS transistor”, “NMOS transistor”, or “PMOS transistor” are used, they are always used in a typical manner, unless their usage characteristics are explicitly or explicitly stated. They include different types of MOS devices including, for example, devices with different VTs, material types, insulator thicknesses, gate configurations, and the like. Further, unless specifically stated to be MOS or the like, the term “transistor” refers to, for example, junction field effect transistors, bipolar junction transistors, metal semiconductor FETs, and various types of three-dimensional transistors as well as today's knowledge. Other suitable types of transistors that have been developed or have not yet been developed.

  The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be understood that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLA), memory chips, network chips, and the like. There is no.

  Further, it can be seen that in some of the drawings, the signal conductor is represented by a line. Some of them may be drawn thicker to indicate more constituent signal paths, and may have numeric labels to indicate the number of constituent signal paths, and / or There may be arrows at one or more ends to indicate the direction in which the primary information flows. However, these should not be construed as limiting purposes. More precisely, such additional details may be used with respect to one or more exemplary embodiments to make the circuit more understandable. Any of the signal lines shown may include one or more signals that are actually sent in multiple directions, regardless of whether they have additional information, and are, for example, digital or analog lines implemented in different combinations May be implemented with any suitable type of signaling scheme, such as fiber optic lines, and / or single terminated lines.

  Although exemplary sizes / models / values / ranges are given, it should be understood that the invention is not so limited. As production technologies (eg, photolithography) mature over time, it is expected that smaller devices can be manufactured. Also, well-known power / ground connections to IC chips and other components may or may not be shown in the figures to simplify the drawings and specification and not to obscure the present invention. There is also. Furthermore, arrangements may be shown in block diagram form in order not to obscure the present invention, and details regarding the implementation of the arrangements shown in such block diagrams may be implemented in accordance with the invention. In view of the fact that the platform is highly dependent, that is, such details are well known to those skilled in the art. It will be understood that the invention may be practiced with or without these specific details, even if specific details (eg, circuitry) are described to describe embodiments of the invention. It will be obvious to the contractor. Accordingly, this description is to be understood as illustrative rather than restrictive.

402 cell stack group,
406 Combinational logic 408 Set dominant latch (SDL)
503 Pull-down stack 601 Dynamic NOR gate 701 SDL circuit 902 Processor 903 Register file (RF)
904 Interface control function 906 Memory 908 Wireless network interface 909 Antenna GBL Global bit line LBL Local bit line PG Pre-global bit line Wl Word line

Claims (14)

  At least one dynamic coupled to a suppressed pull-up device that turns on when the bit line is evaluated high and off when the bit line is evaluated low A chip comprising a register file circuit having bit lines.   2. The chip of claim 1, wherein the controlled pull-up device has a gate coupled to the output of a memory cell to control the controlled pull-up device.   A P-type access disposed between the controlled pull-up device and the bit line to couple the controlled pull-up device to the bit line when the bit line is evaluated The chip according to claim 2, comprising a device.   4. The chip of claim 3, wherein the P-type access device is controlled by a word line with respect to the bit line.   5. The chip of claim 4, wherein the P-type access device has gates coupled in an inverted form of the word lines.   The chip of claim 1, wherein at least one of the bit lines is a plurality of local bit lines in one or more columns of the register file circuit.   The chip of claim 6, wherein at least one of the bit lines includes a plurality of global bit lines in the register file circuit.   The chip of claim 1 wherein the controlled pull-up device is part of a controllably coupled inverter coupled to the bit line.   9. The chip of claim 8, wherein the controllably connectable inverter is coupled to an access device for supplying power thereto.   10. The chip of claim 9, wherein the access device is controlled by a preceding clock. Maintaining the bit line in a controlled device when the bit line is evaluated high;
Turning off the controlled device when the bit line is evaluated as low;
A method comprising:   The method of claim 11, wherein the controlled device is a controlled P-type device.   The method of claim 11, wherein the controlled device is directly controlled by a memory cell.   The method of claim 11, wherein the bit line is part of a set dominant latch.

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