JP2010148182A - Bias voltage generation circuit, audio signal processing circuit using the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the noise of a circuit which generates a bias voltage. <P>SOLUTION: This bias voltage generation circuit 50 generates the bias voltage Vbias. A charging circuit 54 charges a capacitor C3 by feeing a charging current Ichg to the capacitor. A charging current control circuit CNT1 compares the bias voltage Vbias generated at the capacitor C3 and its target value Vset, and adjusts a value of the charging current Ichg according to the comparison result. A first constant current source CCS1 feeds a first constant current Ic1 to the capacitor C3. A first variable current source VCS1 generates a first variable current Iv1 whose value is changed according to a comparison result generated by the charging current control circuit CNT1. The charging circuit 54 charges the capacitor C3 by using a composite current (Ic1-Iv1) of the first constant current Ic1 and the first variable current Iv1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier circuit that amplifies an AC signal.

  In audio equipment, an audio signal that is a weak electric signal is amplified and output to an electroacoustic transducer such as a speaker or an earphone. In such an audio device, signal processing for performing desired signal processing such as amplification, volume control, and filtering on an analog audio signal (hereinafter simply referred to as an audio signal) including an AC component in an audible band of several Hz to several tens of kHz. A circuit is installed.

  In the first stage of the signal processing circuit, an amplifier circuit (amplifier) is provided to increase the input impedance. The amplifier circuit amplifies the audio signal with a predetermined bias potential as a reference. Therefore, the input terminal of the amplifier circuit is biased to a predetermined bias potential, the audio signal to be processed is coupled to the input terminal via the coupling capacitor, and the audio signal is superimposed on the bias potential.

If the bias voltage is suddenly raised at the start-up of the amplifier circuit, noise is generated and an unpleasant sensation is given to the human ear. Therefore, it is necessary to raise the bias voltage (reference voltage) gently.
JP 2003-258559 A JP 2008-148147 A US Pat. No. 5,993,938

  For example, FIG. 1 of Patent Document 3 shows a resistance voltage dividing circuit including two resistors (R1, R2) provided in series between a power supply terminal and a ground terminal, and a connection point between two resistors (R1, R2). And a bypass capacitor (CB) provided between the ground terminal and a reference voltage (VREF) generating circuit. According to this circuit, since the reference voltage (VREF) increases according to the CR time constant, the time differential value (dVREF / dt) immediately after the start of charging or discharging increases. Referring to FIG. 5A of the cited document 3, at the time of start-up, the reference voltage (VREF) corresponds to the output voltage of the amplifier (116/124), and the speaker (114a) is connected via the coupling capacitor (Cc). The output voltage of the amplifier is supplied. Since the output voltage waveform of the amplifier is differentiated by the coupling capacitor (Cc), a voltage having a steeper waveform is given to the speaker, and noise is generated.

  7, 9 and 10 of Patent Document 3 also disclose a circuit that charges a bypass capacitor (CB) using a constant current source (152) instead of a resistor. In this circuit, the reference voltage (VREF) increases and decreases linearly according to the constant current value as shown in FIG. According to this circuit, noise can be reduced as compared with the case where resistors (R1, R2) are used, but further noise reduction is desired.

  The present invention has been made in view of these problems, and one of its comprehensive purposes is to provide an amplifier circuit that suppresses noise.

  One embodiment of the present invention relates to a bias voltage generation circuit that generates a bias voltage. This bias voltage generation circuit compares a capacitor, a charging circuit that supplies a charging current to the capacitor for charging, and compares the voltage of the capacitor with a target value of the bias voltage and adjusts the value of the charging current according to the comparison result. A current control circuit. The bias voltage generation circuit outputs the capacitor voltage as a bias voltage.

  According to this aspect, the value of the charging current can be optimized according to the level of the bias voltage, and the bias voltage can be gradually raised to reduce noise.

  The charging circuit includes a first current source that supplies a first current to the capacitor, and a first variable current source that generates a first variable current whose value changes according to a comparison result by the charging current control circuit, The capacitor may be charged with a combined current of the first current and the first variable current.

The charging current control circuit may include a differential amplifier in which a predetermined reference voltage is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal. The charging current control circuit may control the first variable current source according to the differential current generated by the differential amplifier.
According to this aspect, by setting the value of the reference voltage according to the target value of the bias voltage, the bias voltage and the target value can be compared, and the charging current can be set to a value according to the comparison result.

  The charging current control circuit may control the first variable current source according to one of the two polar differential currents of the differential amplifier. In this case, the change in the bias voltage can be moderated immediately after the start of charging or immediately before the completion of charging.

The charging current control circuit may control the first variable current source according to a current obtained by synthesizing both of the two polar differential currents of the differential amplifier.
In this case, the change in the bias voltage can be moderated both immediately after the start of charging and immediately before the completion of charging.

The charging current control circuit includes a first differential amplifier in which a predetermined reference voltage is applied to one input terminal and a detection voltage corresponding to a bias voltage is applied to the other input terminal, and a predetermined reference is applied to one input terminal. A second differential amplifier to which a voltage is applied and a detection voltage corresponding to the bias voltage is applied to the other input terminal. The charging current control circuit responds to a current obtained by synthesizing one of the two differential currents generated by the first differential amplifier and one of the two differential currents generated by the second differential amplifier. Thus, the first variable current source may be controlled.
In this case, the charging current can be gradually changed even at the timing when the charging current takes the maximum value, and noise can be further reduced.

A bias voltage generation circuit according to an aspect includes a discharge circuit that draws a discharge current from a capacitor and discharges it, and a discharge current control that compares the voltage of the capacitor with a target value of the bias voltage and adjusts the value of the discharge current according to the comparison result And a circuit.
According to this aspect, even during discharge, noise can be reduced by gradual change in bias voltage.

  The charging circuit includes a first current source that supplies a first current to the capacitor, and a first variable current source that generates a first variable current whose value changes according to a comparison result by the charging current control circuit, The capacitor may be charged with a combined current of the first current and the first variable current. The discharge circuit includes a second current source that extracts the second current from the capacitor, and a second variable current source that generates a second variable current whose value changes according to a comparison result by the discharge current control circuit, The capacitor may be discharged by a combined current of the two currents and the second variable current.

  The charge current control circuit and the discharge current control circuit share a differential amplifier in which a reference voltage corresponding to a target value is applied to one input terminal and a detection voltage corresponding to a bias voltage is applied to the other input terminal. The first variable current source and the second variable current source may be controlled according to the differential current that is configured integrally and generated by the differential amplifier.

  The charge current control circuit and the discharge current control circuit may control each of the first variable current source and the second variable current source according to a current obtained by combining both of the two differential currents of the differential amplifier.

  The charging current control circuit and the discharge current control circuit include a first differential amplifier in which a reference voltage corresponding to the target value is applied to one input terminal and a detection voltage corresponding to a bias voltage is applied to the other input terminal; And a second differential amplifier in which a reference voltage corresponding to a target value is applied to one input terminal and a detection voltage corresponding to a bias voltage is applied to the other input terminal. Good. The charge current control circuit and the discharge current control circuit each include one of the two differential currents generated by the first differential amplifier and one of the two differential currents generated by the second differential amplifier. Each of the first variable current source and the second variable current source may be controlled according to the synthesized current.

  The first variable current source may include a transistor that is provided in a path that draws current from the capacitor, and that has a potential corresponding to the bias voltage input to its control terminal, and turns off as the bias voltage increases. The second variable current source may include a transistor that is provided in a path for supplying a current to the capacitor, and that has a potential corresponding to the bias voltage input to its control terminal, and turns off as the bias voltage decreases.

Another aspect of the present invention is an audio signal processing circuit. The audio signal processing circuit includes an amplifier circuit that amplifies the audio signal, and a bias voltage generation circuit according to any one of the above-described modes that generates a bias voltage for the amplifier circuit.
In this specification, “amplification” includes not only the case where the gain is larger than 1, but also the case where the gain is smaller than 1, that is, “attenuation”, or the case where the gain is 1 (simply impedance conversion).

  Yet another embodiment of the present invention is an electronic device. The electronic device includes an audio signal generation unit that outputs an analog audio signal, the above-described audio signal processing circuit that performs predetermined signal processing on the audio signal, and an output signal of the audio signal processing circuit that is converted into an acoustic signal. An audio output unit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, noise can be suppressed.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a block diagram showing a configuration of an audio playback device 300 including an amplifier circuit 100 according to the present embodiment. The audio playback device 300 has a function of outputting an audio signal (audio signal), and is mounted on an electronic device such as a mobile phone terminal, a portable audio player, a digital still camera, and a digital video camera. The audio playback device 300 includes an audio management IC 200, an audio signal generation unit 210, and an audio output unit 220.

  The audio signal generation unit 210 generates an analog audio signal S 1 and outputs it from the output terminal 202. The audio signal S1 generated by the audio signal generation unit 210 differs depending on the electronic device. For an audio player, the audio signal S1 is music or a beep sound. For a mobile phone terminal, a ring tone, a call partner, other sounds, etc. It is.

  The audio management IC 200 functions as an audio signal processing circuit that executes predetermined signal processing on the audio signal S1. The predetermined signal processing differs depending on the electronic device, and examples thereof include amplification, volume control, and filtering. The audio management IC 200 is preferably integrated on a single semiconductor substrate.

  The coupling capacitor C1 is provided between the audio signal generation unit 210 and the audio management IC 200. The audio output unit 220 is an electroacoustic conversion element such as a speaker, headphones, or earphones. The audio output unit 220 receives the output signal S2 of the audio management IC 200 via the coupling capacitor C2, converts it into an acoustic signal, and outputs it.

  The audio management IC 200 includes an amplifier circuit 100. In FIG. 1, the audio management IC 200 is the amplifier circuit 100 itself. However, the audio management IC 200 may actually include circuit blocks (not shown) other than the amplifier circuit 100.

  The amplifier circuit 100 is provided in the first stage of the audio management IC 200, and also functions as an input buffer of the audio management IC 200. In addition, the amplifier circuit 100 superimposes the audio signal S1 on the bias potential Vbias. That is, in the audio management IC 200, the audio signal S1 vibrates around the bias voltage Vbias. For example, the bias voltage Vbias is set to the midpoint Vdd / 2 between the power supply voltage Vdd supplied to the audio management IC 200 and the ground potential.

  In FIG. 1, the audio management IC 200 and the audio signal generation unit 210 are configured as separate ICs, but may be configured as the same IC.

  The overall configuration of the audio playback device 300 has been described above. Next, the configuration of the amplifier circuit 100 will be described. The amplification circuit 100 includes an amplification unit 10 and a bias voltage generation circuit 50.

  The amplifying unit 10 amplifies the audio signal S1 input via the coupling capacitor C1. 1 is an inverting amplifier, but the present invention is not limited to this, and may be a non-inverting amplifier or a simple voltage follower (buffer).

  The amplifying unit 10 includes an operational amplifier 12, a feedback resistor R1, and an input resistor R2. A bias voltage Vbias is applied to the non-inverting input terminal (+) of the operational amplifier 12. The input resistor R2 is provided between the inverting input terminal (−) of the operational amplifier 12 and the coupling capacitor C1. The feedback resistor R1 is provided between the output terminal of the operational amplifier 12 and the inverting input terminal (−).

When the voltage of the output signal S2 of the amplifier 10 is Vo and the voltage amplitude of the input audio signal S1 is Vi,
Vo = Vbias + (Vbias−Vi) × R1 / R2 (1)
Holds.

  The output terminal of the operational amplifier 12 is connected to the output pad 104. The output pad 104 is connected to the audio output unit 220 via the coupling capacitor C2.

  The bypass switch SW1 is provided between the first node N1 on the output terminal side of the amplification unit 10 and the second node N2 on the input terminal side of the amplification unit 10. The first node N1 is an output terminal of the operational amplifier 12, and the second node N2 is an inverting input terminal (−).

  The on / off state of the bypass switch SW1 is controlled by the control unit 30.

  The bias voltage generation circuit 50 generates a bias voltage Vbias to be superimposed on the audio signal S1 in the amplification unit 10. The bias voltage generation circuit 50 includes a capacitor C3 and a charge / discharge circuit 52.

  One end of the capacitor C3 is grounded and its potential is fixed, and the other end is connected to the capacitor terminal 106. The charging / discharging circuit 52 includes a charging circuit 54 that supplies a charging current Ichg to the capacitor C3 and a discharging circuit 56 that extracts the discharging current Idis, and controls the amount of charge in the capacitor C3. The bias voltage generation circuit 50 outputs a bias voltage Vbias corresponding to the amount of charge stored in the capacitor C3.

  The above is the configuration of the amplifier circuit 100. Next, the operation will be described.

  When the audio playback device 300 is turned on or returned from the standby state (hereinafter simply referred to as startup), the potential of the input terminal 102 is the ground potential (0 V). When the audio playback device 300 is activated, the control unit 30 turns on the bypass switch SW1. When the bypass switch SW1 is turned on, the operational amplifier 12 and the amplification unit 10 function as a voltage follower circuit. Therefore, the potentials of the first node N2 and the second node N2 are bias voltages input to the non-inverting input terminal of the operational amplifier 12. It becomes equal to Vbias.

In this state, when the charging / discharging circuit 52 starts charging the capacitor C3, the bias voltage Vbias gradually rises with time. As a result, the potentials of the first node N1 and the second node N2 also rise gradually with time.
When the bias voltage Vbias reaches a predetermined target value Vset, the bypass switch SW1 is switched from on to off. After the bypass switch SW1 is turned off, the mute is released (active state), and the amplifying unit 10 can amplify the audio signal S1 and output it to the audio output unit 220.

  The above is the operation of the audio playback device 300. The audio reproduction device 300 according to the embodiment is characterized by the configuration of the bias voltage generation circuit 50. Hereinafter, the configuration of the bias voltage generation circuit 50 will be described in detail.

  FIG. 2 is a circuit diagram showing a configuration of the bias voltage generation circuit 50 according to the embodiment. The bias voltage generation circuit 50 includes a capacitor C3 and a charge / discharge circuit 52. The charging / discharging circuit 52 includes a charging circuit 54, a charging current control circuit CNT1, a discharging circuit 56, and a discharging current control circuit CNT2.

  First, pay attention to the charging side. The charging circuit 54 charges the capacitor C3 by supplying a charging current Ichg. The charging current control circuit CNT1 compares the bias voltage Vbias generated in the capacitor C3 with a target value Vset (for example, Vdd / 2) of the bias voltage, and controls the value of the charging current Ichg according to the comparison result.

  Specifically, the charging circuit 54 includes a first constant current source CCS1, a first variable current source VCS1, and a first switch SW11.

  The first constant current source CCS1 generates a predetermined first constant current Ic1 and supplies it to the capacitor C3. The first variable current source VCS1 generates a first variable current Iv1 whose value changes based on the control signal S11 according to the comparison result by the charging current control circuit CNT1.

  The first switch SW11 is provided between the first constant current source CCS1 and the capacitor C3. When the bypass switch SW1 is turned on, a differential current (Ic1-Iv1) between the first constant current Ic1 and the first variable current Iv1 flows through the first switch SW11. The charging circuit 54 charges the capacitor C3 using the differential current (Ic1-Iv1) as the charging current Ichg.

  In the circuit of FIG. 2, the first variable current source VCS1 is configured by an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a control signal S10 corresponding to a comparison result is input to a control terminal (gate). The various transistor elements in this specification may be bipolar transistors.

  The charging current control circuit CNT1 includes a differential amplifier AMP1. The differential amplifier AMP1 includes transistors M11 and M12 that form a differential pair, a tail current source CS10 that supplies a predetermined tail current It1 to the differential pair, and transistors M13 and M14 that are provided as loads for the differential pair. . Here, each of the tail current It1 and the first variable current Iv1 is set smaller than the first constant current Ic1.

  A reference voltage Vref corresponding to the target value Vset of the bias voltage Vbias is applied to one input terminal of the differential amplifier AMP1. A detection voltage Vs1 corresponding to the bias voltage Vbias is applied to the other input terminal. In the configuration of FIG. 2, the detection voltage Vs1 is the bias voltage Vbias, but a voltage obtained by dividing the bias voltage Vbias may be used as the detection voltage Vs1.

  The charging current control circuit CNT1 outputs one of the differential output signals (voltage signals) of the differential amplifier AMP1 as the control signal S11. The control signal S11 is a signal corresponding to the comparison result between the detection voltage Vs1 and the reference voltage Vref. The control signal S11 is applied to the gate of the first variable current source VCS1, and the first variable current Iv1 flowing through the first variable current source VCS1 is adjusted. The MOSFET of the transistor M13 and the first variable current source VCS1 forms a current mirror circuit. Therefore, the first variable current Iv1 generated by the first variable current source VCS1 is proportional to one (Id1) of the differential current generated by the differential amplifier AMP1.

  From another viewpoint, the MOSFET of the first variable current source VCS1 and the charging current control circuit CNT1 can be grasped as a voltage-current conversion circuit that converts the detection voltage Vs1 into the first variable current Iv1.

  Next, focus on the discharge side. The discharge circuit 56 draws the discharge current Idis from the capacitor C3 and discharges the capacitor C3. The discharge current control circuit CNT2 compares the bias voltage Vbias generated in the capacitor C3 with its target value Vset (for example, Vdd / 2), and adjusts the value of the discharge current Idis according to the comparison result.

  The function and configuration of the discharge circuit 56 correspond to those of the charging circuit 54, and the function and configuration of the discharge current control circuit CNT2 also correspond to those of the charging current control circuit CNT1. The correspondence between the charge side and the discharge side is shown below.

  The discharge circuit 56 is a charging circuit 54, the second constant current source CCS2 is a first constant current source CCS1, the second variable current source VCS2 is a first variable current source VCS1, the second switch SW12 is a first switch SW11, The discharge current control circuit CNT2 corresponds to the charge current control circuit CNT1, the transistors M21 to M24 correspond to the transistors M11 to M14, and the tail current source CS20 corresponds to CS10.

  The discharge circuit 56 becomes active when the second switch SW12 is turned on, and a discharge current corresponding to the difference (Ic2-Iv2) between the predetermined constant current Ic2 and the second variable current Iv2 generated by the second variable current source VCS2. The capacitor C3 is discharged by Idis.

  FIG. 3 is a time chart showing operation waveforms at the start of the bias voltage generation circuit 50 of FIG. Before time t0, the capacitor C3 is completely discharged, and the bias voltage Vbias is 0V. At time t0, the first switch SW11 is turned on, and the bias voltage generation circuit 50 is set to a charged state. Immediately after the start of charging, since Vbias <Vref, most of the tail current It1 of the differential amplifier AMP1 flows to the transistor M11 side. That is, the first variable current Iv1 becomes maximum immediately after the start of charging. The size of each transistor and the value of each constant current are designed so that the maximum value of the first variable current Iv1 matches the first constant current Ic1.

  Immediately after the start of charging, since Iv1≈Ic1 is established, the charging current Ichg has a very small value. Thereafter, when the charging current Ichg is supplied to the capacitor C3, the bias voltage Vbias increases. As the bias voltage Vbias increases, the differential balance of the differential amplifier AMP1 changes, the value of the first variable current Iv1 gradually decreases, and the charging current Ichg increases. When the bias voltage Vbias reaches the target value Vset, the first switch SW11 is turned off and the charging of the capacitor C3 is stopped.

  As described above, according to the bias voltage generation circuit 50 of FIGS. 1 and 2, since the charging current Ichg can be set to a very small value immediately after the start of charging, the bias voltage Vbias can be gradually changed, and noise can be reduced. Generation | occurrence | production can be suppressed suitably.

  Since the operation on the discharge side is the same as that on the charge side, description thereof is omitted.

  FIG. 4 is a circuit diagram showing a modification of the bias voltage generation circuit of FIG. The bias voltage generating circuit 50a of FIG. 4 is characterized in that the charging current control circuit CNT1 and the discharging current control circuit CNT2 are configured using a common differential amplifier AMP1. Hereinafter, the charge current control circuit CNT1 and the discharge current control circuit CNT2 configured by sharing a single differential amplifier AMP1 are collectively referred to as a charge / discharge current control circuit CNT.

  The transistor M31 forms a current mirror circuit with the transistor M14. The transistor M32 forms a current mirror circuit with the transistor of the second variable current source VCS2, and is provided to return the current flowing through the transistor M31.

  In this configuration, the second variable current Iv2 generated by the second variable current source VCS2 is proportional to the other differential current (Id2) of the differential amplifier AMP1.

  According to the circuit of FIG. 4, since the differential amplifier AMP1 can be shared by the charging current control circuit CNT1 and the discharging current control circuit CNT2, the circuit area can be reduced. In FIG. 4, it is also possible to replace the differential amplifier AMP1 with the form of the differential amplifier AMP2 in FIG. 2 by appropriately folding back each current signal.

  FIG. 5 is a circuit diagram showing a modification of the bias voltage generation circuit of FIG. Also in the bias voltage generation circuit 50b of FIG. 5, the charging current control circuit CNT1 and the discharging current control circuit CNT2 are configured to share the differential amplifier AMP1.

Comparing FIG. 5 and FIG. 4, the configuration and function of the charge / discharge current control circuit CNT are different. That is, the charge / discharge current control circuit CNT in FIG. 4 adjusts the charge current Ichg based on only one of the differential currents Id1 and Id2 (Id1) of the differential amplifier AMP1, and conversely, the discharge current Idis The adjustment is made based only on the other (Id2) of the differential currents Id1 and Id2 of the dynamic amplifier AMP1.
On the other hand, the charge / discharge current control circuit CNT in FIG. 5 adjusts the charge current Ichg based on both the differential currents Id1 and Id2. Similarly, the discharge current Idis is adjusted based on both the differential currents Id1 and Id2.

  The charge / discharge current control circuit CNT of FIG. 5 further includes current sources CS11 and CS12 and transistors M15 and M16 in addition to those of FIG.

  Current sources CS11 and CS12 are connected to transistors M13 and M14, respectively. The current source CS11 draws the constant current It1 from the drain of the transistor M13 to another path. Further, the current source CS12 draws the constant current It1 from the drain of the transistor M14 to another path. The constant current It1 is set to ½ of the tail current (2 × It1) generated by the tail current source CS10. A current Id1 '(= Id1-It1) flows through the transistor M13, and a current Id2' (= Id2-It1) flows through the transistor M14.

  The transistors M15 and M16 are respectively connected to the transistors M13 and M14 so as to form a current mirror circuit, and copy currents Id1 and Id2 flowing through the transistors M13 and M14. The drains of the transistors M15 and M16 are connected in common, and a sum current (Id1 ″ + Id2 ″) of the copied differential currents Id1 ″ and Id2 ″ is generated. Hereinafter, this sum current (Id1 ″ + Id2 ″) is also referred to as a correction current Icmp.

  The charge / discharge current control circuit CNT adjusts the charge current Ichg and the discharge current Ichg based on the correction current Icmp. Specifically, the first variable current Iv1 and the second variable current Iv2 are set to values corresponding to the correction current Icmp.

  The transistors M33, M34, and M35 are current mirror circuits for copying or folding the correction current Icmp. With this configuration, the first variable current source VCS1 and the second variable current source VCS2 respectively suitably generate the first variable current Iv1 and the second variable current Iv2 that are proportional to the correction current Icmp.

  In FIG. 5, a modification in which differential amplifiers AMP1 and AMP2 are provided for the charging-side charging current control circuit CNT1 and the discharging-side discharging current control circuit CNT2 is also effective as an aspect of the present invention.

  The operation of the bias voltage generation circuit 50b in FIG. 5 will be described. FIG. 6 is a time chart showing operation waveforms when the bias voltage generation circuit 50b of FIG. 5 is started. Before time t0, the capacitor C3 is completely discharged, and the bias voltage Vbias is 0V. At time t0, the first switch SW11 is turned on, and the bias voltage generation circuit 50 is set to a charged state.

  As the bias voltage Vbias increases, the first variable current Iv1 (Icmp) decreases, and Id1 = Id2 = It1 is established in a state where the differential amplifier AMP1 is balanced. At this time, the first variable current Iv1 (Icmp) is substantially zero. When the bias voltage Vbias further increases, the first variable current Iv1 starts to increase.

  That is, the charging current Ichg is substantially zero at the charging start timing t0, increases with time to reach the maximum value (time t1), starts to decrease, and substantially reaches the charging completion timing (t2). To zero.

  The effect of the bias voltage generation circuit 50b of FIG. 5 is further clarified by comparing the time chart of FIG. 6 with the time chart of FIG. In the time chart of FIG. 3, the bias voltage Vbias changes abruptly at the charging completion timing (t2). On the other hand, referring to the time chart of FIG. 6, the bias voltage Vbias gradually converges to the target value Vset at the charging completion timing (t2), so that the generation of noise can be further suppressed.

FIG. 7 is a circuit diagram showing a modification of the charge / discharge current control circuit of FIG.
The charge / discharge current control circuit CNT in FIG. 5 generates two differential currents Id1 and Id2 by a single differential amplifier AMP1. On the other hand, the charge / discharge current control circuit CNT of FIG. 7 is provided with a differential amplifier AMP11 that generates a differential current Id1 and a differential amplifier AMP12 that generates a differential current Id2. The configuration of each differential amplifier AMP11, AMP12 is the same as that of the differential amplifier AMP1 in FIG.

  FIG. 8 is a time chart showing operation waveforms at the start of the bias voltage generation circuit using the charge / discharge current control circuit CNT of FIG. The effect of the charge / discharge current control circuit CNT of FIG. 7 is further clarified by comparing the time chart of FIG. 8 with the time chart of FIG. In the time chart of FIG. 6, the charging current Ichg changes rapidly at the timing (t1) when the charging current Ichg takes a maximum value. On the other hand, when the charging / discharging current control circuit CNT of FIG. 7 is used, the charging current Ichg gradually changes even at the timing (t1) when the charging current Ichg takes a maximum value, so that the waveform of the bias voltage Vbias is changed. Furthermore, it can be changed smoothly, and the generation of noise can be further suppressed.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  FIG. 9 is a circuit diagram showing a configuration of a modification of the bias voltage generation circuit of FIG. In the bias voltage generation circuit 50c of FIG. 9, an N-channel MOSFET is provided as the first variable current source VCS1, and a P-channel MOSFET is provided as the second variable current source VCS2. A bias voltage Vbias is directly applied to the gate of the transistor of the first variable current source VCS1 and the gate of the transistor of the second variable current source VCS2. That is, the charge current control circuit CNT1 and the discharge current control circuit CNT2 are substantially omitted, and the circuit area can be reduced.

  FIGS. 10A to 10C are circuit diagrams illustrating modifications of the charge / discharge circuit 52 (the charge circuit 54 and the discharge circuit 56). In FIG. 10A, the charge / discharge circuit 52 includes a first constant current source CCS1, a second constant current source CCS2, and a switch SW12. The second constant current Ic2 generated by the second constant current source CCS2 is set to be twice the first constant current Ic1 generated by the first constant current source CCS1. The charging / discharging circuit 52 functions as a charging circuit 54 when the switch SW12 is off, and functions as a discharging circuit 56 when the second switch SW12 is on.

  The charge / discharge circuit 52 of FIG. 10B is a circuit in which the second constant current source CCS2 of the charging circuit 54 of FIG. 2 is replaced with a resistor. The charge / discharge circuit 52 in FIG. 10C is a circuit in which the first constant current source CCS1 of the discharge circuit 56 in FIG. 2 is replaced with a resistor Rc1.

  The charge / discharge circuit 52 shown in FIGS. 2, 4, 5, 9 and the like can be replaced with the charge / discharge circuit 52 shown in FIGS. 10 (a) to 10 (c). include.

  The bias voltage generation circuit 50 may be provided with a target voltage setting circuit for holding the bias voltage Vbias at the target value Vset. 11A to 11D are circuit diagrams showing the configuration of the target voltage setting circuit.

  The target voltage setting circuit 60a in FIG. 11A includes a comparator CMP1 and resistors Rs1 and Rs2. The resistors Rs1 and Rs2 divide the power supply voltage Vdd to generate a target value Vset of the bias voltage Vbias. The comparator CMP1 compares the bias voltage Vbias with the target value Vset, and when Vbias reaches Vset, both the first switch SW11 and the second switch SW12 are turned off.

  The target voltage setting circuits 60b to 60c in FIGS. 11B to 11C are clamp circuits that fix the bias voltage Vbias to a predetermined voltage. The target voltage setting circuit 60b in FIG. 11B includes transistors M31 to M34 and resistors Rs3 and Rs4. Target value Vset is set according to the values of resistors Rs3 and Rs4.

  The target voltage setting circuit 60c in FIG. 11C includes n (n is a natural number) diodes provided between the capacitor C3 and the power supply terminal. In this circuit, the target value Vset is set to (Vdd−n × Vf). Vf is the forward voltage of the diode.

  The target voltage setting circuit 60d in FIG. 11D includes n (n is a natural number) diodes provided between the capacitor C3 and the ground terminal. In this circuit, the target value Vset is set to n × Vf.

  Note that the configuration of the target voltage setting circuit 60 is not limited to those shown in FIGS. 11A to 11D, and may be other configurations.

  In the embodiment, the bias voltage generation circuit 50 having both the function of charging and discharging the capacitor C3 has been described. However, the bias voltage generation circuit including only one of them is also effective as an aspect of the present invention.

It is a block diagram which shows the structure of an audio reproduction apparatus provided with the amplifier circuit which concerns on this Embodiment. It is a circuit diagram which shows the structure of the bias voltage generation circuit which concerns on embodiment. 3 is a time chart showing operation waveforms at the time of starting the bias voltage generation circuit of FIG. 2. FIG. 6 is a circuit diagram showing a modification of the bias voltage generation circuit of FIG. 2. FIG. 5 is a circuit diagram illustrating a modification of the bias voltage generation circuit of FIG. 4. 6 is a time chart showing operation waveforms when the bias voltage generation circuit of FIG. 5 is started. FIG. 6 is a circuit diagram showing a modification of the charge / discharge current control circuit of FIG. 5. It is a time chart which shows the operation waveform at the time of starting of the bias voltage generation circuit using the charging / discharging current control circuit of FIG. FIG. 3 is a circuit diagram showing a configuration of a modification of the bias voltage generation circuit of FIG. 2. FIGS. 10A to 10C are circuit diagrams illustrating modifications of the charging / discharging circuit (charging circuit and discharging circuit). 11A to 11D are circuit diagrams showing the configuration of the target voltage setting circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Amplifier part, 12 ... Operational amplifier, C1 ... Coupling capacitor, C3 ... Capacitor, R1 ... Feedback resistance, R2 ... Input resistance, SW1 ... Bypass switch, 100 ... Amplification circuit, 102 ... Input terminal, 200 ... Audio management IC , 210... Audio signal generation unit, 220. Audio output unit, 300. Audio reproduction device, 50... Bias voltage generation circuit, 52... Charge / discharge circuit, 54. CNT2 ... discharge current control circuit, CNT ... charge / discharge current control circuit, CCS1 ... first constant current source, CCS2 ... second constant current source, VCS1 ... first variable current source, VCS2 ... second variable current source, Ic1 ... first 1 constant current, Ic2 ... second constant current, Iv1 ... first variable current, Iv2 ... second variable current, Ichg ... charge current, Idis ... discharge current, W11 ... first switch, SW12 ... second switch, AMP1 ... differential amplifier, 60 ... target voltage setting circuit.

Claims (13)

A bias voltage generation circuit for generating a bias voltage,
A capacitor;
A charging circuit for charging the capacitor by supplying a charging current;
A charge current control circuit that compares the voltage of the capacitor with a target value of the bias voltage and adjusts the value of the charge current according to a comparison result;
A bias voltage generating circuit, wherein the capacitor voltage is output as the bias voltage. The charging circuit is
A first current source for supplying a first current to the capacitor;
A first variable current source for generating a first variable current whose value changes according to the comparison result by the charging current control circuit;
2. The bias voltage generation circuit according to claim 1, wherein the capacitor is charged by a combined current of the first current and the first variable current. The charging current control circuit includes:
A differential amplifier in which a predetermined reference voltage is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal;
3. The bias voltage generation circuit according to claim 2, wherein the first variable current source is controlled in accordance with a differential current generated by the differential amplifier. The charging current control circuit includes:
4. The bias voltage generation circuit according to claim 3, wherein the first variable current source is controlled in accordance with a current obtained by synthesizing both of two differential currents of the differential amplifier. 5. The charging current control circuit includes:
A first differential amplifier in which a predetermined reference voltage is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal;
A second differential amplifier in which a predetermined reference voltage is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal;
Including
In accordance with a current obtained by combining one of the bipolar differential currents generated by the first differential amplifier and one of the bipolar differential currents generated by the second differential amplifier, 4. The bias voltage generating circuit according to claim 3, wherein one variable current source is controlled. A discharge circuit for discharging a discharge current from the capacitor and discharging;
A discharge current control circuit that compares the voltage of the capacitor with a target value of the bias voltage and adjusts the value of the discharge current according to a comparison result;
The bias voltage generation circuit according to claim 1, further comprising: The charging circuit is
A first current source for supplying a first current to the capacitor;
A first variable current source for generating a first variable current whose value changes according to the comparison result by the charging current control circuit;
The capacitor is charged with a combined current of the first current and the first variable current, and the discharge circuit includes:
A second current source for drawing a second current from the capacitor;
A second variable current source for generating a second variable current whose value changes according to the comparison result by the discharge current control circuit;
The bias voltage generation circuit according to claim 6, wherein the capacitor is discharged by a combined current of the second current and the second variable current. The charge current control circuit and the discharge current control circuit are:
A reference voltage corresponding to the target value is applied to one input terminal, and a differential amplifier in which a detection voltage corresponding to the bias voltage is applied to the other input terminal is configured integrally.
8. The bias voltage generation circuit according to claim 7, wherein each of the first variable current source and the second variable current source is controlled in accordance with a differential current generated by the differential amplifier. The charge current control circuit and the discharge current control circuit are:
9. The bias according to claim 8, wherein each of the first variable current source and the second variable current source is controlled in accordance with a current obtained by combining both of the two differential currents of the differential amplifier. Voltage generation circuit. The charge current control circuit and the discharge current control circuit are:
A first differential amplifier in which a reference voltage corresponding to the target value is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal;
A second differential amplifier in which a reference voltage corresponding to the target value is applied to one input terminal and a detection voltage corresponding to the bias voltage is applied to the other input terminal;
Are integrated into one unit,
In accordance with a current obtained by combining one of the bipolar differential currents generated by the first differential amplifier and one of the bipolar differential currents generated by the second differential amplifier, 8. The bias voltage generation circuit according to claim 7, wherein each of the first variable current source and the second variable current source is controlled. The first variable current source includes a transistor that is provided in a path for drawing a current from the capacitor, has a potential corresponding to the bias voltage input to a control terminal thereof, and is turned off as the bias voltage increases.
The second variable current source includes a transistor provided in a path for supplying a current to the capacitor, a potential corresponding to the bias voltage is input to a control terminal thereof, and a transistor that is turned off as the bias voltage decreases. 8. The bias voltage generating circuit according to claim 7, wherein An amplifier circuit for amplifying the audio signal;
The bias voltage generation circuit according to any one of claims 1 to 11, which generates a bias voltage for the amplifier circuit;
An audio signal processing circuit comprising: An audio signal generator for outputting an analog audio signal;
The audio signal processing circuit according to claim 12, wherein predetermined signal processing is performed on the audio signal;
An audio output unit that converts an output signal of the audio signal processing circuit into an acoustic signal;
An electronic device comprising:

Images