JP2010147409A - Semiconductor device with field effect type transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a function as a gate insulating film ensuring a good insulating property and an extremely high dielectric ratio and a function as a metallic gate electrode where no depletion layer is formed, and which can significantly increase an electrostatic control power over a channel region of a gate voltage. <P>SOLUTION: The semiconductor device includes: a first source region 12a and a first drain region 12b of a second conductivity type spaced from each other in a first semiconductor layer 12 of a first conductivity type; a first channel region 12c in the first semiconductor layer between the first source region and the first drain region; a first gate electrode 60 of a half-metal ferromagnetic metal on the first channel region; and a first source electrode 50a of a half-metal ferromagnetic metal to be connected to the first source region. The direction of magnetization 64c of the first gate electrode is substantially anti-parallel to the direction of magnetization 64a of the first source electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a field effect transistor.

  As represented by the remarkable spread of high-frequency mobile communications, the realization of ultra-high-speed and high-performance semiconductor devices has significantly promoted information on social life. Along with this, demands for speeding up, miniaturization, large-scale integration, and one-chip integration of individual semiconductor elements used in these semiconductor devices are increasing over time.

  However, when considering miniaturization and speeding up of MOSFETs, which are the main components of these semiconductor elements, various difficulties are associated with this. For example, as the channel length of the MOSFET (ie, the length of the gate electrode) decreases, the threshold voltage decreases (short channel effect). If an element different from the threshold voltage intended at the time of designing the semiconductor device is formed, an element operation different from the design intention is caused to impair the function of the entire device.

  Such a short channel effect can be suppressed by reducing the thickness of the gate insulating film in accordance with the miniaturization of the MOSFET (that is, based on the scaling law). That is to say, the gate insulating film is made thinner, so that the electrostatic dominance of the gate voltage on the channel region is increased, and even if the gate voltage is miniaturized, the threshold voltage can be prevented from fluctuating.

  However, when such a thin film is used while a conventionally used silicon oxide film is used as the gate insulating film, the tunnel leakage current directly increases and the insulating property is remarkably lowered. For this reason, when a silicon oxide film is used, the difficulty that the film thickness of a gate insulating film cannot be thinned to 2.0 nm or less arises.

In order to cope with such difficulties, in recent years, so-called “high dielectric gate insulating films”, such as ZrO ₂ and HfO ₂ , which have a higher dielectric constant than silicon oxide films, have been vigorously developed. This is because if the dielectric constant is high, it is easier to transmit the electrostatic dominant force of the gate voltage to the channel region than the insulating film having a low dielectric constant even with the same physical film thickness.

  However, the dielectric constant of a material depends on the ease of electrical polarization in the material, including the generation of virtual electron / hole pairs, and increasing the dielectric constant reduces the forbidden bandwidth (band gap) of the material. However, there is a fundamental physical and physical difficulty that the insulating property is significantly deteriorated (see, for example, Non-Patent Document 1). If the band gap is reduced, naturally, the insulating properties of the material deteriorate. In fact, a substance having an effectively infinite dielectric constant is called a metal, but it is a well-known fact that a metal has no band gap and is a good conductor.

  In order to cope with such inevitable deterioration of the insulating property due to an increase in the dielectric constant, the film thickness of the high dielectric gate insulating film must be increased. However, increasing the film thickness naturally reduces the electrostatic dominance of the gate voltage. Therefore, even if an attempt is made to increase the electrostatic control power of the gate voltage by increasing the dielectric constant, it is necessary to increase the film thickness in order to ensure insulation. As a result, we are faced with a situation where a sufficient improvement in the electrostatic control of the gate voltage cannot be achieved.

On the other hand, in order to increase the electrostatic dominance of the gate voltage by reducing the thickness of the gate insulating film, it is necessary to consider the material of the gate electrode itself. As the gate insulating film becomes thinner, the electric field generated in the gate insulating film naturally increases. At this time, if the gate electrode is formed of polysilicon doped with conductive impurities as conventionally used, a depletion layer is also formed in the gate electrode. Since this depletion layer substantially acts as an additional gate insulating film, a sufficient improvement of the electrostatic dominance of the gate voltage on the channel region cannot be achieved. Therefore, as the gate insulating film is made thinner, it is essential to use a metallic substance for the gate electrode.
J. Robertson, Rep. Prog. Phys. 69 (2006) p.327

  As described above in detail, it is necessary to increase the electrostatic dominance of the gate voltage on the channel region as the element is miniaturized. However, even if this is achieved by the high dielectric gate insulating film, it is difficult to increase the dielectric constant while ensuring good insulation.

  In addition, if a depletion layer is formed in the gate electrode as the gate insulating film becomes thinner, there is a disadvantage that sufficient improvement in the electrostatic control power of the gate electrode cannot be achieved.

  The present invention has been made in consideration of the above circumstances, and has a function of a gate insulating film having an extremely high dielectric constant while ensuring good insulation, and a metallic property in which a depletion layer is not formed. An object of the present invention is to provide a semiconductor device having the function of a gate electrode and capable of increasing the electrostatic control power of a gate voltage to a channel region as much as possible.

  A semiconductor device according to a first aspect of the present invention includes a first source region and a first drain region of a second conductivity type provided separately from a first semiconductor layer of a first conductivity type, the first source region, A first channel region provided in the first semiconductor layer between the first drain region; a first gate electrode of a half-metal ferromagnetic metal provided on the first channel region; and the first source region. A first source electrode of a half metal ferromagnetic metal provided so as to be connected to the first metal electrode, and a magnetization direction of the first gate electrode is substantially antiparallel to a magnetization direction of the first source electrode. It is characterized by.

  According to a second aspect of the present invention, there is provided a semiconductor device formed on a substrate and having a pair of opposing side surfaces, a first conductivity type first semiconductor layer, the first semiconductor layer, and the pair of paired side surfaces. A first source region and a first drain region of a second conductivity type, which are provided parallel to the side surfaces and spaced apart from each other in a direction parallel to the upper surface of the substrate, each including a part of the pair of side surfaces; A first layer formed in the first semiconductor layer between the first source region and the first drain region and including a part of the pair of side surfaces not included in the first source region and the first drain region. A channel region, a first gate electrode of a half metal ferromagnetic metal provided so as to cover the pair of side surfaces included in the first channel region, and a half metal provided so as to be connected to the first source region Ferromagnetic And a first source electrode of the genus, the magnetization direction of the first gate electrode, characterized in that it is a parallel magnetization orientation and Ryakuhan of the first source electrode.

  According to the present invention, it has a function of a gate insulating film having a very high dielectric constant while ensuring good insulating properties, and a function of a metallic gate electrode in which a depletion layer is not formed. It is possible to provide a semiconductor device capable of increasing the electrostatic dominance over the channel region as much as possible.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 8 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. The semiconductor device of this embodiment has an n-type field effect transistor structure formed on an SOI (Silicon On Insulator) substrate, and is manufactured as follows.

  First, a silicon semiconductor substrate 10 formed using a known technique, a silicon oxide film (also referred to as a buried insulating film (BOX)) 11 formed on the silicon semiconductor substrate 10, and the silicon oxide film 11 An SOI wafer composed of the formed single crystal silicon semiconductor layer (SOI layer) 12 for element formation is prepared. Next, the SOI layer 12 other than the element formation region is removed by using a known technique such as a lithography technique or an RIE (Reactive Ion Etching) method (FIG. 1).

  Next, a dummy gate 20 made of, for example, carbon is formed in a region where a gate electrode is to be formed by using, for example, lithography technology and RIE method (FIG. 2). Subsequently, using the dummy gate 20 as a mask, an n-type impurity is introduced into the SOI layers 12 on both sides of the dummy gate 20 using a known technique such as an ion implantation method, and then heat treatment is performed to remove the n-type impurity. By activation, the source region 12a and the drain region 12b are formed (FIG. 2). At this time, the SOI layer 12 immediately below the dummy gate 20 becomes the channel region 12c. That is, the channel region 12c is sandwiched between the source region 12a and the drain region 12b (FIG. 2).

  Note that a p-type impurity having a conductivity type opposite to that of the source region 12a and the drain region 12b may be introduced into the SOI layer 12 serving as the channel region 12c in advance. In the case of forming a fully depleted transistor, it is not necessary to introduce a conductive impurity into the channel region 12c.

Next, gate sidewalls 22 are formed on the side surfaces of the dummy gate 20 (FIG. 3). The gate sidewall 22 is formed, for example, by a CVD (Chemical Vapor Deposition) method using a high dielectric insulating film such as a silicon nitride film or HfO ₂ , and this high dielectric insulating film is etched by anisotropic etching such as RIE. It is formed by doing. Thereafter, an interlayer insulating film 30 made of, for example, a silicon oxide film is formed using, for example, a CVD method so as to cover the source region 12a, the drain region 12b, the dummy gate 20, and the gate sidewall 22 (FIG. 3). Subsequently, the interlayer insulating film 30 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method. Next, an interlayer insulating film 32 made of, for example, a silicon nitride film is formed on the interlayer insulating film 30 (FIG. 3).

  Next, as shown in FIG. 4, openings 40 a and 40 b that penetrate the interlayer insulating films 32 and 30 and reach the source region 12 a and the drain region 12 b are formed by using, for example, a lithography technique and an RIE method. Thereafter, only the interlayer insulating film 30 in the openings 40a and 40b is eroded by isotropic etching such as HF vapor. As a result, the interlayer insulating film 32 protrudes like a ridge above the openings 40a and 40b.

  By depositing the half metal ferromagnetic metal 50 in such a structure by using, for example, a directional sputtering method, the source electrode 50a and the drain electrode 50b made of a half metal ferromagnetic metal are respectively formed on the source region 12a and the drain region 12b. Form. Since the interlayer insulating film 32 protrudes like a ridge in the openings 40a and 40b, the half-metal ferromagnetic metal is not deposited on the side surfaces of the openings 40a and 40b.

As the half metal ferromagnetic metal forming the source electrode 50a and the drain electrode 50b, for example, Co ₄₀ Fe ₄₀ B ₂₀ , Co ₂ MnX (where X is Ga, Si, Al, Ge, Sn, Sb, etc.) Or Co ₂ (Cr _x Fe _1-x ) Al (0 ≦ x ≦ 1) or Co ₂ FeAl _x Si _1-x (0 ≦ x ≦ 1) Heusler alloy, CaBi For example, SiC, KCrSe ₂ , CrO ₂ , CrAs, CrSb, Fe ₃ O ₄ , Fe _x Co _1-x S ₂ (0 ≦ x ≦ 1) or the like into which Cr or Mn is introduced by several atomic percent or more can be used. .

Then, an opening 40a reaching the source region 12a and drain region 12b, and 40b, (represented Spin on Glass, i.e., a silicon compound _{R n Si (OH) 4-} n, R is an organic molecule and additive) for example, SOG The insulating film 34 is filled by applying and forming a material that includes a silicon oxide film material and exhibits fluidity. Subsequently, the surface half-metal ferromagnetic metal 50 and the interlayer insulating film 32 are etched away by, for example, the RIE method. Thereafter, the upper surface of the insulating film 34 is planarized using a CMP method to expose the upper surface of the dummy gate 20 made of carbon (FIG. 5).

  Next, the dummy gate 20 made of carbon is selectively removed by exposure to oxygen plasma, for example. Then, a groove 54 for forming a gate electrode is formed in the region where the dummy gate 20 is removed, and the channel region 12c is exposed on the bottom surface of the groove 54 (FIG. 6).

  Next, a half metal ferromagnetic metal is filled in the groove 54 by using a technique such as sputtering, RIE, or CMP (damascene gate forming method) to form a gate electrode 60 made of half metal ferromagnetic metal (FIG. 7). The gate electrode 60 made of the half metal ferromagnetic metal is preferably formed directly on the channel region 12c without forming an insulating film on the channel region 12c.

In addition, as a half metal ferromagnetic metal used as the material of the gate electrode 60, for example, Co ₄₀ Fe ₄₀ B ₂₀ , Co ₂ MnX (where X represents an element such as Ga, Si, Al, Ge, Sn, or Sb). ), Co ₂ (Cr _x Fe _1-x ) Al (0 ≦ x ≦ 1) system, or Co ₂ FeAl _x Si _1-x (0 ≦ x ≦ 1) system Heusler alloy, CaBi, Cr or Mn SiC, KCrSe ₂ , CrO ₂ , CrAs, CrSb, Fe ₃ O ₄ , Fe _x Co _1-x S ₂ (0 ≦ x ≦ 1) or the like into which several atomic percent or more is introduced can be used. It is not necessarily the same as the half metal ferromagnetic metal forming the source electrode 50a and the drain electrode 50b.

  Next, as shown in FIG. 8, the source electrode 50a and the drain electrode 50b are provided with magnetizations 64a and 64b that are substantially parallel to each other (magnetization in substantially the same direction), and the source electrode 50a and the drain are applied to the gate electrode 60. Magnetization 64a and 64b of the electrode 50b and magnetization 64c whose directions are substantially antiparallel to each other (substantially opposite magnetization) 64c are applied.

  When magnetizing each electrode, it is desirable to apply a magnetic field in the direction in which it is desired to magnetize while setting the temperature of the substrate to an appropriate temperature for each process. The directions of the magnetizations 64a and 64b of the source electrode 50a and the drain electrode 50b are substantially parallel to the film surface, and the direction of the magnetization 64c of the gate electrode 60 is substantially parallel to the film surface. Here, the “film surface” means the upper surface. That is, the film surface of the source electrode 50a means the upper surface of the source electrode 50a.

  Thereafter, an interlayer insulating film (not shown) is further formed, and contact holes (not shown) reaching the source electrode 50a, the drain electrode 50b, and the gate electrode 60 are formed in the interlayer insulating film and the insulating film 34, respectively. The contact hole is filled with a metal such as Al to form a contact. Then, a metal wiring connected to the contact is processed and formed on the interlayer insulating film. If necessary, a multilayer wiring is constructed and a semiconductor device is completed through a mounting process and the like.

  The semiconductor device according to the present embodiment formed as described above includes an n-type field effect transistor formed on the semiconductor layer. In this embodiment, the semiconductor layer is the SOI layer of the SOI substrate. However, the semiconductor layer may be a partial region of the semiconductor substrate or a well region formed in the semiconductor substrate.

  Source and drain regions 12a and 12b, which are n-type impurity regions formed apart from the semiconductor layer, are provided. A region of the semiconductor layer between the source region 12a and the drain region 12b becomes a channel region 12c. On the source region 12a and the drain region 12b, a source electrode 50a and a drain electrode 50b of a half metal ferromagnetic metal are provided, respectively.

  A gate electrode 60 made of a half metal ferromagnetic metal is provided on the channel region 12c. The direction of the magnetization 64a of the source electrode 50a and the direction of the magnetization 64b of the drain electrode 50b are substantially parallel. The direction of the magnetization 64c of the gate electrode 60 is substantially antiparallel to the direction of the magnetizations 64a and 64b of the source and drain electrodes 50a and 50b.

  Next, the operation principle of the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 9 is a cross-sectional view for explaining the operation of the semiconductor device of the present embodiment. FIG. 10 is a cross-sectional view taken along the cutting line AA shown in FIG. FIG. 6 is an energy band diagram of electrons when a positive voltage is applied.

  Free electrons near the Fermi level in the half-metal ferromagnetic metal source electrode 50a are 100% spin-polarized so as to be aligned with the direction of the magnetization 64a of the source electrode 50a. Similarly, the free electrons near the Fermi level in the half-metal ferromagnetic metal drain electrode 50b are 100% spin-polarized so as to be aligned with the direction of the magnetization 64b of the drain electrode 50b. Free electrons near the Fermi level in the gate electrode 60 are 100% spin-polarized so as to be aligned with the direction of the magnetization 64 c of the gate electrode 60.

  In order to simply express the above situation, as shown in FIG. 9, spin-polarized free electrons 70a in the source electrode 50a are formally indicated by a circle with a right-pointing arrow. Of course, the spin-polarized free electrons 70b in the drain electrode 50b are also indicated by a circle with a right-pointing arrow. On the other hand, the free electrons 70c in the gate electrode 60 spin-polarized in the antiparallel direction are indicated by a circle with a left-pointing arrow.

  Now, a transistor is turned on by applying a predetermined voltage to the gate electrode 60, and electrons are applied from the source electrode 50a to the drain electrode 50b by applying a predetermined voltage to the source electrode 50a and the drain electrode 50b, respectively. Consider the case of flowing. At this time, the electrons 72a supplied from the half metal source electrode 50a and injected into the source region 12a are naturally spin-polarized in the same direction as the free electrons 70a in the source electrode 50a. The electrons 72c that continuously flow out to the channel region 12c naturally maintain the same spin polarization as the free electrons 70a in the source electrode 50a.

  However, only free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region 12c can exist in the gate electrode 60 of the half metal ferromagnetic metal. This is because there is no electronic state suitable for the spin-polarized electron 72c injected into the channel region 12c near the Fermi level in the gate electrode 60. Of course, the spin-polarized electrons 72 c in the channel region 12 c cannot flow into the gate electrode 60. Therefore, the gate electrode 60 functions as an insulating film for the spin-polarized electrons 72c in the channel region 12c.

  On the other hand, in the gate electrode 60, there are free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region 12c. Can be considered. The electric field is not penetrated into the gate electrode 60 by being shielded by the freely movable charge. That is, the gate electrode 60 functions as an insulating film having an infinite dielectric constant for the spin-polarized electrons 72c in the channel region 12c, and is a metal gate that is not depleted electrostatically. It works as well. As described above, the gate electrode 60 made of a half-metal ferromagnetic metal acts as a gate insulating film having an infinite dielectric constant as it is at the same time as the metal gate electrode.

  In this embodiment, since the dielectric constant of the gate electrode 60 is effectively infinite, the dominance of the gate voltage is directly transmitted to the channel region 12c, and the film thickness of the gate electrode 60 of this half metal ferromagnetic metal is arbitrary. Can be thick. If the thickness of the gate electrode 60 made of a half metal ferromagnetic metal is increased, the spin-polarized electrons 72c injected into the channel region 12c cannot penetrate the gate electrode 60 by the quantum mechanical tunnel mechanism. Therefore, the gate electrode 60 can maintain a sufficient insulation at the same time while effectively having an infinite dielectric constant.

  Since the gate electrode 60 acts as a gate insulating film having an effectively infinite dielectric constant, if the gate electrode 60 is formed in direct contact with the channel region 12c without any other insulating film, the gate voltage The electrostatic dominance over the channel region can be maximized. Further, since the gate electrode 60 behaves electrostatically as a metal, no depletion layer is formed here. Therefore, the maximization of the electrostatic dominant force on the channel region of the gate voltage is maintained.

  By the way, the spin-polarized electrons 72c in the channel region 12c reach the drain electrode without flowing into the gate electrode, but in the drain electrode 50b, the spin-polarized direction of the electrons 72c injected into the channel region 12c There are only free electrons 70b spin-polarized in the parallel direction. Of course, the spin-polarized electrons 72c in the channel region 12c can freely flow into the drain electrode 50b. Therefore, the drain electrode 50b functions as a normal electrode for the spin-polarized electrons 72c in the channel region 12c.

  Since the channel region 12c is formed on the buried insulating film 11, the current flowing through the channel region 12c is limited to that caused by the spin-polarized electrons 72a flowing out from the source electrode 50a.

  The channel region 12c is formed on the buried insulating film 11, and the spin-polarized electrons 70c in the gate electrode 60 cannot flow into either the source electrode 50a or the drain electrode 50b. No leakage current from 60 to the source electrode 50a or the drain electrode 50b occurs.

  Next, the operation principle of the semiconductor device of this embodiment will be described in more detail with reference to FIG. The gate electrode 60 is in direct contact with the channel region 12c, and the Fermi level of the half-metal ferromagnetic metal gate electrode 60 is fixed (pinned) near the center of the band gap of the channel region 12c, as normally observed. It will be. For the spin-polarized conduction electrons 72c flowing in the channel region 12c, there is no electronic state capable of transition in the gate electrode 60 of the half metal ferromagnetic metal, and the gate electrode 60 of the half metal ferromagnetic metal has an insulating film (rectangular shape in the figure). Behaves as a barrier layer). However, the half-metal ferromagnetic metal gate electrode 60 has free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region 12c. No electric field penetrates into 60. Therefore, no voltage drop is observed in the rectangular barrier layer, and the upper end of the barrier layer is horizontal.

  Further, since the gate electrode 60 of half metal ferromagnetic metal has an infinite dielectric constant and no voltage drop is observed, the film thickness can be arbitrarily increased. For spin-polarized electrons 72c flowing in the channel region 12c, a horizontal barrier is formed thick, so that the quantum mechanical conduction mechanism of both FN (Fowler-Nordheim) tunnel injection and direct tunnel is blocked. Therefore, the insulating property of the gate electrode 60 of half metal ferromagnetic metal is ensured.

  On the other hand, the spin-polarized free electrons 70c in the gate electrode 60 are not injected into the channel region 12c because they are hindered by a Schottky barrier formed between the semiconductor and the channel region 12c.

  In this way, the gate insulating film function having an extremely high dielectric constant and the function of a metallic gate electrode without forming a depletion layer are realized at the same time while ensuring good insulation. A semiconductor device having a field effect transistor in which the electrostatic dominance of the voltage on the channel region is made as large as possible is realized.

  The semiconductor device of this embodiment has an n-type field effect transistor. However, if the n-type source region and drain region are replaced with a p-type source region and drain region, the semiconductor device has a p-type field effect transistor. It becomes. The above description of the operation of this embodiment also applies to a semiconductor device having a p-type field effect transistor in which the charge carriers injected into the channel are holes.

  In the present embodiment, the half metal ferromagnetic metal electrodes are formed on the source region and the drain region, respectively. However, only the electrode on the side into which charges are injected, that is, only the source electrode is used as the half metal ferromagnetic metal electrode. You may form with a metal.

(First modification)
Next, a semiconductor device according to a first modification of the first embodiment will be described with reference to FIG. The semiconductor device of this modification is the same as that of the semiconductor device of the first embodiment shown in FIG. In order to firmly and firmly fix the magnetization, the antiferromagnetic layers 90a, 90b, and 90c are provided. For example, FeMn, PtMn, NiMn, IrMn, NiO, Fe ₂ O ₃ or the like is used as the material of the antiferromagnetic layers 90a, 90b, and 90c.

  In this modification, in order to firmly and stably fix the magnetizations of the source electrode 50a, the drain electrode 50b, and the gate electrode 60, the temperature is raised to the Neel temperature of the antiferromagnetic layers 90a, 90b, and 90c. It is effective to cool in a magnetic field. For this reason, the antiferromagnetic layers 90a and 90b and the antiferromagnetic layer 90c are preferably made of materials having different Neel temperatures. By adding an antiferromagnetic layer having a different Neel temperature to each electrode, magnetization can be applied at an appropriate temperature, and individual magnetization can be applied to each electrode.

  Similarly to the first embodiment, the semiconductor device of the first modification also has a function of a gate insulating film having an extremely high dielectric constant while ensuring good insulation, and a metallic property in which a depletion layer is not formed. And the gate electrode voltage function can be increased as much as possible. In this modification, an antiferromagnetic layer is provided on both the source electrode 50a and the drain electrode 50b and the gate electrode 60. However, only one of the source electrode 50a and the drain electrode 50b or the gate electrode 60 has an antiferromagnetic strength. A magnetic layer may be provided.

(Second modification)
Next, a semiconductor device according to a second modification of the first embodiment will be described with reference to FIG. The semiconductor device of this modification is the same as that of the semiconductor device of the first embodiment shown in FIG. 8, except that a nonmagnetic layer 80a made of Ru, for example, and a ferromagnetic layer 82a are stacked on the source electrode 50a of a half-metal ferromagnetic metal. In addition to providing a film, a laminated film of a nonmagnetic metal layer 80b made of, for example, Ru and a ferromagnetic layer 82b is provided on the drain electrode 50b of the half metal ferromagnetic metal. The ferromagnetic layer 82a is ferromagnetically coupled or antiferromagnetically coupled to the half metal ferromagnetic metal source electrode 50a via the nonmagnetic layer 80a, and the ferromagnetic layer 82b is half coupled via the nonmagnetic layer 80b. The metal ferromagnetic metal drain electrode 50b is ferromagnetically or antiferromagnetically coupled.

  As in the semiconductor device of this modification, a ferromagnetic layer that is ferromagnetically or antiferromagnetically coupled to the source and drain electrodes 50a and 50b on the source and drain electrodes 50a and 50b with the nonmagnetic layer interposed therebetween, respectively. By providing, the volume of the laminated structure that is ferromagnetically coupled or antiferromagnetically coupled is increased compared to the single source and drain electrodes 50a and 50b of the half metal ferromagnetic metal. For this reason, it is possible to increase the resistance to thermal disturbance related to the magnetization of the source and drain electrodes 50a and 50b when miniaturized.

  Similarly to the first embodiment, the semiconductor device of the second modification also has a function of a gate insulating film having an extremely high dielectric constant while ensuring good insulating properties, and a metallic property in which a depletion layer is not formed. And the gate electrode voltage function can be increased as much as possible.

  In this modification, for example, a laminated film of a nonmagnetic metal layer 80b made of Ru and a ferromagnetic layer 82b may be laminated a plurality of times.

  Further, in this modified example, as in the first modified example shown in FIG. 11, the antiferromagnetic layers are provided on the ferromagnetic layers 82a and 82b, respectively, and the magnetization of the structure that is ferromagnetically coupled or antiferromagnetically coupled is obtained. You may comprise so that it may adhere firmly and stably.

(Third Modification)
Next, a semiconductor device according to a third modification of the first embodiment will be described with reference to FIG. The semiconductor device of this modification example is the same as the semiconductor device of the first embodiment shown in FIG. 8, except that a tunnel barrier layer 13a is provided between the source region 12a and the source electrode 50a, and between the drain region 12b and the drain electrode 50b. Is provided with a tunnel barrier layer 13b.

  The tunnel barrier layers 13a and 13b are provided in order to prevent the ferromagnetic metal from diffusing into the semiconductor layer, that is, the source region 12a and the drain region 12b, and to maintain the spin polarization of injected electrons. As the tunnel barrier layers 13a and 13b, for example, a natural oxide film or MgO can be used. Note that, as the half metal ferromagnetic metal material of the source electrode 50a and the drain electrode 50b, when SiC in which Mn is introduced, for example, several atomic% or more is used, the source region 12a and the drain region 12b can be provided without providing a tunnel barrier layer. It is not necessary to prevent the diffusion of the ferromagnetic metal, and the spin polarization rate of the injected electrons can be maintained.

  Similarly to the first embodiment, the semiconductor device of the third modified example also has a function of a gate insulating film having an extremely high dielectric constant while ensuring good insulation, and a metallic property in which a depletion layer is not formed. And the gate electrode voltage function can be increased as much as possible.

  In the semiconductor device according to the first embodiment and the first to second modifications thereof, the tunnel barrier layer 13a is provided between the source region 12a and the source electrode 50a and the drain region 12b is provided as in the third modification. A tunnel barrier layer 13b may be provided between the drain electrode 50b and the drain electrode 50b.

  In the semiconductor device according to the first embodiment and the first to third modifications thereof, the gate electrode 60 is preferably formed directly on the channel region 12c, but between the semiconductor layer that becomes the channel region 12c. An extremely thin barrier film such as MgO may be further provided for the purpose of preventing the diffusion of the ferromagnetic metal and improving the interface characteristics with the semiconductor layer. Of course, this barrier film only needs to have a function of restricting the movement of a substance such as a metal and a function of electrically inactivating crystal defects (dangling bonds, etc.) at the interface with the semiconductor layer (passivation). Needless to say, it is not always necessary to provide electrical insulation. The fact that such an ultra-thin barrier film does not have electrical insulation means that no voltage drop occurs in the barrier film, so that the dominance of the gate voltage on the channel region is reduced. There is nothing.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In the semiconductor device according to the first embodiment and the first to third modifications, the source electrode 50a and the drain electrode 50b are stacked on the source region 12a and the drain region 12b, respectively. However, in the semiconductor device of the second embodiment, as shown in FIG. 14, the source region 12a and the drain region 12b exist only directly below the gate sidewall 22, and the channel region 12c of the source region 12a and the drain region 12b. A source electrode 50a and a drain electrode 50b made of a half metal ferromagnetic metal are provided so as to be in contact with the side surface opposite to the side surface in contact with each other. That is, the source electrode 50 a and the drain electrode 50 b are formed on the buried oxide film 11. This configuration is facilitated by removing the impurity regions by etching when forming the gate sidewalls 22 on the left and right sides of the dummy gate 20 described in the manufacturing process of the first embodiment, and then performing the same process as in the first embodiment. Can be formed.

  Similar to the first embodiment, the semiconductor device of the second embodiment also has a function of a gate insulating film having an extremely high dielectric constant while ensuring good insulating properties, and a metallic property in which a depletion layer is not formed. And the gate electrode voltage function can be increased as much as possible.

  The semiconductor device of the first embodiment and its various modifications and the second embodiment includes an n-type field effect transistor. However, a p-type field effect transistor is provided instead of the n-type field effect transistor. You may comprise. It goes without saying that a plurality of sets of field effect transistors may be provided.

(Third embodiment)
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 15 is a cross-sectional view of the semiconductor device of this embodiment. The semiconductor device of this embodiment includes an n-type field effect transistor 1 and a p-type field effect transistor 1A, and constitutes a complementary field effect transistor circuit.

  The n-type field effect transistor 1 is the n-type field effect transistor described in the first embodiment. That is, a buried insulating film 11 is formed on the silicon semiconductor substrate 10, and a semiconductor channel region 12 c is formed on the buried insulating film 11. An n-type semiconductor source region 12a and drain region 12b are formed on the buried insulating film 11 so as to sandwich the channel region 12c. That is, the channel region 12c is formed between the source region 12a and the drain region 12b.

  A half metal ferromagnetic metal source electrode 50a is provided on the source region 12a, and a half metal ferromagnetic metal drain electrode 50b is provided on the drain region 12b. The direction of the magnetization 64a of the source electrode 50a and the direction of the magnetization 64b of the drain electrode 50b are substantially parallel and substantially parallel to the film surface.

  A gate electrode 60 made of a half metal ferromagnetic metal is provided on the channel region 12c. The direction of the magnetization 64c of the gate electrode 60 is substantially antiparallel to the directions of the magnetizations 64a and 64b of the source and drain electrodes 50a and 50b, and is substantially parallel to the film surface. A gate side wall 22 made of an insulator is provided on the side surface of the gate electrode 60.

  On the other hand, the p-type field effect transistor 1A has a semiconductor channel region 12Ac formed on the buried insulating film 11. A p-type semiconductor source region 12Aa and drain region 12Ab are formed on the buried insulating film 11 so as to sandwich the channel region 12Ac. That is, the channel region 12Ac is formed between the source region 12Aa and the drain region 12Ab.

  A half metal ferromagnetic metal source electrode 50Aa is provided on the source region 12Aa, and a half metal ferromagnetic metal drain electrode 50Ab is provided on the drain region 12Ab. The direction of the magnetization 64Aa of the source electrode 50Aa and the direction of the magnetization 64Ab of the drain electrode 50Ab are substantially parallel and substantially parallel to the film surface.

  A gate electrode 60A made of a half metal ferromagnetic metal is provided on the channel region 12Ac. The direction of the magnetization 64Ac of the gate electrode 60A is substantially antiparallel to the direction of the magnetizations 64Aa and 64Ab of the source and drain electrodes 50Aa and 50Ab, and is substantially parallel to the film surface.

  A gate side wall 22A made of an insulator is provided on the side surface of the gate electrode 60A. In this embodiment, the n-type field effect transistor 1 and the p-type field effect transistor 1A are covered with an interlayer insulating film 35.

  Further, as in the present embodiment, an n-type field effect transistor 1 and a p-type field effect transistor 1A are provided, and these n-type field effect transistor 1 and p-type field effect transistor 1A are shown in FIG. When arranged adjacent to each other, the drain electrode 50b of the n-type field effect transistor 1 and the source electrode 50Aa of the p-type field effect transistor 1A adjacent to the drain electrode 50b have respective magnetizations 64b. , 64Aa is preferably approximately antiparallel. In this way, the effect of the demagnetizing field appearing at the end of each half metal electrode is reduced, and the magnetization of each electrode can be stabilized. Although not shown, each transistor may be connected by a nonmagnetic metal wiring.

  Similarly to the first embodiment, the semiconductor device according to the third embodiment also has a function of a gate insulating film having a very high dielectric constant while ensuring good insulation, and a metallic property in which a depletion layer is not formed. And the gate electrode voltage function can be increased as much as possible.

  In the first to third embodiments and the modifications thereof, the magnetization directions of the source electrode 50a, the drain electrode 50b, and the gate electrode 60 are substantially parallel to the film surface, but are substantially perpendicular. There may be. Also in this case, it goes without saying that the magnetization direction of the source electrode 50a and the drain electrode 50b and the magnetization direction of the gate electrode 60 are substantially antiparallel.

  In the first to third embodiments and modifications thereof, the semiconductor substrate on which the field effect transistor is formed is an SOI substrate, but may be a bulk Si substrate. In place of the Si substrate, a Ge substrate, a SiGe substrate having a mixed crystal layer of Si and Ge, a semiconductor substrate such as GaAs, or a composite substrate in which these compound semiconductor and Si are formed on the same substrate, etc. It is possible to use.

(Fourth embodiment)
Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. The semiconductor device of this embodiment includes an n-type field effect transistor having a Fin structure formed on an SOI substrate. 16 to 18 are bird's-eye views for explaining the manufacturing process of the semiconductor device according to the present embodiment.

  The semiconductor device of this embodiment is manufactured as follows. In the first embodiment, the SOI layer 12 serving as an element formation region extending on the upper surface of the buried insulating film 11 is formed. However, in this embodiment, the SOI layer 12 is processed into a thin wall (Fin) shape using a known technique. The Fin-shaped SOI layer is formed with a pair of side surfaces that are substantially parallel to each other in the thickness direction. In the present embodiment, the pair of side surfaces intersects the upper surface of the substrate substantially perpendicularly. Further, a dummy gate 20 made of carbon, for example, is formed so as to cover a pair of both side surfaces (FIG. 16). Subsequently, by introducing an n-type impurity into the SOI layer 12 on both sides of the dummy gate 20 and performing heat treatment, the source region 12a and the drain region 12b are parallel to the pair of both side surfaces and parallel to the upper surface of the substrate. They are formed so as to face each other in the direction (that is, in the horizontal direction) (FIG. 16). A region of the SOI layer 12 sandwiched between the source region 12a and the drain region 12b and covered with the dummy gate 20 becomes a channel region.

  Next, the half metal ferromagnetic metal source electrode 50a and drain electrode 50b are opposed to each other across the channel region and are in contact with only a pair of end faces of the SOI layer, which are in contact with only the source region 12a and the drain region 12b, respectively. (FIG. 17). The source electrode 50a and the drain electrode 50b can be performed using a known lithography technique and deposition technique.

  Next, the dummy gate 20 made of carbon is selectively removed using a known technique. Thereafter, a half-metal ferromagnetic metal gate electrode 60 is formed at a location where the dummy gate 20 is removed using a known technique (FIG. 18). Therefore, the gate electrode 60 is formed in contact with a pair of opposite side surfaces of the opposing SOI layers in contact with the channel region so as to cover the channel region.

  Thereafter, magnetizations that are antiparallel to each other are applied to the source electrode 50a, the drain electrode 50b, and the gate electrode 60. For example, when the magnetization directions of the source electrode 50 a and the drain electrode 50 b are substantially perpendicular to the upper surface of the buried insulating film 11 and toward the upper surface, the magnetization direction of the gate electrode 60 is the upper surface of the buried insulating film 11. It is assumed to be substantially perpendicular to the above and facing away from the upper surface.

  The operation of the transistor according to this embodiment formed as described above will be described below with reference to FIGS. 19 is a cross-sectional view taken along a plane 300 shown in FIG. 18, and FIG. 20 is a cross-sectional view taken along the cutting line BB shown in FIG. 19 when the transistor of this embodiment is ON (a positive voltage is applied to the gate electrode). It is an energy band figure of an electron (when applied).

  Now, a transistor is turned on by applying a predetermined voltage to the gate electrode 60, and electrons are allowed to flow from the source electrode 50a to the drain electrode 50b by applying predetermined voltages to the source electrode 50a and the drain electrode 50b, respectively. Think about the case. At this time, the electrons supplied from the half metal source electrode 50a and injected into the source region 12a are naturally spin-polarized in the same direction as the free electrons 70a in the source electrode 50a. The electrons 72c that continuously flow out to the channel region 12c naturally maintain the same spin polarization as the free electrons 70a in the source electrode 50a.

  However, in the half-metal ferromagnetic metal gate electrode 60, only free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region 12c can exist. This is because there is no electronic state suitable for the spin-polarized electron 72c injected into the channel region 12c near the Fermi level in the gate electrode 60. Of course, the spin-polarized electrons 72 c in the channel region 12 c cannot flow into the gate electrode 60. Therefore, the gate electrode 60 functions as an insulating film for the spin-polarized electrons 72c in the channel region 12c.

  On the other hand, in the gate electrode 60, there are free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region 12c. Can be considered. The electric field is not penetrated into the gate electrode 60 by being shielded by the freely movable charge. That is, the gate electrode 60 functions as an insulating film having an infinite dielectric constant for the spin-polarized electrons 72c in the channel region 12c, and is a metal gate that is not depleted electrostatically. Also works. As described above, the gate electrode 60 made of a half-metal ferromagnetic metal acts as a gate insulating film having an infinite dielectric constant as it is at the same time as the metal gate electrode.

  In this embodiment, since the dielectric constant of the gate electrode 60 is effectively infinite, the dominance of the gate voltage is directly transmitted to the channel region 12c, and the film thickness of the gate electrode 60 of this half metal ferromagnetic metal is arbitrary. Can be thick. If the thickness of the gate electrode 60 made of a half metal ferromagnetic metal is increased, the spin-polarized electrons 72c injected into the channel region 12c cannot penetrate the gate electrode 60 by the quantum mechanical tunnel mechanism. Therefore, the gate electrode 60 can maintain a sufficient insulation at the same time while effectively having an infinite dielectric constant.

  Since the gate electrode 60 acts as a gate insulating film having an effectively infinite dielectric constant, if the gate electrode 60 is formed in direct contact with the channel region 12c without any other insulating film, the gate voltage The electrostatic dominance over the channel region can be maximized. Further, since the gate electrode 60 behaves electrostatically as a metal, no depletion layer is formed here. Therefore, the maximization of the electrostatic dominant force on the channel region of the gate voltage is maintained.

  On the other hand, the spin-polarized electrons 72c in the channel region 12c reach the drain electrode without flowing into the gate electrode, but in the drain electrode 50b, the spin-polarized direction of the electrons 72c injected into the channel region 12c Since only the free electrons 70b spin-polarized in the parallel direction exist, the spin-polarized electrons 72c in the channel region 12c can freely flow into the drain electrode 50b. Therefore, the drain electrode 50b functions as a normal electrode for the spin-polarized electrons 72c in the channel region 12c.

  Since the channel region 12c is formed on the buried insulating film 11, the current flowing through the channel region 12c is limited to that caused by the spin-polarized electrons 72a flowing out from the source electrode 50a.

  The channel region 12c is formed on the buried insulating film 11, and the polarized electrons 70c in the gate electrode 60 cannot flow into either the source electrode 50a or the drain electrode 50b. Thus, no leakage current to the source electrode 50a or the drain electrode 50b occurs.

  Next, the operation principle of the transistor according to this embodiment will be described in more detail with reference to FIG. The gate electrode 60 is in direct contact with both side surfaces of the channel region, and the Fermi level of the half metal ferromagnetic metal gate electrode 60 is fixed (pinned) near the center of the band gap of the channel region, as normally observed. Will be. Since both sides of the channel region are pinned, the relative positions of the energy level of the conduction band edge Ec and the valence band edge Ev of the channel region and the Fermi level of the gate electrode 60 are completely fixed. Therefore, the energy levels of the conduction band edge Ec and the valence band edge Ev in the channel region change completely following the change of the gate voltage. That is, the electrostatic dominance of the gate voltage on the channel region is maximized. Of course, for the spin-polarized electrons 72c flowing in the channel region, there is no electronic state capable of transition in the gate electrode 60, and the gate electrode 60 is an insulating film (corresponding to the rectangular barrier layer sandwiching the channel region in the figure). Behave as. However, free electrons 70c spin-polarized in a direction antiparallel to the electrons 72c injected into the channel region exist in the gate electrode 60, and an electric field does not enter the gate electrode 60. Therefore, no voltage drop is seen in the rectangular barrier and the upper end of the barrier is horizontal. Further, since the gate electrode 60 has an infinite dielectric constant and no voltage drop is observed, the film thickness can be arbitrarily increased. Since the spin-polarized electrons 72c flowing in the channel region have a thick horizontal barrier, the quantum mechanical conduction mechanism of both FN tunnel injection and direct tunnel is blocked. Therefore, the insulating property of the gate electrode 60 is ensured.

  In addition, since energy barriers are formed on both side surfaces of the channel region, the thickness of the thin-walled (Fin-shaped) channel region sandwiched between the energy barriers is determined by the wave function of electrons conducted through the channel region. If the thickness is reduced below the extent of the channel thickness direction (direction perpendicular to both side surfaces of the channel), the energy degeneration of the electronic state of the conduction band in the silicon layer can be released. As a result, only electrons having a small effective mass, that is, high-speed electrons are induced in the channel region, the mobility of the channel region is increased, and the device speed is increased (S. Takagi, et. Al. Jpn). J. Appl. Phys., Vol. 37, p.1289 (1998)).

  In addition, since the absolute value of the wave function of electrons conducted through the channel region becomes large at the center of the silicon layer (channel region) that is far from the interface with the gate electrode 60, the influence of interface scattering with the gate electrode 60 is reduced. The mobility of the channel region is further improved.

  On the other hand, the spin-polarized free electrons 70c in the gate electrode 60 are not injected into the channel region by being inhibited by a Schottky barrier formed with the semiconductor (channel region).

  In this way, the gate insulating film function having an extremely high dielectric constant and the metallic gate electrode function in which a depletion layer is not formed are simultaneously realized while ensuring good insulation, and the gate voltage is reduced. A semiconductor device having a field effect transistor with a large electrostatic control over the channel region is realized.

  In the present embodiment, as shown in the first modification of the first embodiment, the source electrode 50a, the drain electrode 50b, and the gate electrode 60 are respectively formed on the source electrode 50a, the drain electrode 50b, and the gate electrode 60. In order to fix the magnetization, an antiferromagnetic layer may be provided.

  In this embodiment, as shown in the second modification of the first embodiment, a laminated film of a nonmagnetic layer made of, for example, Ru and a ferromagnetic layer is provided on the source electrode 50a and the drain electrode 50b, respectively. The ferromagnetic layer and the electrode of the half metal ferromagnetic layer may be configured to be ferromagnetically coupled or antiferromagnetically coupled via the nonmagnetic layer.

  The gate electrode 60 is preferably in direct contact with the channel region. However, the gate electrode 60 is intended to prevent diffusion of ferromagnetic metal between the semiconductor layer serving as the channel region and the interface characteristics between the semiconductor layer and the semiconductor layer. For the purpose, an extremely thin barrier film such as MgO may be further provided. Of course, this barrier film only needs to have a function of restricting the movement of a substance such as a metal and a function of electrically inactivating crystal defects (dangling bonds, etc.) at the interface with the semiconductor layer (passivation). Needless to say, it is not always necessary to provide electrical insulation. The fact that such an ultra-thin barrier film does not have electrical insulation means that no voltage drop occurs in the barrier film, so that the dominance of the gate voltage on the channel region is reduced. There is nothing.

  Although the semiconductor device of this embodiment includes a Fin-type n-type field effect transistor, it may be configured to include a Fin-type p-type field-effect transistor instead of the n-type field-effect transistor. Good. Further, a Fin-type n-type field effect transistor and a Fin-type p-type field effect transistor may be formed on the same substrate. It goes without saying that a plurality of Fin-type field effect transistors may be provided.

  In the fourth embodiment, the semiconductor substrate on which the Fin-type field effect transistor is formed is an SOI substrate, but may be a bulk Si substrate. Also, instead of the Si substrate, a Ge substrate, a SiGe substrate having a mixed crystal layer of Si and Ge, a semiconductor substrate such as GaAs, or a composite substrate in which these compound semiconductor and Si are formed on the same substrate are used. Is possible.

As described above in detail, according to an embodiment of the present invention, the gate electrode is formed of a half-metal ferromagnetic material magnetized in the first direction, and the source and drain electrodes are antiparallel to the first direction. It has a configuration formed of a half-metal ferromagnet magnetized in any direction. This
(1) Spin-polarized electrons injected from the source electrode into the channel region cannot flow into the gate electrode. Therefore, from the viewpoint of spin-polarized electrons existing in the channel region, the half metal gate electrode functions as an insulating film.
(2) Electrons that are spin-polarized in anti-parallel to the spin-polarized electrons existing in the channel region exist as free electrons in the gate electrode, so that a metal, that is, a dielectric constant is effective electrostatically. It functions as an infinite substance.
(3) Since spin-polarized electrons injected into the channel region can flow into the drain electrode magnetized in a direction aligned with the spin-polarized direction of the electrons, a channel current is generated. On the other hand, spin-polarized electrons in the gate electrode cannot flow into either the source electrode or the drain electrode through the channel region. Therefore, no leak current is generated from the gate electrode to the source electrode or the drain electrode.
(4) Since the gate electrode acts as a gate insulating film having an effectively infinite dielectric constant, if the gate electrode is formed in direct contact with the channel region without any other insulating film, the gate voltage channel The electrostatic dominance over the region can be increased as much as possible.
(5) Since the dielectric constant of the gate electrode is effectively infinite, the dominance of the gate voltage is directly transmitted to the channel region, and the thickness of the gate electrode (gate insulating film) can be arbitrarily increased. If the thickness of the gate electrode is increased, spin-polarized electrons injected into the channel region cannot penetrate the gate electrode (gate insulating film) by the quantum mechanical tunnel mechanism. Therefore, sufficient insulation can be maintained.
(6) Since the gate electrode behaves as a metal electrostatically, no depletion layer is formed here.
(7) If the gate electrode is formed on both side surfaces of the channel region, the relative positions of the energy level of the conduction band edge Ec and the valence band edge Ev of the channel region and the Fermi level of the gate electrode are completely fixed by pinning. Is done. Therefore, the energy levels of the conduction band edge Ec and the valence band edge Ev of the channel region change completely following the change of the gate voltage. That is, the electrostatic dominance of the gate voltage on the channel region is maximized.
(8) When the gate electrode is formed on both side surfaces of the channel region, the thickness of the channel region is the extent of the channel thickness direction (direction perpendicular to the channel side surfaces) of the wave function of electrons conducted through the channel region. If the thickness is reduced below, the energy degeneracy of the electronic state of the conduction band in the silicon layer (channel region) is released. As a result, only a small effective mass, that is, high-speed electrons are induced in the channel region, the mobility of the channel region is increased, and the speed of the device is increased. In addition, since the absolute value of the wave function of electrons conducted through the channel region increases at the center of the channel region far from the interface with the gate electrode, it is less susceptible to the effect of interface scattering with the gate electrode. The mobility is further improved.

  In this way, the gate insulating film function having an extremely high dielectric constant and the metallic gate electrode function in which a depletion layer is not formed are simultaneously realized while ensuring good insulating properties. A semiconductor device including a field effect transistor having an electrostatic dominance as large as possible in the channel region is realized.

Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. Sectional drawing for demonstrating operation | movement of the semiconductor device of 1st Embodiment. The energy band figure in case the transistor of 1st Embodiment in the cross section cut | disconnected by cutting line AA shown in FIG. 9 is ON. Sectional drawing of the semiconductor device by the 1st modification of 1st Embodiment. Sectional drawing of the semiconductor device by the 2nd modification of 1st Embodiment. Sectional drawing of the semiconductor device by the 3rd modification of 1st Embodiment. Sectional drawing of the semiconductor device by 2nd Embodiment. Sectional drawing of the semiconductor device by 3rd Embodiment. The perspective view which shows the manufacturing process of the semiconductor device by 4th Embodiment. The perspective view which shows the manufacturing process of the semiconductor device by 4th Embodiment. The perspective view which shows the manufacturing process of the semiconductor device by 4th Embodiment. Sectional drawing for demonstrating operation | movement of the semiconductor device of 4th Embodiment. The energy band figure in case the transistor of 4th Embodiment in the cross section cut | disconnected by the cutting line BB shown in FIG. 19 is ON.

Explanation of symbols

10 silicon semiconductor substrate 11 silicon oxide film (buried oxide film (BOX)
12 Silicon semiconductor layer 12a Source region 12b Drain region 12c Channel region 13a Tunnel barrier layer 13b Tunnel barrier layer 20 Dummy gate 22 Gate sidewall 30 Interlayer insulation film 32 Interlayer insulation films 40a and 40b Openings reaching source and drain regions 50 Half metal ferromagnetism Body metal 50a Source electrode 50b Drain electrode 54 Groove 60 Gate electrode 64a Source electrode magnetization 64b Drain electrode magnetization 64c Gate electrode magnetization 70a Free electrons 70b in source electrode Free electrons 72a in drain electrode Injected into source region Polarized electrons 72b Polarized electrons injected into the drain region 72c Polarized electrons injected into the channel region

Claims (12)

A first source region and a first drain region of a second conductivity type provided separately from the first semiconductor layer of the first conductivity type;
A first channel region provided in the first semiconductor layer between the first source region and the first drain region;
A first gate electrode of a half-metal ferromagnetic metal provided on the first channel region;
A first source electrode of a half-metal ferromagnetic metal provided to connect to the first source region;
With
The semiconductor device according to claim 1, wherein the magnetization direction of the first gate electrode is substantially antiparallel to the magnetization direction of the first source electrode.   A tunnel barrier layer is provided between the first source electrode and the first source region, and the first source electrode is connected to the first source region through the tunnel barrier layer. The semiconductor device according to claim 1. A first semiconductor layer of a first conductivity type formed on a substrate and having a pair of opposing side surfaces;
Second conductivity type second electrodes formed on the first semiconductor layer and spaced apart from each other in a direction parallel to the pair of side surfaces and parallel to the top surface of the substrate, each including a portion of the pair of side surfaces. One source region and a first drain region;
The first semiconductor layer is formed in the first semiconductor layer between the first source region and the first drain region, and includes a part of the pair of side surfaces not included in the first source region and the first drain region. One channel region;
A first gate electrode of a half-metal ferromagnetic metal provided so as to cover the pair of side surfaces included in the first channel region;
A first source electrode of a half-metal ferromagnetic metal provided to connect to the first source region;
With
The semiconductor device according to claim 1, wherein the magnetization direction of the first gate electrode is substantially antiparallel to the magnetization direction of the first source electrode.   4. The semiconductor device according to claim 1, wherein an antiferromagnetic layer is provided on at least one of the first source electrode and the first gate electrode. 5.   5. The semiconductor device according to claim 1, wherein a laminated film in which a nonmagnetic layer and a ferromagnetic layer are laminated in this order is provided on the first source electrode.   The semiconductor device according to claim 1, wherein a barrier film is provided between the first gate electrode and the channel region. The half-metal ferromagnetic metal of the source electrode and the gate _{electrode, Co 40 Fe 40 B 20,} Co 2 MnX (X is Ga, Si, Al, Ge, Sn, Sb), Co 2 (Cr x Fe 1- _x ) Al alloy (0 ≦ x ≦ 1), Co ₂ FeAl _x Si _1-x alloy (0 ≦ x ≦ 1), SiC containing CaBi, Cr or Mn, KCrSe ₂ , CrO ₂ , CrAs, CrSb, Fe The semiconductor device according to claim 1, wherein the semiconductor device is ₃ O ₄ or a Fe _x Co _1-x S ₂ alloy (0 ≦ x ≦ 1).   8. The semiconductor device according to claim 1, further comprising a first drain electrode made of a half metal ferromagnetic metal so as to be connected to the first drain region.   The semiconductor device according to claim 1, further comprising an insulating film formed on a substrate, wherein the first semiconductor layer is formed on the insulating film.   10. The semiconductor device according to claim 1, wherein the first semiconductor layer is a Si layer, a Ge layer, a mixed crystal layer of Si and Ge, or a GaAs layer. A first conductivity type second source region and a second drain region provided apart from the second conductivity type second semiconductor layer;
A second channel region provided in the second semiconductor layer between the second source region and the second drain region;
A second gate electrode of a half-metal ferromagnetic metal provided on the second channel region;
A second source electrode of half-metal ferromagnetic metal provided to connect to the second source region;
Further comprising
The magnetization direction of the second gate electrode is substantially antiparallel to the magnetization direction of the second source electrode;
2. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed on the same substrate. A second semiconductor layer of a second conductivity type formed on the substrate and having a pair of opposing side surfaces;
Formed in the second semiconductor layer and provided apart from each other in a direction parallel to the pair of side surfaces and parallel to the upper surface of the substrate, and each of which forms part of the pair of side surfaces of the second semiconductor layer A second source region and a second drain region of the first conductivity type including;
The second semiconductor layer is formed in the second semiconductor layer between the second source region and the second drain region, and includes a part of the pair of side surfaces not included in the second source region and the second drain region. A two-channel region;
A second gate electrode of a half-metal ferromagnetic metal provided to cover the pair of side surfaces included in the second channel region;
A second source electrode of half-metal ferromagnetic metal provided to connect to the second source region;
Further comprising
4. The semiconductor device according to claim 3, wherein the magnetization direction of the second gate electrode is substantially antiparallel to the magnetization direction of the second source electrode.

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