JP2010147267A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that suppresses the increase of defect modes due to variance in inter-pad-rewiring resistance even when an operation speed becomes fast, and to provide a method of manufacturing the same. <P>SOLUTION: A barrier-metal layer including a lower-layer titanium layer, an intermediate titanium nitride layer, and an upper-layer titanium layer is interposed between an aluminum-based pad 2p and rewiring 16 of a wafer-level-package type semiconductor integrated circuit device (LSI) and the thickness of the lower-layer titanium layer is made ≥5 to ≤60 nm so as to stabilize resistance between the aluminum-based pad 2p and rewiring 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a device structure of a semiconductor integrated circuit device and a technology effective when applied to a pad peripheral structure forming technology in a method of manufacturing a semiconductor integrated circuit device (or semiconductor device).

  Japanese Patent Application Laid-Open No. 2008-60145 (Patent Document 1) or corresponding US Patent Publication No. 2008-0054479 (Patent Document 2) describes an aluminum-based pad on a semiconductor device chip and an upper layer rewiring. There is disclosed a technique of providing a base metal layer formed by laminating a plurality of conductive materials such as titanium, titanium nitride, and copper by sputtering or the like.

  Japanese Patent Application Laid-Open No. 2000-306938 (Patent Document 3) discloses a titanium film for the purpose of improving adhesion between the aluminum alloy pad on the semiconductor device chip and the rewiring of the upper aluminum alloy. Alternatively, a technique for forming a titanium nitride film or a composite film of a titanium film and a titanium nitride film is disclosed.

JP 2008-60145 A US Patent Publication No. 2008-0054479 JP 2000-306938 A

  The inventors of the present application have found that the resistance variation between the aluminum-based pad and the rewiring ("pad-rewiring resistance variation") in a wafer level package type semiconductor integrated circuit device (LSI) having rewiring is a device. The effect on the operating characteristics of the system was examined. According to this, in the conventional product, it has been said that the resistance variation between the pad rewirings hardly affects the product characteristics in the normal range. However, with the recent increase in operating speed, it has become clear that failure modes due to variations in resistance between pad rewirings are increasing.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in the present invention, in order to stabilize the resistance between the aluminum-based pad and the rewiring in the semiconductor integrated circuit device (LSI) of the wafer level package system, the lower titanium layer and the intermediate titanium nitride are interposed between them. A barrier metal layer including a layer and an upper titanium layer is interposed, and the thickness of the lower titanium layer is 5 nm or more and 60 nm or less.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in order to stabilize the resistance between the aluminum-based pad and the rewiring in the semiconductor integrated circuit device (LSI) of the wafer level package system, the lower titanium layer, the middle titanium nitride layer, the upper titanium layer are interposed between them. By interposing a barrier metal layer including a layer and setting the thickness of this lower titanium layer to 5 nm or more and 60 nm or less, avoiding an increase in resistance or an increase in process cost while maintaining the barrier effect Can do.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) an aluminum-based pad electrode provided on the multilayer wiring layer on the device surface of the semiconductor substrate including the multilayer wiring layer;
(B) an insulating film having an opening on at least a part of the aluminum-based pad electrode;
(C) a redistribution metal pattern provided on the aluminum-based pad electrode and the insulating film so as to cover the opening;
(D) a barrier metal layer provided on the aluminum-based pad electrode under the redistribution metal pattern and on the insulating film;
Here, the barrier metal layer includes:
(D1) a first metal layer containing titanium as a main component;
(D2) a second metal layer mainly composed of titanium nitride provided on the first metal layer;
(D3) a third metal layer mainly composed of titanium provided on the second metal layer,
Here, the thickness of the first metal layer is not less than 5 nm and not more than 60 nm.

  2. In the semiconductor integrated circuit device according to the item 1, the thickness of the first metal layer is 50 nm or less.

  3. In the semiconductor integrated circuit device according to the item 1, the thickness of the first metal layer is 25 nm or less.

4). 4. In the semiconductor integrated circuit device according to any one of items 1 to 3, the redistribution metal pattern includes:
(C1) a first plating layer containing copper as a main component;
(C2) A second plating layer mainly composed of nickel provided on the first plating layer.

  5. 5. In the semiconductor integrated circuit device according to any one of items 1 to 4, a layer containing aluminum oxide as a main component exists on the aluminum-based pad electrode immediately below the first metal layer.

6). 6. The semiconductor integrated circuit device according to any one of 1 to 5, wherein the insulating film includes:
(B1) an inorganic first passivation film;
(B2) An organic second passivation film provided on the first passivation film.

  7). 7. In the semiconductor integrated circuit device according to any one of 1 to 6, solder bumps are provided on the redistribution metal pattern.

  8). 7. The semiconductor integrated circuit device according to item 6, wherein the second passivation film is a polyimide resin film.

  9. In the semiconductor integrated circuit device according to the item 7, the solder bumps are lead-free.

  10. In the semiconductor integrated circuit device according to the item 7 or 9, the solder bump includes gold.

11. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an aluminum-based pad electrode on the multilayer wiring layer on the device surface side of the semiconductor wafer including the multilayer wiring layer;
(B) forming an insulating film having an opening on at least a part of the aluminum-based pad electrode;
(C) forming a seed metal film connected to the aluminum-based pad electrode by sputtering on substantially the entire device surface side of the wafer;
(D) forming a resist film pattern on the seed metal film;
(E) forming a redistribution metal pattern on the seed metal film by electrolytic plating in the presence of the resist film pattern;
(F) using the redistribution metal pattern as an etching mask, removing the seed metal film in a portion without the redistribution metal pattern;
Here, the step (c) includes the following substeps:
(C1) performing a plasma treatment on the device surface side of the semiconductor wafer in a gas phase containing argon gas as a main component;
(C2) After the step (c1), forming a first metal layer containing titanium as a main component by sputtering;
(C3) forming a second metal layer containing titanium nitride as a main component on the first metal layer by sputtering;
(C4) forming a third metal layer containing titanium as a main component on the second metal layer by sputtering;
(C5) forming a fourth metal layer acting as a seed on the third metal layer by sputtering with respect to the redistribution metal pattern;
Here, the thickness of the first metal layer is not less than 5 nm and not more than 60 nm.

  12 In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the step (c) is performed in the same sputtering apparatus without exposure to the atmosphere.

  13. In the method for manufacturing a semiconductor integrated circuit device according to the item 11 or 12, the substeps (c2) to (c4) are performed in the same chamber.

  14 14. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 13, wherein the first metal layer has a thickness of 50 nm or less.

  15. 14. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 13, the thickness of the first metal layer is 25 nm or less.

16. 16. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 15, wherein the redistribution metal pattern includes:
(C1) a first plating layer containing copper as a main component;
(C2) A second plating layer mainly composed of nickel provided on the first plating layer.

17. 17. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 16, wherein the insulating film includes:
(B1) an inorganic first passivation film;
(B2) An organic second passivation film provided on the first passivation film.

  18. In the method for manufacturing a semiconductor integrated circuit device according to the item 17, the second passivation film is a polyimide resin film.

  19. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 18, solder bumps are provided on the redistribution metal pattern.

  20. 20. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 19, a layer containing aluminum oxide as a main component on the aluminum-based pad electrode at the time when the substep (c2) is started. Exists.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”.

  Specifically, even if "gold", "nickel", "copper", "titanium", "titanium nitride", "aluminum", etc., it is not so specifically stated or not theoretically. Except in cases where the above is obvious, it means “a member having each substance as a main component”. In addition, for example, “aluminum pad” and “aluminum-based pad” are not all made of a member whose main component is aluminum, but a member whose main component is aluminum. It represents that a structural element occupies the main part of a pad structure. The same applies to aluminum wiring, copper wiring, and the like.

  Furthermore, for example, “silicon member” or the like is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and other additives. Needless to say. Similarly, the term “silicon oxide film” refers not only to relatively pure undoped silicon oxide, but also to FSG (Fluorosilicate Glass), TEOS-based silicon oxide, and SiOC ( Silicon Oxicarbide) or Carbon-doped Silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, SOG (Spin ON Glass) , Nano-clustering silica (NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous insulating film) in which pores are introduced in similar members, and these are the main Needless to say, it includes a composite film with another silicon-based insulating film as an essential component.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed. Insulation of an epitaxial wafer, an SOI substrate, an LCD glass substrate, etc. Needless to say, it includes a composite wafer such as a substrate and a semiconductor layer.

  6). In the case of “wiring metal pattern”, “rewiring metal pattern”, and “rewiring metal film”, the seed metal layer as a base is not included in principle. The underlying seed metal layer is composed of a lower barrier metal layer, an uppermost seed copper layer, and the like.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Description of process flow after aluminum pad in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 1 to 18)
Hereinafter, based on FIGS. 1 to 16 (see FIGS. 17 and 18), an aluminum-based pad 2p (see FIG. 1, the same applies hereinafter) mainly in a wafer process of a semiconductor integrated circuit device. The pad electrode is a copper-based pad. Others may be used) The area around the formation process will be described. Below the aluminum-based pad layer 2, there is usually a copper-based damascene multilayer wiring layer 1w or an aluminum-based ordinary multilayer wiring layer 1w (generally about 3 to 10 layers).

  As shown in FIG. 1 and FIG. 2, which is a detail of the pad vicinity C, the tungsten plug 7 and the uppermost layer on the device surface 1a (main surface facing the back surface 1b) side of the semiconductor wafer 1 (chip region 1c). On the interlayer insulating film 6, an aluminum-based pad 2p is formed. On the device surface 1a side of the semiconductor substrate 1p (the original substrate portion 1s is usually a 300-type p-type single crystal silicon wafer) including the multilayer wiring layer 1w under the bonding pad 2p, an inorganic final is provided. A passivation film 3 is formed. The aluminum-based pad layer 2 constituting the bonding pad 2p also serves as the uppermost wiring layer 2w in this example (may be dedicated to the pad). The bonding pad 2p and the final passivation film 3 are formed as follows. First, an aluminum-based metal film (usually about 10 nm above and below a main wiring metal layer 2p having a thickness of about 1000 nm, which is mainly composed of intermediate aluminum and added with several percent of copper or the like, is sputtered onto the multilayer wiring layer. And titanium nitride films 8b and 9 having a thickness of about 50 to 75 nm, etc. The pad base metal layer 8 is composed of the titanium films 8a and 8c and the titanium nitride film 8b. Film). The aluminum-based metal film is patterned by ordinary lithography to form a bonding pad 2p. Next, for example, a silicon oxide insulating film (for example, a thickness of about 200 nm) to be the underlying inorganic final passivation film 3a is formed on the entire surface of the semiconductor wafer 1 on the device surface 1a side by a plasma CVD method. Subsequently, a silicon nitride insulating film (for example, a thickness of about 600 nm) to be the upper inorganic final passivation film 3b is formed thereon by plasma CVD, for example. Next, a pad opening 5 is formed in the inorganic final passivation film 3 composed of two layers by ordinary lithography (after this, a titanium nitride film 9 on the main wiring metal layer is generally made of, for example, argon, chlorine, etc.) It is dry-etched and removed in a self-aligned manner in a mixed gas atmosphere (this results in a cross-sectional form as shown in FIG. 2). Next, for example, a polyimide film (for example, a thickness of about 4 micrometers) serving as the lower organic final passivation film 4 is applied to almost the entire surface of the semiconductor wafer 1 on the device surface 1a side. Subsequently, a pad opening 5 is formed again by ordinary lithography at the same opening position as before (lower polyimide layer patterning step 101 in FIG. 17). Therefore, the composite final passivation film 10 (insulating film) at this stage is a three-layered film including the silicon oxide film 3a, the silicon nitride film 3b, and the polyimide film 4 from the lower layer. As will be described later, usually, an organic insulating film is further formed thereon as another final passivation film.

  Here, the aluminum-based metal surface of the aluminum-based pad electrode 2p (the pad upper surface on which the surface containing aluminum as a main component is exposed) is very easily oxidized. Therefore, the lower organic final passivation film 4 is patterned. In the stage where the next process is started, as shown in FIG. 3, there is a natural oxide film 11 (aluminum oxide film) of about several nm. If this is the case, the resistance variation between the pad and the rewiring may increase. Therefore, in the state of FIG. 3, plasma etching processing (sputtering etching) such as argon sputtering is performed on the device surface 1a of the wafer 1. When executed (processing conditions are, for example, room temperature, argon atmosphere, atmospheric pressure of about 0.05 Pa, processing time of about 30 seconds), as shown in FIG. 4, the aluminum oxide film 11 is removed or thinned to about 3 nm or less. Is effective (argon sputtering step 102b in FIG. 18). In the plasma etching process (argon sputtering step 102b) here, it is not necessary to completely remove the aluminum oxide film 11, and it is sufficient to make the whole thin. This is because the thin aluminum oxide film 11 has an effect of protecting the aluminum surface, and even if it is completely removed, it is generated again, so that a substantial effect cannot be expected. If the plasma etching process is performed excessively, the device characteristics may be deteriorated due to the influence of the product from the lower organic final passivation film 4 (polyimide film). It has been confirmed microscopically that a thin aluminum oxide film 11 remains even in a non-defective product stage.

  Next, as shown in FIG. 5, a seed metal layer 12 is formed on almost the entire device surface 1a of the wafer 1 by sputtering (seed layer sputtering step 102 in FIGS. 17 and 18). Details of the seed layer sputtering step 102 will be described with reference to FIGS. 6 to 9 and FIG.

  First, as shown in FIG. 6, a metal film (relatively pure titanium) containing titanium as a main component is formed on almost the entire device surface 1a of the wafer 1 as a seed base metal lowermost layer 12a (first metal layer). The film can be exemplified as a suitable film) by sputtering (processing conditions are, for example, a wafer stage set temperature of about 300 degrees Celsius, an argon atmosphere, an atmospheric pressure of about 0.5 Pa, and a processing time of about 8 seconds) (see FIG. 18 underlayer titanium sputter process 102c). This film acts to reduce the aluminum oxide film on the pad surface.

  Next, as shown in FIG. 7, a metal film containing titanium nitride as a main component as a seed base metal intermediate layer 12b (second metal layer) is formed on the entire device surface 1a of the wafer 1 in a nitrogen gas atmosphere. The film is formed by sputtering (the processing conditions are, for example, a wafer stage set temperature of about 300 degrees Celsius, an argon + nitrogen gas atmosphere, an atmospheric pressure of about 0.5 Pa, and a processing time of about 30 seconds) (titanium nitride in FIG. 18). -Sputtering process 102d). This film contains a large amount of nitrogen and has a high diffusion barrier property against copper or the like. Since the barrier property is high relative to the thickness of a titanium film or the like, the use of a titanium nitride film has an advantage of making the entire barrier metal film thinner. However, the electric resistance alone is high, and there are some problems with the adhesion to the upper layer.

  Subsequently, as shown in FIG. 8, a metal film containing titanium as a main component is sputtered (processing conditions) as a seed base metal uppermost layer 12c (third metal layer) on almost the entire device surface 1a of the wafer 1. Is formed by, for example, a wafer stage set temperature of about 300 degrees Celsius, an argon atmosphere, an atmospheric pressure of about 0.5 Pa, and a processing time of about 8 seconds (upper titanium sputtering process 102e in FIG. 18). This film is for improving adhesion with the upper layer, and does not need to be relatively pure.

  These seed base metal lowermost layer 12a, seed base metal intermediate layer 12b, and seed base metal uppermost layer 12c constitute a barrier metal layer 14 (FIG. 8). Further, the barrier metal sputtering process 112 is constituted by the lower titanium sputtering process 102c to the upper titanium sputtering process 102e. The target film thickness of the seed base metal bottom layer 12a and the seed base metal top layer 12c is, for example, about 10 nm, and the practical range is about 5 nm to 60 nm. The target thickness of the seed base metal intermediate layer 12b is about 50 nm, for example, and the practical range is about 30 nm to 100 nm.

  Further, as shown in FIG. 9, a metal film containing copper as a main component is sputtered as a seed copper layer 12d (fourth metal layer) on almost the entire device surface 1a of the wafer 1 (processing conditions are, for example, The wafer stage is set at room temperature, argon atmosphere, atmospheric pressure of about 0.05 Pa, and processing time of about 15 seconds. The film thickness target value of the seed copper layer 12d is, for example, about 150 nm, and the practical range is about 100 nm to 200 nm. The barrier metal layer 14 and the seed copper layer 12d constitute the seed metal layer 12.

  Next, as shown in FIG. 10, a resist film pattern 15 is formed on the seed metal layer 12 by ordinary lithography (resist patterning step in FIG. 17). Subsequently, as shown in FIG. 11, a redistribution metal film lower layer film 16a containing copper as a main component by electrolytic plating (the target film thickness is about 5.7 micrometers, for example, and is within a practical range. Is about 4 to 10 micrometers). Next, on the redistribution metal film lower layer film 16a, a redistribution metal film upper layer film 16b containing nickel as a main component is formed by electrolytic plating (the target thickness is about 2.7 micrometers, for example). The typical range is about 2 to 4 micrometers) (rewiring electrolytic plating step 104 in FIG. 17). A rewiring metal film (rewiring metal pattern, wiring metal pattern) 16 is constituted by the rewiring metal film lower layer film 16a, the rewiring metal film upper layer film 16b, and the like.

  Next, as shown in FIG. 12, the unnecessary resist film pattern 15 is removed and the outside of the redistribution metal pattern 16 is removed. Next, in FIG. 13, the seed metal layer 12 is removed in a self-aligned manner by wet etching (resist removal & wet etching step 105 in FIG. 17).

  Next, as shown in FIG. 13, a bump forming opening 17 (with a land opening diameter of, for example, 90 is formed on the device surface 1a side of the wafer 1 as an upper organic final passivation film 22 by ordinary lithography. A polyimide film pattern (for example, about 6 micrometers in thickness) having a thickness of 200 micrometers is formed (upper polyimide layer patterning step 106 in FIG. 17).

  Further, as shown in FIG. 14, a protective metal layer 18 containing gold as a main component is formed by electroless plating on the surface of the bump forming portion 21 in the bump forming opening 17 (electroless gold plating step of FIG. 17). ).

  Next, as shown in FIG. 15, the probe inspection is executed by bringing the probe needle 19 into contact with the protective metal layer 18 (probe inspection step in FIG. 17). Next, as shown in FIG. 16, solder bumps 20 are formed on the nickel surface of the bump forming portion 21 by a solder paste printing method, a ball arrangement method, or the like and a solder reflow process. At this time, since the gold of the protective metal layer 18 diffuses into the bumps, the protective metal layer 18 eventually disappears as a result of the solder reflow process.

  Note that the probe inspection process 108 and the BG process 109 in FIG. 17 may be performed after the bump formation process 110.

2. Description of manufacturing apparatus used for manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (refer mainly to FIG. 19 to FIG. 22, FIG. 17 and FIG. 18)
In this section, some of the processes described in Section 1 are described in terms of each manufacturing equipment process. First, the seed layer sputter film forming step 102 of FIGS. 17 and 18 will be described. The process after the solder reflow process is also described in this section for convenience.

  After the lower polyimide layer patterning step 101 of FIG. 17, as shown in FIG. 19, first, the wafer 1 accommodated in the hoop 52 is loaded by a multi-chamber type sputtering apparatus 51 ( It is introduced into a buffer chamber 56 of a device that continuously performs sputtering and related processing. After that, it is introduced into the vacuum transfer chamber 58 through the load lock chamber 57 by the load and unload robot 59 and introduced into the argon / sputter chamber 53 by the vacuum transfer robot 60. Therefore, first, a degas process 102a (FIG. 18) for releasing the gas adsorbed on the surface of the wafer 1 is performed (the process conditions are, for example, the wafer stage set temperature is about 250 degrees Celsius, and the additive gas is No emptying state, atmospheric pressure of about 1 KPa, processing time of about 30 seconds from reaching the specified pressure). Subsequently, the argon sputtering process 102b is performed as it is.

  Next, the wafer 1 is transferred to the titanium-based metal sputtering chamber 54 by the vacuum transfer robot 60. Therefore, the barrier metal sputtering step 112 is continuously performed. That is, a lower titanium layer sputtering step 102c, a titanium nitride layer sputtering step 102d, and an upper titanium layer sputtering step 102e in this order.

  Next, the wafer 1 is transferred to the copper sputtering chamber 55 by the vacuum transfer robot 60. Therefore, a copper seed layer sputtering step 102f is performed. Here, the wafer 1 is first introduced into the load lock chamber 57, until the processing of each of the processing chambers 53, 54, 55 is completed and returns to the load lock chamber 57 again (the same as there are a plurality of load lock chambers). (But not limited to).

  Thereafter, the wafer 1 is transferred to the load lock chamber 57 by the vacuum transfer robot 60, and is then returned into the FOUP 52 by the load & unload robot 59, and in the next resist patterning step 103 (FIG. 17). To the processing section for. Therefore, the wafer 1 on which the resist film pattern 15 is formed is returned to the hoop 52 again and transferred to the plating apparatus 71 (plating related processing apparatus). In the plating apparatus 71, processing is performed as follows.

  As shown in FIG. 20, first, the wafer 1 is introduced into the buffer chamber 56 from the inside of the hoop 52 by the loading and unloading robot 59. From there, it is transferred to the pre-dip tank 79 in the electroplating unit 72 by the internal transfer robot 75 of the internal transfer unit 74, where it is pre-treated with a phosphoric acid-based treatment solution for improving wettability and removing organic components ( The liquid temperature is room temperature and the processing time is about 200 seconds). Next, the wafer 1 is transferred to the water washing tank 78 by the internal transfer robot 75 where it is washed with water (the liquid temperature is room temperature and the processing time is about 30 seconds). Next, the wafer 1 is transferred to the copper electroplating bath 81 by the internal transfer robot 75, where the copper electroplating process, which is the first step of the rewiring electroplating step 104 (FIG. 17), is performed, for example, sulfate-based copper plating. The liquid is used (the liquid temperature is room temperature and the processing time is about 460 seconds). Next, the wafer 1 is transferred again to the water washing tank 78 by the internal transfer robot 75, where it is washed with water (liquid temperature is room temperature, processing time is about 30 seconds). Next, the wafer 1 is transferred to an acid treatment tank 77 by an internal transfer robot 75, where pretreatment is performed with a sulfuric acid-based treatment liquid for removing surface metal oxides (the liquid temperature is room temperature, the treatment is performed). Time is about 80 seconds). Next, the wafer 1 is transferred again to the water washing tank 78 and washed with water by the internal transfer robot 75 (the liquid temperature is room temperature and the processing time is about 30 seconds). Next, the wafer 1 is transferred to the nickel electroplating tank 82 by the internal transfer robot 75, where the nickel electroplating process, which is the second step of the rewiring electroplating step 104 (FIG. 17), is performed, for example, borate nickel. -It is performed using a plating solution (the solution temperature is about 55 degrees Celsius and the processing time is about 450 seconds). Next, the wafer 1 is transferred again to the water washing tank 78 by the internal transfer robot 75, where it is washed with water (liquid temperature is room temperature, processing time is about 50 seconds). Further, the wafer 1 is transferred to the spin rinse & dry stage 76 by the internal transfer robot 75, and rinse and spin drying are performed on the spin stage (the liquid temperature is room temperature and the processing time is about 90 seconds). ). Thereafter, the wafer 1 is returned to the FOUP 52 by the internal transfer robot 75 and the load & unload robot 59. Next, the hoop 52 is transferred to a unit for resist removal & wet etching step 105 (FIG. 17).

  When the upper polyimide layer patterning step 106 (FIG. 17) is completed, the wafer 1 is again accommodated in the hoop 52 and transferred to the plating apparatus 71. As before, the wafer 1 is introduced from the FOUP 52 into the buffer chamber 56 by the load and unload robot 59. From there, it is transferred to the pre-dip tank 79 in the electroplating unit 72 by the internal transfer robot 75 of the internal transfer unit 74, where it is pretreated with an organic hydrochloric acid-based processing solution for improving wettability and removing organic components. Is implemented. Next, the wafer 1 is transferred by an internal transfer robot 75 to a water washing tank 78 where it is washed with water (the liquid temperature is room temperature and the processing time is about 30 seconds). Next, the wafer 1 is transferred to the acid treatment tank 77 by the internal transfer robot 75, where pretreatment is performed with hydrochloric acid-based treatment liquid for removing surface metal oxide, surface activation, and the like (the liquid temperature is room temperature). The processing time is about 80 seconds). Next, the wafer 1 is transferred again to the water washing tank 78 and washed with water by the internal transfer robot 75 (the liquid temperature is room temperature and the processing time is about 30 seconds). Next, the wafer 1 is transferred to the electroless plating tank 91 by the internal transfer robot 75, where the electroless gold plating step 107 (FIG. 17) is performed using, for example, a gold sulfite plating solution (the liquid temperature is about 55 degrees Celsius). The processing time is about 450 seconds). Next, the wafer 1 is transferred again to the water washing tank 78 by the internal transfer robot 75, where it is washed with water (the liquid temperature is room temperature and the processing time is about 100 seconds). Further, the wafer 1 is transferred to the spin rinse & dry stage 76 by the internal transfer robot 75, and rinse and spin drying are performed on the spin stage (the liquid temperature is room temperature and the processing time is about 90 seconds). ). Thereafter, the wafer 1 is returned to the FOUP 52 by the internal transfer robot 75 and the load & unload robot 59. Next, the hoop 52 is transferred to a unit for resist removal & wet etching step 105 (FIG. 17).

  Thereafter, the hoop 52 containing the wafer 1 can be sequentially sent to the units for the probe inspection process 108 (FIG. 17) and the back-grinding process 109 (FIG. 17). For the bump forming step 110 (FIG. 17), it is conveyed to the solder paste printing device 61 (FIG. 21) or the solder bump arranging device 62 (FIG. 22). The solder paste printing device 61 is suitable for general products, and the solder bump arranging device 62 is suitable for narrow pitch products having a bump pitch of about 100 micrometers or less.

  First, the bump formation process 110 (FIG. 17) using the solder paste printer 61 will be described. As shown in FIG. 21, the squeegee is horizontally placed with the print mask 32 overlaid on the wafer 1 so that the plurality of bump forming portions 21 on the wafer 1 and the mask openings 37 of the print mask 32 coincide with each other. By moving, the solder paste 33 fills each mask opening 37. Thereafter, when the printing mask 32 is peeled off, the solder paste 33 is printed on the bump forming portion 21. When this is subjected to a reflow process, the solder becomes a shape as shown in FIG.

  Next, the bump formation process 110 (FIG. 17) using the solder bump array device 62 will be described. As shown in FIG. 22, first, flux 35 is printed on the plurality of bump forming portions 21 on the wafer 1. In this state, the solder balls shaped from above with the alignment masks 32 stacked on the wafer 1 at a predetermined interval so that each mask opening 37 of the alignment mask 34 coincides with the plurality of bump forming portions 21. 36 is supplied. One solder ball 36 enters each mask opening 37 and is temporarily bonded to the flux 35. Thereafter, when the alignment mask 32 is removed and the reflow process is performed in the same manner as described above, the solder becomes a shape as shown in FIG.

  After these bump formation processes 110 (FIG. 17) are completed, a dicing process 111 (FIG. 17) for dividing the wafer 1 into individual chips 1c is performed.

3. Explanation of various data (mainly FIGS. 23 to 26)
In this section, various verification data, reference data, and the like regarding the embodiment of the present invention described in the previous two sections will be described.

  FIG. 23 is a data plot diagram showing the relationship between the lower layer titanium film thickness and the pad-rewiring resistance (for a single contact) (for a single contact) in the structure of FIG. In this figure, the square data is measured for a normal 10 micrometer square pad opening and the circular data is measured for a 5 micrometer square pad opening for testing. The latter tends to be more sensitive to resistance variations.

  As shown in FIG. 23, when the film thickness of the seed base metal bottom layer (first metal layer), that is, the lower layer titanium film is about 3 nm, the resistance value between the pad rewirings is equivalent to that without the lower layer titanium film. is there. On the other hand, when the thickness of the lower titanium film is about 5 nm or more, the resistance value between the pad rewirings is stably low. Therefore, considering the process variation, the lower limit of the thickness of the lower titanium film is preferably about 5 nm.

  FIG. 24 is a data plot diagram showing the distribution of rewiring resistance in the structure of FIG. 12 (when the pad opening is 10 micrometer square). FIG. 25 is a data plot diagram showing the distribution of rewiring resistance in the structure of FIG. 12 (when the pad opening is 5 micrometer square). From these, it can be seen that the distribution of the resistance value between the pad rewirings is small when the thickness of the lower titanium film is about 5 nm or more.

  Next, an appropriate upper limit of the thickness of the lower titanium film will be examined. FIG. 26 is a data plot diagram showing the relationship between the lower layer titanium film thickness and the resistance between the pad and the rewiring (for a single contact) in the structure of FIG. Measured via). Although this data includes several series connections and bumps and other resistances, the absolute value is high, but it is useful to see relative changes.

  As shown in FIG. 26, a remarkable increase in resistance is observed when the thickness of the lower titanium film is about 25 nm or more, and it is considered that the practical range is up to about 60 nm in consideration of practical and process costs. It is done. Therefore, the appropriate upper limit of the thickness of the lower layer titanium film is considered to be about 60 nm.

  From FIG. 23, FIG. 26, etc., the practical film thickness range of the lower layer titanium film is 5 nm or more and 60 nm or less. An appropriate range in consideration of mass productivity is 5 nm or more and 50 nm or less. Furthermore, the most preferable range in consideration of low resistance and the like is 5 nm or more and 25 nm or less.

4). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the two-layer rewiring composed of the lower copper rewiring layer and the upper nickel rewiring layer has been specifically described. However, the present invention is not limited thereto, Needless to say, the present invention can also be applied to a single rewiring layer structure and other multilayer rewiring structures. Further, an example in which a p-type single crystal silicon substrate is used as the semiconductor substrate has been specifically described. However, the present invention is not limited thereto, and other single crystal semiconductor substrates such as an n-type single crystal silicon substrate are used. Needless to say, the present invention can also be applied to an insulating substrate such as an SOI substrate or a glass substrate, a compound semiconductor substrate such as GaAs, or the like.

  Moreover, in the said embodiment, although the example which uses a polyimide-type resin film was shown as an organic type final passivation film, this invention is not limited to it, BCB (Benzo-Cyclo-Butene) and others Needless to say, the heat-resistant polymer resin film may be used.

It is a device section flow figure (lower layer polyimide layer patterning process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. FIG. 2 is a device enlarged cross-sectional flow diagram (lower polyimide layer patterning step) showing a detailed process of a pad vicinity portion C in FIG. 1. FIG. 2 is a device enlarged cross-sectional flowchart showing a detailed process of a pad vicinity portion C in FIG. 1 (showing a state of forming a natural oxide film between steps). FIG. 2 is a device enlarged cross-sectional flow diagram (argon sputtering step) showing a detailed process of a pad vicinity C in FIG. 1. It is a device section flow figure (seed metal layer sputtering process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. FIG. 6 is a device enlarged cross-sectional flow diagram (lower titanium layer sputtering step) showing a detailed process of the pad vicinity portion C of FIG. 5. FIG. 6 is a device enlarged cross-sectional flow diagram (titanium nitride layer sputtering step) showing a detailed process of the pad vicinity portion C of FIG. 5. FIG. 6 is a device enlarged cross-sectional flow diagram (upper titanium layer sputtering step) showing a detailed process of the pad vicinity portion C of FIG. 5. FIG. 6 is a device enlarged cross-sectional flow diagram (copper seed layer sputtering step) showing a detailed process of the pad vicinity portion C of FIG. 5. It is a device section flow figure (resist film patterning process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device cross section flowchart (rewiring metal electroplating process) which shows the flow of the process after the aluminum-type pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device section flow figure (resist film removal process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device section flow figure (upper layer polyimide film patterning process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device section flow figure (gold electroless plating process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device section flow figure (probe inspection process) which shows the flow of the process after the aluminum system pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a device cross section flowchart (bump formation process) which shows the flow of the process after the aluminum-type pad in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. FIG. 5 is a process block flow diagram illustrating a process flow after an aluminum-based pad in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 18 is a detailed process block flow diagram showing details of the seed sputtering process of FIG. 17. It is a plane layout figure of the sputtering device used for the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. 1 is a plan layout view of a plating apparatus used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. 1 is a plan layout view of a solder printing apparatus used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. 1 is a plan layout view of a solder ball mounting device used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 13 is a data plot diagram showing the relationship between the lower layer titanium film thickness and the pad-rewiring resistance (for a single contact) (for a single contact) in the structure of FIG. FIG. 13 is a data plot diagram showing the distribution of resistance between rewirings in the structure of FIG. 12 (in the case where the pad opening is 10 μm square). FIG. 13 is a data plot diagram showing the distribution of resistance between rewirings in the structure of FIG. 12 (in the case where the pad opening is 5 μm square). 16 is a data plot diagram showing the relationship between the lower layer titanium film thickness and the resistance between the pad and the rewiring (for a single contact) in the structure of FIG. Measurement).

Explanation of symbols

1 Semiconductor wafer or semiconductor substrate (including those in the process of manufacturing integrated circuits)
1a Device surface of semiconductor wafer or semiconductor chip (upper surface or first main surface)
1b Rear surface of semiconductor wafer or semiconductor chip (second main surface)
1c Semiconductor chip or chip region 1p Semiconductor wafer or semiconductor substrate including multilayer wiring layer under pad 1s Single crystal substrate portion of semiconductor wafer or semiconductor substrate including well region (p-type silicon single crystal substrate)
1w (including pre-metal layer, etc.) multilayer wiring layer under pad 2 uppermost aluminum metal layer 2p aluminum pad electrode 2w aluminum wiring 3 inorganic final passivation film 3a lower inorganic final passivation film 3b upper inorganic layer System final passivation film 4 lower organic final passivation film 5 pad opening 6 uppermost interlayer insulating film 7 tungsten plug 8 pad base metal layer 8a pad base metal layer bottom layer 8b pad base metal layer intermediate layer 8c pad base metal layer Top layer 9 Pad upper metal layer 10 Composite final passivation film 11 Aluminum oxide layer (natural oxide film)
12 Seed metal layer 12a Seed base metal bottom layer (first metal layer)
12b Seed base metal intermediate layer (second metal layer)
12c Top layer of seed base metal (third metal layer)
12d seed copper layer (fourth metal layer)
14 Barrier metal layer 15 Resist film pattern 16 Redistribution metal film (Redistribution metal pattern)
16a Redistribution metal film lower layer film 16b Redistribution metal film upper layer film 17 Bump formation opening (land opening)
18 Protective metal layer (electroless gold plating film)
19 Probe Needle 20 Solder Bump 21 (Rewiring) Bump Formation 22 Upper Organic Final Passivation Film 31 Squeegee 32 Print Mask 33 Solder Paste 34 Alignment Mask 35 Flux 36 Solder Ball 37 Mask Opening 51 Sputtering Device 52 Hoop 53 Argon Sputtering chamber 54 Titanium metal sputtering chamber 55 Copper sputtering chamber 56 Buffer chamber 57 Load lock chamber 58 Vacuum transfer chamber 59 Load and unload robot 60 Vacuum transfer robot 61 Solder paste printing device 62 Solder bump array device 71 Plating device 72 Electrolysis Plating unit 73 Electroless plating unit 74 Internal transfer unit 75 Internal transfer robot 76 Spin rinse & dry stage 77 Acid treatment tank 78 Pure water cleaning tank 79 Pre-D Flop tank 81 electrolytic copper plating tank 82 Nickel electroless plating tank 91 gold electroless plating bath 101 underlying polyimide layer patterning step 102 the seed layer sputtering process (including a base barrier metal sputtering step)
102a Degassing step 102b Argon sputtering step 102c Lower titanium layer sputtering step 102d Titanium nitride layer sputtering step 102e Upper titanium layer sputtering step 102f Copper seed layer sputtering step 103 Resist patterning step 104 Rewiring electroplating step 105 Resist removal & wet etching process 106 Upper polyimide layer patterning process 107 Electroless gold plating process 108 Probe inspection process 109 Back grinding process 110 Bump formation process 111 Dicing process 112 Barrier metal sputtering process C Near the pad

Claims (20)

Semiconductor integrated circuit devices including:
(A) an aluminum-based pad electrode provided on the multilayer wiring layer on the device surface of the semiconductor substrate including the multilayer wiring layer;
(B) an insulating film having an opening on at least a part of the aluminum-based pad electrode;
(C) a wiring metal pattern provided on the aluminum-based pad electrode and the insulating film so as to cover the opening;
(D) a barrier metal layer provided on the aluminum-based pad electrode under the wiring metal pattern and on the insulating film;
Here, the barrier metal layer includes:
(D1) a first metal layer containing titanium as a main component;
(D2) a second metal layer mainly composed of titanium nitride provided on the first metal layer;
(D3) a third metal layer mainly composed of titanium provided on the second metal layer,
Here, the thickness of the first metal layer is not less than 5 nm and not more than 60 nm.     In the semiconductor integrated circuit device according to the item 1, the thickness of the first metal layer is 50 nm or less.     In the semiconductor integrated circuit device according to the item 1, the thickness of the first metal layer is 25 nm or less. In the semiconductor integrated circuit device according to the item 1, the wiring metal pattern includes:
(C1) a first plating layer containing copper as a main component;
(C2) A second plating layer mainly composed of nickel provided on the first plating layer.     In the semiconductor integrated circuit device according to the item 1, a layer containing aluminum oxide as a main component exists on the aluminum-based pad electrode immediately below the first metal layer. In the semiconductor integrated circuit device according to the item 1, the insulating film includes:
(B1) an inorganic first passivation film;
(B2) An organic second passivation film provided on the first passivation film.     In the semiconductor integrated circuit device according to the item 1, solder bumps are provided on the wiring metal pattern.     7. The semiconductor integrated circuit device according to item 6, wherein the second passivation film is a polyimide resin film.     In the semiconductor integrated circuit device according to the item 7, the solder bumps are lead-free.     10. The semiconductor integrated circuit device according to item 9, wherein the solder bump includes gold. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an aluminum-based pad electrode on the multilayer wiring layer on the device surface side of the semiconductor wafer including the multilayer wiring layer;
(B) forming an insulating film having an opening on at least a part of the aluminum-based pad electrode;
(C) forming a seed metal film connected to the aluminum-based pad electrode by sputtering on substantially the entire device surface side of the wafer;
(D) forming a resist film pattern on the seed metal film;
(E) forming a wiring metal pattern on the seed metal film by electrolytic plating in the presence of the resist film pattern;
(F) using the wiring metal pattern as an etching mask, removing the seed metal film in a portion without the wiring metal pattern;
Here, the step (c) includes the following substeps:
(C1) performing a plasma treatment on the device surface side of the semiconductor wafer in a gas phase containing argon gas as a main component;
(C2) After the step (c1), forming a first metal layer containing titanium as a main component by sputtering;
(C3) forming a second metal layer containing titanium nitride as a main component on the first metal layer by sputtering;
(C4) forming a third metal layer containing titanium as a main component on the second metal layer by sputtering;
(C5) forming a fourth metal layer acting as a seed on the third metal layer by sputtering with respect to the wiring metal pattern;
Here, the thickness of the first metal layer is not less than 5 nm and not more than 60 nm.     In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the step (c) is performed in the same sputtering apparatus without exposure to the atmosphere.     In the method for manufacturing a semiconductor integrated circuit device according to the item 12, the substeps (c2) to (c4) are performed in the same chamber.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the thickness of the first metal layer is 50 nm or less.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the thickness of the first metal layer is 25 nm or less. 12. The method for manufacturing a semiconductor integrated circuit device according to the item 11, wherein the wiring metal pattern includes:
(C1) a first plating layer containing copper as a main component;
(C2) A second plating layer mainly composed of nickel provided on the first plating layer. 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the insulating film includes:
(B1) an inorganic first passivation film;
(B2) An organic second passivation film provided on the first passivation film.     In the method for manufacturing a semiconductor integrated circuit device according to the item 17, the second passivation film is a polyimide resin film.     12. In the method of manufacturing a semiconductor integrated circuit device according to the item 11, solder bumps are provided on the wiring metal pattern.     In the method for manufacturing a semiconductor integrated circuit device according to the item 11, a layer containing aluminum oxide as a main component exists on the aluminum-based pad electrode when the substep (c2) is started.

Images