JP2010147103A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device superior in a charge deletion characteristic and a charge holding characteristic. <P>SOLUTION: The semiconductor device includes a semiconductor region 101, a tunnel insulating film 102 formed on a surface of the semiconductor region, a charge accumulation insulating film 103 formed on a surface of the tunnel insulating film, a block insulating film 104 formed on a surface of the charge accumulation insulating film and a control gate electrode 105 formed on a surface of the block insulating film. The tunnel insulating film includes a first region 102a which is formed on the surface of the semiconductor region and contains silicon and oxygen, a second region 102b which is formed on the surface of the first region and contains silicon and nitrogen, a third region 102d which is formed on a rear face of the charge accumulation insulating film and contains silicon and oxygen, and a fourth region 102c which is formed between the second region and the third region, contains silicon, nitrogen and oxygen, has nitrogen concentration lower than that of the second region and has oxygen concentration lower than that of the third region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Currently, a charge trapping nonvolatile semiconductor memory device using a charge trapping insulating film for charge trapping as a charge storage layer has been developed (see, for example, Patent Document 1). In this charge trap type nonvolatile semiconductor memory device, charges are accumulated in the charge storage insulating film by trapping the charge injected into the charge storage insulating film through the tunnel insulating film at the trap level in the charge storage insulating film. Is done. As a typical charge trapping type nonvolatile semiconductor memory device, a MONOS type or SONOS type nonvolatile semiconductor memory device is known, and a silicon nitride film or the like is used as a material of the charge storage insulating film.

In the above-described charge trap type nonvolatile semiconductor memory device, a tunnel insulating film having a laminated structure (ONO structure) composed of a silicon oxide film, a silicon nitride film and a silicon oxide film has been proposed for the purpose of increasing the charge erasing speed. (For example, refer to Patent Document 2). However, it has not been said that a nonvolatile semiconductor memory device excellent in both charge erasing characteristics and charge holding characteristics has been proposed.
JP 2004-158810 A JP 2006-216215 A

  An object of the present invention is to provide a semiconductor device excellent in charge erasing characteristics and charge holding characteristics and a method for manufacturing the same.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor region, a tunnel insulating film formed on the surface of the semiconductor region, a charge storage insulating film formed on the surface of the tunnel insulating film, and the charge storage A semiconductor device comprising: a block insulating film formed on a surface of the insulating film; and a control gate electrode formed on the surface of the block insulating film, wherein the tunnel insulating film is formed on the surface of the semiconductor region A first region containing silicon and oxygen as main components, a second region formed on the surface of the first region and containing silicon and nitrogen as main components, and a back surface of the charge storage insulating film. Formed between the second region and the third region, containing silicon, nitrogen and oxygen, and the second region containing silicon and oxygen as main components. Territory Has a lower nitrogen concentration than the nitrogen concentration, characterized in that it comprises a fourth region having a lower oxygen concentration than the oxygen concentration in the third region.

  A semiconductor device manufacturing method according to a second aspect of the present invention includes a semiconductor region, a tunnel insulating film formed on the surface of the semiconductor region, a charge storage insulating film formed on the surface of the tunnel insulating film, A block insulating film formed on the surface of the charge storage insulating film, and a control gate electrode formed on the surface of the block insulating film, the tunnel insulating film is formed on the surface of the semiconductor region, A first region containing silicon and oxygen as main components, a second region containing silicon and nitrogen as main components, and formed on the back surface of the charge storage insulating film. A third region containing silicon and oxygen as main components, and formed between the second region and the third region, containing silicon, nitrogen, and oxygen; Nitrogen concentration And a fourth region having an oxygen concentration lower than that of the third region and a step of forming the fourth region. Is performed by depositing an insulating film serving as a fourth region between the step of forming the second region and the step of forming the third region.

  According to the present invention, it is possible to provide a semiconductor device having excellent charge erasing characteristics and charge holding characteristics and a method for manufacturing the same.

  Hereinafter, a semiconductor device according to an embodiment of the present invention (a charge trap type nonvolatile semiconductor memory device using a charge trapping charge storage insulating film as a charge storage layer) will be described.

(First embodiment)
The basic configuration of the semiconductor device according to the first embodiment will be schematically described with reference to FIGS.

  FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention, and mainly shows the configuration of a memory cell transistor. 1A is a cross-sectional view along the channel length direction (bit line direction), and FIG. 1B is a cross-sectional view along the channel width direction (word line direction).

  As shown in FIGS. 1A and 1B, a tunnel insulating film 102 is formed on the surface of a semiconductor substrate (silicon substrate) 101, and a charge storage insulating film 103 is formed on the surface of the tunnel insulating film 102. Has been. A block insulating film 104 is formed on the surface of the charge storage insulating film 103, and a control gate electrode 105 is formed on the surface of the block insulating film 104. An interlayer insulating film 106 is formed so as to cover the memory cell transistor. An element isolation insulating film 107 is formed between adjacent memory cell transistors.

  The tunnel insulating film 102 includes an oxide film (first region) 102a formed on the surface of the semiconductor substrate 101, a nitride film (second region) 102b formed on the surface of the oxide film 102a, and a nitride film. An oxynitride film (fourth region) 102c formed on the surface of 102b and an oxide film (third region) 102d formed on the surface of the oxynitride film 102c are provided.

  The oxide film 102a and the oxide film 102d are, for example, silicon oxide films containing silicon and oxygen as main components. The nitride film 102b is, for example, a silicon nitride film containing silicon and nitrogen as main components. The oxynitride film 102c is, for example, a silicon oxynitride film containing silicon, nitrogen, and oxygen as main components.

  FIG. 2 shows the nitrogen concentration distribution in the depth direction of the nitride film 102b and the oxynitride film 102c. FIG. 2A is a cross-sectional view schematically showing the configuration of the tunnel insulating film 102 of the first embodiment. FIG. 2B shows the nitrogen concentration distribution in the nitride film 102b and the oxynitride film 102c.

  As shown in FIG. 2, the nitrogen concentration of the oxynitride film 102c decreases from the boundary between the nitride film 102b and the oxynitride film 102c toward the boundary between the oxide film 102d and the oxynitride film 102c. Conversely, the oxygen concentration increases from the boundary between the nitride film 102b and the oxynitride film 102c toward the boundary between the oxide film 102d and the oxynitride film 102c. Further, the nitrogen concentration distribution in (A) is a distribution when the nitrogen concentration decreases at a constant rate, and the distribution in (B) has more nitrogen and oxygen than the distribution in (A). The distribution is small. Further, the distribution of (C) is a case where there is less nitrogen and more oxygen than the distribution of (A).

  FIG. 3 is an energy band diagram showing the charge erasing operation and after the charge erasing operation of the memory cell transistor. 3A is an energy band diagram at the time of charge erasing operation of the comparative example (the tunnel insulating film is ONO structure), and FIG. 3B is a diagram at the time of charge erasing operation of the memory cell transistor of the first embodiment. FIG. 3C is an energy band diagram after charge erasure (during charge retention) of the memory cell transistor of the first embodiment.

  As shown in FIG. 3A, when the tunnel insulating film 102 has the ONO structure of the oxide film 102a, the nitride film 102b, and the oxide film 102e, the valence of the oxide film 102e is more than the valence band edge of the nitride film 102b. Since the electron band edge has a higher energy barrier against holes, holes are injected into the charge storage insulating film 103 by the barrier of the oxide film 102e against holes during the charge erasing operation (hole injection). Is disturbed. Therefore, holes are trapped in the potential well of the nitride film 102b.

  In the tunnel insulating film 102 of the present embodiment, an oxynitride film 102c is formed between the nitride film 102b and the oxide film 102d. For this reason, as shown in FIG. 3B, holes are injected into the charge storage insulating film 103 without being blocked by a barrier, and holes are not trapped in the tunnel insulating film 102. For this reason, saturation of the erasing characteristics due to hole traps is suppressed, and good erasing characteristics can be obtained.

  In the present embodiment, as shown in FIG. 3C, the oxynitride film 102c and the oxide film 102d function as a barrier against holes during charge retention, so that deterioration of charge retention characteristics can be suppressed. It is.

  As a result, in this embodiment, it is possible to obtain a memory cell transistor having good charge erasing characteristics and charge holding characteristics.

  As shown in FIGS. 3B and 3C, in the case of (B) (corresponding to (B) of FIG. 2), the barrier against holes is reduced from the low electric field side during the erase operation. , Erase speed is improved. In the case of (C) (corresponding to (C) in FIG. 2), the energy barrier on the tunnel insulating film 102 side with respect to the holes accumulated in the charge storage insulating film 103 is increased, so that the charge retention characteristics at the time of erasing are increased. Will improve.

  A basic manufacturing method of the semiconductor device according to the first embodiment will be schematically described with reference to FIGS. 1 and 4 to 7.

  4 to 7 are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 4A to 7A are cross-sectional views along the bit line direction, and FIGS. 4B to 7B are cross-sectional views along the word line direction.

  First, as shown in FIG. 4, by exposing the surface of a semiconductor substrate 101 doped with a desired impurity to an oxygen atmosphere at 700 ° C., silicon oxide having a thickness of about 1.5 nm is formed as an oxide film (first region) 102a. A film is formed. Further, a silicon nitride film having a thickness of about 3.5 nm is deposited using an ALD (Atomic Layer Deposition) method. Thereafter, at least the surface region of the silicon nitride film is oxidized in an atmosphere containing oxygen radicals at a substrate temperature of 700 ° C. to form a nitride film (second region) 102b and an oxynitride film (fourth region) 102c in FIG. A silicon nitride film and a silicon oxynitride film having a nitrogen concentration distribution as shown in b) are formed. Thereafter, a silicon oxide film having a thickness of about 0.5 nm is deposited as an oxide film (third region) 102d by using ALD at a substrate temperature of 550 ° C. using dichlorosilane and ozone gas. As a result, a tunnel insulating film 102 having a stacked structure including the oxide film 102a, the nitride film 102b, the oxynitride film 102c, and the oxide film 102d having a thickness of about 6 nm is formed.

  Subsequently, a silicon nitride film having a thickness of about 5 nm to be the charge storage insulating film 103 is deposited by using a CVD (Chemical Vapor Deposition) method, and a processing mask material 108 is formed on the charge storage insulating film 103 by using the CVD method. accumulate.

  Next, as shown in FIG. 5, the processing mask material 108, the charge storage insulating film 103, and the tunnel insulating film 102 are sequentially etched by RIE (Reactive Ion Etching) using a resist mask (not shown). Then, the exposed semiconductor substrate is etched by a depth of about 100 nm to form an element isolation groove 107a.

  Next, as shown in FIG. 6, a silicon oxide film is formed by a coating method, and planarized by a CMP (chemical mechanical polishing) method to form an element isolation insulating film 107. Thereafter, the processing mask material 108 is removed, and an alumina film having a thickness of about 13 nm to be the block insulating film 104 is deposited by ALD. Next, polycrystalline silicon doped with impurities to be the control gate electrode 105 is deposited by CVD, and a processing mask material 109 is deposited.

  Next, as shown in FIG. 7, the processing mask material 109, the control gate electrode film 105, the block insulating film 104, and the charge storage insulating film 103 are sequentially etched by RIE using a resist mask (not shown). A plurality of gate structures having a width and interval of about 20 nm are formed. At this time, the surface of the tunnel insulating film 102 is exposed. Subsequently, an impurity diffusion layer (not shown) for source / drain is formed by ion implantation and thermal annealing.

  Next, as shown in FIG. 1, the processing mask material 109 is removed, a silicon oxide film to be the interlayer insulating film 106 is formed by a coating method, and planarized by a CMP method. Thereafter, a wiring layer or the like (not shown) is formed using a well-known technique to complete the nonvolatile semiconductor memory device.

  According to the first embodiment, an oxynitride film 102c having a desired nitrogen concentration distribution can be formed by oxidizing the silicon nitride film formed on the oxide film 102a.

  As a result, in this embodiment, it is possible to obtain a memory cell transistor having good charge erasing characteristics and charge holding characteristics.

  Next, a basic configuration of a semiconductor device according to a modification of the first embodiment will be schematically described with reference to FIGS. The nitrogen concentration distribution in (A) in each figure is a distribution when the nitrogen concentration decreases at a constant rate, and the distribution in (B) in each figure is compared with the distribution in (A). Thus, the distribution is when the amount of nitrogen is large and the amount of oxygen is small. Further, the distribution of (C) in each figure is a case where there is less nitrogen and more oxygen than the distribution of (A).

  FIGS. 9, 11 and 13 are energy band diagrams showing the charge erasing operation and after the charge erasing operation (when holding the charge) of the memory cell transistor.

(Modification 1)
FIG. 8A is a cross-sectional view schematically showing the configuration of the tunnel insulating film 102. FIG. 8B shows a nitrogen concentration distribution in the oxynitride film 102f.

  As shown in FIG. 8A, this modification has an oxide film 102a (first region) and an oxide film 102d (third region) as in the above-described embodiment. A region which is the nitride film 102b and the oxynitride film 102c in the form is an oxynitride film (silicon oxynitride film) 102f. Other basic configurations are the same as those of the above-described embodiment.

  As shown in FIG. 8B, the nitrogen concentration of the oxynitride film 102f decreases from the boundary between the oxide film 102a and the oxynitride film 102f toward the boundary between the oxide film 102d and the oxynitride film 102f. Conversely, the oxygen concentration increases from the boundary between the oxide film 102a and the oxynitride film 102f toward the boundary between the oxide film 102d and the oxynitride film 102f. Note that the region where the oxynitride film 102f is formed is virtually composed of two regions, and a region where the nitrogen concentration is equal to or higher than a certain value (or the oxygen concentration is equal to or less than a certain value) corresponds to the second region 102f1, and A region where the concentration is lower than a certain value (or the oxygen concentration is higher than a certain value) corresponds to the fourth region 102f2.

  FIG. 9A is an energy band diagram at the time of charge erasing operation of the memory cell transistor of this modification, and FIG. 9B is a diagram after charge erasing of the memory cell transistor of this modification (at the time of charge holding). It is an energy band figure.

  As shown in FIG. 9A, during the charge erasing operation, as in the above-described embodiment, the barrier as shown in FIG. 3A is eliminated, so that the charge is stored without trapping holes in the potential well. It is injected into the insulating film 103. As a result, as in the first embodiment, saturation of the erasing characteristics due to hole traps is suppressed, and good erasing characteristics can be obtained.

  In addition, as shown in FIG. 9B, during charge retention, the oxynitride film 102f and the oxide film 102d function as a barrier against holes, so that deterioration of charge retention characteristics can be suppressed.

(Modification 2)
FIG. 10A is a cross-sectional view schematically showing the configuration of the tunnel insulating film 102. FIG. 10B shows the nitrogen concentration distribution in the nitride film 102b and the oxynitride film 102g.

  As shown in FIG. 10A, the present modification example includes an oxide film 102a (first region) and a nitride film 102b (second region) as in the above-described embodiment. A region that is the oxynitride film 102c and the oxide film 102d in the form is an oxynitride film (silicon oxynitride film) 102g. Other basic configurations are the same as those of the above-described embodiment.

  As shown in FIG. 10B, the nitrogen concentration of the oxynitride film 102g decreases from the boundary between the nitride film 102b and the oxynitride film 102g toward the boundary between the charge storage insulating film 103 and the oxynitride film 102g. Yes. Conversely, the oxygen concentration increases from the boundary between the nitride film 102b and the oxynitride film 102g toward the boundary between the charge storage insulating film 103 and the oxynitride film 102g. Note that the region where the oxynitride film 102g is formed is virtually composed of two regions, and a region where the oxygen concentration is equal to or higher than a certain value (or the nitrogen concentration is equal to or less than a certain value) corresponds to the third region 102g1, and the oxygen concentration The region where is lower than a certain value (or the nitrogen concentration is higher than the certain value) corresponds to the fourth region 102g2.

  FIG. 11A is an energy band diagram at the time of charge erasing operation of the memory cell transistor of the present modification, and FIG. 11B is a diagram after charge erasing of the memory cell transistor of the present modification (at the time of charge holding). It is an energy band figure.

  As shown in FIG. 11A, during the charge erasing operation, the barrier as shown in FIG. 3A disappears as in the above-described embodiment, so that holes are not trapped in the potential well and accumulated. It is injected into the insulating film 103. As a result, as in the first embodiment, saturation of the erasing characteristics due to hole traps is suppressed, and good erasing characteristics can be obtained.

  In addition, as shown in FIG. 11B, at the time of charge retention, the oxynitride film 102g functions as a barrier against holes, so that deterioration of charge retention characteristics can be suppressed.

(Modification 3)
FIG. 12A is a cross-sectional view schematically showing the configuration of the tunnel insulating film 102. FIG. 12B shows a nitrogen concentration distribution in the oxynitride film 102h.

  As shown in FIG. 12A, this modification has an oxide film 102a as in the above-described embodiment. In the above-described embodiment, the nitride film 102b, the oxynitride film 102c, and the oxide film 102d are formed. This region is an oxynitride film (silicon oxynitride film) 102h. Other basic configurations are the same as those of the above-described embodiment.

  As shown in FIG. 12B, the nitrogen concentration of the oxynitride film 102h decreases from the boundary between the oxide film 102a and the oxynitride film 102h toward the boundary between the charge storage insulating film 103 and the oxynitride film 102h. Yes. Conversely, the oxygen concentration increases from the boundary between the oxide film 102a and the oxynitride film 102h toward the boundary between the charge storage insulating film 103 and the oxynitride film 102h. Note that the region where the oxynitride film 102h is formed is virtually composed of three regions, and a region where the nitrogen concentration is equal to or higher than a certain value (or the oxygen concentration is equal to or less than a certain value) corresponds to the second region 102h1, and the oxygen concentration Is higher than a certain value (or the nitrogen concentration is lower than a certain value) corresponds to the third region 102h2, and the region between the second region 102h1 and the third region 102h2 is the fourth region. Corresponds to 102h3.

  FIG. 13A is an energy band diagram at the time of charge erasing operation of the memory cell transistor of this modification, and FIG. 13B is a diagram after charge erasing of the memory cell transistor of this modification (at the time of charge holding). It is an energy band figure.

  As shown in FIG. 13A, during the charge erasing operation, as in the above-described embodiment, the barrier as shown in FIG. 3A is eliminated, so that charges are accumulated without trapping holes in the potential well. It is injected into the insulating film 103. As a result, as in the first embodiment, saturation of the erasing characteristics due to hole traps is suppressed, and good erasing characteristics can be obtained.

  Further, as shown in FIG. 13B, at the time of charge holding, the oxynitride film 102h functions as a barrier against holes, so that deterioration of charge holding characteristics can be suppressed.

  In each of the above-described modified examples, the silicon nitride film formed on the oxide film 102a is oxidized by controlling the oxidation amount, so that FIG. 8B, FIG. 10B, and FIG. It is possible to form a silicon oxynitride film having a nitrogen concentration distribution as shown.

  Further, by controlling the oxidation temperature at the time of oxidation of the silicon nitride film formed on the oxide film 102a from a low temperature to a high temperature (700 degrees or more), (B in FIG. 2, FIG. 8, FIG. 10 and FIG. 12). ), (A), or (C), a silicon oxynitride film having a nitrogen concentration distribution can be formed.

  In the embodiment described above, the oxynitride film having a desired nitrogen concentration distribution is formed by oxidizing the nitride film. However, an oxynitride film having a desired nitrogen concentration distribution can be formed even by a manufacturing method using the ALD method. Below, an example of a formation method is demonstrated.

First, silicon of one atomic layer is formed using a Si source gas (for example, SiH ₂ Cl ₂ ). Next, active oxygen (for example, O ₂ radical, O radical, O _3, etc.) is supplied at a flow rate x to oxidize the silicon layer. Subsequently, a nitriding gas (for example, NH radical, NH ₃ or the like) is supplied at a flow rate y to nitride the silicon oxide film. Thereby, a silicon oxynitride film is formed. Then, a silicon layer for one atomic layer is formed on the oxynitride film, and the flow rate x and the flow rate y are appropriately changed, thereby forming an oxynitride film in which the nitrogen concentration and the oxygen concentration are changed. In this manner, by depositing an oxynitride film having a changed concentration until a desired film thickness is obtained, an oxynitride film having a desired nitrogen concentration distribution and oxygen concentration distribution can be formed.

In the above-described embodiment, the nitride film 102b is formed using the CVD method. However, the nitride film 102b may be formed by directly thermally nitriding the thick oxide film 102a in an ammonia gas atmosphere. Good. In this case, since the nitride film 102b contains hydrogen, the hole trap density decreases. Therefore, the erase saturation phenomenon can be further suppressed. Further, the nitride film 102b may be formed by directly nitriding the thick oxide film 102a with a plasma using a nitrogen-based gas containing hydrogen atoms, for example, NH ₃ gas. Note that the nitride film 102b may be formed by nitriding the oxide film 102a with plasma using a mixed gas of a rare gas and a nitriding gas. In the case of using plasma, nitridation at low temperature is possible, diffusion of nitrogen into the oxide film 102a is suppressed, and an increase in low electric field leakage current can be suppressed.

(Second Embodiment)
The second embodiment is a non-volatile semiconductor memory device having a three-dimensional structure using a three-dimensional stacking technology BiCS (Bit Cost Scalable).

  The basic configuration of the semiconductor device according to the second embodiment of the present invention will be schematically described with reference to FIGS.

  FIG. 14 is a diagram showing a configuration of a memory cell transistor according to the second embodiment of the present invention. FIG. 14A is a cross-sectional view along the channel length direction, and FIG. 14B is a perspective view.

  As shown in FIG. 14, a tunnel insulating film 202 is formed on the surface of a cylindrical semiconductor region (silicon region) 201, that is, around it. A charge storage insulating film 203 is formed on the surface of the tunnel insulating film 202, and a block insulating film 204 is formed on the surface of the charge storage insulating film 203. A control gate electrode 205 is formed on the surface of the block insulating film 204, and the block insulating film 204 and the control gate electrode 205 are covered with an interlayer insulating film 206.

  The tunnel insulating film 202 includes an oxide film (first region) 202a formed on the surface of the semiconductor region 201, a nitride film (second region) 202b formed on the surface of the oxide film 202a, and a nitride film. An oxynitride film (fourth region) 202c formed on the surface of 202b and an oxide film (third region) 202d formed on the surface of the oxynitride film 202c are provided.

  The oxide film 202a and the oxide film 202d are, for example, silicon oxide films containing silicon and oxygen as main components. The nitride film 202b is, for example, a silicon nitride film containing silicon and nitrogen as main components. The oxynitride film 202c is, for example, a silicon oxynitride film containing silicon, nitrogen, and oxygen as main components.

  The width of the memory cell transistor and the interval between adjacent memory cell transistors are both about 50 nm.

  FIG. 15 shows a structure in which memory cell transistors according to the second embodiment of the present invention are continuously provided in the vertical direction (channel long line direction). FIG. 15A is a cross-sectional view along the channel length direction, and FIG. 15B is a cross-sectional view along the direction perpendicular to the channel length direction.

  As shown in FIG. 15, the memory cell transistors described with reference to FIG. 14 are continuously stacked on a semiconductor substrate 200.

  FIG. 15 shows a case where two layers of memory cell transistors are formed, but any number of layers may be stacked as necessary.

  Similar to the first embodiment described above, in the tunnel insulating film 202 of this embodiment, the oxynitride film 202c is formed between the nitride film 202b and the oxide film 202d. Therefore, as in the first embodiment, holes are injected into the charge storage insulating film 203 without being blocked by a barrier, and holes are not trapped in the tunnel insulating film 202. For this reason, saturation of the erasing characteristics due to hole traps is suppressed, and good erasing characteristics can be obtained.

  Further, in this embodiment, as in the first embodiment, the oxynitride film 202c and the oxide film 202d function as a barrier against holes during charge retention, so that deterioration of charge retention characteristics can be suppressed. is there.

  As a result, in the present embodiment, it is possible to obtain a memory cell transistor having good charge erasing characteristics and charge holding characteristics, as in the first embodiment.

  A basic manufacturing method of the semiconductor device according to the second embodiment will be schematically described with reference to FIGS.

  15 to 18 are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIGS. 15A to 18A are cross-sectional views along the channel length direction, and FIGS. 15B to 18B are cross-sectional views along the direction perpendicular to the channel length direction.

  First, as shown in FIG. 16, a silicon oxide film having a thickness of about 50 nm to be the interlayer insulating film 206 and an impurity having a thickness of about 50 nm to be the control gate electrode 205 are formed on the surface of the semiconductor substrate 200 using the CVD method. Doped silicon films are alternately deposited a desired number of times. As the control gate electrode 205, for example, a metal material such as tantalum nitride may be used.

  Next, as shown in FIG. 17, the interlayer insulating film 206 and the control gate electrode 205 are selectively removed by RIE using a resist mask (not shown) to expose the semiconductor substrate 200. . As a result, a cylindrical groove 207 having a diameter of about 60 nm is formed in the laminated structure of the interlayer insulating film 206 and the control gate electrode 205. Thereafter, for example, an alumina film containing aluminum and oxygen having a thickness of about 10 nm to be the block insulating film 204 as main components is deposited on the inner wall of the groove 207 using the CVD method. The block insulating film 204 may be, for example, a silicon oxide film containing silicon and oxygen as main components.

Next, as shown in FIG. 18, a silicon nitride film having a thickness of about 5 nm to be the charge storage insulating film 203 is deposited by using the ALD method. Subsequently, a silicon oxide film having a thickness of about 4 nm is formed, the surface of the silicon oxide film is nitrided by about 1.5 nm by plasma using NH ₃ gas, and a silicon oxynitride film having a distribution in nitrogen concentration is formed. Form. Thereby, an oxide film 202d and an oxynitride film 202c are formed. Thereafter, a silicon nitride film having a thickness of about 2 nm is formed using the ALD method to form a nitride film 202b, and a silicon oxide film having a thickness of about 1.5 nm is formed using the ALD method to form the oxide film 202a. Thus, a tunnel insulating film 202 having a laminated structure including the oxide film 202a, the nitride film 202b, the oxynitride film 202c, and the oxide film 202d is formed.

  Next, as shown in FIG. 15, the block insulating film 204, the charge storage insulating film 203, the tunnel insulating film 202, and the semiconductor formed on the bottom surface of the trench 207 by RIE using a resist mask (not shown). The surface of the substrate 200 is selectively removed by etching. Thereafter, a silicon film doped with an impurity serving as a channel region is deposited by a CVD method, and the semiconductor region 201 is formed by performing heat treatment in a nitrogen atmosphere at about 600 ° C. Thereafter, a wiring layer or the like (not shown) is formed using a well-known technique to complete the nonvolatile semiconductor memory device.

  According to the second embodiment, by nitriding the silicon oxide film formed on the surface of the block insulating film 204, the oxynitride film 202c having a desired nitrogen concentration distribution can be formed.

  As a result, in the present embodiment, it is possible to obtain a memory cell transistor having good charge erasing characteristics and charge holding characteristics, as in the first embodiment.

  In the second embodiment described above, the tunnel insulating film 202 has a laminated structure including the oxide film 202a, the nitride film 202b, the oxynitride film 202c, and the oxide film 202d. However, similar to the modifications of the first embodiment, the same modification can be applied to the second embodiment.

  In the above-described embodiment, the oxynitride film having a desired nitrogen concentration distribution is formed by nitriding the oxide film. However, an oxynitride film having a desired nitrogen concentration distribution can be formed even by a manufacturing method using the ALD method. Below, an example of a formation method is demonstrated.

First, silicon of one atomic layer is formed using a Si source gas (for example, SiH ₂ Cl ₂ ). Next, active oxygen (for example, O ₂ radical, O radical, O _3, etc.) is supplied at a flow rate x to oxidize the silicon layer. Subsequently, a nitriding gas (for example, NH radical, NH ₃ or the like) is supplied at a flow rate y to nitride the silicon oxide film. Thereby, a silicon oxynitride film is formed. Then, a silicon layer for one atomic layer is formed on the oxynitride film, and the flow rate x and the flow rate y are appropriately changed, thereby forming an oxynitride film in which the nitrogen concentration and the oxygen concentration are changed. In this manner, by depositing an oxynitride film having a changed concentration until a desired film thickness is obtained, an oxynitride film having a desired nitrogen concentration distribution and oxygen concentration distribution can be formed.

In the second embodiment described above, the oxide film formed on the surface of the block insulating film 204 is nitrided using plasma to form the oxynitride film 202c. However, the nitride film 202b is formed using the ALD method. At the time of formation, the oxynitride film 202c may be formed at the same time. Examples of the formation method include plasma nitridation using a nitriding gas such as NH ₃ or thermal nitridation with heat of 700 ° C. before the nitride film 202b is formed. In this case, since the oxynitride film 202c and the nitride film 202b can be continuously formed without being exposed to the atmosphere, a silicon oxide film is not formed between the oxynitride film 202c and the nitride film 202b. An increase in the pore energy barrier is prevented. Therefore, the erase saturation phenomenon can be further suppressed.

  In an actual nonvolatile semiconductor memory device, a plurality of memory cell transistors are arranged in the word line direction and the bit line direction. A typical example of the nonvolatile semiconductor memory device described above is a NAND nonvolatile memory having a configuration in which a plurality of memory cell transistors connected in series are provided between select transistors.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as long as a predetermined effect can be obtained.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is the figure which showed the nitrogen concentration distribution of the tunnel insulating film which concerns on the 1st Embodiment of this invention. It is an energy band figure of the tunnel insulating film which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure which showed nitrogen concentration distribution of the tunnel insulating film which concerns on the modification 1 of the 1st Embodiment of this invention. It is an energy band figure of the tunnel insulating film which concerns on the modification 1 of the 1st Embodiment of this invention. It is the figure which showed nitrogen concentration distribution of the tunnel insulating film which concerns on the modification 2 of the 1st Embodiment of this invention. It is an energy band figure of the tunnel insulating film which concerns on the modification 2 of the 1st Embodiment of this invention. It is the figure which showed nitrogen concentration distribution of the tunnel insulating film which concerns on the modification 3 of the 1st Embodiment of this invention. It is an energy band figure of the tunnel insulating film which concerns on the modification 3 of the 1st Embodiment of this invention. It is sectional drawing which showed typically the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate 102 ... Tunnel insulating film 102a ... Silicon oxide film 102b ... Silicon nitride film 102c ... Silicon oxynitride film 102d ... Silicon oxide film 103 ... Charge storage insulating film 104 ... Block insulating film 105 ... Control gate electrode 106 ... Interlayer insulation Film 107 ... Isolation insulating film 200 ... Semiconductor substrate 201 ... Semiconductor region 202 ... Tunnel insulating film 202a ... Silicon oxide film 202b ... Silicon nitride film 202c ... Silicon oxynitride film 202d ... Silicon oxide film 203 ... Charge storage insulating film 204 ... Block Insulating film 205 ... Control gate electrode 206 ... Interlayer insulating film

Claims (5)

A semiconductor region, a tunnel insulating film formed on the surface of the semiconductor region, a charge storage insulating film formed on the surface of the tunnel insulating film, a block insulating film formed on the surface of the charge storage insulating film, A control gate electrode formed on the surface of the block insulating film, and a semiconductor device comprising:
The tunnel insulating film is formed on the surface of the semiconductor region and includes a first region containing silicon and oxygen as main components, and is formed on the surface of the first region and contains silicon and nitrogen as main components. A second region, a third region formed on the back surface of the charge storage insulating film, containing silicon and oxygen as main components, and formed between the second region and the third region; And a fourth region containing silicon, nitrogen and oxygen, having a nitrogen concentration lower than the nitrogen concentration in the second region, and having an oxygen concentration lower than the oxygen concentration in the third region. A semiconductor device characterized by the above.   The nitrogen concentration in the fourth region decreases from a boundary between the second region and the fourth region toward a boundary between the third region and the fourth region. Item 14. A semiconductor device according to Item 1.   The nitrogen concentration in the second region and the fourth region decreases from the boundary between the first region and the second region toward the boundary between the third region and the fourth region. The semiconductor device according to claim 1.   The oxygen concentration in the fourth region and the third region increases from the boundary between the second region and the fourth region toward the boundary between the charge storage insulating film and the third region. The semiconductor device according to claim 1. A semiconductor region, a tunnel insulating film formed on the surface of the semiconductor region, a charge storage insulating film formed on the surface of the tunnel insulating film, a block insulating film formed on the surface of the charge storage insulating film, A control gate electrode formed on the surface of the block insulating film,
The tunnel insulating film is formed on the surface of the semiconductor region and includes a first region containing silicon and oxygen as main components, and is formed on the surface of the first region and contains silicon and nitrogen as main components. A second region, a third region formed on the back surface of the charge storage insulating film, containing silicon and oxygen as main components, and formed between the second region and the third region; A semiconductor containing silicon, nitrogen and oxygen, having a nitrogen concentration lower than the nitrogen concentration of the second region and having an oxygen concentration lower than the oxygen concentration of the third region; A device manufacturing method comprising:
The step of forming the fourth region is performed by depositing an insulating film to be the fourth region between the step of forming the second region and the step of forming the third region. A method for manufacturing a semiconductor device.

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