JP2010141721A - A-d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a sufficient accuracy even if there is great variations in frequency characteristics among signal paths. <P>SOLUTION: Each of a plurality of first estimation means 22 estimates a value between a sample value and a next sample value of a respective one of a plurality of A-D converters 12 using sample values of the other A-D converters, and provides the estimated value and the sample values in chronological order to a respective one of a plurality of first equalizers 23 to compensate a difference among signal paths, and the output value of the first equalizer 23 is output from a first signal switch 24. Because estimation processing by a second estimation means 30 and correction processing by a second equalizer 31 are performed on the signals output from the first signal switch 24 and the output values of the second equalizer 31 are sequentially selected, more accurate A-D conversion processing can be done. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention provides an interleaving method for equivalently performing high-speed sampling on an input signal by commonly inputting an analog input signal to a plurality of A / D converters and shifting the sampling timing of each A / D converter. The present invention relates to a technique for improving the accuracy of the A / D converter.

  FIG. 11 shows the basic configuration of the interleaved A / D converter 10, and FIG. 12 shows its operation.

This A / D converter 10 branches an analog input signal x (t) as shown in FIG. 12A input to an input terminal 10a into a plurality of N signal paths by a signal distributor 11. , N pieces of A / D converters 12 _{0 to} 12 _N−1 are respectively input.

As shown in (b1) to (bN) of FIG. 12, the sampling controller 13 has sampling periods C _{0 to} C _N each having a period T and having a phase shifted by ΔT (= T / N). ₋₁ are generated and given to the A / D converters 12 _{0 to} 12 _N−1 , respectively, and sampling is performed among the A / D converters 12 _{0 to} 12 _N−1 as shown in FIG. A designation signal ADNUM that designates the A / D converter to be performed is supplied to the signal switch 14.

Each A / D converter 12 _{0 to} 12 _N−1 samples input values x (P), x (P + 1), x (P + 2),... When receiving the clocks C _{0 to} C _N−1. Are converted into digital values, and the sample values X0 _{, P} , X1 _{, P + 1} , X2 _{, P + 2} ,... Are output to the signal switcher 14 as shown in (c1) to (cN) of FIG.

The signal switch 14 includes sample values X _{0, P} , X _{1, P + 1} output from the A / D converter designated by the designation signal ADNUM among the A / D converters 12 _{0 to} 12 _{N− 1} . X _{2, P + 2, ...} are sequentially selected, as (e) in FIG. 12, the sample value is output to the output terminal 10b of the digital signal sequence Y (n) arranged in the sampling order.

  The digital signal sequence Y (n) thus obtained is equivalent to that obtained by sampling the input signal x (t) at a sampling period ΔT that is 1 / N of the clock period T, and is low-speed A / D conversion. High-speed sampling can be performed with the instrument.

However, when the input signal x (t) is distributed and input to the plurality of A / D converters 12 _{0 to} 12 _{N−1 as} in the A / D conversion apparatus 10, the distribution characteristics and distribution of the signal distributor 12 itself are distributed. Due to the difference in the frequency characteristics of the path, the difference in the frequency characteristics of each of the A / D converters 12 _{0 to} 12 _N−1 and the deviation from the ideal timing of the sampling clock, an error is generated in the result of signal processing of the obtained sample value Let

  As a technique for solving this problem, the applicant of the present application performs an equalization process (equalization process) for equalizing the frequency characteristics of the signal paths from the input terminal to each A / D converter by eliminating the difference. (Patent Document 1).

Japanese Patent No. 3756237

  In the technique of Patent Document 1, since the sampling period of each A / D converter is long with respect to the signal frequency, and equivalent processing cannot be performed only with the sample value, apparent sampling of each A / D converter is performed. Equivalent processing is performed by increasing the period. The value between the sample value of each A / D converter and the next sample value is estimated using the sample value of another A / D converter, and the estimation is performed. The difference between each signal path is compensated by giving the value and the sample value to the equalizer in time series.

  However, even in the A / D conversion device having the above-described configuration, sufficient accuracy may not be obtained when there is a large variation in the frequency characteristics of each signal path, and higher accuracy processing has been desired.

  The present invention has been made to solve this problem, and an object of the present invention is to provide an A / D conversion device with higher accuracy.

In order to achieve the above object, the A / D conversion device of the present invention includes:
An input terminal (10a) for inputting a signal;
A plurality of A / D converters (12);
A signal distributor (11) for inputting an input signal from the input terminal to the A / D converter;
Sampling that gives a clock of a predetermined cycle for sampling to each A / D converter in a predetermined order and cyclically with a time difference substantially equal to the time obtained by dividing the predetermined period by the number of A / D converters. A control unit (21);
Each of the frequency characteristics from the input terminal to the output terminal of each A / D converter with one of the plurality of A / D converters as a reference, and the output of the reference A / D converter from the input terminal An AD characteristic table (25) that stores in advance the coefficients of a filter having an impulse response that satisfies the characteristic of the difference from the frequency characteristic up to the terminal;
The A / D receiving the clock based on a sample value provided for each A / D converter and converted and output by the plurality of A / D converters and a coefficient stored in the AD characteristic table A plurality of first estimating means (22) for respectively estimating sample values obtained on the assumption that another A / D converter performs a conversion process at a timing when the converter updates the sample value;
An equalizer coefficient table (27) preliminarily storing coefficients of a filter having an impulse response that satisfies a frequency characteristic that cancels out a difference in frequency characteristic between the reference A / D converter and each A / D converter;
Each of the first estimating means is provided corresponding to each of the first estimating means, and the output value of each first estimating means is subjected to filtering based on the coefficient stored in the equalizer coefficient table, and the error is corrected. A plurality of first equalizers (23) each outputting a value;
A first signal switch that receives the output values of the plurality of first equalizers, and selects and outputs the output values of the plurality of first equalizers in the order in which the A / D converters sample with the clock. 24)
Based on the coefficient provided corresponding to each of the first equalizers and stored in the AD characteristic table, the signal output from the first signal switcher is opposite to that of the corresponding equalizer. A plurality of second estimation means (30) for performing frequency correction processing and replacing the data of the sampling timing of the corresponding A / D converter with the original sample value among the data obtained by the correction processing. )When,
The coefficient stored in the equalizer coefficient table is processed for correcting the difference in the frequency characteristics of the signal path from the input terminal to each A / D converter with respect to the output value of each second estimating means. A plurality of second equalizers (31) to perform based on;
Second signal selection means (32) which receives the output value of each of the second equalizers and selects and outputs the output values of the plurality of second equalizers in the order in which each of the A / D converters samples with the clock. ).

  Thus, in the present invention, the estimation process by the second estimation unit and the correction process by the second equalizer are performed on the signal output from the first signal switch, and the output of the second equalizer is output. Since the values are sequentially selected, it is possible to perform A / D conversion processing with higher accuracy.

First, a technique that is a premise of the present invention will be described.
First, an arbitrary one of the N A / D converters 12 is defined as a reference A / D converter, and an input from the input terminal to the A / D converter is provided for each A / D converter. The frequency characteristics are calculated by combining the characteristics, conversion characteristics, and phase error characteristics of the sampling system, the difference between each frequency characteristic and the frequency characteristic of the reference A / D converter is obtained, and this is defined as the mismatch characteristic. .

  Further, the input signal x (t) handled in the present invention is band-limited from 0 to Fs / 2, where Fs (= 1 / ΔT) is a high-speed sampling frequency realized using N A / D converters. Suppose that

Next, a mismatch circuit having each mismatch characteristic is inserted in the front stage of each A / D converter, and its frequency characteristic is defined as H _i (ω) (i = 0, 1,..., N−1). further, define the equalizing characteristic G _{i (ω)} of the virtual equalizer to cancel each mismatch characteristics H _{i (ω).}

Here, when the input / output signal is band-limited to a frequency range of 0 to Fs, when the continuous system is replaced with a discrete system represented by a sampling period ΔT (= 1 / Fs), the mismatch characteristic H _i (omega) and mismatch characteristics shown equalizing characteristic _{G i} (omega) and the equivalent output characteristics _H ^{i * (ω)} and the equalizing characteristic _G ^{i * (ω)} thinking, the impulse response _{h i} corresponding to these characteristics _{, U} and g _{i, k} are calculated by the following equation. Note that the lengths u and k of the impulse train are adjusted with necessary accuracy.

G _i ^* (ω) = 1 / H _i ^* (ω) (1)
h _{i, u} = F ⁻¹ {H _i ^* (ω)} (2)
g _{i, k} = F ⁻¹ {G _i ^* (ω)} (3)
However, i = 0, 1,..., N
The symbol F ⁻¹ indicates a discrete Fourier inverse transform operation

Here, based on the A / D converter 12 _0, consider the equivalent circuit of FIG.

Each A / D converter ₁₂ 1 _{to 12 N-1,} since the mismatch component to A / D converter 12 ₀ of the reference is converted to a mismatch circuit characteristics, as shown in the equivalent circuit of FIG. 1, the input signal x (t) is the reference of the a / D converter 12 ₀ conversion characteristics 110 in signal x is converted into a discrete system (n), passing through the mismatch circuits ₁₁₂ 0 to 112 _n-1 for each a / D converter This is equivalent to the case where A / D conversion is performed by ideal A / D converters 130 _{0 to} 130 _N−1 having no error.

Further, digital values sequentially output from the ideal A / D converters 130 _{0 to} 130 _N−1 are respectively input to the virtual equalizers 131 _{0 to} 131 _N−1 and defined for each individual A / D converter. After the equivalent processing is performed by the equalizer (defined by the impulse response g _{i, k} ), the sample values Y (n) are output from the virtual equalizers 131 _{0 to} 131 _N−1 .

  In the following, in order to simplify the explanation, it is assumed that the reference A / D conversion characteristic 110 transmits the input signal as it is to the output, but this characteristic may be corrected as necessary. .

In the above equivalent circuit, if the length u of the impulse train representing the frequency characteristics of the mismatch circuits 112 _{0 to} 112 _N−1 is equally expressed by U, the input x _{i of the} ideal A / D converters 130 _{0 to} 130 _{N−1 , N} are expressed by the following equations.

x _{i, n} = _u Σx (n−u) · h _{i, u} (4)
However, i = 0, 1,..., N−1
The symbol _u Σ indicates the sum of u = − (U−1) to (U−1).

Here, if equal to the sampling timing of the A / D converters _{12 0-12} sampling timing _N-1 and the ideal A / D converter ₁₃₀ 0 to 130 DEG _N-1, the ideal A / D converter ₁₃₀ 0 ~ 130 _N−1 performs A / D conversion processing on the input values x _{i, n} at a period T, and then converts the sample values to virtual equivalents 131 _{0 to} 131 _N− according to the sampling timing of each A / D converter. since output to _1, the ideal a / if D converter 130 ₀ outputs the P-th sample value, sample values are output to the n-th is expressed by the following equation J (n) th ideal a / It is output from the D converter.

x _{J (n), n} = _u Σx (n−u) · h _{J (n), u} (5)
The symbol _u Σ indicates the sum of u = − (U−1) to (U−1).

Where J (n) is a positive value modulo N;
J (n) = n-P mod (N)
It expresses.

That is, each ideal A / D converter outputs data to the virtual equalizer every N (period T seconds) for the input values x _{i, n} .

If the ideal A / D converter outputs a sample value every ΔT, the value x _{i, n} output from the mismatch circuit is input to the virtual equalizer as it is, and the virtual equivalent Since the corresponding equalizer inside the unit works to correct the characteristics of the mismatch circuit by definition, if the coefficient is determined so that the calculation delay of the mismatch circuit and the equalizer becomes zero, the input value x (n) Sample values Y (n) having the same value as N are output from the _N virtual equalizers 131 _{0 to} 131 _N−1 .

When it is assumed that the ideal A / D converter outputs a sample value for each ΔT, the processing by the equalizers in the virtual equalizers 131 _{0 to} 131 _N−1 is an equalizer determined for each corresponding A / D converter. Is determined by the following equation using the impulse responses g _{i, k} .

Y (n) = _k Σx _{J (n), nk} · g _{J (n), k} (6)
Here, K indicates the length of the impulse train of the equalizer, and the symbol _k Σ indicates the sum total from k = − (K−1) to K−1.

Here, in order for the above equation (6) to hold, all values for k = − (K−1) to K−1 are necessary for x _{J (n), nk} , Each A / D converter can output only every N values as described above.

  Therefore, the sample value required for equalization is estimated using the sample value of the other A / D converter, and then the equivalent operation processing of Expression (6) is performed.

Further, among the n-th output candidates calculated by the virtual equalizers 131 _{0 to} 131 _N−1 , from the J (n) -th virtual equivalent (when the delay due to the calculation is 0) from which the error is minimized The output is output as a sample value Y (n).

Here, in order to estimate the J (n) th A / D conversion result, A / D conversion outputs x _{J (n−r), n−r−k} other than the J (n) th.
However, r ≠ q × N (q: 0, ± 1, ± 2, ...)
Consider the case of.

  In this case, the (n−r−P) mod (N) th A / D converter has the n−rth value, and the n−rth input value x (n−r) by definition. Is equal to the equalized output value Y (n−r), and the following equation is established.

x (n−r) = Y (n−r)
= _K Σx _{J (n−r), n−r−k} · g _{J (n−r), k} (7)
However, the symbol _k sigma, k = - shows the sum up to (K-1) ~K-1

Also, in equation (4), an estimated sample value x obtained on the assumption that the ideal A / D converter has shifted the sampling timing and the J (n) th A / D converter has performed the nr-th sampling. _{J (n) and n−r} are obtained as follows.

x _{J (n), nr} = _u Σx (n−r−u) · h _{J (n), u} (8)
However, the symbol _u Σ indicates the sum of u = − (U−1) to U−1.

By substituting Equation (7) into Equation (8) above, estimated sample values x _{J (n), nn} are obtained, and the processing of Equation (6) is performed on the obtained estimated sample values. Thus, an output value y (n) by N A / D converters can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 shows a configuration of an interleaved A / D conversion apparatus 20 according to the embodiment based on the above-described prerequisite technology.

In FIG. 2, an input terminal 10a, a signal distributor 11, N A / D converters 12 _{0 to} 12 _N-1 and an output terminal 10b are the same as the A / D converter 10 described above, and therefore have the same reference numerals. A description will be given.

In the A / D conversion device 20, similarly to the A / D converter 10 described above, an analog input signal x (t) input to the input terminal 10 a is put into a plurality of N signal paths by the signal distributor 11. The N signals x ₀ (t) to x _N−1 (t) that are branched and have substantially the same frequency characteristics are respectively input to the A / D converters 12 _{0 to} 12 _N−1 .

Further, sampling clocks C _{0 to} C _N−1 whose phases are shifted by ΔT (= T / N) time in cycle T are generated from sampling control unit 21, and A / D converters 12 _{0 to} 12 _N are respectively generated. ₋₁ and sampling of the input signal is performed by each of the A / D converters 12 _{0 to} 12 _N−1 .

The sampling control unit 21 generates the clocks C _{0 to} C _N-1 based on a sampling timing signal (hereinafter simply referred to as a timing signal) Ct having a period ΔT, and in accordance with the timing of the timing signal Ct, A designation signal ADNUM that designates an A / D converter for updating the A / D conversion result (sample value) is supplied to first estimation means 22 _{0 to} 22 _N−1 , first signal switcher 24, second, which will be described later. output to the estimator ₃₀ 0 _{~30 N-1} and the second signal switching device 32.

The outputs of the A / D converters 12 _{0 to} 12 _N−1 are respectively input to _{N first} estimating means 22 _{0 to} 22 _N−1 .

Each of the first estimation means 22 _{0 to} 22 _N−1 receives the outputs of _N A / D converters 12 _{0 to} 12 _N−1 and the designation signal ADNUM from the sampling control unit 21.

Each of the first estimating means 22 _{0 to} 22 _N−1 is based on the inputted N sample values, the designation signal ADNUM, and the coefficient of the AD characteristic table 25 described later at every timing indicated by the timing signal Ct. A number E determined by a predetermined estimated value calculation process (E = 1 or more when an estimated value is obtained using three sampling points, and E = when an estimated value is obtained using one sampling point) A sample value is estimated when it is assumed that the A / D converter performs a sampling operation at the previous sampling timing (which is 0 or more).

  For example, when estimation is performed using three sampling points, the number of the A / D converter having the updated sample value is a (ADNUM = a), and a positive number b modulo N, c is obtained by the following equation.

b = a-1 mod (N) (11a)
c = a-2 mod (N) (11b)

When i = b, the estimated sample value W _{i, n} is
W _{i, n} = x _{b, n} (12a)
And

When i ≠ b, the estimated sample value W _{i, n} is obtained by the following calculation.

W _{i, n} = x _{b, n} · h _{i, 0} / h _{b, 0}
+ X _{a, n} · (hi _{, 0} / h _{a, 0} )
* {(Hi _{, -1} / hi _{, 0} )-( _{hb, -1} / _{hb, 0} )}
+ _{Xc, n.} (Hi _{, 0} / _{hc, 0} )
-{(Hi _{, 1} / hi _{, 0} )-( _{hb, 1} / _{hb, 0} )}
(12b)

In the above formulas, h _{i, −1} , h _{i, 0} , h _{i, 1} are coefficients stored in advance in an AD characteristic table 25 described later. The first term of the above formula (12b) is a term mainly related to the amplitude error, and the second and third terms are terms mainly related to the phase error.

The estimated sample values W output from the first estimating means 22 are respectively input to the first equalizers 23 ₀ to 23 _N−1 .

Each of the first equalizers 23 ₀ to 23 _N−1 performs an equivalent operation process on the input estimated sample value W using a coefficient (filter coefficient) stored in an equalizer coefficient table 27 described later. As a result, that is, the sample value y corrected for error with respect to the reference A / D converter is output to the first signal switch 24 at the timing indicated by the timing signal Ct.

The first signal switching unit 24 receives the sample values output from the equalizers 23 ₀ to 23 _N−1 , and is a value specified by the designation signal ADNUM (here, ADNUM = a), a number determined by the estimated value calculation process. E and a value e for designating an equalizer using an offset value a0 determined when defining the equalizer coefficient table 27,
e = a−E−a0 mod (N)
The output result y _{e, n} of the e-th equalizer 23e is selected for the value a designated by the designation signal ADNUM, and output as the final AD conversion result Y (n).

  The obtained A / D conversion result is obtained by delaying the sampling timing by E + a0 from the theoretical calculation by the estimated value calculation process.

On the other hand, in the AD characteristic table 25, a reference A for the frequency characteristic from the input terminal 10a to the output terminal of each A / D converter when considering a discrete system represented by a sampling period ΔT (= T / N). The equalizer coefficient determined by the impulse response corresponding to the difference H _i ^* (ω) in frequency characteristics from the / D converter is stored in advance as the required number of points. The number of points of this equalizer coefficient includes not only the three points used in the first estimating means 22 but also more than that used in the second estimating means 30 described later.

In order to obtain the impulse response, the difference characteristic H _i ^* (ω) of the frequency characteristic is changed from the frequency characteristic HO ^* (ω) for the reference A / D converter and each A / D converter 120 _{0 to} 12 _{N−. 1} is calculated from the frequency characteristic HO _i ^* (ω) for 1 by the following equation. The characteristic of the difference is a ratio as follows in the calculation.

H _i ^* (ω) = HO _i ^* (ω) / HO ^* (ω) (13)

Next, an FIR filter having an impulse response equivalent to the frequency characteristic H _i ^* (ω) is designed within a range that satisfies the sampling theorem. However, when designing a filter having an equivalent impulse response, each filter is designed after arbitrarily setting an absolute delay amount τ0 (seconds) common to all N filters to be designed.

When the obtained filter coefficients are expressed in order of time series, ..., hi _{, -1} , hi _{, 0} , hi _{, 1} , ... (where i = 0, 1, 2, ..., N-1). The absolute delay amount τ0 is the sum of the squares of the coefficients Σ (h _{i, −1} ) ² when the absolute value of the coefficient h _{i, 0} is maximized and the coefficients of the N FIR filters to be designed are taken into account. And Σ (h _{i, 1} ) ² are set so that the absolute delay amount τ 0 is substantially equal.

Next, a minimum value U1 that satisfies | _{hi, U1} | <ε (where ε is a predetermined allowable error) is determined from the obtained coefficients, and similarly, | hi _{, U2} 3 is determined using the coefficient sequence h _{i, U1} ,..., H _{i, −1} , h _{i, 0} , h _{i, 1} ,..., H _{i, U2} . The AD characteristic table 25 shown in FIG.

The AD characteristic table 25, for example, a table position (i, -1) _{h i} to _{the -1} and _{h i, 0} is the table position (i, 0), the table position (i, 1) h _{Let i, 1} correspond.

On the other hand, the equalizer coefficient table 27 calculates the frequency characteristic G _i ^* (ω) by the following expression based on the frequency characteristic difference H _i ^* (ω) calculated by the above-described expression (13).

G _i ^* (ω) = 1 / H _i ^* (ω) (14)
However, H _i ^* (ω) ≠ 0

In the range that satisfies the sampling theorem, an equalizer (filter) having an impulse response equivalent to the frequency characteristic G _i ^* (ω) is defined as an equalizer corresponding to the i-th A / D converter, and is required for the equalizer. Filter coefficients to be obtained are prepared in the equalizer coefficient table 27 in advance. However, when designing a filter having an equivalent impulse response, each filter is designed after setting an absolute delay τ1 (seconds) common to all N filters to be designed.

When the obtained filter coefficients are expressed in order of time series,..., G _{i, −1} , g _{i, 0} , g _{i, 1} ,..., The set value of the absolute delay amount τ1 common to all filters is arbitrary. However, in the design of the equalizer coefficient table 27 _, the absolute value of the coefficient g _{i, 0} is maximized, and the sum of squares of the N filter coefficients to be designed Σ (g _{i, −1} ) ² and Σ (g _{i , 1} ) The absolute delay amount τ1 is set so that ² is substantially equal.

Next, a minimum value M1 that satisfies | g _{i, M1} | <ε (where ε is a predetermined allowable error) is determined from the obtained coefficients, and in the same manner, | g _{i, M2} 4 is determined using the coefficient sequence g _{i, M1} ,..., G _{i, −1} , g _{i, 0} , g _{i, 1} ,..., G _{i, M2} . Thus, the equalizer coefficient table 27 is created. In this case, for example, the table position (i, M1) is associated with gi _{, M1} , the table position (i, M1 + 1) is associated with hi _{, M1 + 1} , and thereafter, similarly, the table position (i, M2) is sequentially handled. Let

  At this time, the offset value a0 = 1 (which varies depending on the absolute delay amount of the constituent circuit) is determined in accordance with the time response of the first estimating means 22 and the first equalizer 23 to be designed.

  Next, the operation of the A / D converter 20 up to the first signal switch 24 will be described with reference to FIGS.

Figure 5 (a) input terminal 10a is input to the input signal x (t) as is, the signal distributor 11 is branched into the signal path of the N, the A / D converters ₁₂ 0 _{to 12 N- 1} is input.

Each of the A / D converters 12 _{0 to} 12 _N−1 receives the clocks C _{0 to} C ₁₂ output from the sampling control unit 21 as shown in (b1) to (bN) of FIG. The A / D conversion processing for the input signals x ₀ (t) to x _N-1 (t) is sequentially performed at a timing delayed by approximately ΔT time, and sample values X _{0, P 1,} X ₁ obtained by the conversion processing are sequentially performed _{. P + 1} ,..., _{XN−1, P + N−1} are output as shown in (c1) to (cN) of FIG.

Here, numbered in order of sampling timing, P th in the sampling, A / D converter 12 ₀ is defined to have updated its sample value by performing A / D conversion processing, the sample value is the updated X _Let it be expressed as _{0, P.}

At this time, the sampling control unit 21, as shown in (d), (e) in FIG. 5, in accordance with the update timing of the A / D conversion results to specify the A / D converter 12 ₀ updating the sample value A designation signal ADNUM (for example, ADNUM = 0) and a timing signal Ct indicating sampling timing for the input signal are output.

Since the other A / D converters 12 _{1 to} 12 _N−1 do not update the conversion result, the values held before the P-th sampling is performed are output.

That is,
X1 _{, P} = X1 _{, P-1} , X2 _{, P} = X2 _{, P-1} ,...
X _{N-1, P} = X _{N-1, P-1}
It becomes.

The following P + 1-th sampling timing, ADNUM = 1, and the sample values of the A / D converter 12 ₁ is updated, the other A / D converters _{12 0,} 12 2 _{to 12 N-1} is, P th The same value as that at the sampling timing is output.

Thereafter, similarly, the conversion processing by each of the A / D converters 12 _{0 to} 12 _N−1 is sequentially performed, and after the sample value of the _N− 1th A / D converter 12 _N−1 is updated, 0 again. th update of the sample value by the a / D converter 12 ₀ is performed, the operations are repeated cyclically.

As described above, each of the first estimating means 22 _{0 to} 22 _N−1 is updated with the sample value when it is assumed that the A / D converter whose sample value has not been updated has sampled at that timing. Estimate using the sample value.

For example, in the case N is 3 or more, looking for the first estimation means 22 ₀ one, as shown in FIG. 6, the timing at which the sample values P + 1 th by the A / D converter 12 ₁ is updated, For each A / D converter, the P-th sample value can be estimated at the previous sampling timing. As the first estimator 22 ₀ of P-th estimated sample value _{W 0, P,} from the A / D converter 12 ₀ already has a sample value _{X 0, P,} and outputs the value as it is. That is, this corresponds to the case of i = b = 0 in the formula (12a).

Also, the next P + 2-th estimated sample value W at the sampling timing _{0, P + 1} is the sample value X _{2, P + 2} of the updated sampling timing the A / D converter 12 _2, the previous sampling timing Using the sample values X _{1 and P + 1} , the sample value X _{0 and P at the} previous sampling timing _, and the coefficients of the AD characteristic table 25, the calculation shown in the case of i ≠ b in the equation (12b) Calculate according to the formula.

Furthermore, the next P + 3 th estimated sample value W at the sampling timing _{0, P + 2} includes a sample value X _{3, P + 3} of the A / D converter 12 ₃ that have been updated on the sampling timing, the previous sampling timing Using the sample values X _{2 and P + 2} , the sample values X _{1 and P + 1 at the} previous sampling timing, and the coefficients of the AD characteristic table 25, the calculation shown in the case of i ≠ b in the equation (12b) Calculate according to the formula.

The following have been made the same estimation process, the estimated sample values sample sequence arranged in time series _{W 0, P, W 0,} P + 1, ... are output to the first equalizer 23 _0.

Similar estimation processing is performed for the other first estimation means 22 _{1 to} 22 _N−1 , and the estimated sample values W _{m, P} , W _{m, P + 1} ,... (M = 1, 2,..., N−1). ) Are output to the first equalizers 23 ₁ to 23 _N−1 , respectively.

The first equalizers 23 ₀ to 23 _N−1 perform an equivalent process (filtering) on the input estimated sample values W using the coefficients of the equalizer coefficient table 27, and the frequency characteristics of the reference A / D converter .., (I = 0, 1,..., N−1) are output to the first signal switcher 24, respectively, as sample values y _{i, P} , y _{i, P + 1} ,.

  The first signal switch 24 corresponds to the A / D converter designated by the designation signal ADNUM at a timing shifted by the offset value e with respect to the designation signal ADNUM designating the A / D converter. The output values of the first equalizer 23 are sequentially selected, and a digital signal sequence Y (n) in which the selected values are arranged in time series is output.

The thus obtained A / D conversion result Y (n), each A / D converter ₁₂ 0 actually obtained sample values _{to 12 N-1} of the conversion process and the first estimation means 22 The error is corrected by the first equalizers 23 ₀ to 23 _{N−1 for} each of the sample strings including the sample values estimated and calculated in step 1, so that the frequency between the A / D converters including the signal distributor 11 and the wirings The influence of errors due to characteristic differences can be significantly reduced.

In addition, among the sample trains output from the first equalizers 23 ₀ to 23 _N−1, the first signal switch 24 selects the sample value with the least error obtained at the same sampling timing. Therefore, analysis errors due to time waveform analysis and frequency spectrum can be greatly improved.

  However, as described above, when there is a large variation in the frequency characteristics of each signal path, sufficient accuracy may not be obtained, and higher accuracy processing has been desired.

  FIG. 7A shows a spectrum generated from data obtained by sampling with a conventional interleaved A / D converter having eight A / D converters, and the horizontal axis represents the entire apparatus. This is a frequency normalized by 1/2 of the sampling frequency fs, and is a result when a sine wave signal having a frequency of about 0.19 is given.

On the other hand, in the configuration using the first estimating means 22 _{0 to} 22 _N-1 , the first equalizers 23 ₀ to 23 _N-1 and the first signal switch 24 described above, (b) of FIG. As described above, spurious can be significantly reduced, but the SFDR (spurious free dynamic range) is only about -70 dB.

Therefore, in this embodiment, as shown in FIG. 2, a plurality of second estimating means 30 ₀ to 30 _N−1 , a plurality of second equalizers 31 _{0 to} 31 _N−1 and a second signal switcher. 32 is provided to realize a more accurate A / D conversion device.

Here, as shown in FIG. 8, the second estimation means 30 ₀ to 30 _N−1 are provided corresponding to the first equalizers 23 ₀ to 23 _N−1 , respectively, and the AD characteristic table 25. , H _{i, −1} , h _{i, 0} , h _{i, 1} ,..., H _{i, U2} are output from the first signal switcher 24 based on the coefficients h _{i, U1} ,. Of the correction processing unit 30a that performs frequency correction processing opposite to each of the first equalizers 23 ₀ to 23 _N−1 corresponding to the signal sequence Y (n), and among the data sequence Q obtained by the correction processing, A data replacement unit 30b that replaces the sampling timing data Q (k) of the corresponding A / D converter with the original sample value X (k) based on the designation signal ADNUM. By performing such processing, it is possible to obtain an estimated value with higher accuracy (with less error) than the estimation results obtained by the first estimating means 22 _{0 to} 22 _N−1 .

Then, with respect to the estimated value W ′ with less error, the second equalizer 31 _{0 to} 31 _N−1 configured in the same manner as the first equalizer 23 ₀ to 23 _N−1 described above is connected from the input terminal 10a. The processing for correcting the difference in the frequency characteristics of the signal paths from the respective A / D converters 12 _{0 to} 12 _N−1 is performed based on the coefficients stored in the equalizer coefficient table 27, and correction processing by these equalizers is performed. The obtained output values z _{0 to} z _N−1 are given to the second signal switch 32, and a plurality of second equalizers 31 _{0 in} the order in which the A / D converters 12 _{0 to} 12 _N−1 sample with the clock. select to 31 output values _z 0 _{~z N-1} of _N-1, and outputs.

The spurious characteristic of the digital signal sequence Z (n) obtained in such a configuration is (c) in FIG. 7, and the second estimating means 30 ₀ to 30 _N−1 and the second equalizer 31 ₀ to By using 31 _N-1 and the second signal switcher 32, SFDR could be improved to about -90 dB.

  FIG. 9 and FIG. 10 show the simulation results for obtaining the sampling waveform of one A / D converter and the error of each part for a sine wave signal having a constant amplitude.

9A is the sampling value, FIG. 9B is the output error of the first estimating means 22, FIG. 9C is the output error of the first equalizer 23, and FIG. 9D. Is an output error of the first signal switch 24, and the maximum value of the error at this point is approximately 10 ⁻³ V (1 mV).

10A shows the output error of the second estimating means 30, FIG. 10B shows the output error of the second equalizer 31, and FIG. 10C shows the second signal switcher. 32 output errors, that is, the final output error of the A / D converter 20 of the present embodiment, the maximum value thereof is approximately 10 ⁻⁴ V (0.1 mV), which is improved by approximately 20 dB like the above-described spectrum. You can see that

The figure for demonstrating the premise technique of this invention The figure which shows the structure of embodiment of this invention Table of the main part of the embodiment Table of the main part of the embodiment Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment The figure which shows the characteristic of embodiment Configuration diagram of the main part of the embodiment The figure which shows the output error of each part of embodiment The figure which shows the output error of each part of embodiment Diagram showing the basic configuration of the interleaved conventional device Operation explanatory diagram of conventional equipment

Explanation of symbols

  10a: input terminal, 10b: output terminal, 11: signal distributor, 12: A / D converter, 20: A / D converter, 21: sampling controller, 22: first Estimating means 23... First equalizer 24... First signal switcher 25... AD characteristic table 27 .. Equalizer coefficient table 30. Equalizer, 32 …… Second signal selector

Claims (1)

An input terminal (10a) for inputting a signal;
A plurality of A / D converters (12);
A signal distributor (11) for inputting an input signal from the input terminal to the A / D converter;
Sampling that gives a clock of a predetermined cycle for sampling to each A / D converter in a predetermined order and cyclically with a time difference substantially equal to the time obtained by dividing the predetermined period by the number of A / D converters. A control unit (21);
Each of the frequency characteristics from the input terminal to the output terminal of each A / D converter with one of the plurality of A / D converters as a reference, and the output of the reference A / D converter from the input terminal An AD characteristic table (25) that stores in advance the coefficients of a filter having an impulse response that satisfies the characteristic of the difference from the frequency characteristic up to the terminal;
The A / D receiving the clock based on a sample value provided for each A / D converter and converted and output by the plurality of A / D converters and a coefficient stored in the AD characteristic table A plurality of first estimating means (22) for respectively estimating sample values obtained on the assumption that another A / D converter performs a conversion process at a timing when the converter updates the sample value;
An equalizer coefficient table (27) preliminarily storing coefficients of a filter having an impulse response that satisfies a frequency characteristic that cancels out a difference in frequency characteristic between the reference A / D converter and each A / D converter;
Each of the first estimating means is provided corresponding to each of the first estimating means, and the output value of each first estimating means is subjected to filtering based on the coefficient stored in the equalizer coefficient table, and the error is corrected. A plurality of first equalizers (23) each outputting a value;
A first signal switch that receives the output values of the plurality of first equalizers, and selects and outputs the output values of the plurality of first equalizers in the order in which the A / D converters sample with the clock. 24)
Based on the coefficient provided corresponding to each of the first equalizers and stored in the AD characteristic table, the signal output from the first signal switcher is opposite to that of the corresponding equalizer. A plurality of second estimation means (30) for performing frequency correction processing and replacing the data of the sampling timing of the corresponding A / D converter with the original sample value among the data obtained by the correction processing. )When,
The coefficient stored in the equalizer coefficient table is processed for correcting the difference in the frequency characteristics of the signal path from the input terminal to each A / D converter with respect to the output value of each second estimating means. A plurality of second equalizers (31) to perform based on;
Second signal selection means (32) which receives the output value of each of the second equalizers and selects and outputs the output values of the plurality of second equalizers in the order in which each of the A / D converters samples with the clock. A / D conversion device.

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