JP2010140151A - Multi-processor and state control method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of reducing electric power while properly performing processing across a plurality of processors. <P>SOLUTION: The multi-processor has: local resource control sections 506, 509 on processor elements 401, 402; and a global resource control section 512. If a task on the processor element 402 ends ahead of schedule, the global resource control section 512 determines whether to stop it in response to a stop request from the local resource control section 509. As a result, the local resource control section 509 stops the processor element 402. If the task (MODL2) on the processor element 402 is required by the task (MODL1) on the other processor element 401, the local resource control section 506 issues a boot request, and the global resource control section 512 starts the processor element 402 and the task (MODL2) through the local resource control section 509. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control method for dynamically changing a clock frequency and a voltage value in accordance with task progress in a multiprocessor. In particular, in order to reduce power consumption, not only the clock frequency or voltage value is changed, but also when a certain processor is changed to the sleep state, that is, the clock stopped state or the power-off state, this state change The present invention relates to a technique that is effective when applied to a processor state and task control method that allows the operation of the application to operate without contradiction.

  In recent years, in an embedded system, speeding up by a single processor has reached the limit due to the limit of frequency improvement by miniaturization and the improvement of power caused by the frequency improvement. In response to this situation, various companies are investigating a technique for speeding up the processing by parallel processing using a multiprocessor.

  Multiprocessors have been developed for large computers and personal computers, but the multiprocessor is a technology related to symmetric multiprocessors in which the role of the processor for software processing (hereinafter referred to as tasks) and memory is equivalent. is there. On the other hand, the multiprocessor handled in the present invention relates to an asymmetric multiprocessor that distributes tasks to the right place for an embedded system. In many cases, the memory space is also individual.

  Since the asymmetric multiprocessor has an advantage of good processing efficiency, a method of controlling the frequency and voltage value according to the progress of the task is effective in order to further enhance the advantage. For example, Patent Document 1 is an example of such a control method although not on a multiprocessor.

  By the way, the most effective control for reducing the power consumption is to stop the processor clock or cut off the voltage.

  Such a sleep state or stop state is one of the abnormal states of the processor, and a technique for notifying this abnormal state to the control of the entire multiprocessor is also disclosed in, for example, Patent Document 2. In this prior art, after notification, it is only determined whether to continue or stop.

  Further, Patent Document 3 relates to a method for dynamically changing task processor assignment, but this conventional technique does not consider changing the processor state.

The control of the processor state handled in the present invention needs to be started again when it is necessary to execute a task on the processor according to the progress of the application after a while after sleep or power is stopped. An object of the present invention is to provide such a processor state control method.
JP 2002-202893 A JP 2005-346328 A JP 2007-133723 A

  By the way, in the above-described conventional technology, after the processor is put into sleep or powered off, it is impossible to perform control for starting the processor according to the progress of the application after a while. This problem is solved in the present application. That is, if a processor is in a sleep state or a stop state, and the task on the other processor is not informed of this fact, when the next task to be executed is in the sleep processor, the task is started without starting the processor. Because it tries to start, it does not execute correctly. It is necessary to restart the processor before starting the task.

  In addition, it is necessary to always know when the processor is required next to determine whether or not the processor can enter the sleep state. If this determination is not possible, the transition cannot be made.

  To determine whether or not the processor is activated or in sleep mode, keep track of the progress of all the processors on which the task is mounted, and maintain the order relationship between tasks even if the initial schedule is incorrect. Thus, it is necessary to determine and change whether or not the processor state can be changed.

  Therefore, the present invention has an object to provide such control, and an object of the present invention is to provide a technique for realizing low power while normally performing processing over a plurality of processors.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In other words, the outline of a representative one is that a local state that grasps the progress of a task on the processor on each processor (processor element) and issues a sleep / power stop request of the processor according to the progress of the task. Global resource control that monitors the progress of all tasks on other multiprocessors on the resource control unit and the overall management processor (task control processor element) and controls the processor state based on requests from individual processors Part.

  In this configuration, when the second task is mounted on another processor based on a request for starting another second task from the first task on the processor, the local resource control unit A request to start the second task is issued to the resource control unit. Then, the global resource control unit sends a sleep or power stop request from the local resource control unit of each processor, and a second task on another second processor from the local resource control unit of a certain first processor. An activation request is accepted. Further, for the former request, the sleep / power supply stoppage determination is performed and the determination result is returned to the processor. When the second processor is in the sleep / power supply stop state, the local resource of the second processor is returned. A request for restart and a request for starting the second task are sent to the control unit.

  For example, a first local resource control unit on a first processor element to which a first task is assigned; a second local resource control unit on a second processor element to which a second task is assigned; In a multiprocessor having a global resource control unit, when a task on the second processor element is completed earlier than scheduled, the global resource control unit receives a request to stop the second processor element from the second local resource control unit. Determine whether or not to stop. In response to the result, the second local resource control unit stops the second processor element. If the second task on the second processor element requires a task on another first processor element, the first local resource control unit of the first processor element globally issues the second task activation request. Issued to the resource control unit, the global resource control unit activates the second processor element and the second task via the second local resource control unit.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, the effect obtained by the representative one can provide a technique for realizing low power while normally performing processing across a plurality of processors.

  Hereinafter, representative embodiments according to the present invention will be described in detail with reference to the drawings. Note that in all the drawings for describing the embodiments, the same reference numerals and symbols represent the same or similar elements, and repeated description thereof is omitted.

  In the following, two embodiments will be described, but since the hardware configuration and the software configuration are common to both, the common portions will be described first. After that, the control of shifting the task flow and the processor to the sleep state when there is no interrupt from outside the LSI is described as the first embodiment, and then the case where there is an interrupt from outside the LSI as the second embodiment. State the flow.

<Parts common to 1 embodiment>
As a part common to the embodiments, a system configuration using a multiprocessor, an example application, a system LSI configuration, and a software installation location will be described with reference to FIGS.

  FIG. 2 shows a configuration diagram of a system using a multiprocessor. In this system, audio data compressed from the hard disk (HDD) 205 is input to the system board 201 through the connector 204, then decoded through the multiprocessor chip (MPCHIP) 200, and then the audio controller (AUDC) 207. Audio digital data is converted into audio data, and the audio is reproduced by the headphones 209 through the connector 208.

  On the system board 201, in addition, a crystal oscillator (OSC) 202 for transmitting a clock, a flash memory (FLSH) 203 for storing a program, and a dynamic random access memory for storing intermediate data for executing processing, etc. (DRAM) 206 is mounted.

  The terminals of the multiprocessor chip (MPCHIP) 200 will be described. 210 is a clock input terminal (CL), 211 is a multi-bit data terminal (B1), 214 is a multi-bit data terminal (B2), 212 is an HDD interface terminal (HIF) with the HDD, and 213 is a DRAM interface with the DRAM. Terminal (DR).

  FIG. 3 shows a data processing flow of an application and an audio decoder as examples in the embodiment.

  The frame data (FD-In) 310 is input from the hard disk (HDD) 205, and the software module (MODL1) 308 performs an error check on the data, and then decomposes the frame data into data of a plurality of subbands for each frequency band. To do. Thereafter, information called side information is acquired for each subband, and inverse quantization is performed based on this information. Thereafter, the software module (MODL2) 306 synthesizes the decoding results for each subband and performs a process called a filter bank. Finally, the processing result (FD-Ou) 309 for each frame is output to the headphones 209.

  FIG. 4 shows a block diagram of a multiprocessor chip (MPCHIP) 200 on which an application is mounted.

  In the multiprocessor chip (MPCHIP) 200, the processor elements that manage application processing are a first processor element (CPU 1) 401 and a second processor element (CPU 2) 402. There is a task control processor element (SCPU) 404 to manage overall resource control. In addition, a shared memory (CM) 406, an interrupt controller (IntC) 408, a timer (Tim) 409, and a clock generator (CKGEN) 403 connected to a clock input terminal (CL) 210 are required. There is a bus arbiter (BUS_ARB) 405 for internal processing that performs input / output control of signals that connect them, and there is a peripheral bus 414 for managing peripheral input / output, an input / output path from the peripheral bus 414, and a peripheral bus There is a peripheral bus controller (PBC) 407 that performs control.

  As modules connected to the peripheral bus 414, an HDD interface controller (HIFC) 410 that controls an HDD interface through an interface terminal (HIF) 212, a DRAM controller (DRC) 411 that controls a DRAM through a DRAM interface terminal (DR) 213, and a data terminal There are a data controller (B1C) 412 that controls data signals through (B1) 211 and a data controller (B2C) 413 that controls data signals through data terminals (B2) 214.

  In FIG. 4, the clock generator (CKGEN) 403 is shown as a component for changing or stopping the clock frequency, but a circuit for stopping the potential supply for controlling the power is not shown, but the present invention is not described. The control method described in the above section is omitted because it is essentially the same regardless of the state transition to sleep or the transition to potential supply stop.

  FIG. 5 shows a block diagram of an example in which the application and control software shown in FIG. 3 are installed in the multiprocessor of FIG. In FIG. 5, the following is omitted from the peripheral bus controller (PBC) 407 serving as an input / output path.

  In the audio decoder of FIG. 3, the soft module (MODL1) 308 is mounted on the first processor element (CPU1) 401, and the soft module (MODL2) 306 is mounted on the second processor element (CPU2) 402. Each processor element observes the progress status of the task mounted on each processor element, and changes the clock frequency of the processor element according to the progress status, or stops the clock to change to and return to the sleep state. As the control unit, there is a local resource control unit (LRCL) 506 corresponding to the first processor element 401 and a local resource control unit (LRCL) 509 corresponding to the second processor element 402. Specifically, the sleep state is a state in which the supply of the clock is stopped, and the clock generator (CKGEN) 403 controls the clock.

  As other components for transitioning to the sleep state, on the processor state register (PReg) 501 and the task control processor element (SCPU) 404, the transition request to the sleep state from the local resource control units (LRCL) 506 and 509 And a global resource control unit (CRCL) 512 that determines whether or not transition is possible. Real-time OSs (RTOS) 507, 510 and 513 that directly manage hard resources for the local resource control unit and the audio decoder are also constituent elements. Other constituent elements not shown in FIG. 3 include a local memory (LM) 502 and the like.

<2 First Embodiment: Control for Setting Processor to Sleep>
In the first embodiment, the control to put the processor in the sleep state will be described. First, as preparation, the flow of task processing by a plurality of processors will be described according to FIG. 6 in Section 2.1, and the sleep in Section 2.2. As an example in which the state is required, a flow when the task is completed earlier than the budget time will be described with reference to FIG. Finally, in Section 2.3, the flow for changing the processor to the sleep state and returning to the original state will be described with reference to FIGS.

<< 2.1 Task Processing Flow by Software Pipeline: Fig. 6 >>
In FIG. 6, a process for executing the audio decoder of FIG. 3 by a software pipeline with a task as a processing unit is shown in a Gantt chart. Resources are listed in the vertical direction, and the time axis is shown in the horizontal direction.

  In FIG. 6, in accordance with the flow shown in FIG. 3, frame data (FD-In) 310 is input from the hard disk (HDD) 205, and the software module (MODL1) 308 as the first task is transferred to the first processor element (CPU1). ) 401, the second module soft module (MODL2) 306 is processed by the second processor element (CPU2) 402, and finally the processing result (FD-Ou) 309 for each frame is supplied to the headphones (HP). To 209.

  These flows are executed in a pipeline manner. That is, for the first frame data (FD-In1) 3101, when the processing of the software module (MODL 1) 3081 ends in the processor element (CPU 1) 401, the result is displayed as the software module (MODL 2) 3061 as indicated by 601. In parallel with the processing by the processor element (CPU2) 402, the processing of the soft module (MODL1) 3082 is processed by the processor element (CPU1) 401 for the second frame data (FD-In2) 3102. That is, a parallel operation by a multiprocessor is performed.

  Similarly, for the first frame data, the processing of the software module (MODL2) 3061 ends in the processor element (CPU2) 402 and is output as the processing result (FD-Ou1) 3091. The processor element (CPU2) 402 executes the processing of the software module (MODL2) 3062 for the second frame data. This is also a parallel operation.

  Finally, the processing of the software module (MODL2) 3062 is completed on the processor element (CPU2) 402 for the second frame data, and the result is output as the processing result (FD-Ou2) 3092.

<< 2.2 Processing flow when task finishes earlier than scheduled: Fig. 7 >>
FIG. 7 shows an example when the soft module (MODL2) 3061 ends earlier than the scheduled time in the parallel operation 601 of FIG. At this time, the processor element (CPU 2) 402 does not do anything in the section indicated by 702 for the time (IntT) 701 and waits for the next processing.

  For this section 702, the processor element (CPU2) 402 is set in the sleep state to reduce power. In order to return to the normal state again after entering the Sleep state, it is necessary to devise the control. This control will be described below.

<< 2.3 Flow of Transitioning Processor to Sleep State: FIGS. 1 and 8 >>
A flow for transitioning to the sleep state and then returning to the normal state from the sleep state will be described with reference to FIGS.

  First, according to FIG. 1, the flow of processing after the task is completed earlier than planned by the software module (MODL2) 3061 in FIG. 7 will be described below.

  The software module (MODL2) 3061 notifies the local resource control unit (LRCL) 509 that it has passed the checkpoint (CP1) 4020 just before the task is finished. In response to this notification, the local resource control unit (LRCL) 509 recognizes that the task is being completed at a time earlier than scheduled in the progress grasping process 4021. Therefore, in step 4022, the task control processor element (SCPU) 404 is requested to shift the processor element (CPU2) 402 to the sleep state in order to reduce power consumption.

  In response to the sleep request, the global resource control unit (CRCL) 512 on the task control processor element (SCPU) 404 determines whether or not the sleep is possible in the process 102. return. In response to this, the local resource control unit (LRCL) 509 changes the processor element (CPU 2) 402 to the sleep state 4025 in a process 4024, and the state variable (CPU_S) 101 of each processor element on the shared memory (CM) 406. , The value of the state variable (CPU2_S) 1010 of the processor element (CPU2) 402 is rewritten to a value indicating the sleep state.

  After that, when the software module (MODL1) 3082 on the processor element (CPU1) 401 approaches the end for the second frame in FIG. 7, the processor element (CPU2) 402 returns to the normal state, and the software module (MODL2) ) 3062 needs to be executed.

  Therefore, in FIG. 1, when the local resource control unit (LRCL) 506 is notified that the software module (MODL1) 3082 on the processor element (CPU1) 401 has passed the checkpoint (CPa) 4010, the local resource control unit In step 4011, the progress is grasped in step 4011, and if it is determined from the remaining time of the software module (MODL1) 3082 that it is necessary to start the next process, the software module (MODL2) 3062, the step 103 starts. A request is made to the task control processor element (SCPU) 404.

  In response to this activation request, the global resource control unit (CRCL) 512 on the task control processor element (SCPU) 404 receives the state variable (CPU2_S) 1010 of the processor element (CPU2) 402 that executes the software module (MODL2) 3062. Whether or not it is necessary to start up the processor element (CPU 2) 402 is determined in process 104 based on the value. In this case, since it is in the sleep state, activation is necessary, and activation is requested in processing 4029.

  In response to the activation request of the processor element (CPU2) 402, the processor element (CPU2) 402 returns to the normal state in processing 4026, and the local resource control unit (LRCL) 509 is activated. (MODL2) 3062 is activated to enter the Running state, and waits for data from the software module (MODL1) 3082.

  Next, the flow of the processing 102 for determining whether or not the sleep is possible in FIG. 1 will be described with reference to FIG.

  In step 802, it is determined whether the sleep target processor (processor element (CPU2) 402 in FIG. 1) does not accept an external interrupt or can be set to be unacceptable for the time being. Here, the external interrupt is set to be unacceptable for the time being. . In order to accept an external interrupt (described later in the second embodiment), it is necessary to consider the influence on task scheduling and the task deadline, and this determination is made by the global resource control unit (CRCL) 512. . If this is OK (Y), go to Step 803, and if it is NG (N), Sleep is not possible (Step 805).

  In step 803, the time until the sleep target processor is next required is determined from the task Gantt chart of this task in step 807 (in this example, FIG. 7), and whether IntT is equal to or longer than the sleep and return treatment time R_IntT. Judging. That is, it is a determination as to whether or not there is sufficient time to realize Sleep. If this is OK (Y), Sleep is possible (step 804), and if NG (N), Sleep is not possible (step 805).

  In step 806, the sleep determination result determined in steps up to step 805 is returned to the target processor in process 4028 of FIG.

<< Effects of First Embodiment >>
According to the first embodiment, the local resource control units (LRCL) 506 and 509, the global resource control unit (CRCL) 512, and the like are provided. The global resource control unit 512 includes the local resource control units 506 and 509. Receives a request to change the processor element to the stopped state, determines whether the change to the stopped state is possible, instructs the local resource control unit that requested the state to change, and controls the state of the processor element can do.

  For example, the local resource control unit (LRCL) 506 controls the first processor element (CPU1) 401 that executes the first task, and the local resource control unit (LRCL) 509 executes the second task. When controlling the processor element (CPU2) 402, it is necessary to restart the second task to be executed next to the first task after the processor element (CPU2) 402 that executes the second task is stopped. Is determined based on a request from the local resource control unit 506, a restart request is issued to the processor element (CPU 2) 402 based on this determination, and then the second task is set to the running state. Can return to. Similarly, when the first processor element (CPU1) 401 that executes the first task is restarted from the stopped state, the first task can be returned to the running state.

  Therefore, in order to reduce power consumption, even if a certain processor element is sleeped or the power is stopped, it can be operated in cooperation with a task on another processor element, and an application can be operated without any contradiction in the entire multiprocessor. That is, in a situation where an application is processed by a plurality of processor elements, when a certain task is completed earlier than scheduled, the application can be operated without hindering normal operation. As a result, it is possible to realize low power consumption while normally performing processing across a plurality of processors.

  In addition, when the external interrupt is not accepted and it is set to be unacceptable for the time being, the time interval until the time when the task on the processor element needs to be executed next is the time when the processor element is stopped and then returned. By determining that it is possible to change to the stopped state when the total time required is longer, it is possible to execute task cooperation and overall operation of the application without contradiction.

<3 Second Embodiment: Task Scheduling when an External Interrupt is Entered>
An external interrupt is a dynamic request that cannot be predicted before execution that requests a change in the initial task scheduling, like a sleep request.

  In this case, the overall management is performed by the global resource control unit (CRCL) 512 as in the case of the Sleep request. However, unlike the Sleep request, during the time until the interruption is completed, all tasks are shifted to the wait state, and scheduling is performed so that the Gantt chart of the task shown in FIG.

  According to the second embodiment, in addition to the effects of the first embodiment, even when an external interrupt is received, an external interrupt is entered in order to perform control while always grasping the progress. Even if the overall progress may be out of sync with the scheduled time, the task linkage and the overall operation of the application can be executed without contradiction.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a control method for dynamically changing a clock frequency and a voltage value in accordance with task progress in a multiprocessor. In particular, not only the clock frequency and voltage value are changed to reduce power consumption, but also when a certain processor is changed to the sleep state, this state change causes the entire application to operate consistently. And can be used as a method for controlling tasks.

It is a Gantt chart showing the execution procedure of the transition to a Sleep state which is one embodiment of the present invention, and a return. It is a block diagram which shows the system using the multiprocessor which is one embodiment of this invention. It is a figure which shows the data processing flow of the application and audio decoder which are performed on the multiprocessor which is one embodiment of this invention. It is a block diagram which shows the multiprocessor chip | tip which is one embodiment of this invention. FIG. 5 is a block diagram illustrating an example in which the application and control software of FIG. 3 according to an embodiment of the present invention are mounted on the multiprocessor of FIG. 4. FIG. 4 is a Gantt chart showing a process of executing the audio decoder of FIG. 3 according to an embodiment of the present invention by a software pipeline with a task as a processing unit. FIG. 7 is a Gantt chart showing an example of processing when a task is completed earlier than scheduled in FIG. 6 according to an embodiment of the present invention. It is a flowchart which shows the process of judgment of the sleep availability of FIG. 1 which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 200 ... Multiprocessor chip 201 ... System board 202 ... Crystal oscillator 203 ... Flash memory 204 ... Connector 205 ... Hard disk 206 ... Dynamic random access memory 207 ... Audio controller 208 ... Connector 209 ... Headphone 210 ... Clock input terminal 211 ... Data terminal 212 ... HDD interface terminal 213 ... DRAM interface terminal 214 ... Data terminal 306 ... Soft module 308 ... Soft module 309 ... Processing result 310 ... Frame data 401 ... Processor element 402 ... Processor element 403 ... Clock generator 404 ... Task control processor element 405 ... Bus arbiter 406 ... Shared memory 407 ... Peripheral bus control unit 408 ... Interrupt Controller 409 ... timer 410 ... HDD interface controller 411 ... DRAM controller 412 ... data controller 413 ... data controller 414 ... peripheral bus 501 ... processor status register 502 ... local memory 506 ... local resource control unit 507 ... Real-Time OS
509 ... Local resource control unit 510 ... Real-time OS
512 ... Global resource control unit 513 ... Real-time OS

Claims (6)

A multiprocessor including a first processor element, a second processor element, and a task control processor element that controls execution of the first processor element and the second processor element;
In a software process that repeatedly executes a second task next to a first task, the first task is assigned to the first processor element, and the second task is assigned to the second processor element. When allocating and executing,
A first local resource control unit that determines a progress status of the first task and controls a state of the first processor element on the first processor element;
A second local resource control unit that controls a state of the second processor element by determining a progress status of the second task on the second processor element;
On the task control processor element, a request to change the processor element to the stop state is received from the first local resource control unit and the second local resource control unit, and it is determined whether or not the change to the stop state is possible. And a global resource control unit that instructs the local resource control unit that has made the request whether or not to change the state,
The first local resource control unit and the second local resource control unit control the state of the first processor element or the second processor element based on the instruction from the global resource control unit. Multiprocessor characterized by. The multiprocessor according to claim 1, wherein
After the second processor element that executes the second task is stopped,
Based on a request from the first local resource control unit, the global resource control unit determines that the second task to be executed next to the first task needs to be started again. The global resource control unit issues a restart request to the second processor element based on the restart request, restarts the second processor element based on the restart request, and then sets the second task to a running state. Multiprocessor characterized by returning. The multiprocessor according to claim 1, wherein
The global resource control unit receives a request to change to the stopped state, and determines whether to change to the stopped state.
The time interval until the time at which the first or second task on the first or second processor element needs to be executed next is determined as being unacceptable for external interrupts or not when requested. A multiprocessor according to claim 1, wherein when the first or second processor element is in a stopped state and is longer than a total time required for returning, the multiprocessor determines that the change to the stopped state is possible. A multiprocessor state control method including a first processor element, a second processor element, and a task control processor element that controls execution of the first processor element and the second processor element,
In a software process that repeatedly executes a second task next to a first task, the first task is assigned to the first processor element, and the second task is assigned to the second processor element. When allocating and executing,
A first local resource control unit that determines a progress status of the first task on the first processor element and controls a state of the first processor element;
A second local resource control unit that determines a progress status of the second task on the second processor element to control a state of the second processor element;
The global resource control unit receives a request to change the processor element from the first local resource control unit and the second local resource control unit to the stopped state on the task control processor element, and enters the stopped state. To determine whether or not to change the state, instruct the local resource control unit that made this request whether to change the state,
The first local resource control unit and the second local resource control unit control the state of the first processor element or the second processor element based on the instruction from the global resource control unit. A multiprocessor state control method. The multiprocessor state control method according to claim 4.
After the second processor element that executes the second task is stopped,
Based on a request from the first local resource control unit, the global resource control unit determines that the second task to be executed next to the first task needs to be started again. The global resource control unit issues a restart request to the second processor element based on the restart request, restarts the second processor element based on the restart request, and then sets the second task to a running state. A multiprocessor state control method characterized by returning. The multiprocessor state control method according to claim 4.
The global resource control unit receives a request to change to the stopped state, and determines whether to change to the stopped state.
The time interval until the time at which the first or second task on the first or second processor element needs to be executed next is determined as being unacceptable for external interrupts or not when requested. A multiprocessor state control method, comprising: determining that a change to a stop state is possible when the total time required for the first or second processor element to stop and return thereafter is longer.

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