JP2010135900A - Ofdm demodulator, ofdm demodulation method, ofdm demodulation program, and computer readable recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an OFDM demodulator for precisely correcting a frequency error without enlarging a circuit scale. <P>SOLUTION: The OFDM demodulator 1 receives digital broadcast wave and samples it on the basis of a clock signal of a frequency oscillator different from that of a broadcast station. A delay profile peak position detection part 15 detects a peak position of differential output of complex correlation strength. A clock frequency error detection part 16 detects a frequency error on the basis of a difference between a peak position in the (n-1)th cycle and a peak position in the n-th cycle. A PLL 19 changes an operation clock on the basis of a frequency error from the clock frequency error detection part 16 and corrects the frequency error. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a receiving apparatus and a receiving method for a signal transmitted by a digital transmission method, and more particularly, an orthogonal frequency division multiplexing (hereinafter, abbreviated as OFDM) that can efficiently transmit a video signal and an audio signal. The present invention relates to a demodulation device, an OFDM demodulation method, a program, and a computer-readable recording medium.

  The terrestrial digital broadcast is a broadcast performed by a digital radio station, and is characterized in that the received video has high image quality and high sound quality, and that information can be transmitted and received bidirectionally.

  Various technologies have been applied to realize the characteristics of high image quality and high sound quality, and one of them is multicarrier, which is a suitable modulation method for overcoming ghost interference such as fading or multipath. OFDM modulation / demodulation schemes are listed. Here, the ghost obstruction is a phenomenon that occurs mainly due to a building or the like and adversely affects image quality, sound quality, or the like.

  The OFDM modulation / demodulation scheme has a feature that a large number of orthogonal subcarriers are used to transmit and receive information. Specifically, it is a digital modulation / demodulation method in which a large number (about 256 to 1024) of subcarriers are provided in one channel band and video signals and audio signals can be efficiently transmitted. The broadcast station generates a baseband (BB) signal in which all carriers are OFDM-modulated by inverse fast Fourier transform (IFFT) and transmits the generated signal on a broadcast wave.

  In this way, since the OFDM modulation / demodulation method distributes information to a large number of subcarriers and transmits the information, it is possible to restore correct information by error correction even if the information of some subcarriers cannot be correctly reproduced by multipath. it can.

  In addition, the OFDM modulation / demodulation method adds a signal of a certain time interval, called a guard interval, to a valid symbol to form a transmission symbol, thereby preventing interference for each symbol and reducing multipath degradation. There are features.

FIG. 24 is a diagram illustrating a configuration of a symbol signal included in the OFDM signal. As shown in FIG. 24, an actual transmission symbol is usually configured by adding a period t _g called a guard interval (GI) 202a to an effective symbol period 201. The waveform of the GI period t _g (202a) is obtained by repeating the signal waveform of the rear part 202b of the effective symbol period t _u . The symbol period 203 of the transmission symbol is the sum of the effective symbol period 201 and the GI period 202a. For example, according to the broadcast standard described in Non-Patent Document 1, the effective symbol period length is defined as shown in Table 1 below by a parameter called MODE.

  Further, the GI period (unit: μs) is defined as shown in Table 2 below by a parameter called GI period length (GI ratio) which is a ratio to each effective symbol period length.

  A collection of several transmission symbols is called a transmission frame. This is a collection of about 100 information transmission symbols plus frame synchronization symbols and service identification symbols. For example, in Non-Patent Document 1, one frame is defined as 204 symbols.

  As described above, various techniques for overcoming ghost interference have been incorporated into the OFDM modulation / demodulation system. In order to maintain better reception, for example, the operating clock frequency of the reference broadcast station and the receiver It is necessary to accurately measure the error from the operation clock frequency of the receiver and feed it back to the reception system so that the operation clock frequency of the receiver is as close as possible to the operation clock frequency of the broadcasting station.

  Patent Document 1 discloses an OFDM demodulator including a clock frequency error detection circuit that calculates a clock frequency error. This OFDM demodulator calculates the guard correlation signal, which is the strength of the complex correlation between the OFDM time domain signal and the delayed signal delayed by the symbol period, and detects the amount of change in the intensity peak timing value of the guard correlation signal with respect to the time axis. Thus, the clock frequency error is detected. FIG. 25 is a block diagram of the guard correlation / peak detection circuit in the OFDM demodulator described in Patent Document 1. In FIG. The guard correlation / peak detection circuit includes a delay circuit 31, a complex conjugate circuit 32, a complex multiplication circuit 33, a moving sum circuit 34, an amplitude calculation circuit 35, an angle conversion circuit 36, a free-running counter 37, a peak A detection circuit 38 and an output circuit 39 are provided.

  By the way, since the OFDM demodulator disclosed in Patent Document 1 receives both the main wave and the delayed wave when multipath or frequency selective fading occurs, the time of the intensity peak timing value of the guard correlation signal When detecting the amount of change with respect to the axis, the amount of change between the intensity peak timing value of the guard correlation signal of the main wave and the intensity peak timing value of the guard correlation signal of the delayed wave may be detected. The amount of change detected in this case may be significantly different from the amount of change in the intensity peak timing value of the guard correlation signal detected for the same wave, and is not an appropriate value.

Therefore, although it is necessary to detect the clock frequency error using only the change amount of the intensity peak timing value of the guard correlation signal detected for the same wave, the OFDM demodulator disclosed in Patent Document 1 This is done by detecting the amount of change of the intensity peak with respect to the time axis using the detection interval, and detecting the clock frequency error using the most appropriate value (for example, the mode value of the amount of change). Is realized.
"Transmission method for digital terrestrial television broadcasting ARIB STD-B31 1.5 edition", the radio industry, the first edition of May 31, 2001, revised version 1.5 on July 29, 2003 Japanese Patent Application Laid-Open No. 2004-214962 (published July 29, 2004)

  However, in the conventional configuration, when the multipath occurs and the electric field intensity ratio between the direct wave and the delayed wave approaches 1: 1, the intensity peak timing of the detected guard correlation signal is the intensity peak of the main wave guard correlation signal. It takes an intermediate value between the timing and the intensity peak timing of the guard correlation signal of the delayed wave. For this reason, even if the amount of change of the intensity peak timing with respect to the time axis is detected using a plurality of different periods as long as it is detected in a short period, it takes various values each time it is detected. Therefore, for example, even if the clock frequency error is detected using the mode value of the change amount, the detected clock frequency error is not accurate because the mode value of the change amount is not always an appropriate value of the change amount. Not necessarily.

  Also, in an environment where the delay profile changes frequently, the intensity peak timing value of the guard correlation signal changes frequently, and the clock frequency error is detected by detecting the amount of change of the intensity peak timing with respect to the time axis with a small number of samples. Is difficult to do.

  Therefore, in order to accurately detect the clock frequency error using the change amount of the intensity peak timing of the guard correlation signal in the conventional configuration, it is necessary to detect using a large number of samples over a long period of time. Then, there arises a problem that the circuit scale of the OFDM demodulator increases.

  In particular, in a multipath environment in an urban area, or in an SFN (Same Frequency Network) environment in which a plurality of broadcasting stations transmit the same broadcast on the same channel, the problem that it takes a long time to detect a frequency error has also become clear. Yes.

  The present invention has been made in view of the above problems, and an object of the present invention is to detect an error between its own reception frequency and broadcast wave frequency in a short time without increasing the circuit scale. An object of the present invention is to realize an OFDM demodulator, an OFDM demodulation method, a control program, and a computer-readable recording medium.

  In order to solve the above-described problems, an OFDM demodulator according to the present invention receives an OFDM signal including a transmission symbol having a valid symbol and a guard interval, and generates a received sample sequence signal by sampling with a predetermined sampling clock. An OFDM demodulator comprising a sampling means, wherein an averaged complex correlation strength signal having a length of one transmission symbol period is calculated from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period. Complex correlation strength calculating means for generating a boundary, boundary detecting means for detecting a boundary of the effective symbol in the averaged complex correlation strength signal, and first generated successively by the complex correlation strength calculating means. For the complex correlation strength signal and the second complex correlation strength signal, the first complex From the difference between the position of the boundary in the correlation strength signal and the position of the boundary in the second complex correlation strength signal, and the processing time required for the complex correlation strength calculation means to average the complex correlation strength signal, A frequency error detecting means for detecting a frequency error between the transmission clock of the OFDM signal and the sampling clock, and a frequency error correcting means for correcting the frequency error detected by the frequency error detecting means are provided.

  According to the above configuration, in the OFDM demodulator according to the present invention, the sampling means receives an OFDM signal including a transmission symbol having a valid symbol and a guard interval, samples it with a predetermined sampling clock, and receives the received sample sequence signal. Is generated.

  That is, the OFDM demodulator receives a digital signal such as an OFDM-modulated broadcast wave and samples it at a predetermined sampling clock frequency based on the operation clock of the OFDM demodulator itself. The OFDM-modulated digital signal is transmitted by a transmission clock independent of the operation clock of the OFDM demodulator. The OFDM-modulated digital signal is not limited to a broadcast wave, and may be a data signal transmitted through a wireless or wired transmission path or a communication network.

  Further, according to the above configuration, the complex correlation strength calculating means averages one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period. A complex correlation strength signal is generated. An OFDM signal sampled as a received sample sequence signal consists of transmission symbols including effective symbols and guard intervals, and shows a significant correlation between the signal delayed by the effective symbol period and the guard interval period. Get higher. When calculating the complex correlation strength, the complex correlation strength calculating means, for example, calculates the complex correlation strength after reducing the fluctuation of the complex correlation data by performing symbol direction integration or moving average calculation processing of the complex correlation. There may be. Further, the complex correlation strength calculating means may be configured to perform a moving average process for smoothing the complex correlation strength calculated from the complex correlation in the direction of the sample point and a filtering process for removing high frequency components.

  Further, the complex correlation strength calculating means may be configured to calculate the complex correlation strength for one elementary wave, or complex for a synthesized wave of one elementary wave and the elementary wave arrived after the element wave is delayed. A configuration for calculating the correlation strength may be used, and is not particularly limited.

  Further, according to the above configuration, the boundary detection means detects the boundary of the effective symbol in the averaged complex correlation strength signal. As described above, since the correlation strength is high in the guard interval period, it is possible to detect the boundary of the effective symbol from the change in the correlation strength.

  The boundary detection means, for example, performs a differential operation of the complex correlation strength, and obtains a peak position of the differential output (a positive differential output when the complex correlation strength increases and a negative differential output when the complex correlation strength decreases). It may be detected as the boundary position of the guard interval period, or may be detected as the boundary position of the guard interval period by analyzing the waveform of the complex correlation strength, and is not particularly limited.

  Further, according to the above configuration, the frequency error detection means performs the first complex correlation strength signal and the second complex correlation strength signal generated continuously by the complex correlation strength calculation means with respect to the first complex correlation strength signal. From the difference between the position of the boundary in the correlation strength signal and the position of the boundary in the second complex correlation strength signal, and the processing time required for the complex correlation strength calculation means to average the complex correlation strength signal, A frequency error between the transmission clock of the OFDM signal and the sampling clock is detected.

  If there is a difference between the operating clock frequency on the transmitting side and the operating clock frequency on the receiving side, the number of clocks per fixed time will be different between the receiving side and the transmitting side. The boundary position is shifted forward or backward. On the contrary, the frequency error between the transmission side and the reception side can be detected based on this deviation (that is, the difference between the continuously calculated complex correlation strength symbol boundary positions).

  Therefore, the frequency error detection means calculates the difference between the positions of the symbol boundaries between the first complex correlation strength signal and the second complex correlation strength signal generated continuously, and the averaged complex correlation strength signal. The frequency error is detected by analyzing the processing time required for. The frequency error detection means is configured to use, for example, a value obtained by dividing a difference in symbol boundary position by a processing time, or a value obtained by integrating the difference over a plurality of frequency error detection cycles as a frequency error. Also good.

  The frequency error correcting unit corrects the frequency error detected by the frequency error detecting unit. The frequency error correction means is configured as a PLL circuit, for example, and may directly change the sampling clock frequency, or may be configured as a filter that interpolates sampling data at the true sampling timing according to the frequency error. Well, there is no particular limitation.

  After the frequency error detection means corrects the frequency error detected in one frequency error detection cycle, the frequency error detection means detects the frequency error again by the same processing, but the frequency detected in each frequency error detection cycle. Even if the error still includes a detection error (difference from the true frequency error), in the next frequency error detection cycle, it is only necessary to detect the frequency error of the difference, and this frequency detection error cycle is repeated. Thus, the true frequency error is detected and corrected.

  Thereby, the OFDM demodulator according to the present invention can calculate the frequency error from the difference between the positions of the symbol boundaries in the continuously calculated complex correlation strength. The waveform of the complex correlation strength can be analyzed stably, and a highly reliable detection result can be obtained even if the difference in symbol boundary position due to the frequency error is a small number of samples. Therefore, it is possible to detect and correct the frequency error accurately in a short time without increasing the circuit scale.

  An OFDM demodulation method according to the present invention is an OFDM demodulation method for receiving an OFDM signal including a transmission symbol having a valid symbol and a guard interval and generating a received sample sequence signal by sampling with a predetermined sampling clock. A complex correlation strength calculation step of generating an averaged complex correlation strength signal of one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period; A detection step for detecting a boundary of the effective symbol in the averaged complex correlation strength signal, and a first complex correlation strength signal and a second complex correlation strength signal successively generated by the complex correlation strength calculation step The position of the boundary in the first complex correlation strength signal From the difference from the boundary position in the second complex correlation strength signal and the processing time required by the complex correlation strength calculation step to average the complex correlation strength signal, the transmission clock of the OFDM signal and the sampling clock And a frequency error correction step for correcting the frequency error detected by the frequency error detection step.

  According to said structure, there exists an effect similar to the OFDM demodulator based on this invention.

  In the OFDM demodulator according to the present invention, the complex correlation strength calculating means adds a correlation value between the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period every transmission symbol period. Symbol number direction integration means for generating a complex correlation signal integrated in the symbol number direction, and smoothing means for generating a complex correlation strength signal from the complex correlation signal and smoothing the complex correlation strength signal. It is preferable to provide.

  According to the above configuration, the symbol number direction integrating means adds the correlation value of the OFDM signal delayed by the effective symbol period every other transmission symbol period, and integrates the complex correlation signal in the symbol number direction.

  Also, according to the above configuration, the smoothing means smoothes the complex correlation strength signal generated from the complex correlation signal integrated in the symbol number direction.

  As a result, the complex correlation strength calculation means significantly reduces the fluctuation of the complex correlation signal, calculates a complex correlation strength with a small fluctuation, and performs a filtering process to remove a slight fluctuation remaining in the calculated complex correlation strength. As a result, a complex correlation strength signal having a smooth waveform can be generated. Therefore, the OFDM demodulator according to the present invention can accurately detect the boundary of the effective symbol from the waveform of the complex correlation strength signal.

  The OFDM demodulator according to the present invention preferably further comprises integration period determining means for determining the integration period in the symbol number direction based on an internal parameter.

  According to said structure, an integration period determination means determines the integration period of the symbol number direction by a symbol number direction integration means based on an internal parameter.

  The difference in the position of the boundary of the effective symbol in the complex correlation strength signal calculated continuously has detection accuracy depending on the integration period in the symbol number direction (symbol direction filtering period, so-called interval average cycle number). If the detected frequency error and the actual frequency error are large, the correlation strength will be integrated while shifting. Therefore, if the symbol direction filtering period is increased, the correlation strength will rise and fall, and the differential will be differentiated. The waveform is distorted.

  Therefore, in the OFDM demodulator according to the present invention, the integration period determining means determines the symbol direction integration period according to the elapsed time from the start of the operation of the OFDM demodulator as an internal parameter. For example, the integration period determining means sets the symbol direction integration period to be short, especially under conditions where the frequency error is predicted to be large, such as immediately after the start of the operation, and increases the symbol direction integration period after determining that the frequency error is stable. The configuration may be set.

  Thereby, in the OFDM demodulator according to the present invention, the symbol direction integration period can be appropriately changed according to the internal parameters, so that the position of the boundary of the effective symbol in the continuously calculated complex correlation strength signal The difference can be detected with high accuracy.

  In the OFDM demodulator according to the present invention, the boundary detection means may generate a differential output signal obtained by differentiating the averaged complex correlation strength signal and detect a peak position of the differential output signal as the boundary. preferable.

  According to said structure, a boundary detection means detects the peak position in the differential output of a complex correlation strength signal as a boundary of an effective symbol.

  As a result, the OFDM demodulator according to the present invention can accurately detect the boundary of the effective symbols with a simple configuration.

  In the OFDM demodulator according to the present invention, when the boundary detection unit detects the peak position in the second complex correlation strength signal after detecting the peak position in the first complex correlation strength signal, It is preferable that the peak position in the second complex correlation strength signal is detected within a set range from the peak position of the boundary in the first complex correlation strength signal.

  According to the above configuration, the boundary detection unit detects the peak position in the first complex correlation strength signal, and then detects the boundary position in the second complex correlation strength signal. At this time, the boundary detection means detects the peak position in the second complex correlation strength signal within the set range.

  Under conditions such as multipath and fading where the strength of each wave is switched, the peak position indicating the maximum value among the differential output peaks of the complex correlation strength signal differs. For example, when a symbol boundary is detected for a composite wave composed of a plurality of elementary waves, a peak indicating a symbol boundary of a certain elementary wave in the complex correlation strength signal (first complex correlation strength signal) of the (m-1) th detection cycle. When the maximum peak value is indicated at the position peak (m−1), it corresponds to the peak position peak (m−1) in the complex correlation strength signal (second complex correlation strength signal) of the m-th detection cycle. If the peak value of the peak position peak (m) becomes smaller than the peak value of the peak position peak ′ (m) indicating the symbol boundary of another elementary wave, the peak position difference ( That is, Δpeak (m) = peak (m−1) −peak ′ (m)) is calculated, and the frequency error is calculated based on this difference. , So that the correct frequency error can not be obtained.

  Therefore, in the OFDM demodulator according to the present invention, after detecting the peak position peak (m−1) indicating the maximum peak value in the first complex correlation strength signal, the second complex correlation strength is detected in the next detection cycle. The range in which the peak position is detected is limited to the set range. For example, when the detection range is set to W, the peak position is detected in the range of peak (m−1) ± W.

  Note that the set value may be a predetermined value or a configuration that changes according to the internal state of the receiving apparatus such as the elapsed time immediately after initialization, the number of symbols to be integrated, or the reception status. Also good.

  This makes it possible to detect an appropriate peak position even under conditions where the strength of each element wave is switched, such as multipath and fading, so the frequency error can be accurately detected from the difference between the peak positions calculated correctly. can do.

  In the OFDM demodulator according to the present invention, there exists output data exceeding a set threshold value among the storage means for storing the frequency error detected by the frequency error detection means and the output data constituting the differential output signal. A determination unit that determines that the detection of the boundary position by the boundary detection unit is effective, and the frequency error detection unit detects the position of the boundary in the first complex correlation strength signal and The frequency error is detected only when both of the detection of the boundary position in the complex correlation strength signal of 2 are determined to be valid by the determination means, and the frequency error correction means detects the frequency error detection. When the means detects the frequency error, the frequency error detected by the frequency error detection means is corrected and the frequency error detection means is corrected. But it does not detect the frequency error, it is preferable to correct the frequency error stored in the storage means.

  According to the above configuration, the storage unit stores the frequency error detected by the frequency error detection unit.

  The determination means determines that the position detection of the symbol boundary is effective by the boundary detection means when there is output data exceeding the set threshold among the output data of the differential output signal.

  The frequency error detecting means detects the frequency error only when both the position detection of the symbol boundary in the first complex correlation strength signal and the position detection of the symbol boundary in the second complex correlation strength signal are effective. To detect.

  The frequency error correction means corrects the frequency error when the frequency error detection means detects the frequency error, and stores the frequency error in the storage means when the frequency error detection means does not detect the frequency error. Correct the frequency error.

  The difference in peak position used when calculating the frequency error is the peak position detected in the immediately preceding detection cycle, that is, the peak position is correctly detected in the first complex correlation strength signal and the second complex correlation strength signal. It is assumed that it is made. For example, when the receiver moves, if the desired OFDM wave cannot be obtained during frequency error detection due to the radio wave being interrupted or the strength changing during frequency error detection, peak position detection is inaccurate. become.

  Therefore, the determination unit determines whether or not the peak position has been accurately detected based on the presence / absence of output data that exceeds the set threshold among the output data of the differential output signal. If no peak value exceeding the threshold is detected, for example, the detected value is discarded together with the previously detected peak position data so that the frequency error is not detected. Instead, the previous frequency error stored in the storage means is used. Thereafter, when a significant peak position of the differential output is detected twice in succession, the frequency error is calculated again based on the difference of the peak positions. The threshold value may be a predetermined value, or may be configured to be calculated and set based on the differential output signal.

  As a result, the frequency error can be calculated based on the accurately detected difference between the peak positions, so that a more accurate frequency error can be detected.

  In the OFDM demodulator according to the present invention, the number of output data exceeding a set threshold among the storage means for storing the frequency error detected by the frequency error detection means and the output data constituting the differential output signal is And a determination unit that determines that the detection of the position of the boundary by the boundary detection unit is valid when it is within a predetermined range, wherein the frequency error detection unit includes the first complex correlation strength signal. The frequency error is detected only when both the position detection of the boundary and the position detection of the boundary in the second complex correlation strength signal are determined to be valid by the determination means, and the frequency The error correction means corrects the frequency error detected by the frequency error detection means when the frequency error detection means detects the frequency error. , When the frequency error detecting means does not detect the frequency error, it is preferable to correct the frequency error stored in the storage means.

  According to the above configuration, the storage unit stores the frequency error detected by the frequency error detection unit.

  In addition, when the number of output data exceeding the set threshold is within a predetermined range among the output data of the differential output signal, the determination unit is effective in detecting the position of the symbol boundary by the boundary detection unit. Judge that there is.

  The frequency error detecting means detects the frequency error only when both the position detection of the symbol boundary in the first complex correlation strength signal and the position detection of the symbol boundary in the second complex correlation strength signal are effective. To detect.

  The frequency error correction means corrects the frequency error when the frequency error detection means detects the frequency error, and stores the frequency error in the storage means when the frequency error detection means does not detect the frequency error. Correct the frequency error.

  The difference in peak position used when calculating the frequency error is the peak position detected in the immediately preceding detection cycle, that is, the peak position is correctly detected in the first complex correlation strength signal and the second complex correlation strength signal. It is assumed that it is made. For example, when the receiver moves, if the desired OFDM wave cannot be obtained during frequency error detection due to the radio wave being interrupted or the strength changing during frequency error detection, peak position detection is inaccurate. become.

  Therefore, the determination means determines whether the peak position has been accurately detected based on whether or not the number of output data exceeding the set threshold is within a predetermined range among the output data of the differential output signal. . For example, the number of times the threshold value was exceeded in the differential output of all sections was counted, and if this value exceeded a predetermined value, it was determined that the effective peak position could not be detected, The detection value is discarded together with the data so that the frequency error is not detected. Instead, the previous frequency error stored in the storage means is used. Thereafter, when a significant peak position of the differential output is detected twice in succession, the frequency error is calculated again based on the difference of the peak positions. The threshold value may be a predetermined value, or may be configured to be calculated and set based on the differential output signal.

  As a result, the frequency error can be calculated based on the difference between the detected peak positions more accurately, so that it is possible to detect the frequency error with higher accuracy.

  The OFDM demodulator according to the present invention preferably further comprises threshold setting means for calculating and setting the threshold from the differential output.

  According to said structure, a threshold value setting means calculates and sets a threshold value from the said differential output.

  Thereby, since the threshold value for determining whether or not the peak position detection in the differential output is correctly performed can be set dynamically according to the differential output, a more appropriate threshold value can be set.

  In the OFDM demodulator according to the present invention, it is preferable that the frequency error detecting means detects a cumulative value obtained by accumulating a division value obtained by dividing the difference by the processing time as the frequency error.

  According to said structure, a frequency error detection means detects the cumulative value which accumulated the division value obtained by dividing | segmenting the said difference by the said processing time as a frequency error. That is, an integrated value obtained by integrating the divided values detected over a plurality of frequency error detection cycles is calculated as a frequency error.

  The division value calculated in each frequency error detection cycle indicates a frequency shift between the transmission side and the reception side, but includes fluctuations with respect to the true value, for example, the signal strength and the magnitude of noise, Alternatively, the magnitude of the fluctuation changes depending on a cause represented by a Doppler shift when the receiving apparatus moves. Therefore, by accumulating the division value, an error component included in the division value, that is, fluctuation with respect to the true value is canceled out, and an accumulation value closer to the true frequency error can be obtained.

  Thereby, the OFDM demodulator according to the present invention can detect a frequency error with higher accuracy.

  In the OFDM demodulator according to the present invention, the frequency error detecting means obtains a division value obtained by dividing the difference by the processing time, and detects the boundary position in the first complex correlation strength signal and the second It is preferable to detect the accumulated value as the frequency error only when both of the detection of the boundary position in the complex correlation strength signal are determined to be valid by the determination means.

  According to the above configuration, the frequency error detecting means, among the division values obtained by dividing the difference by the processing time, the cumulative value obtained by accumulating only the values determined to be valid by the determining means, Detect as frequency error.

  Thereby, the OFDM demodulator according to the present invention can detect a frequency error with higher accuracy.

  In the OFDM demodulator according to the present invention, the frequency error detection means calculates a multiplication value obtained by multiplying the division value obtained by dividing the difference by the processing time by a coefficient determined by an internal parameter, and calculates the multiplication value. It is preferable to detect the accumulated value as the frequency error.

  According to the above configuration, the frequency error detection unit calculates a multiplication value obtained by dividing the difference by the processing time and a value determined by an internal parameter, and accumulates the calculated multiplication value. The accumulated value is detected as a frequency error.

  That is, for example, if the calculated division value is too large compared to the true frequency error, the frequency error obtained as the cumulative value obtained by accumulating the division value diverges and does not converge. In such a case, the frequency error detecting means does not integrate the division value as it is, but integrates by multiplying by a coefficient less than 1. This coefficient may be a constant value from the beginning, or may be changed at regular intervals after the start of operation, or may be calculated based on a difference in symbol boundary position.

  Thereby, the OFDM demodulator according to the present invention can prevent the divergence of the calculated frequency error.

  In the OFDM demodulator according to the present invention, it is preferable that the frequency error correction unit corrects the frequency error by changing the predetermined sampling clock.

  According to the above configuration, the frequency error correction unit is configured as a PLL circuit, for example, and corrects the frequency error by changing the sampling clock in accordance with the detected frequency error.

  Thereby, since the OFDM demodulator according to the present invention can directly change the sampling clock, the frequency error can be easily corrected.

  In the OFDM demodulator according to the present invention, the frequency error correction means includes sampling timing specifying means for generating sampling timing specifying information for specifying the sampling timing of the OFDM signal, and the sampling timing specifying information from the received sample sequence signal. It is preferable that an interpolation means for interpolating the sampling value at the sampling timing specified by

  According to the above configuration, the frequency error correction means identifies the sampling timing on the broadcast station side of the OFDM signal, that is, the true sampling timing, and interpolates the sampling value at the true sampling timing using the received sample sequence signal. To do.

  As a result, even in a configuration such as a PLL circuit where the sampling clock cannot be directly changed, the frequency error can be corrected only by the logic unit.

  The OFDM demodulator according to the present invention further comprises oversampling means for converting the predetermined sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself, and the interpolation means receives the oversampled received samples. It is preferable to interpolate the sampling value at the sampling timing specified by the sampling timing specifying information from the series signal.

  According to the above configuration, the oversampling unit converts the sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself, and the interpolation unit performs true sampling from the oversampled received sample sequence signal. Interpolate sampling data at timing.

  Thereby, the sampling data at the true sampling timing can be accurately interpolated over the entire desired frequency region.

  In the OFDM demodulator according to the present invention, the sampling means converts the predetermined sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself, and the interpolation means receives the oversampled received sample sequence. It is preferable to interpolate the sampling value at the sampling timing specified by the sampling timing specifying information from the signal.

  According to the above configuration, the sampling unit converts the sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself, and the interpolation unit converts the true sampling timing from the oversampled received sample sequence signal. Interpolate sampling data at.

  Thereby, the sampling data at the true sampling timing can be accurately interpolated over the entire desired frequency region.

  In the OFDM demodulator according to the present invention, the orthogonal demodulation means for demodulating the orthogonal frequency division multiplex modulated OFDM signal received as the received sample sequence signal, and the signal demodulated by the orthogonal demodulation means by the FFT operation in the frequency domain FFT calculation means for converting the data into a data signal, and FFT window position control means for shifting the start position of the FFT calculation. The sampling timing specifying means has a predetermined sampling timing specified by the sampling timing specifying information. If it exceeds the specified range, the sampling timing is shifted by one cycle of the predetermined sampling clock, and the FFT window position control means is responsive to the sampling timing shift in the sampling timing specifying means in response to the FFT. The starting position of the calculation, it is preferable to simultaneously shifted by one period of the predetermined sampling clock.

  According to the above configuration, the orthogonal demodulation means demodulates the OFDM signal that has been subjected to orthogonal frequency division multiplexing modulation and received as the received sample sequence signal. Then, the FFT operation means converts the signal demodulated by the orthogonal demodulation means into a frequency domain data signal by FFT operation. Further, the FFT window position control means shifts the start position of the FFT calculation.

  The sampling timing specifying means shifts the sampling timing by one period of a predetermined sampling clock when the specified sampling timing exceeds a predetermined range, and the FFT window position control means Shift the calculation start position.

  Thereby, since the FFT window always starts at the same timing with respect to the true sampling timing corresponding to the interpolation point, the sampling timing can be corrected without much.

  In addition, by performing the FFT window position control simultaneously with the frequency error detection, the circuit can be shared, so that the circuit scale can be reduced and the power consumption can be reduced.

  Note that the OFDM demodulator may be realized by a computer. In this case, a control program for realizing the OFDM demodulator in the computer by operating the computer as each of the above means and a computer-readable recording medium on which the control program is recorded also fall within the scope of the present invention.

  As described above, the OFDM demodulator according to the present invention receives an OFDM signal including a transmission symbol having a valid symbol and a guard interval, and generates a received sample sequence signal by sampling with a predetermined sampling clock. A complex correlation strength calculating means for generating an averaged complex correlation strength signal of one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period. Boundary detection means for detecting a boundary of the effective symbol in the averaged complex correlation strength signal, and a first complex correlation strength signal generated by the complex correlation strength calculation means and a second For the complex correlation strength signal, the position of the boundary in the first complex correlation strength signal and From the difference from the boundary position in the second complex correlation strength signal and the processing time required by the complex correlation strength computing means to average the complex correlation strength signal, the transmission clock of the OFDM signal and the sampling clock And a frequency error correcting means for correcting the frequency error detected by the frequency error detecting means.

  An OFDM demodulation method according to the present invention is an OFDM demodulation method for receiving an OFDM signal including a transmission symbol having a valid symbol and a guard interval and generating a received sample sequence signal by sampling with a predetermined sampling clock. A complex correlation strength calculation step of generating an averaged complex correlation strength signal of one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period; A detection step for detecting a boundary of the effective symbol in the averaged complex correlation strength signal, and a first complex correlation strength signal and a second complex correlation strength signal successively generated by the complex correlation strength calculation step The position of the boundary in the first complex correlation strength signal From the difference from the boundary position in the second complex correlation strength signal and the processing time required by the complex correlation strength calculation step to average the complex correlation strength signal, the transmission clock of the OFDM signal and the sampling clock And a frequency error correction step for correcting the frequency error detected by the frequency error detection step.

  Therefore, the frequency error can be calculated from the difference between the symbol boundary positions in continuously calculated complex correlation strengths, and a highly reliable detection result can be obtained even with a small number of samples. There is an effect that the frequency error can be detected and corrected accurately in a short time without increasing the circuit scale.

[Embodiment 1]
(Configuration of OFDM demodulator 1)
The configuration of the OFDM demodulator 1 according to this embodiment will be described below with reference to FIG. FIG. 1 is a block diagram showing a main configuration of the OFDM demodulator 1.

  The OFDM demodulator 1 includes an analog-digital converter (ADC, sampling means) 11, a sampling receiver (oversampling means) 12, an orthogonal demodulation generator 13, a fast Fourier transform calculator (FFT section) 14, a delay Profile / peak position detector 15 (complex correlation strength calculator), clock frequency error detector 16 (frequency error detector), fast Fourier transform window position detector (FFT window position detector) 17, and frequency oscillator 18 And a phase lock loop circuit (PLL) 19 (frequency error correction means). The OFDM demodulator 1 is connected to the tuner 10. Furthermore, the OFDM demodulator 1 includes a control unit and a storage unit (not shown).

  The tuner 10 receives a digital broadcast wave from a broadcasting station via an antenna, performs frequency conversion on an RF (high frequency) signal, and supplies the obtained IF (intermediate frequency) signal to the ADC 11.

  The frequency oscillator 18 generates a clock signal and supplies it to the PLL 19. The PLL 19 generates an operation clock signal based on the clock signal from the frequency oscillator 18 and supplies it to each part of the OFDM demodulator 1. Each unit of the OFDM demodulator 1 operates based on an operation clock from the PLL 19. When the clock frequency error is supplied from the clock frequency error detector 16, the PLL 19 further generates an operation clock signal based on the clock frequency error.

  The ADC 11 digitizes the IF signal and supplies the digitized IF signal to the sampling receiver 12. The sampling receiver 12 samples and receives the digitized IF signal from the ADC 11 based on the operation clock from the PLL 19, and supplies it to the quadrature demodulation generator 13. The quadrature demodulation generation unit 13 performs quadrature demodulation of the corrected IF signal using a carrier signal having a set carrier frequency, and includes a base composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). A band OFDM signal is generated and supplied to the FFT unit 14 and the delay profile / peak position detection unit 15.

  The delay profile / peak position detection unit 15 detects the peak position of the change amount of the complex correlation strength calculation value based on the baseband OFDM signal supplied from the direct demodulation generation unit 13 and supplies the detected peak position to the clock frequency error detection unit 16. . Further, the delay profile / peak position detection unit 15 generates delay profile information and supplies it to the FFT window position detection unit 17. The clock frequency error detection unit 16 detects a clock frequency error based on the supplied peak position and outputs it to the PLL 19. The FFT window position detection unit 17 generates an FFT window position signal representing optimum FFT operation timing based on the delay profile information and supplies the FFT window position signal to the FFT unit 14.

  The FFT unit 14 performs a fast Fourier transform (FFT operation) on the baseband OFDM signal supplied from the orthogonal demodulation generation unit 13 based on the FFT window position signal supplied from the FFT window position detection unit 17, Convert to domain complex signal.

  In the OFDM demodulator 1 according to the present embodiment, the delay profile / peak position detector 15 detects the peak position of the complex correlation strength, and the clock frequency error detector 16 detects the frequency error based on the peak position of the complex correlation strength. Then, the frequency error detected in each detection cycle is integrated. Then, the PLL 19 corrects the frequency error of the operation clock to be generated based on the integrated frequency error.

(Complex correlation strength)
Here, the complex correlation strength of the OFDM broadcast wave will be described. As shown in FIG. 24, the OFDM broadcast wave is composed of a valid interval and a guard interval that is a copy of the data in the rear _tg period of the effective symbol period (t _u ) data, and the guard interval is added before the effective symbol. Included symbols. The _tg period from the beginning of this symbol is called a guard period. In addition, one symbol period is t _u + t _g .

  FIG. 3 is a diagram showing the relationship between the complex correlation strength of an OFDM broadcast wave and its differential output (the amount of change in the time direction of the complex correlation strength) in a multipath environment. In a multipath environment, multiple elementary waves are mixed in the same band. In FIG. 3, for example, the elementary wave 1 is a broadcast wave that reaches the receiving device directly from the transmitting station, and the elementary wave 2 is a broadcast wave that is emitted from the transmitting station and reflected after being reflected by a mountain or a building. .

Here, for each of the elementary waves 1 and rays 2, each symbol data taking a complex correlation which is delayed by the effective symbol period t _u, is calculated intensity, as shown in FIG. 3, the rays 1 The complex correlation strength and the complex correlation strength of the elementary wave 2 each have significant strength during the GI period.

The OFDM demodulator 1 receives an elementary wave 1 and an elementary wave 2 having the same symbol as the elementary wave 1 that arrives after being delayed by τ _A from the elementary wave 1. Therefore, in the OFDM demodulator 1, the complex correlation strengths of the elementary wave 1 and the elementary wave 2 are added, and the sum of the complex correlation strengths shown in FIG. 3 is obtained. When the complex correlation strength obtained in this way is differentiated, a differential output waveform shown in FIG. 3 is obtained, and the peak position of the complex correlation strength is detected. By detecting the shift of the peak position of the differential waveform, the OFDM demodulator 1 detects the clock frequency error and corrects the operation clock, and performs control so that the peak position obtained for each detection cycle does not shift. A good reception state can be obtained.

  In the present embodiment, the OFDM demodulator 1 performs a process of detecting the peak value of the complex correlation strength for a composite wave in a state where a plurality of elementary waves are mixed, but the complex correlation strength of a single elementary wave is detected. It may be configured to detect the peak position. Alternatively, it may be configured to further include a function of separating the elementary wave 1 and the elementary wave 2 from the synthesized wave, and to detect the peak position of the complex correlation intensity for each separated elementary wave, and is not particularly limited.

(Delay Profile / Peak Position Detection Unit 15)
The delay profile / peak position detection unit 15 will be described below with reference to FIG. FIG. 2 is a diagram showing the configuration of the delay profile / peak position detector 15 and the clock frequency error detector 16. As shown in FIG. 2, the delay profile / peak position detection unit 15 includes a delay circuit unit 151, a complex conjugate calculation unit 152, a complex multiplication unit 153, a first filtering unit 154 (symbol number direction integration means), a complex correlation strength calculation. 155, a second filtering unit 156 (smoothing unit), a differential operation unit 157, a peak position detection unit 158 (boundary detection unit), and a free-running counter 159. The function of these members will be described below.

Delay circuit 151 is a shift register composed of N _u register groups, delaying the effective symbol period the input baseband OFDM signal. The OFDM time domain signal delayed by the effective symbol time by the delay circuit unit 151 is input to the complex conjugate calculation unit 152. N _u is the number of samplings in one effective symbol.

  The complex conjugate calculator 152 calculates the complex conjugate of the baseband OFDM signal delayed by the effective symbol period, and supplies the complex conjugate to the complex multiplier 153.

  The complex multiplier 153 multiplies the baseband OFDM signal that has not been delayed by the complex conjugate signal of the baseband OFDM signal delayed by the effective symbol period for each sample, and calculates a complex correlation value. Then, a complex correlation signal representing the calculated complex correlation value is supplied to the first filtering unit 154.

  The first filtering unit 154 calculates an average value of complex correlation values in one or more symbol periods for each of the real axis component (I channel signal) and the imaginary axis component (Q channel signal) of the complex correlation signal. For example, the first filtering unit 154 averages the intervals in the symbol period for each complex component. That is, the first filtering unit 154 is an interval integration circuit in the symbol direction, and repeatedly adds and averages complex correlation signals at the number of sampling points in one symbol period. That is, for a symbol period composed of a predetermined number of symbols, the complex correlation value is integrated in the symbol direction in each symbol period, and the integrated value in each symbol period is divided by the predetermined number of symbols in the symbol period. An average value of complex correlation values is calculated. The integral value of the complex correlation value in each symbol interval is the sum of the complex correlation values for a predetermined number of symbols for each sampling point in the symbol interval. In this way, a signal (complex correlation calculation value series signal) composed of the average value of complex correlation values for each sampling point in a predetermined symbol period is output to the complex correlation strength calculation unit 155.

  Further, regarding the integration of the complex correlation value in the symbol direction in the first filtering unit 154, for example, immediately after the start of the detection of the frequency error, there are cases where restrictions such as a reduction in the number of integration points occur to improve the detection speed. is there. For this reason, the structure which changes the period (integration period) which calculates in the 1st filtering part 154 may be sufficient. For example, a configuration may be adopted in which detection is frequently performed in a short period at first, the frequency error is quickly converged, and then the number of integration points is increased to detect the frequency error more accurately in a long period. In the configuration for realizing the change of the integration period, for example, the first filtering unit (integration period determining means) reads and determines various parameters stored in a memory (not shown) for each elapsed time from the start of detection. To do.

  The complex correlation strength calculation unit 155 squares the real axis component (I channel signal) and the imaginary axis component (Q channel signal) of the complex correlation calculation value series signal, adds them, and adds the square root of the addition result. By calculating the amplitude component (complex correlation strength) of the complex correlation calculation value series signal. Then, a complex correlation strength signal representing the calculated complex correlation strength is supplied to the second filtering unit 156.

  FIG. 4 is a diagram illustrating the complex correlation strength when the first filtering unit 154 does not perform the interval averaging process. As shown in FIG. 4, when the section averaging process is not performed in the first filtering unit 154, the waveform of the complex correlation strength signal has a large fluctuation for each sample point. For this reason, a desired differential waveform cannot be obtained even if the complex correlation strength is differentiated as it is. Therefore, as described above, the first filtering unit 154 integrates the complex correlation in symbol units to reduce fluctuations.

  FIG. 5 is a diagram illustrating the complex correlation strength when the first filtering unit 154 performs the interval averaging process. As shown in FIG. 5, most of the fluctuations are reduced by the processing of the first filtering unit 154, but some fluctuations remain.

  The second filtering unit 156 outputs a complex correlation strength calculation value obtained by performing moving average processing in the time direction on the complex correlation strength supplied from the complex correlation strength calculation unit 155 to the differential calculation unit 157.

  FIG. 6 is a diagram illustrating a complex correlation strength calculation value signal (averaged complex correlation strength signal) obtained by moving average processing in the second filtering unit 156. By performing a filtering process in the direction of the sample point by the moving average process in the second filtering unit 156 on the complex correlation strength signal, as shown in FIG. The signal is reduced in fluctuation. Note that the second filtering unit 156 may be configured to perform other filtering processing that cuts high-frequency components of the complex correlation strength signal in addition to the moving average processing.

  The differential calculation unit 157 calculates the amount of change (differential output) in the time direction of the complex correlation strength calculation value supplied from the second filtering unit 156 and supplies it to the peak position detection unit 158. That is, the differential output of the complex correlation strength calculation value is supplied from the differential calculation unit 157 to the peak position detection unit 158.

  FIG. 7 is a diagram showing a waveform of a differential output obtained by differentiating the complex correlation strength calculation value signal shown in FIG. As shown in FIG. 7, a positive (+) differential output is obtained at the portion where the complex correlation strength calculation value signal shown in FIG. 6 increases, and a negative (−) differentiation at the portion where the complex correlation strength calculation value signal decreases. Output is obtained.

  The peak position of this differential output indicates the start position (boundary position) of the GI period of the elementary wave. For this reason, when the elementary wave is shifted to the right and left due to the frequency error between the transmission clock frequency of the broadcast wave and the sampling clock frequency in the receiving device, the peak position is also shifted to the left and right. Then, the OFDM demodulator 1 analyzes this peak position shift and detects a frequency error.

The free-running counter 159 is a counter that counts operation clocks. The counter value N of the free-running counter 159 is incremented by 1 from 0 to N _s −1 and returns to 0 when it exceeds N _s −1. Here, N _s is the number of samplings in one OFDM symbol. That is, the free-running counter 159 is a cyclic counter that is one cycle in the number of samplings in the OFDM symbol period. The count value N of the free-running counter 159 is supplied to the peak position detector 158 and the clock frequency error detector 16.

The peak position detection unit 158, for each predetermined cycle (a period composed of one or more symbols), among the peaks included in the differential output of the complex correlation strength calculation value in the cycle, the peak position of the maximum value (in the time direction) The point having the largest change amount) is detected, and the count value at that point is detected. When the peak position detection unit 158 proceeds to the next cycle, the peak position of the maximum value (the point at which the amount of change in the time direction becomes maximum) among the peaks newly included in the differential output of the complex correlation strength calculation value is again determined. To detect. The count value detected by the peak position detection unit 158 becomes a peak timing value P _peak indicating the peak position of the differential output of the complex correlation strength calculation value (the peak position of the change amount with respect to the time direction). The peak position detection unit 158 determines whether or not the differential output (change amount with respect to the time direction) of the complex correlation strength calculation value at the detected peak timing value P _peak is an effective value, and the peak timing value is determined. This is supplied to the clock frequency error detector 16.

FIG. 8 shows the peak position P _peak (n) obtained in the n-th detection cycle and the peak position P _peak (n−1) obtained one time before. Then, in the OFDM demodulator 1, the peak positions P _peak (n−1) (boundary positions in the first complex correlation strength signal) and P _peak (n) (boundary positions in the second complex correlation strength signal). The difference Δpeak (n) (= P _peak (n) −P _peak (n−1)) is analyzed to obtain a frequency error. By supplying the frequency error obtained in this way to a block having a function of correcting the clock frequency, such as a PLL circuit, the operation clock frequency of the receiving apparatus can be made equal to the operation clock frequency of the broadcasting station. .

(Clock frequency error detector 16)
As shown in FIG. 2, the clock frequency error detection unit 16 includes a peak position difference detection unit 161 and an integration calculation unit 162. Then, the clock frequency error detector 16 detects an error between the frequency of the clock signal from the frequency oscillator 18 (PLL 19) and the frequency of the broadcast wave based on the peak timing value from the delay profile / peak position detector 15. . The operation of the clock frequency error detector 16 will be described below.

  The peak position difference detection unit 161 acquires the peak timing value supplied from the peak position detection unit 158, calculates the difference from the previously supplied peak timing value, and calculates the difference between the calculated peak timing values as the peak timing. Divide by the time required to detect the value (the product of the number of symbols used to detect one peak timing value and the processing time per symbol) to detect as a frequency error in each cycle (referred to as cycle frequency error). . Then, the peak position difference detection unit 161 supplies the cycle frequency error to the integration calculation unit 162. The integration calculation unit 162 integrates the cycle frequency error and supplies it to the PLL 19 as a true frequency error. Then, the PLL 19 changes the clock frequency based on the integrated frequency error, and corrects the frequency error of the operation clock.

(Frequency error detection processing of OFDM demodulator 1)
An operation performed by the OFDM demodulator 1 according to the present embodiment for detecting a frequency error will be described below with reference to FIGS. 10 and 11. FIG. 10 is a flowchart showing one cycle of processing for detecting a frequency error in the OFDM demodulator 1. Hereinafter, the operation in the nth cycle will be described as an example.

  In S1, the delay profile / peak position detection unit 15 determines the number of integrations C (n) in the nth cycle, that is, the number of symbols used for detecting one frequency error, and proceeds to S2. Here, since the delay profile / peak position detector 15 integrates the complex correlation value of the baseband OFDM signal for each symbol, the number of integrations C (n) is equal to the number of symbols used for detecting one peak position. .

  In S2, the delay profile / peak position detection unit 15 performs integration in symbol units (that is, one symbol period period in the symbol direction) over a period of the number of symbols determined by C (n), and averages the integration results. . As a result, a complex correlation calculation value series signal composed of the average value of the complex correlation values for each sampling point is generated, and the process proceeds to S3. As a result, a complex correlation calculation value sequence signal for one symbol period is generated from the complex correlation value signal in the C (n) symbol period.

  In S3, the delay profile / peak position detection unit 15 calculates the complex correlation strength from the complex correlation calculation value sequence signal. Thereafter, the delay profile / peak position detection unit 15 performs filtering in the sampling point direction with respect to the complex correlation strength. For example, the delay profile / peak position detection unit 15 performs complex averaging by performing a moving average on the complex correlation strength signal, or by performing other filter processing such as removing a high frequency component of the complex correlation strength signal. An intensity calculation value signal is generated, and the process proceeds to S4.

  In S4, the delay profile / peak position detection unit 15 performs a differentiation operation in the sampling point direction. That is, the delay profile / peak position detection unit 15 calculates the amount of change in the time direction of the complex correlation strength calculation value, and proceeds to S5.

  In S5, the delay profile / peak position detector 15 determines whether or not the differential waveform (the waveform represented by the amount of change in the complex correlation strength calculation value in the time direction) can be analyzed (whether or not the detection of the peak position is valid). )). Details of the operation (determination process of whether or not the peak position detection is effective) performed by the delay profile / peak position detection unit 15 to perform this determination will be described later. If analysis is possible (YES in S5), the process proceeds to S6. If analysis is not possible (NO in S5), the process proceeds to S14.

In S6, the delay profile / peak position detection unit 15 determines whether or not the previous detection of the peak position P _peak (n−1) was effective. If the previous peak position detection is valid (YES in S6), the process proceeds to S8, and if the previous peak position P _peak (n-1) is not valid (NO in S6), the process proceeds to S7.

In S7, the delay profile / peak position detection unit 15 determines the peak position of the change amount of the complex correlation strength calculated value with respect to the time direction in the entire range of the complex correlation strength calculated value signal of the nth cycle from the result of the differential calculation in S4. P _peak (n) is detected, and the process proceeds to S14. In each cycle of frequency error detection, as described above, the interval averaging process is performed by the first filtering unit 154, and the complex correlation strength calculation value signal has a length of one symbol period.

  In S8, the delay profile / peak position detector 15 determines whether or not the frequency error has already converged. If the frequency error has converged (YES in S8), the process proceeds to S9. If the frequency error has not converged (NO in S8), the process proceeds to S10. Whether or not the frequency error has converged is determined by whether or not the previously detected frequency error is smaller than a predetermined threshold value. The threshold value may be configured according to the accuracy of the allowable frequency error, and is not particularly limited.

In S9, the delay profile / peak position detection unit 15 determines that the result of the differential calculation in S4 is not in the entire range of the complex correlation strength calculation value signal in the nth cycle but in the range of P _peak (n−1) ± W. The peak position P _peak (n) of the change amount in the time direction of the complex correlation strength calculation value is detected, and the process proceeds to S11. Here, P _peak (n−1) is the previously detected peak position, and W is a predetermined value. FIG. 9 is a diagram illustrating a peak position detection example when the detection range of the differential peak position is limited to ± W from the previously detected position. Details of an example of limiting the detection range of the peak position shown in FIG. 9 will be described later. The value of W may be uniquely determined, may be configured to be set in a register, or may be configured to be adaptively set, and is not particularly limited.

In S10, the delay profile / peak position detection unit 15 determines the peak position of the change amount of the complex correlation strength calculated value with respect to the time direction in the entire range of the complex correlation strength calculated value signal of the nth cycle from the result of the differential calculation in S4. P _peak (n) is detected, and the process proceeds to S11.

In S11, as shown in FIG. 8, the clock frequency error detector 16 calculates a difference Δpeak (n) between the detected peak position P _peak (n) and the previously detected peak position P _peak (n−1). , Go to S12.

  In S12, the clock frequency error detection unit 16 calculates the frequency error Δppm (n) detected in each cycle out of the true frequency error between the frequency of the operation clock from the PLL 19 and the transmission clock frequency of the broadcast wave as the cycle frequency. The error is calculated by the following equation, and the process proceeds to S13.

Δppm (n) = Δpeak (n) / N (n); N (n) = N _s * C (n) = (N _u + N _g ) * C (n)
Here, N _s is the number of broadcast clock (0 ppm) period of a symbol period length, N _u is the broadcast clock (0 ppm) number of cycles of the effective symbol period length, N _g is the guard interval period length of the broadcast clock (0 ppm ) The number of periods, and C (n) is the number of symbols used in the frequency error detection of the nth cycle. That is, N (n) is the processing time required for averaging the complex correlation strength signal. Δppm (n) corresponds to the division value in the claims.

  In S13, the clock frequency error detector 16 calculates the frequency error ppm (n) by the following equation, supplies the frequency error ppm (n) to the PLL 19, and proceeds to S15. Note that ppm (n) corresponds to the cumulative value in the claims.

ppm (n) = ppm (n−1) + Δ ppm (n)
In S <b> 14, the clock frequency error detection unit 16 supplies the frequency error ppm (n) to the PLL 19 as the frequency error ppm (n) of the nth cycle = the frequency error ppm (n−1) of the (n−1) th cycle. That is, the frequency error ppm (n-1) in the n-1th cycle is set as the frequency error ppm (n) in the nth cycle. That is, the current frequency error is not changed from the previously detected frequency error. The frequency error ppm (n-1) at the (n-1) th cycle is stored in a storage unit (storage means) (not shown).

In S15, the clock frequency error detector 16 stores a value of the peak position P _peak (n) in the nth cycle and a value (not shown) indicating whether or not the detection of P _peak (n) has succeeded. And the process proceeds to S16. In S16, n is incremented, and the process returns to S1.

(Peak position detection valid / invalid judgment processing)
Details of the operation of the delay profile / peak position detection unit 15 (more specifically, the peak position detection unit 158) in S5 of FIG. 10 will be described with reference to FIG. FIG. 11 shows the process in S5 of FIG. 10, that is, whether or not the differential waveform of the complex correlation strength calculation value (the waveform represented by the amount of change in the complex correlation strength calculation value in the time direction) can be analyzed (that is, It is a figure which shows the process which determines whether the detection of a peak position is effective.

In S501, the peak position detection unit 158 determines the peak value (the maximum value of the change amount in the time direction of the complex correlation strength calculation value) A (n)
Then, the peak position X (n) is calculated, and the process proceeds to S502.

  In S502, the peak position detection unit 158 determines a section having no significant correlation from X (n), and proceeds to S503. Here, the interval without correlation is a portion shifted by ½ symbol length from X (n) where significant correlation is estimated to start, and the number of sampling points in the interval without correlation is between 32 and 256. Thus, a predetermined sampling number is determined as necessary.

  In S503, the peak position detection unit 158 calculates the average value B (n) of the complex correlation strength in the non-correlated section, and proceeds to S504. B (n) is a value indicating the intensity of the noise component of the complex correlation.

  In S504, the peak position detection unit 158 (threshold setting means) calculates a differential output threshold D (n) of the complex correlation strength from the peak value A (n) and the average value B (n), and proceeds to S505. .

For example, D (n) is
D (n) = αA (n) + βB (n) 0 <α <1, 0 <β <1, 0 <(α + β) <1
As follows, α and β are determined and calculated. D (n) is a threshold value and is required to be larger than the noise component and smaller than the peak value A (n). As long as this is satisfied, α and β may be constant, or may be determined in consideration of the magnitude of a noise component that appears in a portion uncorrelated with the peak value A (n). Furthermore, since noise appearing in the uncorrelated part is related to the number of integration points in the symbol direction, it can be determined based on the number of integration points.

In S505, the peak position detection unit 158 analyzes the differential output of all sections, counts the number of sampling points where the differential output exceeds the threshold value D (n), stores it in TH (n), and proceeds to S506. Here, if the differential output exceeds D (n), the differential output at the mth sampling point is div (m).
div (m−1) ≦ D (n) and
div (m)> D (n)
Means satisfying.

  In S506, the peak position detection unit 158 determines whether TH (n) = 0. If TH (n) is 0 (YES in S506), it is estimated that the peak value is low and cannot be distinguished from noise, and the flow proceeds to S509. If TH (n) is not 0 (NO in S506), the process proceeds to S507.

  In S507, the peak position detection unit 158 determines whether TH (n)> α is satisfied. Here, a predetermined value is also set in advance for α, but it may be determined uniquely, may be set in a register, or may be set adaptively. There is no particular limitation. If TH (n) is equal to or smaller than α (NO in S507), the process proceeds to S508. If TH (n) is larger than α (YES in S507), it is estimated that the delay profile is disturbed or that the noise is erroneously determined, and the process proceeds to S509.

  That is, in the present embodiment, in S506 and S507, whether or not the number TH (n) of sampling points exceeding the threshold value D (n) is within a predetermined range (0 <TH (n) ≦ α). It will be determined. Note that it may be configured to determine whether or not there is a sampling point exceeding the threshold value D (n), that is, only TH (n)> 0.

  In S508, the peak position detection unit 158 determines that the differential waveform can be analyzed. In step S509, the delay profile / peak position detection unit 15 determines that the differential waveform cannot be analyzed, and ends the determination operation as to whether the differential waveform can be analyzed.

(Frequency error integration)
As described above, the OFDM demodulator 1 calculates the frequency error by the following equation in S13 of FIG.

ppm (n) = ppm (n−1) + Δ ppm (n)
The above equation can also be expressed as Equation 1.

  That is, the clock frequency error detector 16 calculates the frequency error ppm (n) by integrating the cycle frequency error Δppm (n). The calculation of the frequency error will be described more specifically. The OFDM demodulator 1 detects Δppm (1) in the first detection cycle, and supplies it as a frequency error ppm (1) to the PLL 19 which is a frequency error correction circuit. That is, the frequency error ppm (1) is calculated by the equation ppm (1) = Δppm (1). Then, Δppm (2) is detected in the second detection cycle, and ppm (2) obtained by integrating the frequency error is supplied to the PLL 19, which is a frequency error correction circuit. That is, the frequency error ppm (2) is calculated by the equation ppm (2) = Δppm (2) + Δppm (1) (= Δppm (2) + ppm (1)).

  The advantage of integrating the detection result of Δppm (i) multiple times is that a feedback loop is formed by the flow of frequency error detection → frequency correction → next frequency error detection. It is a point which should just detect only.

  Thus, by gradually bringing ppm (i) closer to the true error, the difference from the true error to be detected decreases as i increases (Δppm (i) → 0). This makes it possible to perform more accurate error detection. It is also possible to cope with a change in frequency error after the frequency error is detected.

  The integration of the frequency error will be described in more detail as follows. As shown in FIG. 3, the peak position of the complex correlation strength indicates the effective symbol position of the OFDM broadcast wave, that is, the boundary position between the current symbol and the next symbol. The FFT unit performs an FFT process using this boundary position as a mark.

  For example, when the frequency on the receiver side is higher than that on the broadcast station side, the frequency error between the broadcast station and the receiving device is larger on the receiver side in the number of clocks per fixed time. For this reason, when the number of clocks is considered, the complex correlation strength of the elementary wave shown in FIG. 3 is shifted backward. Conversely, when the frequency on the receiver side is low, the complex correlation strength is shifted forward. As a result, the complex correlation strength is shifted every measurement cycle by Δpeak (n). Due to the effect of this shift, the data of the previous or next symbol appears within the FFT calculation period, interference occurs, and reception performance deteriorates.

  In the OFDM demodulator 1 according to the present invention, based on Δpeak (n) obtained in each detection cycle, a cycle frequency error Δppm (n) (= Δpeak (n) / N (n )) Is calculated. Δppm (n) includes fluctuations with respect to the true frequency error. Then, the magnitude of fluctuation changes due to the signal strength, the magnitude of noise, and the cause represented by Doppler shift when the receiving apparatus moves.

  Therefore, the cycle frequency error Δppm (n) is integrated for each detection cycle as shown in Equation 1 to obtain the frequency error ppm (n). By integrating with n = 1, 2, 3,..., an error component due to fluctuations included in the cycle frequency Δppm (n) detected in each detection cycle is canceled, and the frequency error ppm (n) is It approaches the true frequency error. Then, as the frequency error ppm (n) approaches the true frequency error, the cycle frequency error Δppm (n) obtained in each cycle also becomes smaller, so that a more accurate frequency error can be detected. As described above, after frequency error detection, integration, frequency error correction, and frequency correction, it is possible to accurately detect a frequency error by repeating the feedback cycle of frequency error detection.

  Further, in the OFDM demodulator 1 according to the present embodiment, as described in the flowchart of FIG. 10, only when the delay profile / peak position detector 15 determines that the detection of the peak position is valid in S5, the integral calculation is performed. The unit 162 performs frequency error integration processing.

  More specifically, when it is determined that the detection of the peak position is valid, the detected Δppm (n) value is set as a frequency error, but when the detection of the peak position is determined to be invalid, Δppm (n) = 0 is set. That is, the frequency error ppm (n) detected at the n-th time is expressed by Equation 2, and the frequency error is substantially integrated only when the detection of the peak position is effective.

  As a result, the influence of erroneous detection of the cycle frequency error Δppm can be reduced, and a more accurate frequency error can be obtained.

  In addition, as described above, the integration of the complex correlation value in the symbol direction in the first filtering unit 154 has restrictions such as reducing the number of integration points in order to improve the detection speed immediately after the start of frequency error detection, for example. May occur. In this case, since the number of integration points is small, Δppm (i) includes a relatively large error, and in some cases, the detected value of the cycle frequency error may greatly exceed the true frequency error. In this case, if the detection value is integrated as it is, ppm (n) may not converge to a true error.

  In this way, when the detected cycle frequency error is predicted to be large, the detected cycle frequency error is integrated by multiplying by a certain ratio, the elapsed time immediately after initialization or the number of symbols to be integrated Integrate by multiplying by the ratio determined by the internal state of the receiving device, such as the reception status. When the i-th ratio is β (i) (coefficient), the frequency error ppm (n) after n times is expressed by Equation 3.

  Here, the multiplication of β takes a value of 0 <β (i) ≦ 1 for the purpose of reducing the error. Thereby, the convergence to the true frequency error is delayed as compared with the case where β (i) is not multiplied, but the influence of the error can be reduced, so that the convergence can be performed more reliably.

(Peak position detection range)
In an environment where multipath occurs, if the intensity difference between the preceding wave and the delayed wave changes frequently, the intensity of the peak position of the preceding wave and the intensity of the peak position of the delayed wave may be switched, resulting in a very large frequency error. May be erroneously detected.

  Therefore, the OFDM demodulator 1 can be configured to limit the detection range of the peak position to prevent occurrence of a frequency error when the peak positions of the preceding wave and the delayed wave are switched. . This configuration will be described in more detail below.

  In the present embodiment, as shown in FIG. 7, the differential output of the complex correlation strength includes four peaks, of which the maximum error (second peak from the left) is used to detect the frequency error. . More specifically, the shift of the peak position of the second peak from the left is detected in the nth cycle and the n−1th cycle, and the frequency error is calculated from the detected peak position difference. For the detection of the frequency error, any configuration that uses the same peak throughout all the detection cycles, that is, a configuration that calculates the frequency error using the corresponding peaks in the nth cycle and the n−1th cycle may be used. . That is, a configuration using the minimum peak position (second peak from the right) may be used.

  FIG. 9 is a diagram showing an example of peak position detection when the differential peak position detection range is limited to ± W from the previously detected position, as described above. FIG. 9 shows the differential output waveform in the (m-1) th detection cycle and the differential output waveform in the mth detection cycle, and the intensity of the preceding wave increases sharply from the (m-1) th to the mth. It has become.

The OFDM demodulator 1 performs frequency error detection based on the peak position P _peak (m−1) of the delayed wave shown in FIG. 9 in the (m−1) th detection cycle. In the example shown in FIG. 9, the frequency error detection in the (m-1) th detection cycle is completed, and the peak position used for frequency error detection changes between the (m-1) th detection cycle and the mth detection cycle. Otherwise, the cycle frequency error Δppm (m) in the mth detection cycle should be zero.

However, if the peak position P ′ (m) of the complex correlation strength of the preceding wave is recognized as the peak position used for frequency error detection in the m-th detection cycle, the cycle frequency error Δppm (m) becomes P Since it has a significant value based on '(m) -P _peak (m), an erroneous frequency error is detected.

In order to prevent this, the OFDM demodulator 1 performs peak detection only in the range of P _peak (m−1) ± W in the m-th detection cycle. In the example shown in FIG. 9, in the m-th detection cycle, the peak value of the preceding wave (the peak value at the peak position P ′ (m)) is the peak value of the delayed wave (the peak value at the peak position P _peak (m)). Since it is outside the range of P _peak (m−1) ± W, the OFDM demodulator 1 determines that the peak position P ′ (m) of the preceding wave is not subject to detection, and P _peak (m− 1) The frequency error is calculated by determining the peak position P _peak (m) of the delayed wave within the range of ± W as the peak position for frequency error detection. Thereby, since the OFDM demodulator 1 has P _peak (m−1) and P _peak (m) at the same position, in the m-th detection cycle of the example shown in FIG. ) = 0.

  In this example, the detection range W of the peak position is constant. However, since it is necessary to detect a large frequency error when detecting an initial frequency error, a large frequency error is taken. After the frequency error detection is stabilized, only a small frequency error is detected. Therefore, it may be configured to take W small. In other words, the OFDM demodulator 1 may detect the peak position while changing the value of W according to the internal state of the receiver such as the elapsed time immediately after initialization, the number of symbols to be integrated, and the reception status.

  FIG. 26 is a diagram illustrating a configuration example of an OFDM receiving apparatus according to the present invention. The configuration shown in FIG. 26 analyzes the multipath interval from the positional relationship between the preceding wave and the delayed wave, calculates the necessary phase correction amount, and applies the correction. Considering the FFT calculation at the time of multipath, if an FFT window is set at the position of the preceding wave, the delayed wave is delayed by the delay and is input to the FFT calculation circuit, causing phase rotation. In order to correct this, as shown in FIG. 26, after calculating the optimum FFT window positions of the preceding wave (Tadv) and the delayed wave (Tdel) at 301, the phase correction amount is calculated as 303, and the FFT operation circuit This is corrected by giving a rotation to the output.

[Embodiment 2]
(Configuration of OFDM demodulator 50)
The configuration of the OFDM demodulator 50 according to this embodiment will be described below with reference to FIG. FIG. 12 is a block diagram showing a main configuration of the OFDM demodulator 50.

  As shown in FIG. 12, the OFDM demodulator 50 includes an analog-digital converter (ADC) 11, a sampling receiver 12, an orthogonal demodulation generator 13, a fast Fourier transform calculator (FFT unit) 14, a delay profile. Peak position detector 15, clock frequency error detector 16, fast Fourier transform window position detector (FFT window position detector) 17, frequency oscillator 18, sampling correction controller 20 (sampling timing specifying means, FFT) A window position control unit) and a frequency error correction unit 21. The OFDM demodulator 50 is connected to the tuner 10.

  The OFDM demodulator 50 according to the present embodiment has a configuration in which the frequency error is corrected by the delay profile / peak position detector 15, the clock frequency error detector 16, the sampling correction controller 20, and the frequency error corrector 21. The correction of the frequency error is repeatedly performed in the OFDM demodulation process. In the OFDM demodulator 50, the delay profile / peak position detector 15 detects the peak position of the complex correlation strength, and the clock frequency error detector 16 detects the frequency error based on the peak position of the complex correlation strength. The frequency error correction unit 21 corrects the frequency error using frequency error correction information (for example, a fractional delay amount) generated by the sampling correction control unit 20 based on the detected frequency error. The frequency error correction unit 21 interpolates the sampling value at the true sampling timing to bring the frequency error to 0 or close to 0.

  Analog-to-digital converter (ADC) 11, sampling receiver 12, quadrature demodulation generator 13, fast Fourier transform calculator (FFT unit) 14, delay profile / peak position detector 15, clock frequency error detector 16, fast Fourier transform Since the window position detection unit (FFT window position detection unit) 17 and the frequency oscillator 18 have been described above, description thereof is omitted here. Accordingly, only the sampling correction control unit 20 and the frequency error correction unit 21 will be described below.

  The sampling correction control unit 20 supplies frequency error correction information (for example, a fractional delay amount) for specifying the true sampling timing to the frequency error correction unit 21 based on the frequency error from the clock frequency error detection unit 16.

  The frequency error correction unit 21 corrects the frequency error by interpolating the sampling value at the true sampling timing specified by the fractional delay amount. Then, the frequency error correction unit 21 supplies the interpolated sampling data to the orthogonal demodulation generation unit 13.

  In the first embodiment, the operation clock frequency supplied by the PLL is corrected. However, the feature of this embodiment is that the operation clock frequency is kept constant and is effectively corrected by data processing called interpolation processing. Therefore, since the OFDM demodulator 50 according to the present embodiment can correct the frequency error by performing interpolation processing on the sample series signal based on the detected frequency error, the clock frequency of the PLL or the like can be changed. Even in an OFDM demodulator that cannot be used, it is possible to correct a deviation between a transmission clock frequency of a broadcast wave transmitted from a broadcast station and a sampling frequency in the receiver.

(Fractional delay filter)
The OFDM demodulator 50 corrects the frequency error by interpolating the sampling data using a fractional delay (interpolation) filter. Examples of the fractional delay filter include a Lagrange interpolation filter, a Farrow filter, and a modified Farrow filter. For details of the fractional delay filter, see, for example, “Chapter 7. Resampling Filters” of “Multirate Signal Processing for Communication Systems” (Fredric Harris, 2004, Prentice Hall).

  If input sample data is {x (0), x (1),..., X (n−1), x (n), x (n + 1),. When the nth sampling value x (n) is input to the filter, N + 1 sampling values {x (n−N), x (n−N + 1),. x (n-1), x (n)} are stored. Then, the fractional delay filter performs N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n) input before the given delay amount D. −1), x (n)}, a sampling value x (n−D) that is D-delayed with respect to the sampling value x (n) currently input is calculated by interpolation processing. Here, the delay amount D may be an integer or a fraction. Interpolation processing when the delay amount D is an integer is called integer delay processing, and interpolation processing when the delay amount D is a fraction is called fractional delay processing. FIG. 13 shows a fourth-order fractional delay filter immediately after x (4) is input. When D = 1 + 1/3 is given as a delay amount, as shown in FIG. 13, the fractional delay filter has five sampled values {x (0), x (1), x From (2), x (3), x (4)}, a fractional delay process is performed to calculate x (4-D) = x (2 + 2/3).

(Lagrange interpolation filter)
The Lagrange interpolation filter will be described with reference to FIG. FIG. 14 is a diagram illustrating a configuration of a FIR (Finite Impulse Response) filter. The coefficients of the FIR filter shown in FIG.

This FIR filter is an interpolation filter for obtaining a value at an interpolation point n-D corresponding to the delay amount D from discretized data in integer time held in a register, and is generally called a Lagrange interpolation filter. The Lagrange interpolation filter is effective even when the delay amount D is a fraction, and a fractional delay filter can be realized. In the Lagrange interpolation filter, when the target point to be interpolated changes with time, it is necessary to calculate the filter coefficient by the calculation of Equation 4 each time. However, since one coefficient per N multipliers are required, N ² multipliers across FIR filter is required. The transfer function (Z function) of this FIR filter is expressed by Equation 5.

  Further, the frequency characteristic of this FIR filter is expressed by Equation 6. Further, the theoretical value Dint of the delay amount in the output signal (hereinafter simply referred to as “delay amount Dint”) is expressed by Equation 7 using the phase component Θ of Equation 6.

  The filter characteristics of the FIR filter, that is, the Lagrange interpolation filter will be described with reference to FIG. FIG. 15 is a diagram illustrating filter characteristics when the delay amount D is changed in a Lagrange interpolation filter with N = 7, (a) is a diagram illustrating amplitude frequency characteristics, and (b) is It is a figure which shows the calculated delay amount Dint, (c) is a figure which shows the signal noise power ratio (SNR) which considered both the amplitude and the phase. In FIG. 15, the horizontal axis represents a normalized frequency obtained by normalizing the frequency f by the sampling frequency Fs. Further, the vertical axis in FIG. 15A is decibel (dB), and the vertical axis in FIG. 15B is the sampling period Ts.

  In FIG. 15A, the frequency component with | H | = 0 dB is output as it is without being attenuated in strength. Further, it can be seen from FIG. 15B that the delay amount Dint obtained from the output signal matches the set value D.

  The frequency region where | H | = 0 dB in FIG. 15A and Dint≈D in FIG. 15B is a frequency region that can be subjected to fractional delay processing in this Lagrange interpolation filter (hereinafter, fractional delay frequency region). Called). Increasing N increases the fractional delay frequency region, but also increases the circuit scale.

(Farrow Structure)
Hereinafter, the Farrow type fractional delay filter and the modified Farrow type fractional delay filter will be described. FIG. 16 is a diagram illustrating a configuration of a Farrow type fractional delay filter. As shown in FIG. 16, the Farrow-type fractional delay filter is obtained by Honer combining a plurality of N-order FIR filters. Here, considering the determinant defined by Equations 8 to 10, the FIR filter constituting the Farrow fractional delay filter shown in FIG. 16 is defined by C _n (z) shown in Equation 11. That is, the n-th column vector q _n (k) of the coefficient matrix Q of Equation 9 (Equation 10) corresponds to the filter coefficient of the FIR filter C _n (z).

  As with the Lagrange interpolation filter, the Farrow type fractional delay filter can also be interpolated with an arbitrary delay amount D. However, in the Farrow type fractional delay filter, the multiplications for the delay amount D are all N-1. Therefore, the Farrow type fractional delay filter can be configured with a smaller circuit scale than the Lagrange interpolation filter.

  The filter characteristics of the Farrow type fractional delay filter will be described with reference to FIG. FIG. 17 is a diagram showing filter characteristics when the delay amount D is changed in a Farrow type fractional delay filter of N = 7, (a) is a diagram showing amplitude frequency characteristics, and (b) is a number. 7 is a diagram illustrating a delay amount Dint calculated by 7 and (c) is a diagram illustrating a signal noise power ratio (SNR) in consideration of both amplitude and phase. The vertical and horizontal axes in FIG. 17 are the same as those in FIG. As in FIG. 15, the frequency component (f≈−0.2 Fs to +0.2 Fs) with | H | = 0 dB in FIG. Further, FIG. 17B shows that the delay amount Dint obtained from the output signal matches the set value D.

  The order of the filter coefficients differs depending on what is important when applying the present invention to an actual system, and is not particularly limited. For example, when emphasis is placed on the actual interpolation timing, the frequency region where Dint≈D in FIG. 17B is considered in the frequency region where fractional delay processing is possible with this Farrow type fractional delay filter. There is also a method of studying with an SNR considering the amplitude and phase in total. For example, the required CNR (Carrier to Noise Ratio) when the modulation method is QPSK slightly changes depending on the coding rate, but is around 4 dB. In this case, the calculation error of SNR ≧ 20 dB can be ignored. Therefore, in the filter having the characteristics of FIG. 17, it is possible to secure a calculation error of SNR ≧ 20 dB in the frequency band component of f = −0.3 Fs to +0.3 Fs from FIG. On the other hand, the required CN of 64QAM varies slightly depending on the coding rate, but is around 20 dB. In this case, since the calculation accuracy of SNR≈20 dB affects the required CN, a calculation accuracy of 30 dB or 40 dB or more is required. From FIG. 17C, it is possible to secure a calculation error of SNR ≧ 40 dB in the frequency band component of f = −0.2 Fs to +0.2 Fs. Thus, if parameters such as the modulation method and coding rate are determined, the required calculation accuracy is determined. The filter order N can be determined by comparing the required calculation accuracy with the calculation accuracy of the filter.

  A modified Farrow type fractional delay filter is a modified Farrow type fractional delay filter. Here, when the matrix T and the matrix Q ′ are defined by Equations 12 and 13, respectively, a combination of a plurality of FIR filters defined by C′n (z) of Equation 14 and Honer combination as shown in FIG. This is called a Farrow type fractional delay filter. That is, the Farrow-type fractional delay filter and the modified Farrow-type fractional delay filter both have the configuration shown in FIG. 16, and only the coefficients are different.

  The Farrow-type fractional delay filter and the modified Farrow-type fractional delay filter differ in the way of setting interpolation points, but share the function of fractional delay processing. The delay amount D given to the Farrow filter is round (N / 2) −1/2 <D <round (N / 2) +1/2 (where round (N / 2) −1/2 <D <round (N / 2) +1/2) in consideration of the number of stages of the shift register in FIG. x) is set within the range of the rounded value of x). That is, it is set within a range of ± 1/2 centering on round (N / 2). On the other hand, the delay amount D ′ applied to the modified Farrow filter is set within a range of ± 1/2 centering on 0. That is, the delay amount D ′ is set within a range of −1/2 <D ′ <+ 1/2. Thus, the delay amount setting method is different. However, when the delay amount D and the delay amount D ′ satisfy the relationship D ′ = D−round (N / 2), the interpolation processing for the Farrow type delay amount D is performed for the modified Farrow type delay amount D ′. It corresponds to processing.

  In the following description, when a Lagrange interpolation filter or a Farrow type fractional delay filter is used, the delay amount D is input to the filter. When a modified Farrow type fractional delay filter is used, a delay is applied to the filter. Assume that the quantity D ′ is entered. The Lagrange interpolation filter or Farrow type fractional delay filter can be interpolated even when a delay amount D outside the range of round (N / 2) -1/2 to round (N / 2) +1/2 is given. is there. That is, the delay amount D may be set, for example, within a range of ± 1/2 sampling points centered around round (N / 2) +1 or round (N / 2) −1. Alternatively, it may be set in the range of round (N / 2) to round (N / 2) +1. Similarly, the fractional delay amount D ′ of the Farrow type fractional delay filter may be set in the range of 0 <D ′ <+ 1 or −1 <D ′ <0.

  Similar to the Lagrange interpolation filter, the frequency region in which | H | = 0 dB in FIG. 17A and Dint≈D in FIG. 17B is the frequency region in which fractional delay processing is possible with this Farrow type fractional delay filter. Become. Further, the fractional delay frequency region is proportional to the circuit scale.

  Note that the N = 7 Lagrange interpolation filter shown in FIG. 15 and the Farrow-type fractional delay filter shown in FIG. 17 can ensure a wide fractional delay frequency region by the fractional delay processing of D = 3-4. Thus, in the case of the Farrow type fractional delay filter, the Nth order fractional delay filter is modified Farrow by performing fractional delay processing in the range of round (N / 2) −½ to round (N / 2) + ½. In the case of a type fractional delay filter, a wide fractional delay frequency region can be secured by fractional delay processing of D = −1 / 2 to +1/2.

(Frequency error correction)
As described above, in the OFDM demodulator 50 according to the present invention, the frequency error is corrected by the frequency error correction unit 21 and the FFT unit 14.

  The frequency error detection unit 16 includes a carrier frequency of a digital broadcast wave (that is, a sampling frequency in OFDM modulation on the transmission side) and an operation clock frequency supplied from the PLL in the OFDM demodulator 50 (that is, in OFDM demodulation on the reception side). The frequency error α with respect to the sampling frequency is detected and supplied to the sampling correction control unit 20. Here, the digital signal obtained by OFDM modulation on the transmission side corresponds to the first sample series signal sampled at the first sampling timing in the claims. And the digital signal (digital signal generated by the ADC 11) subject to OFDM demodulation on the receiving side corresponds to the second sample series signal generated by sampling at the second sampling timing in the claims. To do.

  The sampling correction control unit 20 calculates a sampling timing error as information for correcting the frequency error from the frequency error α, and supplies the fractional part to the frequency error correction unit 21. The sampling timing error is the difference between the sampling timing when sampling the digital broadcast wave received by the OFDM demodulator 50 and the true sampling timing (sampling timing at the time of OFDM modulation at the broadcasting station). The method for calculating the sampling timing error in the sampling correction control unit 20 will be described in more detail as follows.

  In the OFDM demodulator 50, assuming that the receiving side sampling frequency is F's, the true sampling frequency is Fs, and the true sampling clock period is Ts, the receiving side sampling clock period T's is expressed by Equation 15 using the frequency error α.

  Further, the sampling timing error δTs per clock cycle (deviation of the true sampling clock cycle Ts with respect to the receiving-side sampling clock cycle T ′s) is expressed by Equation 16.

  For example, when the MT's time has elapsed in the OFDM demodulator 50, the total error is M times δTs shown in Equation 16. Therefore, if the sampling timing error MδTs (in seconds) is corrected with a fractional delay filter that operates at the receiving-side sampling frequency F ′s, it is possible to extract a value at the true sampling timing.

  The sampling correction control unit 20 calculates the sampling timing error not in units of seconds but in units of reception side sampling clock cycles. That is, the sampling correction control unit 20 calculates the sampling timing error Δ from the frequency error α according to Equation 17.

  Then, the sampling correction control unit 20 decomposes the calculated sampling timing error Δ into an integer part Δint and a fractional part (fractional part) Δfrac (Δ = Δint + Δfrac). Then, the fractional part Δfrac of the sampling timing error Δ is given to the frequency error correction part 21 as sampling timing error information, and the integer part Δint of the sampling timing error Δ is given to the FFT part 14 as sampling timing error information.

  When the frequency error correction unit 21 receives the sampling timing error information Δfrac, the frequency error correction unit 21 performs a fractional delay filter process according to the sampling timing error information Δfrac. For example, when an Nth-order Lagrange filter or Farrow type fractional delay filter is used as the fractional delay filter, D = round (N / 2) −Δfrac is input to the fractional delay filter to obtain a sample value at the true sampling timing. . When an Nth-order modified Farrow-type fractional delay filter is used as the fractional delay filter, D ′ = − Δfrac is input to the fractional delay filter to obtain a sample value at the true sampling timing.

  On the other hand, the FFT unit 14 operates at the reception-side sampling frequency F ′s, and can shift the FFT calculation start time in units of the reception-side sampling clock period T ′s. When the integer part Δint of the sampling timing error information Δ changes, that is, when the sampling timing error MδTs (in seconds) changes by ± T ′s, the FFT calculation start position is shifted by ± T ′s so as to cancel it.

  In this way, by correcting the fractional part Δfrac of the sampling timing error information Δ by the frequency error correction unit 21 and the integer part Δint by the FFT operation unit 14, the entire sampling timing error information Δ can be corrected.

  More specifically, the frequency error correction unit 21 uses the equation 18 for the Lagrange filter, the equation 19 for the Farrow type fractional delay filter, and the equation 20 for the modified Farrow type fractional delay filter. The sampling value at the interpolation point corresponding to the delay amount D or D ′ is interpolated. As described above, the Lagrange interpolation filter and the Farrow-type fractional delay filter obtain the D-delayed sampling value x (n−D) by interpolation when the n-th sampling value x (n) is input. Specifically, the Lagrange interpolation filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}. , X (n−D) is calculated according to Equation 18. Further, the Farrow type fractional delay filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}, X (n−D) is calculated according to Equation 19. The modified Farrow-type fractional delay filter refers to N + 1 sampling values {x (n−N), x (n−N + 1),..., X (n−1), x (n)}. , X (n−D) is calculated according to Equation 20. However, as can be seen from Equation 20, when calculating x (n−D), D ′ = D-round (N / 2) is designated for the modified Farrow type fractional delay filter, not the delay amount D itself. (Input) needs to be done.

  As described above, D = round (N / 2) −Δfrac may be input to the Lagrange filter and the Farrow-type fractional delay filter. On the other hand, D ′ = − Δfrac may be input to the modified Farrow type fractional delay filter. As a result, interpolation can be performed at the same timing within the sampling period T's whether the Lagrange filter or the Farrow type fractional delay filter is used as a fractional delay filter or when the modified Farrow type fractional delay filter is used as a fractional delay filter. it can.

  Since D and D 'are delay amounts, their time axes are set from the present to the past. On the other hand, since the time axis of the timing error information Δ is set from the present to the future, a minus sign is added before Δfrac. When the time axis of D or D ′ is defined from the present to the future in the implementation of the filter, D = round (N / 2) + Δfrac and D ′ = + Δfrac. Thus, when the fractional part Δfrac is input to the fractional delay filter, it is necessary to pay attention to the direction of the time axis in Δfrac, D, and D ′.

  Note that the possible range of the fractional part Δfrac may be −0.5 ≦ Δfrac <+0.5 or 0 ≦ Δfrac <+1. There is no problem in adopting an optimal definition based on the characteristics of the sampling value prediction means used for the implementation and the specifications of the control circuit. The integer part may be defined in accordance with the fractional part Δfrac.

Note that the filter coefficient qn (k) in Expression 19 is an element Q (n, k) of the matrix Q in Expression 10, and Σq _n (k) x (n−k) constitutes the Farrow type filter shown in FIG. 16 corresponds to each FIR filter Cn (z), and Σ {D ⁿ (Σq _n (k) x (nk))} corresponds to the Honer method shown in FIG. Further, the filter coefficient q′n (k) of Expression 20 is an element Q ′ (n, k) of the matrix Q ′ of Expression 13.

  In the OFDM demodulator 50 according to the present embodiment, the frequency error correction unit 21 is repeated by repeating the above processing in the frequency error detection unit 16, the sampling correction control unit 20, the frequency error correction unit 21, and the FFT unit 14. The frequency error at the time of output is converged to 0 or near 0.

  The correction of the frequency error in the OFDM demodulator 50 will be described as follows with reference to FIGS. 18 and 19.

  FIG. 18 is a diagram for explaining a sampling timing error between the sampling timing of the OFDM demodulator 50 and the true sampling timing. In the example shown in FIG. 18, the operation clock cycle of the OFDM demodulator 50 is T's, and sampling is performed every T's. However, the sampling clock cycle in the digital baseband processing at the broadcasting station is Ts, and one cycle A state in which an error of δTs occurs for each time is shown. Here, if the timing at which the sampling timing of the OFDM demodulator 50 coincides with the true sampling timing is t = 0, the timing error at the time of sampling at t = T ′s is δTs, and the timing error at the time of sampling at t = 2T ′s. Is δTs × 2, and the timing error at the time of sampling at t = 3T ′s is δTs × 3. That is, the timing error at the time of sampling at t = MT ′s is MδTs.

  At this time, the sampling correction control unit 20 calculates the sampling timing error Δ = Mα by Equation 17 using the frequency error α received from the frequency error detection unit 16. Then, the fractional part Δfrac of the sampling timing error Δ is supplied to the frequency error correction unit 21, and the integer part Δint of the sampling timing error Δ is supplied to the FFT unit 14. Then, the frequency error correction unit 21 refers to the fractional part Δfrac of the sampling timing error Δ to calculate the sampling value at the true sampling timing, and the FFT unit 14 refers to the integer part Δint of the sampling timing error Δ. Shift the start position of the FFT operation.

  The Lagrange filter calculates an interpolation value at the same interpolation point unless the filter coefficient h (k, D) is changed. On the other hand, in the Farrow type fractional delay filter and the modified Farrow type fractional delay filter, although both the filter coefficients qn (k) and q′n (k) are always fixed, the multiplier (× By changing the value of D), it is possible to dynamically change the point at which interpolation processing is performed.

  FIG. 19 is a diagram showing an image of interpolation processing using a modified Farrow type fractional delay filter, and FIG. 19A is a diagram showing an image of interpolation processing at a certain sampling timing (t = 4T ′s), and FIG. FIG. 4 is a diagram showing an image of interpolation processing at the next sampling timing (t = 5T ′s) of (a).

  In the example shown in FIG. 19, at time t = 4T's, as shown in (a), the true sampling timing (from the five sampling values X (0) to X (4) stored in the register ( The sampling value X (4-D) = X (2-D ′) at the interpolation point corresponding to the delay amount D ′ is calculated, and stored in the register at time t = 5T ′s as shown in FIG. The sampling value X (5-D) = X (3-D ′) at the true sampling timing is calculated from the five sampling values X (1) to X (5). In the example of the modified Farrow-type fractional delay filter shown in FIG. 19, the delay amount D ′ = − Δfrac, and the frequency error correction unit 21 performs the calculation of Equation 20.

  As a result, at each sampling timing in the OFDM demodulator 50, data at the true sampling timing (sampling timing at a broadcasting station that performs OFDM modulation) is sequentially interpolated, so that the frequency error can be corrected.

  The OFDM demodulator according to the present invention may be configured to be connected to a direct conversion type tuner. The tuner receives a digital broadcast wave from a broadcast station, orthogonally demodulates it, generates a baseband OFDM signal composed of an I channel signal and a Q channel signal, and supplies the baseband OFDM signal to an OFDM demodulator. The above-described sampling reception and frequency error correction are performed on the I channel signal and Q channel signal from the tuner, and the frequency error is corrected by the same operation as the OFDM demodulator 50.

  FIG. 20 is a diagram illustrating an example of a configuration for correcting a clock frequency error using a fractional delay filter. The OFDM demodulator 50 according to the present embodiment can also be realized by a configuration example as shown in FIG.

(Oversampling)
The processing and control of the fractional delay filter in the configuration for correcting the frequency error using oversampling will be described. In the OFDM demodulator 50, the ADC 11 or the sampling receiver 12 performs oversampling.

  In the Lagrange interpolation filter and the Farrow type fractional delay filter, as shown in FIGS. 15 and 17, the entire Nyquist region is not the fractional delay frequency region. If the range of about 80% of the Nyquist region is set to the fractional delay frequency region, the order of the Lagrange interpolation filter or the Farrow type fractional delay filter is N ≧ 200, so that circuit implementation is not practical.

Therefore, a filter that can secure the fractional delay frequency region required according to the application is designed. In other words, the width of the desired fractional delay frequency domain as _{F 1,} consider designing a possible filter fractional delay process in the range of _{f = -F 1 / 2~ + F} 1/2. The actual design of OFDM demodulator, the sum of the margin of the carrier frequency error allowed in the frequency band of the OFDM wave is equivalent to F _1.

By the way, it can be seen from FIG. 17B that fractional delay processing is correctly performed in the frequency range of ± 0.2 Fs, and the error is small. Therefore, if the sampling frequency is Fs = 5F ₁ , fractional delay processing is correctly performed in the frequency region of ± F ₁ (= ± 0.2 × 5F ₁ ). That is, when the desired fractional delay frequency region cannot be realized at the reference clock frequency, the sampling frequency is converted into an oversampling state according to the desired fractional delay frequency region, thereby enabling interpolation in the entire desired frequency region. According to the “Multirate Signal Processing for Communication Systems” described above, rate conversion at an integer multiple sampling frequency is a general technique that surpasses digital signal processing. By applying this rate conversion to the OFDM demodulator 50, a wide fractional delay frequency region can be realized by a Farrow type fractional delay filter having a low order N. A configuration in which the sampling rate conversion function and the Farrow type fractional delay filter with a low order N are combined can be easily implemented on a smaller scale than a filter with N ≧ 200.

The sampling frequency is not limited to Fs = 5F _1. For example, from FIG. 17B, when it is necessary to reduce the error, it is necessary to further increase the conversion rate. Conversely, if it is desired to lower the sampling frequency with emphasis on reducing power consumption rather than error, the rate conversion ratio needs to be made smaller.

(Fraction delay processing shift)
FIG. 21 is a block diagram showing a configuration of another OFDM demodulator 51 according to the present invention. The OFDM demodulator 51 includes the same blocks as those of the OFDM demodulator 50 shown in FIG. 1, and each block included in the OFDM demodulator 51 is assigned the same reference numeral in the OFDM demodulator 50 shown in FIG. It has the same basic functions as the block. Hereinafter, operations different from those of the OFDM demodulator 1 of FIG. 1 in each block of the OFDM demodulator 51 will be described.

  The difference from the OFDM demodulator 1 in FIG. 1 is that the sampling clock shift amount is supplied from the sampling correction control unit 20 to the frequency error correction unit 21 and the FFT window shift is similarly performed from the sampling correction control unit 20 to the FFT unit 14. The amount is in the supply.

  As described above, for example, in the modified Farrow type filter, the delay amount D ′ = − Δfrac (fractional delay amount). If the filter characteristic is the characteristic as shown in FIG. Considering calculation error, when N is an even number, it is set within the range of −1/2 <D ′ <+ 1/2, and when N is an odd number, it is set within the range of 0 <D ′ <1. (The upper limit value and the lower limit value are both in units of the sampling clock period on the receiving side). Therefore, even when the fractional delay amount exceeds the range of a finite value (for example, -1/2 to +1/2), a configuration for correcting the frequency error is required. The finite value range corresponds to the predetermined sampling timing range in the claims.

  The operation of the OFDM demodulator 51 will be described below. The sampling clock shift amount and the FFT window shift amount described above are used when the fractional delay amount exceeds the finite value described above. In the OFDM demodulator 51, the sampling clock shift to the frequency error correction unit 21 is performed. By supplying the amount and the FFT window shift amount to the FFT unit 14 in conjunction with each other, a configuration for correcting the frequency error without fail even when the fractional delay amount exceeds a finite value is realized.

  When the time elapsed in the OFDM demodulator 51 is expressed as MT ′s (T ′s is the sampling period in the OFDM demodulator 51) described above, the value of M increases monotonically as time elapses if demodulation is continued. However, the area that can be corrected by the fractional delay filter is finite, and when M increases, the sampling timing error Δ = Mα exceeds the finite value described above.

  Here, taking the case of the modified Farrow type fractional delay filter as an example, the delay amount D ′ = − Δfrac is set to −1/2 to +1/2. Therefore, in the OFDM demodulator 51, if D ′ = + − 1/2 as a result of an increase in M, then it is changed to D ′ = − + 1/2 as shown in FIG. FIG. 22 is a diagram illustrating an example of correcting the sampling value. Each row in FIG. 22 represents the timing within the symbol. The time advances in sampling units from the left to the right of each row, and in symbols from the upper row to the lower row. In FIG. 22, a thick arrow indicates the reception side sampling timing based on the operation clock, and a thin arrow indicates the true sampling timing of the broadcast wave. When the frequency error is constant, the true timing is shifted at regular intervals with time as shown in FIG. Since it is difficult to display the entire symbol in the sampling clock cycle, only the vicinity of the FFT window position is enlarged and displayed in FIG. At the same time, the FFT window is shifted by 1T ′s in the direction opposite to the change of D ′. This is equivalent to shifting the integer part Δint and the fractional part Δfrac of the sampling timing error Δ by 1T ′s in the opposite direction. The total Δ is unchanged before and after the shift. By this processing, the delay amount D ′ and Δfrac can be set to −1/2 to +1/2. In FIG. 22, the processing is performed at the falling timing of the reception side sampling clock, but conversely, the processing may be performed at the rising timing. In that case, the rising and falling in the figure may be reversed.

  For example, if the state shown in FIG. 19B is D ′ = 2/3, for example, the delay amount D ′ exceeds a finite value (= 1/2), and an interpolation value cannot be calculated with high accuracy. . In the example shown in FIG. 19, a fractional delay amount with n = 0 as the reference sampling timing is set as the delay amount D ′ corresponding to the true sampling timing. However, the interpolation point corresponding to the delay amount D ′ is closer to the sampling timing of n = 1 than the sampling timing of n = 0. That is, instead of using n = 0 as the reference sampling timing, the delay amount D ′ is set to a finite value −1/2 to +1/2 by using the delay amount D ′ using n = 1 as the reference sampling timing. The interpolation value (sampling value at the true sampling timing) can be calculated with high accuracy.

  In updating the reference sampling timing, the sampling timing error Δ (sampling clock unit) calculated for each sampling clock is divided into an integer part Δint and a fractional part Δfrac, and the delay amount D ′ is set as D ′ = − Δfrac. (When D ′ falls within the range of −1 to 0). If D ′ falls within −1/2 to +1/2, for example, the delay amount D ′ may be calculated by subtracting 1/2 from the fractional part of (Δ + 1/2). The sampling correction control unit 20 supplies the delay amount D ′ calculated in this way to the frequency error correction unit 21 as a sampling clock shift amount, and simultaneously calculates the integer part of (Δ + 1/2) calculated at the same time as the FTT window shift amount. To the FTT unit 14. Alternatively, the start timing of the FFT window may be generated considering the shift by the integer part, and the start timing may be supplied to the FFT unit 14.

  The frequency error correction unit 21 (1) latches new data in the modified Farrow type fractional delay filter, (2) acquires the delay amount D ′ from the sampling correction control unit 20, and (3) acquires the acquired delay amount D ′. Is input to the modified Farrow-type fractional delay filter to repeat a series of processes for obtaining a new sampling value for each sampling clock. At the same time, the FFT unit 14 acquires (1) the FFT window shift amount (an integer part of Δ + 1/2) from the sampling correction control unit 107, and (2) the acquired FFT window shift amount is the same as the previously acquired FFT window shift amount. When the number is increased or decreased by ± 1 (and only in that case), a series of processes of shifting the FFT calculation start position by ± T ′s is repeated for each sampling clock. Or you may comprise so that an FFT window may be set and FFT processing may be performed according to the FFT window start timing which the frequency error correction | amendment part 21 supplies.

  As a result, the fractional delay amount does not always exceed a finite value, and D ′ falls within the range of −1/2 to +1/2. Further, as shown in FIG. 22, the FFT window always starts at the same timing with respect to the sampling clock. That is, the sampling timing error due to the frequency error can be corrected in an infinite time without being restricted by the interpolation point range (that is, the fractional delay range restriction).

(Interpolation processing in oversampled state)
Further, as described above, when the fractional delay process is performed in the oversampled state, the fractional delay frequency region is effectively widened as described above. Here, however, the fractional delay frequency region exceeds four times the FFT standard sampling clock frequency Fs. Consider the case of sampling and performing fractional delay processing. Even when fractional delay processing is performed by oversampling, the final timing correction target is to correct the error in the Fs clock. Therefore, in order to perform a fractional delay (D ′ = − 1/2 to +1/2) with respect to the reference sampling clock, an integer delay (D ′ = ± 0, ± 1, ± 2, ± 3) with respect to the oversampling clock ( (Hereinafter referred to as “oversampled integer delay”) and fractional delay fractional delay (D ′ = − 1/2 to +1/2) with respect to the oversampling clock (hereinafter referred to as “oversampled fractional delay”) It becomes.

  In this case, the frequency error correction unit 21 that receives the sampling clock shift amount has a configuration in which a sampling clock shift unit is added. FIG. 23 is a diagram showing a specific configuration of the frequency error correction unit 21 corresponding to the integer delay processing.

  As shown in FIG. 23, the frequency error correction unit 21 includes integer delay units 2032 and 2033 for oversampled integer delays (D ′ = ± 0, ± 1, ± 2, ± 3), and oversampled fractional delays (D This is a configuration including a fractional delay unit 2031 for '= -1 / 2 to +1/2). The integer delay unit 2032 is an integer delay unit that corrects the frequency error when the frequency deviation is negative, and the integer delay unit 2033 is an integer delay unit that corrects the frequency error when the frequency deviation is positive. That is, when fractional delay processing is performed in the oversampled state, the oversampled integer delay amount is also shifted while the oversampled fractional delay amount is shifted by the configuration shown in FIG.

  Hereinafter, the oversampled integer delay and the oversampled fractional delay in the oversampling state will be described in more detail. When oversampling is not performed (ie, Fs clock), when the fractional delay amount exceeds a finite value, the oversampled fractional delay amount is changed from D ′ = + − 1/2 to D ′ = − + 1/2. At the same time, as described above, it is necessary to shift the disclosure timing of the FFT window in the reverse direction.

  On the other hand, when the oversampling rate conversion ratio is an integer oversampling state, for example, when the oversampling clock is 4 Fs clock, the oversampling delay amount is changed from D ′ = + − 1/2 to D ′ =. By changing to-+ (4-1 / 2), the start timing of the FFT window is shifted in the reverse direction by the Fs clock and one period T's. That is, it is necessary to shift the oversampled integer delay amount in accordance with the oversampling state. However, as shown in FIG. 23, the frequency error correction unit 21 has a total oversample delay amount before and after the fractional delay filter 2031. With the configuration in which the integer delay units 2032 and 2033 that can be selected are provided, the oversampled integer delay amount can be shifted.

  Further, the rate conversion ratio may be a non-integer due to the restriction of the entire baseband processing unit. For example, when 4.5 times oversampling, 4.5 Fs clock oversampled integer delay (D ′ = ± 0, ± 1, ± 2, ± 3) and oversampled fractional delay (D ′ = − 1/2) Timing adjustment is performed in both of (˜ + 1/2).

  However, in this case, care must be taken because the FFT window start timing is shifted in units of the cycle Ts of the FFT reference clock frequency. Therefore, when the oversampling clock is 4.5 Fs clock, the oversampling delay amount is changed from D ′ = + − 1/2 to D ′ = − + (4.5−1 / 2), but the FFT window starts. The timing is shifted in the reverse direction by the same amount as when the Fs clock is 1 cycle Ts, that is, when the oversampling clock is 4Fs clock.

  In the above description, the case where the rate conversion ratio is 4 times and 4.5 times has been described as an example, but the rate conversion ratio is not limited to this. It can be implemented in the same manner at an arbitrary rate conversion ratio according to the calculation accuracy of fractional delay processing and the request for baseband signal processing.

  In the above-described embodiment, orthogonal detection is performed inside the OFDM demodulator 1, but quadrature detection is performed in a tuner connected outside the OFDM demodulator 1 and the OFDM demodulator 50, and the OFDM demodulator 1 and It is also possible to employ a configuration in which the OFDM demodulator 50 receives the IQ component output after quadrature detection and performs frequency error detection and frequency error correction.

  In the configuration of the first embodiment, the detected frequency deviation is given to the PLL 403 to correct the frequency error of the operation clock. That is, the operation clock fluctuates in the PPM order due to the frequency error correction. On the other hand, in the configuration of the second embodiment, the frequency error of the data string is corrected by interpolation processing while the operation clock frequency remains constant. That is, the operation clock does not fluctuate, and the correction target is the difference between the operation clock and the data string.

(Additional notes)
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  In addition, this invention is realizable also as the following structures.

(First configuration)
An error correction encoded data signal;
Frame synchronization signal and control signal,
An effective symbol is generated by performing orthogonal frequency division multiplexing modulation on a pilot signal that is a reference for waveform equalization processing, and the effective symbol and a guard interval formed by copying the same content as a part of the effective symbol In an OFDM demodulator for receiving and demodulating a digital transmission wave by an orthogonal frequency division multiplex modulation (OFDM) system including a transmission symbol provided,
Use a different clock source from the broadcast station,
Complex correlation calculation means for outputting a complex correlation value for each sample of the received sample sequence signal obtained by sampling the broadcast wave and a delayed signal obtained by delaying the received sample sequence signal by an effective symbol period;
First filter means for filtering the complex correlation value by integrating a predetermined number of symbols in the symbol direction and dividing by the number of symbols to output a complex correlation calculation value series signal;
A complex correlation strength calculating means for calculating a complex correlation strength of the complex correlation calculation value;
A second filter means for filtering the complex correlation strength in a direction in which data is sampled and outputting a complex correlation strength calculation value;
Differential means for receiving the output of the second filter means and differentiating the complex correlation strength calculation value;
Differential output peak position detection means for detecting the peak position of the value output by the differentiation means;
Storage means for storing peak position information output by the differential output peak position detection means for each period in which the differential output peak position detection means outputs peak positions;
The clock frequency error is calculated based on the difference between the differential output peak position stored in the storage means and the peak position output by the differential output peak position detection means, and the period in which the differential output peak position detection means outputs the peak position. A clock frequency error detecting means for detecting;
The selection of the OFDM demodulator characterized by having means for receiving the clock frequency error information output from the clock frequency error detection means in the previous period and correcting the deviation between the operation clock of the broadcasting station and the operation clock of the receiver. A content reproduction apparatus that makes it possible to make decisions.

(Second configuration)
An OFDM demodulator characterized in that the means for adjusting the frequency of the operation clock described in the first configuration to the true sampling frequency in the broadcast wave is an increase or decrease in the clock frequency of the clock source.

(Third configuration)
A sampling correction control unit that calculates a fractional delay amount corresponding to true sampling timing from the frequency error information;
Interpolation means characterized by calculating a sampling value in a fractional delay amount output by the correction control unit of the sample series signal by interpolation processing,
The OFDM demodulator according to the first configuration, wherein the sampling timing is adjusted to the broadcast wave without increasing or decreasing the frequency of the clock source.

(Fourth configuration)
Having oversampling means;
The oversampling means converts the sampling frequency of the sample sequence into an oversampling state with respect to a reference clock frequency,
The OFDM demodulator according to the third configuration, wherein the interpolation processing performs interpolation processing of the oversampled data sequence.

(Fifth configuration)
First filter means;
A second filter means;
Differential means;
Differential output peak position detection means;
A threshold value calculation circuit for calculating a threshold value based on outputs of all the symbol periods of the differentiating means;
A threshold passage determining circuit for determining whether or not the differential output exceeds a threshold;
A count circuit that counts whether the threshold passage discrimination circuit has passed the threshold across the differential output; and
When the previous period count circuit is less than or equal to a predetermined number, or when the previous period count is greater than or equal to another predetermined number, the peak position is output as invalid, and in other cases, it is output as valid. Determination means 1;
Storage means for storing the output of the determination means 1 and the output of the peak position detection means at a frequency error detection period;
If both the output of the determination unit 1 and the current output of the determination unit 1 in the immediately preceding frequency error detection period stored in the storage unit are valid, the output is valid, and in other cases, the output is invalid. Determination means 2;
When the determination unit 2 determines that the output is valid, the difference between the differential output peak position stored in the storage unit and the peak position output by the differential output peak position detection unit and the peak position detection unit outputs the peak position. The clock frequency error is calculated from the period of the clock frequency, and when the effectiveness determining means 2 determines that the clock frequency error is invalid, the clock frequency error at the previous detection is continuously used without updating the frequency error. Having error detection means,
The OFDM demodulator according to any one of the first configuration to the fourth configuration.

(Sixth configuration)
Comprising integration means for integrating the clock frequency error detection value from the frequency error detection means;
An error of a frequency error detection cycle value in each detection cycle is corrected by giving the output of the integration unit to the correction unit according to claim 2 or 3, wherein any one of the first configuration to the fifth configuration is provided. An OFDM demodulator according to the above configuration.

(Seventh configuration)
An integration circuit that integrates only the frequency error detection value determined to be effective by the validity determination means 2;
An error of a frequency error detection cycle value in each detection cycle is corrected by giving the output of the integration unit to the correction unit according to claim 2 or 3,
The OFDM demodulator according to any one of the first to sixth configurations.

(Eighth configuration)
The clock frequency error detection value is integrated after being multiplied by a value determined by an internal parameter of the OFDM demodulator,
The OFDM demodulator according to the sixth configuration or the seventh configuration.

(Ninth configuration)
The OFDM demodulator according to any one of the first to sixth configurations, wherein an integration period of the first filter means is determined by an internal parameter of the OFDM demodulator.

  Here, the internal parameter has the number of symbols included in the integration period as a parameter.

  Immediately after the start of detection, there may be restrictions such as the need to reduce the integration period in order to improve the frequency error detection speed. The OFDM demodulator of the ninth configuration first converges the frequency error quickly by frequently detecting the frequency error in a short cycle, and then lengthens the integration period to detect the frequency error more accurately. It is possible to change the period during which the calculation of the first filter means is performed.

(10th configuration)
In the peak position detection, the section before and after including the previous effective peak position is set as a peak position detection target, and even if a valid peak exists in other sections, it is not set as a detection target. The OFDM demodulator according to any one of the configurations up to the configuration.

(Eleventh configuration)
FFT window position control means for shifting the FFT calculation start position,
When the sampling correction control unit calculates a delay amount exceeding a predetermined value, a fractional delay amount shifted by one period of the reference sampling clock is output,
The FFT window position control means simultaneously shifts the FFT window position by one reference sampling clock period,
The OFDM receiver according to the third configuration or the fourth configuration, wherein sampling timing correction can always be processed.

(Twelfth configuration)
On the computer,
A clock frequency error detection procedure according to any one of the first to eleventh configurations;
An OFDM demodulation program that executes a procedure for correcting a clock frequency error.

(13th configuration)
A computer-readable recording medium in which the program according to the twelfth configuration is recorded.

  Note that in each part and each processing step of the OFDM demodulator of the above embodiment, a calculation means such as a CPU executes a program stored in a storage means such as a ROM (Read Only Memory) or a RAM, and a communication such as an interface part. This can be realized by controlling the means. Therefore, various functions and various processes of the OFDM demodulator according to the present embodiment can be realized simply by a computer having these means reading the recording medium storing the program and executing the program. In addition, by recording the program on a removable recording medium, the various functions and various processes described above can be realized on an arbitrary computer.

  As the recording medium, a program medium such as a memory (not shown) such as a ROM may be used for processing by the microcomputer, and a program reading device is provided as an external storage device (not shown). It may be a program medium that can be read by inserting a recording medium there.

  In any case, the stored program is preferably configured to be accessed and executed by the microprocessor. Furthermore, it is preferable that the program is read out, and the read program is downloaded to a program storage area of the microcomputer and the program is executed. It is assumed that this download program is stored in advance in the main unit.

  The program medium is a recording medium configured to be separable from the main body, such as a tape system such as a magnetic tape or a cassette tape, a magnetic disk such as a flexible disk or a hard disk, or a disk such as a CD / MO / MD / DVD. Fixed disk system, card system such as IC card (including memory card), or semiconductor memory such as mask ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash ROM, etc. In particular, there are recording media that carry programs.

  In addition, if the system configuration is capable of connecting to a communication network including the Internet, the recording medium is preferably a recording medium that fluidly carries the program so as to download the program from the communication network.

  Further, when the program is downloaded from the communication network as described above, it is preferable that the download program is stored in the main device in advance or installed from another recording medium.

  The present invention can be applied to a receiver that can efficiently transmit a video signal and an audio signal by a digital transmission method, and is particularly suitable for an OFDM demodulator, an OFDM demodulation method, a program, and a computer-readable recording medium. is there. In addition, a device that receives a signal in accordance with the OFDM scheme, for example, a demodulator for a wireless LAN, a demodulator for a PLC (Power Line Communication), 3GPP standard 3.9 generation (LTE: mobile phone standard) The present invention can also be applied to an OFDM demodulator for Long Term Evolution), a fourth generation standard, a demodulator for receiving BS digital broadcast and CS digital broadcast, and a demodulator for cable television.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of an OFDM demodulator. FIG. 1, showing an embodiment of the present invention, is a block diagram showing a main configuration of a delay profile / peak position detector and a clock frequency error detector. FIG. It is a figure which shows the relationship between the complex correlation intensity | strength of the OFDM broadcast wave and its differential output in the environment where a multipath generate | occur | produces. It is a figure which shows the complex correlation intensity | strength when not performing an area average process in a 1st filtering part. It is a figure which shows the complex correlation intensity | strength at the time of performing an area average process in a 1st filtering part. It is a figure which shows the complex correlation strength calculation value obtained by the moving average process in a 2nd filtering part. It is a figure of the differential output obtained by differentiating the complex correlation strength calculation value signal shown in FIG. It is a figure which shows that a peak position shifts | deviates by the frequency error of the frequency of a broadcast wave, and the operation clock frequency of an OFDM demodulation apparatus. It is a figure which shows the example of a peak position detection when the detection range of the peak position of a differential output is restrict | limited to +/- W from the peak position detected last time. It is a flowchart figure showing 1 cycle of the process which detects a frequency error. It is a flowchart figure which shows the process which determines whether the waveform of the differential output of a complex correlation strength calculation value is analyzable. It is a block diagram which shows the structural example of an OFDM demodulation apparatus. It is a figure which shows the interpolation process by a fraction delay filter. It is a figure which shows the structure of a FIR filter. In the Lagrange interpolation filter, it is a figure which shows the filter characteristic at the time of changing an interpolation point, (a) is a figure which shows an amplitude frequency characteristic, (b) shows the actual correction timing Dint which considered the phase characteristic. (C) is a figure which shows the signal noise power ratio (SNR) which considered both the amplitude and the phase. It is a figure which shows the structure of a Farrow type | mold fractional delay filter. In the Farrow type fractional delay filter, it is a figure which shows the filter characteristic at the time of changing an interpolation point, (a) is a figure which shows an amplitude frequency characteristic, (b) is the actual correction timing which considered the phase characteristic. (C) is a figure which shows SNR which considered both the amplitude and the phase. It is a figure explaining the sampling timing error of the sampling timing of an OFDM demodulator, and a true sampling timing. It is a figure which shows the image of the interpolation process using a deformation | transformation Farrow type | mold fractional delay filter, Comprising: (a) is a figure which shows the image of the interpolation process in a certain sampling timing, (b) is the next sampling timing of (a). It is a figure which shows the image of the interpolation process in. It is a figure which shows the example of a structure which correct | amends the clock frequency error using a fraction delay filter. It is a block diagram which shows the structure of the other OFDM demodulator based on this invention. It is a figure which shows the example which correct | amends a sampling value. It is a figure which shows the specific structure of the frequency error correction | amendment part corresponding to an integer delay process. It is a figure which shows the structure of the symbol signal contained in the OFDM signal. It is a block block diagram of the guard correlation / peak detection circuit in the OFDM demodulator of the prior art. It is a figure which shows the structural example of the OFDM receiver which concerns on this invention.

Explanation of symbols

1 OFDM demodulator 10 tuner 11 ADC (sampling means)
12 Sampling receiver (oversampling means)
13 Orthogonal demodulation generator (orthogonal demodulation means)
14 FFT unit (FFT operation means)
15 Delay profile / peak position detector (complex correlation strength calculation means)
16 Clock frequency error detector (frequency error detector)
17 FFT window position detector 18 Frequency oscillator 19 PLL circuit (Frequency error correction means)
20 Sampling correction control unit (sampling timing specifying means, FFT window position control unit)
21 Frequency error correction unit (frequency error correction means, interpolation means)
50 OFDM demodulator 151 delay circuit unit 152 complex conjugate arithmetic unit 153 complex multiplier unit 154 first filtering unit (symbol number direction integration means, integration period determination means)
155 Complex correlation strength calculation unit 156 Second filtering unit (smoothing means)
157 Differential calculation unit 158 Peak position detection unit (boundary detection unit, determination unit)
159 Self-running counter 161 Peak position difference detection unit 162 Integration calculation unit 2031 Fractional delay unit 2032 Integer delay unit 2033 Integer delay unit

Claims (19)

An OFDM demodulator comprising sampling means for receiving an OFDM signal including a transmission symbol having an effective symbol and a guard interval, and generating a received sample sequence signal by sampling with a predetermined sampling clock,
A complex correlation strength calculating means for generating an averaged complex correlation strength signal of one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period;
Boundary detecting means for detecting a boundary of the effective symbol in the averaged complex correlation strength signal;
With respect to the first complex correlation strength signal and the second complex correlation strength signal continuously generated by the complex correlation strength calculation means, the position of the boundary and the second complex correlation in the first complex correlation strength signal The frequency error between the transmission clock of the OFDM signal and the sampling clock is detected from the difference between the position of the boundary in the intensity signal and the processing time required for the complex correlation intensity calculation means to average the complex correlation intensity signal. Frequency error detecting means for
An OFDM demodulator comprising frequency error correction means for correcting the frequency error detected by the frequency error detection means. The complex correlation strength calculation means includes:
A complex correlation signal integrated in the symbol number direction is generated by adding a correlation value between the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period every other transmission symbol period. Symbol number direction integration means,
2. The OFDM demodulator according to claim 1, further comprising smoothing means for generating a complex correlation strength signal from the complex correlation signal and smoothing the complex correlation strength signal.   3. The OFDM demodulator according to claim 2, further comprising integration period determining means for determining an integration period in the symbol number direction based on an internal parameter. The boundary detection means is
4. A differential output signal obtained by differentiating the averaged complex correlation strength signal is generated, and a peak position of the differential output signal is detected as the boundary. The OFDM demodulator according to the description. The boundary detection means is
When detecting the peak position in the second complex correlation strength signal after detecting the peak position in the first complex correlation strength signal, from the peak position of the boundary in the first complex correlation strength signal, The OFDM demodulator according to claim 4, wherein the peak position in the second complex correlation strength signal is detected within a set range. Storage means for storing the frequency error detected by the frequency error detection means;
A determination means for determining that the detection of the position of the boundary by the boundary detection means is valid when there is output data that exceeds a set threshold among the output data constituting the differential output signal;
The frequency error detecting means determines that both the position detection of the boundary in the first complex correlation strength signal and the position detection of the boundary in the second complex correlation strength signal are valid by the determination means. The frequency error is detected only when
The frequency error correcting unit corrects the frequency error detected by the frequency error detecting unit when the frequency error detecting unit detects the frequency error, and the frequency error detecting unit does not detect the frequency error. 6. The OFDM demodulator according to claim 4, wherein the frequency error stored in the storage means is corrected. Storage means for storing the frequency error detected by the frequency error detection means;
When the number of output data that exceeds the set threshold among the output data constituting the differential output signal is within a predetermined range, it is determined that the boundary position detection by the boundary detection means is effective And determining means for
The frequency error detecting means determines that both the position detection of the boundary in the first complex correlation strength signal and the position detection of the boundary in the second complex correlation strength signal are valid by the determination means. The frequency error is detected only when
The frequency error correcting unit corrects the frequency error detected by the frequency error detecting unit when the frequency error detecting unit detects the frequency error, and the frequency error detecting unit does not detect the frequency error. 6. The OFDM demodulator according to claim 4, wherein the frequency error stored in the storage means is corrected.   8. The OFDM demodulator according to claim 6, further comprising threshold setting means for calculating and setting the threshold from the differential output signal. The frequency error detecting means is
9. The OFDM demodulator according to claim 1, wherein a cumulative value obtained by accumulating a division value obtained by dividing the difference by the processing time is detected as the frequency error. The frequency error detecting means is
The division value obtained by dividing the difference by the processing time is used for both the boundary position detection in the first complex correlation strength signal and the boundary position detection in the second complex correlation strength signal. 10. The OFDM demodulator according to claim 6, wherein an accumulated value accumulated only when it is determined to be valid by the determination means is detected as the frequency error. 11. The frequency error detecting means is
A multiplication value obtained by dividing the difference by the processing time is multiplied by a coefficient determined by an internal parameter, and a cumulative value obtained by accumulating the multiplication value is detected as the frequency error. The OFDM demodulator according to any one of claims 1 to 8. The frequency error correction means is
The OFDM demodulator according to any one of claims 1 to 11, wherein the frequency error is corrected by changing the predetermined sampling clock. The frequency error correction means is
Sampling timing specifying means for generating sampling timing specifying information for specifying the sampling timing of the OFDM signal;
The interpolating means for interpolating a sampling value at a sampling timing specified by the sampling timing specifying information from the received sample series signal is provided. OFDM demodulator. Further comprising oversampling means for converting the predetermined sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself;
14. The OFDM demodulator according to claim 13, wherein the interpolation means interpolates a sampling value at a sampling timing specified by the sampling timing specifying information from an oversampled received sample sequence signal. The sampling means converts the predetermined sampling clock into an oversampling state with respect to the reference clock of the OFDM demodulator itself,
14. The OFDM demodulator according to claim 13, wherein the interpolation means interpolates a sampling value at a sampling timing specified by the sampling timing specifying information from an oversampled received sample sequence signal. Orthogonal demodulation means for demodulating the orthogonal frequency division multiplexed OFDM signal received as the received sample sequence signal;
FFT operation means for converting the signal demodulated by the orthogonal demodulation means into a frequency domain data signal by FFT operation;
FFT window position control means for shifting the start position of the FFT calculation,
Sampling timing specifying means
When the sampling timing specified by the sampling timing specifying information exceeds a predetermined range, the sampling timing is shifted by one cycle of the predetermined sampling clock,
The FFT window position control means includes:
16. The OFDM demodulation according to claim 14, wherein the FFT calculation start position is simultaneously shifted by one cycle of the predetermined sampling clock in accordance with the sampling timing shift in the sampling timing specifying means. apparatus. An OFDM demodulation method for receiving an OFDM signal including a transmission symbol having a valid symbol and a guard interval and generating a received sample sequence signal by sampling with a predetermined sampling clock,
A complex correlation strength calculation step for generating an averaged complex correlation strength signal of one transmission symbol period length from the received sample sequence signal and a sample sequence signal obtained by delaying the received sample sequence signal by an effective symbol period;
A boundary detecting step for detecting a boundary of the effective symbol in the averaged complex correlation strength signal;
With respect to the first complex correlation strength signal and the second complex correlation strength signal continuously generated by the complex correlation strength calculation step, the position of the boundary and the second complex correlation in the first complex correlation strength signal The frequency error between the transmission clock of the OFDM signal and the sampling clock is detected from the difference from the position of the boundary in the strength signal and the processing time required for the complex correlation strength calculation step to average the complex correlation strength signal. A frequency error detection step to perform,
An OFDM demodulation method comprising a frequency error correction step of correcting the frequency error detected by the frequency error detection step.   An OFDM demodulation program for operating a computer as the OFDM demodulator according to any one of claims 1 to 16, wherein the computer functions as each means.   A computer-readable recording medium on which the OFDM demodulation program according to claim 18 is recorded.

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