JP2010135634A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Method for manufacturing semiconductor device, and semiconductor device Download PDF

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JP2010135634A
JP2010135634A JP2008311273A JP2008311273A JP2010135634A JP 2010135634 A JP2010135634 A JP 2010135634A JP 2008311273 A JP2008311273 A JP 2008311273A JP 2008311273 A JP2008311273 A JP 2008311273A JP 2010135634 A JP2010135634 A JP 2010135634A
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electrode
semiconductor device
insulating film
drive electrode
film
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Tokuhide Kitamura
徳秀 北村
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having movable portions with high reliability, and the semiconductor device. <P>SOLUTION: Upper driving electrodes 23 connected to supports 21 and an upper capacitance electrode 25 are extended in a beam shape through silicon nitride films 27. In other words, the silicon nitride films 27 are formed contacting with each upper surface of an end portion of the upper driving electrode 23 and an end portion of the upper capacitance electrode 25 which are separated and faced, and provided approximately parallel to the upper driving electrodes 23 and the upper capacitance electrode 25. The silicon nitride films 27 are formed by being deposited on an upper surface of a conductive film to be formed into the upper driving electrodes 23 and the upper capacitance electrode 25 in a continuous process by a CVD method, and, thereafter, by being patterned by a RIE method. The silicon nitride films 27 are formed so as to have less discontinuity and unevenness in film thickness or film property, and good adhesiveness to the upper driving electrodes 23 and the upper capacitance electrode 25. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、可動部を有する半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a method of manufacturing a semiconductor device having a movable part and the semiconductor device.

近年、微小なアクチュエータを利用したマイクロマシンもしくはMEMS(Micro-Electro-Mechanical Systems)技術を使用した可変容量素子やスイッチ等に対する需要が高まっている。静電型アクチュエータを使用した可変容量素子等を有する半導体装置は、LSI(Large Scale Integrated circuit)等の製造プロセスと整合性が良く、消費電力が比較的小さい等のために、鋭意開発が進められている。   In recent years, there is an increasing demand for variable capacitance elements, switches, and the like using micromachines using micro actuators or MEMS (Micro-Electro-Mechanical Systems) technology. Semiconductor devices with variable capacitance elements that use electrostatic actuators are well developed and compatible with manufacturing processes such as LSI (Large Scale Integrated circuit) and have relatively low power consumption. ing.

例えば、半導体基板上に配置されたアンカー(支柱)には、駆動用上部電極(上部駆動電極)が固定され、半導体基板上には駆動用下部電極(下部駆動電極)とRF用下部電極(下部容量電極)が形成され、RF用下部電極は駆動用下部電極間に配置され、駆動用下部電極上には、駆動用下部電極を覆うように絶縁膜が形成され、RF用下部電極上にはRF用下部電極を覆うように絶縁膜が形成され、これらRF用下部電極、RF用上部電極(上部容量電極)、及び絶縁膜により、可変容量素子が構成され、また、RF用上部電極と駆動用上部電極との間には絶縁体が挿入されており、RF用上部電極と駆動用上部電極とは電気的にアイソレートされ、RF用下部電極は、RF用上部電極と対向するように配置された半導体装置が開示されている(例えば、特許文献1参照。)。   For example, a driving upper electrode (upper driving electrode) is fixed to an anchor (post) arranged on a semiconductor substrate, and a driving lower electrode (lower driving electrode) and an RF lower electrode (lower part) are fixed on the semiconductor substrate. (Capacitance electrode) is formed, and the lower electrode for RF is disposed between the lower electrodes for driving, and an insulating film is formed on the lower electrode for driving so as to cover the lower electrode for driving, and on the lower electrode for RF An insulating film is formed so as to cover the RF lower electrode, and these RF lower electrode, RF upper electrode (upper capacitive electrode), and insulating film constitute a variable capacitance element, and drive with the RF upper electrode. An insulator is inserted between the upper electrode for RF, the upper electrode for RF and the upper electrode for driving are electrically isolated, and the lower electrode for RF is arranged to face the upper electrode for RF Semiconductor device disclosed That (for example, see Patent Document 1.).

しかしながら、開示された半導体装置は、可動部が機械動作をする上で、信頼性が十分でない可能性を有している。つまり、開示された半導体装置は、RF用上部電極と駆動用上部電極との間に絶縁体が挿入された構造をなしており、製造において、RF用上部電極と駆動用上部電極がパターニングされた後に、下部にある犠牲膜、RF用上部電極、及び駆動用上部電極の上に絶縁体を形成して、CDE(Chemical Dry Etching)等で加工すると推測される。その際、絶縁体は、RF用上部電極及び駆動用上部電極の端部でカバレージが悪い部分が生じ、また、カバレージが悪い部分のエッチングは不均一になることがあり、絶縁体が細くまたは薄く形成される場合があるという問題を有している。
特開2007−242607号公報(第16、17頁、図30A)
However, the disclosed semiconductor device has a possibility that the reliability is not sufficient when the movable portion performs a mechanical operation. That is, the disclosed semiconductor device has a structure in which an insulator is inserted between the upper electrode for RF and the upper electrode for driving, and the upper electrode for RF and the upper electrode for driving are patterned in manufacturing. Later, it is presumed that an insulator is formed on the sacrificial film, the RF upper electrode, and the driving upper electrode in the lower part and processed by CDE (Chemical Dry Etching) or the like. At that time, in the insulator, a portion with poor coverage is generated at the ends of the upper electrode for RF and the upper electrode for driving, and etching of the portion with poor coverage may be uneven, and the insulator is thin or thin. There is a problem that it may be formed.
JP 2007-242607 A (16th and 17th pages, FIG. 30A)

本発明は、信頼性の高い可動部を有する半導体装置の製造方法及び半導体装置を提供する。   The present invention provides a method of manufacturing a semiconductor device having a highly reliable movable part and a semiconductor device.

本発明の一態様の半導体装置の製造方法は、半導体基板の表面に、ほぼ直線状に離間して配置された支持電極、下部駆動電極、及び下部容量電極を形成し、前記支持電極、前記下部駆動電極、及び前記下部容量電極の表面に第1の絶縁膜を形成する工程と、前記第1の絶縁膜を被うように前記半導体基板の表面に犠牲膜を形成して、前記支持電極の表面の前記犠牲膜及び前記第1の絶縁膜に前記支持電極に通ずる開口を形成する工程と、前記開口を埋め込み、前記犠牲膜の表面を被う導電体を形成し、前記導電体の上に、第2の絶縁膜を形成する工程と、前記下部駆動電極と前記下部容量電極との隙間に対向する位置に、前記第2の絶縁膜を残すようにパターニングする工程と、残された前記第2の絶縁膜の中央部の下側を通り、前記下部駆動電極と前記下部容量電極との前記隙間に対向する位置に分離溝を形成し、前記下部駆動電極と前記下部容量電極に対向する位置に前記導電体を残すようにパターニングする工程と、前記導電体がパターニングされて除去された部分から前記犠牲膜を除去する工程とを備えていることを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a support electrode, a lower drive electrode, and a lower capacitor electrode, which are spaced substantially linearly on a surface of a semiconductor substrate; Forming a first insulating film on surfaces of the drive electrode and the lower capacitor electrode; and forming a sacrificial film on the surface of the semiconductor substrate so as to cover the first insulating film; Forming an opening that communicates with the support electrode in the sacrificial film and the first insulating film on the surface; and forming a conductor that fills the opening and covers the surface of the sacrificial film; and A step of forming a second insulating film, a step of patterning so as to leave the second insulating film at a position facing the gap between the lower drive electrode and the lower capacitor electrode, and the remaining first 2 under the central part of the insulating film, Forming a separation groove at a position facing the gap between the electrode and the lower capacitor electrode, and patterning the conductor so as to leave the conductor at a position facing the lower drive electrode and the lower capacitor electrode; and And a step of removing the sacrificial film from the portion removed by patterning.

また、本発明の別態様の半導体装置は、半導体基板と、前記半導体基板上面に形成された支持電極と、前記半導体基板上面に、前記支持電極とは離間して形成された下部駆動電極と、前記半導体基板上面に、前記支持電極及び前記下部駆動電極とは離間して、前記支持電極と前記下部駆動電極とを結ぶ方向に配設された下部容量電極と、前記下部駆動電極と前記下部容量電極とを被覆する第1の絶縁膜と、前記半導体基板の上面に垂直に、前記支持電極に接続された支柱電極と、前記下部駆動電極に対向且つ離間して、前記支柱電極にほぼ垂直に接続された梁状の上部駆動電極と、前記上部駆動電極と面接触で接続され且つ並行に延在する第2の絶縁膜と、前記下部容量電極に対向且つ離間して、前記支柱電極にほぼ垂直に、前記第2の絶縁膜と上面端部で接触して接続された梁状の上部容量電極と
を備えていることを特徴とする。
Further, a semiconductor device according to another aspect of the present invention includes a semiconductor substrate, a support electrode formed on the upper surface of the semiconductor substrate, a lower drive electrode formed on the upper surface of the semiconductor substrate and separated from the support electrode, A lower capacitor electrode disposed on a top surface of the semiconductor substrate in a direction connecting the support electrode and the lower drive electrode apart from the support electrode and the lower drive electrode; and the lower drive electrode and the lower capacitor A first insulating film covering the electrode, a column electrode connected to the support electrode perpendicular to the upper surface of the semiconductor substrate, and opposed to and spaced from the lower drive electrode, and substantially perpendicular to the column electrode A beam-shaped upper drive electrode connected to the upper drive electrode, a second insulating film connected in surface contact with the upper drive electrode and extending in parallel, and opposed to and spaced from the lower capacitor electrode. Vertically, the second insulation Characterized in that it comprises a contact with the connected beam-like upper capacitor electrode on the top surface edge and.

本発明によれば、信頼性の高い可動部を有する半導体装置の製造方法及び半導体装置を提供することが可能である。   ADVANTAGE OF THE INVENTION According to this invention, it is possible to provide the manufacturing method and semiconductor device of a semiconductor device which have a highly reliable movable part.

以下、本発明の実施例について、図面を参照しながら説明する。各図では、同一の構成要素には同一の符号を付す。   Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

本発明の実施例1に係る半導体装置の製造方法及び半導体装置について、図1乃至図4を参照しながら説明する。図1は半導体装置の構成を模式的に示す図で、図1(a)は平面図、図1(b)は図1(a)のA−A線に沿った断面図である。図2は半導体装置の製造方法を工程順に模式的に示す構造断面図である。図3は図2に続く、半導体装置の製造方法を工程順に模式的に示す構造断面図である。図4は、半導体装置の動作の一形態を模式的に示す断面図である。   A semiconductor device manufacturing method and a semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA in FIG. FIG. 2 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps. FIG. 3 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps following FIG. FIG. 4 is a cross-sectional view schematically showing one mode of operation of the semiconductor device.

図1に示すように、半導体装置1は、半導体基板10の相対向する平面の内の上面とする一方の面に形成された支持電極11と、半導体基板10上面に、支持電極11とは離間して形成された下部駆動電極13と、半導体基板10上面に、支持電極11及び下部駆動電極13とは離間して、支持電極11と下部駆動電極13とを結ぶ方向に形成された下部容量電極15と、下部駆動電極13と下部容量電極15とを被覆する第1の絶縁膜である絶縁膜17と、半導体基板10の上面に垂直に、支持電極11に接続された支柱電極である支柱21と、下部駆動電極13に対向且つ離間して、支柱21にほぼ垂直に接続された梁状の上部駆動電極23と、上部駆動電極23の上面に面接触で接続され且つ並行に延在する第2の絶縁膜であるシリコン窒化膜27と、下部容量電極15に対向且つ離間して、支柱21にほぼ垂直に、シリコン窒化膜27と上面端部で接触して接続された梁状の上部容量電極25とを備えている。なお、半導体装置1の表面に形成された上部駆動電極23等を、半導体装置1の表面に対して上とする。   As shown in FIG. 1, the semiconductor device 1 includes a support electrode 11 formed on one surface, which is an upper surface of opposing planes of the semiconductor substrate 10, and the support electrode 11 is separated from the upper surface of the semiconductor substrate 10. The lower drive electrode 13 formed in this manner and the lower capacitor electrode formed on the upper surface of the semiconductor substrate 10 in a direction connecting the support electrode 11 and the lower drive electrode 13 with the support electrode 11 and the lower drive electrode 13 being separated from each other. 15, an insulating film 17 that is a first insulating film covering the lower drive electrode 13 and the lower capacitor electrode 15, and a column 21 that is a column electrode connected to the support electrode 11 perpendicular to the upper surface of the semiconductor substrate 10. A beam-like upper drive electrode 23 facing and spaced apart from the lower drive electrode 13 and connected substantially perpendicularly to the support column 21; and a first electrode extending in parallel to the upper surface of the upper drive electrode 23 in surface contact. Silico, an insulating film of 2 A nitride film 27 and a beam-shaped upper capacitor electrode 25 which is opposed to and spaced from the lower capacitor electrode 15 and is substantially perpendicular to the support column 21 and connected in contact with the silicon nitride film 27 at the upper end portion are provided. . Note that the upper drive electrode 23 and the like formed on the surface of the semiconductor device 1 are set above the surface of the semiconductor device 1.

図1(a)及び図1(b)に示すように、半導体基板10の上面に、一方の側から他方の側に、支持電極11、下部駆動電極13、下部容量電極15、下部駆動電極13、及び支持電極11が、ほぼ直線状に互いに離間して、表面をほぼ同じ高さにして配置されている。支柱21との接続部を除いた支持電極11、下部駆動電極13、及び下部容量電極15を被うように、絶縁膜17が配設されている。   As shown in FIGS. 1A and 1B, the support electrode 11, the lower drive electrode 13, the lower capacitor electrode 15, and the lower drive electrode 13 are formed on the upper surface of the semiconductor substrate 10 from one side to the other side. , And the support electrodes 11 are arranged substantially linearly apart from each other, with the surfaces thereof having substantially the same height. An insulating film 17 is disposed so as to cover the support electrode 11, the lower drive electrode 13, and the lower capacitor electrode 15 except for the connection portion with the support column 21.

支柱21は支持電極11の上面の一部と電気的及び機械的に接続されている。支柱21の支持電極11に対向する上端側の位置に、上部駆動電極23が間に接続部を介して一体的に接続されている。つまり、上部駆動電極23は、支持電極11と下部駆動電極13とが離間して存在しているのとは異なり、支持電極11の上端側から下部駆動電極13に相対する上側に至るまで連続して形成されている。   The column 21 is electrically and mechanically connected to a part of the upper surface of the support electrode 11. The upper drive electrode 23 is integrally connected to the position on the upper end side of the support column 21 facing the support electrode 11 through a connecting portion therebetween. That is, the upper drive electrode 23 is continuous from the upper end side of the support electrode 11 to the upper side opposite to the lower drive electrode 13, unlike the support electrode 11 and the lower drive electrode 13 that are separated from each other. Is formed.

両側の支柱21の間に順に配設された上部駆動電極23、上部容量電極25、及び上部駆動電極23は、下部駆動電極13、下部容量電極15、及び下部駆動電極13にそれぞれ対応するように、例えば、1〜2μm程度の空隙51を置いて上側にほぼ直線状に配置されている。上部駆動電極23と上部容量電極25とは、互いに離間され、相対向する端部の上面側に接触して配設された短冊状のシリコン窒化膜27が、互いを機械的に接続している。支柱21に支えられた一連の上部駆動電極23及び上部容量電極25は、対応する下部駆動電極13及び下部容量電極15に対して、間隔を狭めたり、広げたり(空隙51が間に存在)、機械的な動きが可能である。   The upper drive electrode 23, the upper capacitive electrode 25, and the upper drive electrode 23 that are sequentially disposed between the support columns 21 on both sides correspond to the lower drive electrode 13, the lower capacitive electrode 15, and the lower drive electrode 13, respectively. For example, the air gap 51 of about 1 to 2 μm is placed and arranged almost linearly on the upper side. The upper drive electrode 23 and the upper capacitor electrode 25 are spaced apart from each other, and a strip-shaped silicon nitride film 27 disposed in contact with the upper surface side of the opposite ends mechanically connects each other. . A series of the upper drive electrode 23 and the upper capacitive electrode 25 supported by the support column 21 are narrowed or widened with respect to the corresponding lower drive electrode 13 and the lower capacitive electrode 15 (the gap 51 exists between them). Mechanical movement is possible.

支持電極11、下部駆動電極13、下部容量電極15、支柱21、上部駆動電極23、及び上部容量電極25は、アルミニウム(Al)、または、SiもしくはCu等を有するアルミニウム合金からなる。なお、これらの電極は、他に、例えば、Pt、Sr、Ru、Cr、Mo、W、Ti、Ta、Cu、Niの内の少なくとも1つを主成分として含む材料で形成することが可能である。絶縁膜17は、シリコン窒化膜、アルミニウム酸化膜、またはシリコン窒化膜とアルミニウム酸化膜との積層膜からなる。絶縁膜17は、他に、例えば、シリコン酸化膜、シリコン酸窒化膜、またはこれらの内の少なくとも1つを含む積層膜等に置き換えることが可能である。   The support electrode 11, the lower drive electrode 13, the lower capacitive electrode 15, the support column 21, the upper drive electrode 23, and the upper capacitive electrode 25 are made of aluminum (Al) or an aluminum alloy containing Si or Cu. In addition, for example, these electrodes can be formed of a material containing at least one of Pt, Sr, Ru, Cr, Mo, W, Ti, Ta, Cu, and Ni as a main component. is there. The insulating film 17 is made of a silicon nitride film, an aluminum oxide film, or a laminated film of a silicon nitride film and an aluminum oxide film. In addition, the insulating film 17 can be replaced with, for example, a silicon oxide film, a silicon oxynitride film, or a laminated film including at least one of them.

次に、半導体装置1の製造方法を説明する。製造方法を説明する中で、半導体装置1の構成の補足、使用される材料の補足等を行う。   Next, a method for manufacturing the semiconductor device 1 will be described. In the description of the manufacturing method, supplementation of the configuration of the semiconductor device 1, supplementation of materials used, and the like are performed.

図2(a)に示すように、例えば、表面に絶縁膜(図示略)を有するシリコンからなる半導体基板10の上に、支持電極11、下部駆動電極13、及び下部容量電極15となるAlからなる導電体がほぼ直線状に並び、且つ、下部容量電極15を中央に、下部駆動電極13及び支持電極11がほぼ対称的な配置となるように、スパッタリング法により堆積され、エッチング加工等を含む周知のリソグラフィ法により、所望の形状にパターニングされる。なお、半導体基板10には、予め、トランジスタ、抵抗、及び容量等の素子を含むLSIの一部が形成されていることは可能である。   As shown in FIG. 2A, for example, on the semiconductor substrate 10 made of silicon having an insulating film (not shown) on the surface, the support electrode 11, the lower drive electrode 13, and the lower capacitor electrode 15 are made of Al. The conductors are arranged in a substantially straight line, and are deposited by a sputtering method so that the lower drive electrode 13 and the support electrode 11 are arranged almost symmetrically with the lower capacitor electrode 15 in the center, and includes etching processing and the like. It is patterned into a desired shape by a known lithography method. Note that a part of an LSI including elements such as transistors, resistors, and capacitors can be formed on the semiconductor substrate 10 in advance.

図2(b)に示すように、支持電極11、下部駆動電極13、及び下部容量電極15を被うように、半導体基板10の表面に、例えば、CVD(Chemical Vapor Deposition)法によりシリコン窒化膜からなる絶縁膜17が形成される。なお、絶縁膜17は、スパッタリング法で形成することは可能である。   As shown in FIG. 2B, a silicon nitride film is formed on the surface of the semiconductor substrate 10 by, for example, a CVD (Chemical Vapor Deposition) method so as to cover the support electrode 11, the lower drive electrode 13, and the lower capacitor electrode 15. An insulating film 17 made of is formed. Note that the insulating film 17 can be formed by a sputtering method.

図2(c)に示すように、絶縁膜17を被うように、例えば、感光性のポリイミドからなる犠牲膜31が塗布法により形成され、次に、犠牲膜31は、リソグラフィ法により、支持電極11の上の絶縁膜17に通ずる開口32が形成される。なお、非感光性のポリイミドを使用することは可能で、例えば、フォトレジストを使用して、エッチング加工等を含む周知のリソグラフィ法により、パターニングすることができる。   As shown in FIG. 2C, a sacrificial film 31 made of, for example, photosensitive polyimide is formed by a coating method so as to cover the insulating film 17, and then the sacrificial film 31 is supported by a lithography method. An opening 32 communicating with the insulating film 17 on the electrode 11 is formed. Note that non-photosensitive polyimide can be used, and for example, patterning can be performed using a photoresist by a known lithography method including etching.

図2(d)に示すように、犠牲膜31をマスクとして、開口32の底部に露出した絶縁膜17は、例えば、RIE(Reactive Ion Etching)法によりエッチングされる。開口32は、支持電極11の上面に通ずる。   As shown in FIG. 2D, with the sacrificial film 31 as a mask, the insulating film 17 exposed at the bottom of the opening 32 is etched by, for example, RIE (Reactive Ion Etching). The opening 32 communicates with the upper surface of the support electrode 11.

図2(e)に示すように、開口32を埋め込み、犠牲膜31の表面を被うAlからなる導電膜33がスパッタリング法により堆積され、導電膜33の上に、連続した工程として、導電膜33に対して圧縮する応力を有するシリコン窒化膜27aがCVD法により堆積される。   As shown in FIG. 2E, a conductive film 33 made of Al filling the opening 32 and covering the surface of the sacrificial film 31 is deposited by the sputtering method, and the conductive film is formed on the conductive film 33 as a continuous process. A silicon nitride film 27a having a compressive stress with respect to 33 is deposited by the CVD method.

図3(a)に示すように、下部駆動電極13と下部容量電極15との隙間に対向する上部の位置にシリコン窒化膜27を残すように、シリコン窒化膜27aの表面に、短冊状(図1(a)参照)のシリコン窒化膜27となるようにパターニングされたフォトレジスト38を形成する。   As shown in FIG. 3A, strips (see FIG. 3) are formed on the surface of the silicon nitride film 27a so that the silicon nitride film 27 is left at the upper position facing the gap between the lower drive electrode 13 and the lower capacitor electrode 15. A photoresist 38 patterned so as to be the silicon nitride film 27 of 1 (a) is formed.

図3(b)に示すように、フォトレジスト38をマスクとして、例えば、RIE法によりエッチングを行い、シリコン窒化膜27を形成する。シリコン窒化膜27は、フォトレジスト38の下部で抉られることがほとんどなく、フォトレジスト38の側面を延長するような形状に形成される。   As shown in FIG. 3B, the silicon nitride film 27 is formed by etching, for example, by the RIE method using the photoresist 38 as a mask. The silicon nitride film 27 is hardly formed under the photoresist 38 and is formed in a shape that extends the side surface of the photoresist 38.

図3(c)に示すように、フォトレジスト38を除去した後、シリコン窒化膜27及び導電膜33の表面にフォトレジスト39を形成し、下部駆動電極13と下部容量電極15とにそれぞれ対向した上部駆動電極23と上部容量電極25とを分離するための開口40を、シリコン窒化膜27の中央部を通る位置に形成する。開口40の底部には、シリコン窒化膜27及び導電膜33が露出する。なお、開口40を形成すると同時に、図1(a)に示す上部駆動電極23及び上部容量電極25を膜厚方向に貫通した孔26を形成するための開口を、フォトレジスト39に形成しておくことが可能である。   As shown in FIG. 3C, after removing the photoresist 38, a photoresist 39 is formed on the surface of the silicon nitride film 27 and the conductive film 33, and is opposed to the lower drive electrode 13 and the lower capacitor electrode 15, respectively. An opening 40 for separating the upper drive electrode 23 and the upper capacitor electrode 25 is formed at a position passing through the central portion of the silicon nitride film 27. The silicon nitride film 27 and the conductive film 33 are exposed at the bottom of the opening 40. At the same time that the opening 40 is formed, an opening for forming a hole 26 penetrating the upper drive electrode 23 and the upper capacitor electrode 25 shown in FIG. It is possible.

図3(d)に示すように、フォトレジスト39をマスクとして、例えば、リン酸、硝酸、及び酢酸を主成分とする薬液によるエッチング法により、導電膜33をエッチングする。開口40の底部に露出した導電膜33及びシリコン窒化膜27の下部にある導電膜33が、エッチングされて、分離溝である開口41が形成される。ウェットエッチング法によって、開口41は、フォトレジスト39の開口40につながる底面に沿った方向にもエッチングされるので、開口40より幅の広い部分を有している。また、シリコン窒化膜27の底面に沿った方向にもエッチングされて、シリコン窒化膜27の下部にある導電膜33が除去される。エッチング後、シリコン窒化膜27は、中央部で開口41を跨ぎ、両端部でそれぞれ分離された上部駆動電極23及び上部容量電極25の上面に接触している。   As shown in FIG. 3D, using the photoresist 39 as a mask, the conductive film 33 is etched by, for example, an etching method using a chemical solution mainly composed of phosphoric acid, nitric acid, and acetic acid. The conductive film 33 exposed at the bottom of the opening 40 and the conductive film 33 below the silicon nitride film 27 are etched to form an opening 41 that is a separation groove. Since the opening 41 is also etched in the direction along the bottom surface connected to the opening 40 of the photoresist 39 by the wet etching method, the opening 41 has a portion wider than the opening 40. Further, etching is performed in a direction along the bottom surface of the silicon nitride film 27, and the conductive film 33 under the silicon nitride film 27 is removed. After the etching, the silicon nitride film 27 straddles the opening 41 at the center and is in contact with the upper surfaces of the upper drive electrode 23 and the upper capacitor electrode 25 that are separated at both ends.

図1(b)に示すように、フォトレジスト39を除去した後、例えば、酸素プラズマを用いたCDE法により半導体基板10の上方から犠牲膜31がエッチングされる。エッチングガス等は、上部駆動電極23と上部容量電極25との間の開口41、及び孔26等から入り込み、犠牲膜31と反応してガス化して、犠牲膜31を除去する。その結果、図1に示す半導体装置1が完成する。   As shown in FIG. 1B, after removing the photoresist 39, the sacrificial film 31 is etched from above the semiconductor substrate 10 by, for example, the CDE method using oxygen plasma. Etching gas or the like enters through the opening 41 and the hole 26 between the upper drive electrode 23 and the upper capacitor electrode 25, reacts with the sacrificial film 31, and is gasified to remove the sacrificial film 31. As a result, the semiconductor device 1 shown in FIG. 1 is completed.

半導体装置1は、支持電極11と接続された上部駆動電極23及び下部駆動電極13に、図示を省略した配線等を介して、駆動電圧が印加される。下部駆動電極13と上部駆動電極23の間に静電引力が発生して、両電極は引き合う。   In the semiconductor device 1, a drive voltage is applied to the upper drive electrode 23 and the lower drive electrode 13 connected to the support electrode 11 via a wiring or the like not shown. An electrostatic attractive force is generated between the lower drive electrode 13 and the upper drive electrode 23, and the two electrodes attract each other.

図4に示すように、この静電引力により上部駆動電極23が下部駆動電極13の方に引き寄せられて、主に上部駆動電極23及び上部駆動電極23から支柱21へ延びた接続部が撓み、上部容量電極25が下部容量電極15上の絶縁膜17に接触する。その結果、下部容量電極15と上部容量電極25との間に、一定の容量を有するMIM(Metal Insulator Metal)キャパシタが構成される。そして、駆動電圧を切断すると、静電引力がなくなり、駆動電圧が印加される前の位置に戻り、容量は無視できる程度に小さくなる。下部容量電極15と上部容量電極25に、それぞれ、図示を省略した配線を接続することにより、半導体装置1は電圧印加に応じて一定の容量を持つ回路素子として利用可能となる。   As shown in FIG. 4, the upper drive electrode 23 is attracted toward the lower drive electrode 13 by this electrostatic attraction, and the upper drive electrode 23 and the connection portion extending from the upper drive electrode 23 to the column 21 are bent, The upper capacitor electrode 25 is in contact with the insulating film 17 on the lower capacitor electrode 15. As a result, an MIM (Metal Insulator Metal) capacitor having a certain capacitance is formed between the lower capacitor electrode 15 and the upper capacitor electrode 25. When the drive voltage is cut, the electrostatic attraction is lost, the position returns to the position before the drive voltage is applied, and the capacity becomes small enough to be ignored. By connecting wirings (not shown) to the lower capacitor electrode 15 and the upper capacitor electrode 25, the semiconductor device 1 can be used as a circuit element having a certain capacity in response to voltage application.

上述したように、半導体装置1は、離間し相対向した上部駆動電極23の端部と上部容量電極25の端部の、それぞれの上面に接して、上部駆動電極23及び上部容量電極25にほぼ並行して配設されたシリコン窒化膜27が形成されている。シリコン窒化膜27は、上部駆動電極23及び上部容量電極25となる導電膜33の上面に、連続した工程としてCVD法により堆積され、その後、RIE法でパターニングして形成されたものである。つまり、シリコン窒化膜27は、膜厚や膜質に不連続や不均質な部分が少なく、上部駆動電極23及び上部容量電極25と密着性が良好に形成されている。   As described above, the semiconductor device 1 is substantially in contact with the upper drive electrode 23 and the upper capacitor electrode 25 in contact with the upper surfaces of the end portions of the upper drive electrode 23 and the end portions of the upper capacitor electrode 25 that are spaced apart from each other. A silicon nitride film 27 arranged in parallel is formed. The silicon nitride film 27 is deposited on the upper surface of the conductive film 33 to be the upper drive electrode 23 and the upper capacitor electrode 25 by a CVD method as a continuous process and then patterned by the RIE method. That is, the silicon nitride film 27 has few discontinuous or inhomogeneous portions in film thickness and film quality, and has good adhesion to the upper drive electrode 23 and the upper capacitor electrode 25.

その結果、下部駆動電極13と上部駆動電極23とを静電引力で引き合う機械的な運動を繰り返しても、シリコン窒化膜27は、疲労性の破壊に至るような起点の発生を抑制することが可能となる。また、シリコン窒化膜27は、上部駆動電極23及び上部容量電極25から剥がれる可能性も低くなる。つまり、半導体装置1は、信頼性の高い可動部を有するものとなる。   As a result, the silicon nitride film 27 can suppress the occurrence of a starting point leading to fatigue damage even if the mechanical movement of attracting the lower drive electrode 13 and the upper drive electrode 23 by electrostatic attraction is repeated. It becomes possible. Further, the possibility that the silicon nitride film 27 is peeled off from the upper drive electrode 23 and the upper capacitor electrode 25 is reduced. That is, the semiconductor device 1 has a highly reliable movable part.

本発明の実施例2に係る半導体装置の製造方法及び半導体装置について、図5を参照しながら説明する。図5は半導体装置の構成を模式的に示す図で、図5(a)は断面図、図5(b)は図5(a)の一部を拡大して示す断面図である。実施例1の半導体装置の製造方法とは、シリコン窒化膜が残留応力を有している点が異なる。なお、実施例1と同一構成部分には同一の符号を付して、その説明は省略する。   A semiconductor device manufacturing method and a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. 5A and 5B are diagrams schematically illustrating the configuration of the semiconductor device, in which FIG. 5A is a cross-sectional view, and FIG. 5B is a cross-sectional view illustrating a part of FIG. This is different from the semiconductor device manufacturing method of the first embodiment in that the silicon nitride film has residual stress. In addition, the same code | symbol is attached | subjected to the same component as Example 1, and the description is abbreviate | omitted.

図5に示すように、半導体装置2は、実施例1の半導体装置1のシリコン窒化膜27を残留応力(圧縮応力)が発生するシリコン窒化膜67に置き換えている。シリコン窒化膜67は上部駆動電極23及び上部容量電極25の上面に接して、半導体基板10に対して反対の方向に凸曲面を有する形状となっている(以下、「上に凸に曲がる」という)。   As shown in FIG. 5, in the semiconductor device 2, the silicon nitride film 27 of the semiconductor device 1 of the first embodiment is replaced with a silicon nitride film 67 that generates a residual stress (compressive stress). The silicon nitride film 67 is in contact with the upper surfaces of the upper drive electrode 23 and the upper capacitor electrode 25 and has a shape having a convex curved surface in the opposite direction with respect to the semiconductor substrate 10 (hereinafter referred to as “curve upward”). ).

シリコン窒化膜67の一端に接している上部駆動電極23は、上部容量電極25に対向する端部が、支柱21と接続している接続部に比較して、半導体基板10に近付く方向に曲げられている。   The upper drive electrode 23 in contact with one end of the silicon nitride film 67 is bent in a direction in which the end facing the upper capacitor electrode 25 is closer to the semiconductor substrate 10 than the connection portion connected to the column 21. ing.

シリコン窒化膜67の他端に接している上部容量電極25は、上部駆動電極23に対向する端部が、上部駆動電極23の端部より更に、半導体基板10に近付く位置にあり、上に凸に曲がったシリコン窒化膜67に沿って曲げられている。上部容量電極25は、シリコン窒化膜67との接触がなくなると、シリコン窒化膜67の曲がりとは逆に下に凸に曲げられて、中央部では半導体基板10の表面にほぼ平行となる。   The upper capacitor electrode 25 in contact with the other end of the silicon nitride film 67 has an end facing the upper drive electrode 23 at a position closer to the semiconductor substrate 10 than an end of the upper drive electrode 23, and protrudes upward. Bent along the bent silicon nitride film 67. When the upper capacitor electrode 25 is no longer in contact with the silicon nitride film 67, the upper capacitor electrode 25 is bent downward in a convex manner contrary to the bending of the silicon nitride film 67, and becomes substantially parallel to the surface of the semiconductor substrate 10 at the center.

半導体装置2は、シリコン窒化膜67の製造方法が、シリコン窒化膜27と異なる他は、実施例1の半導体装置1の製造方法と同様である。シリコン窒化膜67は、例えば、CVD時の圧力を変化させることによって、半導体基板10に対して反対の方向に凸曲面を有する形状に形成されている。シリコン窒化膜67の応力は、CVD時、例えば、高真空にすることにより圧縮応力を得ることができ、または、SiHの流量を下げると圧縮応力を得ることができ、または、NH流量を下げると圧縮応力を得ることができる。また、例えば、2周波のRF出力を備えた装置では、低周波の側のRF出力の比率を上げると圧縮応力を得ることができ、2周波合計のRF出力を上げると圧縮応力を得ることができる。 The semiconductor device 2 is the same as the method of manufacturing the semiconductor device 1 of the first embodiment except that the method of manufacturing the silicon nitride film 67 is different from that of the silicon nitride film 27. For example, the silicon nitride film 67 is formed in a shape having a convex curved surface in the opposite direction to the semiconductor substrate 10 by changing the pressure during CVD. As the stress of the silicon nitride film 67, a compressive stress can be obtained during CVD, for example, by applying a high vacuum, or a compressive stress can be obtained by reducing the flow rate of SiH 4 , or the NH 3 flow rate can be increased. When it is lowered, compressive stress can be obtained. Further, for example, in an apparatus having an RF output of two frequencies, compressive stress can be obtained by increasing the ratio of the RF output on the low frequency side, and compressive stress can be obtained by increasing the RF output of the two frequencies. it can.

その結果、実施例1と同様に犠牲膜31が除去されると、シリコン窒化膜67は、上に凸に曲がり、上部駆動電極23のシリコン窒化膜67に接触している端部等が半導体基板10に近付く方向に曲げられ、上部容量電極25は、端部がシリコン窒化膜67に沿って曲げられ、中央部が、実施例1と比較すると、半導体基板10の表面方向に近付いて、表面にほぼ平行な形状となる。   As a result, when the sacrificial film 31 is removed in the same manner as in the first embodiment, the silicon nitride film 67 bends upward, and the end of the upper drive electrode 23 in contact with the silicon nitride film 67 has a semiconductor substrate. 10, the upper capacitor electrode 25 is bent along the silicon nitride film 67 at the end, and the central portion is closer to the surface direction of the semiconductor substrate 10 as compared with the first embodiment, and the surface is closer to the surface. The shape is almost parallel.

半導体装置2は、上部駆動電極23の端部等が半導体基板10、すなわち、下部駆動電極13に近付いているので、実施例1の駆動電圧に比較して、より低い駆動電圧で上部容量電極25が下部容量電極15上の絶縁膜17に接触する。半導体装置2は、その他に、実施例1の半導体装置1が有する効果を同様に有している。   In the semiconductor device 2, since the end of the upper drive electrode 23 is close to the semiconductor substrate 10, that is, the lower drive electrode 13, the upper capacitance electrode 25 is driven at a lower drive voltage than the drive voltage of the first embodiment. Comes into contact with the insulating film 17 on the lower capacitor electrode 15. In addition, the semiconductor device 2 has the same effects as those of the semiconductor device 1 of the first embodiment.

また、上記実施例2の変形例として、半導体装置2のシリコン窒化膜67が、反対の方向に曲がる残留応力を有するシリコン窒化膜と置き換えられることにより、別の半導体装置を形成することが可能である。つまり、シリコン窒化膜が半導体基板10側に凸に曲がることにより、上部容量電極25を、実施例1の上部容量電極25と比較して、半導体基板10から遠ざける位置に配置することが可能となる。半導体基板10側に凸に曲がるシリコン窒化膜を有する半導体装置は、犠牲膜を薄く形成しても、下部容量電極15と上部容量電極25との間隔をより大きく取ることが可能となり、犠牲膜を薄く形成できる分、製造工程の時間短縮が可能となる。   As a modification of the second embodiment, another semiconductor device can be formed by replacing the silicon nitride film 67 of the semiconductor device 2 with a silicon nitride film having a residual stress bending in the opposite direction. is there. That is, when the silicon nitride film is bent convexly toward the semiconductor substrate 10, the upper capacitor electrode 25 can be disposed at a position farther from the semiconductor substrate 10 than the upper capacitor electrode 25 of the first embodiment. . In a semiconductor device having a silicon nitride film that bends toward the semiconductor substrate 10 side, even if the sacrificial film is thinly formed, the gap between the lower capacitor electrode 15 and the upper capacitor electrode 25 can be made larger. The time required for the manufacturing process can be shortened by the thinness.

本発明は、上述した実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内で、種々、変形して実施することができる。   The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

例えば、実施例では、半導体基板がシリコンである例を示したが、半導体基板がGaAs、InP等の化合物半導体、シリコン酸化物等の酸化物基板であってもよく、また、サファイア、シリコン酸化物等の酸化物の上に形成したシリコン、または、化合物半導体等であっても差し支えない。   For example, in the embodiments, the example in which the semiconductor substrate is silicon has been shown. However, the semiconductor substrate may be a compound semiconductor such as GaAs or InP, or an oxide substrate such as silicon oxide, or sapphire or silicon oxide. It may be silicon formed on an oxide such as silicon or a compound semiconductor.

その他、以下の付記に記載されるような構成が考えられる。
(付記1) 半導体基板の表面に、ほぼ直線状に離間して配置された支持電極、下部駆動電極、及び下部容量電極を形成し、前記支持電極、前記下部駆動電極、及び前記下部容量電極の表面に第1の絶縁膜を形成する工程と、前記第1の絶縁膜を被うように前記半導体基板の表面に犠牲膜を形成して、前記支持電極の表面の前記犠牲膜及び前記第1の絶縁膜に前記支持電極に通ずる開口を形成する工程と、前記開口を埋め込み、前記犠牲膜の表面を被う導電体を形成し、前記導電体の上に、第2の絶縁膜を形成する工程と、前記下部駆動電極と前記下部容量電極との隙間に対向する位置に、前記第2の絶縁膜を残すようにパターニングする工程と、残された前記第2の絶縁膜の中央部の下側を通り、前記下部駆動電極と前記下部容量電極との前記隙間に対向する位置に分離溝を形成し、前記下部駆動電極と前記下部容量電極に対向する位置に前記導電体を残すようにパターニングする工程と、前記導電体がパターニングされて除去された部分から前記犠牲膜を除去する工程とを備えている半導体装置の製造方法。
In addition, configurations as described in the following supplementary notes are conceivable.
(Supplementary Note 1) A support electrode, a lower drive electrode, and a lower capacitor electrode, which are spaced apart substantially linearly, are formed on the surface of the semiconductor substrate, and the support electrode, the lower drive electrode, and the lower capacitor electrode are formed. Forming a first insulating film on the surface; forming a sacrificial film on the surface of the semiconductor substrate so as to cover the first insulating film; and the sacrificial film on the surface of the support electrode and the first Forming an opening leading to the support electrode in the insulating film, forming a conductor covering the surface of the sacrificial film by filling the opening, and forming a second insulating film on the conductor A step of patterning so as to leave the second insulating film at a position facing a gap between the lower drive electrode and the lower capacitor electrode; and a step below the central portion of the remaining second insulating film. Side and in front of the lower drive electrode and the lower capacitor electrode Forming a separation groove at a position facing the gap and patterning the conductor so as to leave the conductor at a position facing the lower drive electrode and the lower capacitor electrode; and a portion where the conductor is patterned and removed And a step of removing the sacrificial film from the semiconductor device.

(付記2) 前記導電体は、両端部で前記支持電極と接続され、一方の支持電極から、前記下部駆動電極に対向する上部駆動電極、前記第2の絶縁膜、及び前記下部容量電極に対向する上部容量電極へと接続され、前記上部容量電極の中央部から対称的に他方の支持電極へと接続されている付記1に記載の半導体装置の製造方法。 (Supplementary Note 2) The conductor is connected to the support electrode at both ends, and is opposed to the upper drive electrode facing the lower drive electrode, the second insulating film, and the lower capacitance electrode from one support electrode. The manufacturing method of the semiconductor device according to appendix 1, wherein the semiconductor device is connected to the upper capacitor electrode and connected symmetrically from the center of the upper capacitor electrode to the other support electrode.

(付記3) 前記導電体は、スパッタリング法により形成され、その後、前記第2の絶縁膜がCVD法により形成される付記1に記載の半導体装置の製造方法。 (Additional remark 3) The said conductor is a manufacturing method of the semiconductor device of Additional remark 1 with which the said 2nd insulating film is formed by CVD method after that by the sputtering method.

(付記4) 前記導電体は、前記半導体基板の表面に垂直な貫通孔を有している付記1に記載の半導体装置の製造方法。 (Additional remark 4) The said conductor is a manufacturing method of the semiconductor device of Additional remark 1 which has a through-hole perpendicular | vertical to the surface of the said semiconductor substrate.

(付記5) 前記犠牲膜は、ポリイミド樹脂である付記1に記載の半導体装置の製造方法。 (Additional remark 5) The said sacrificial film is a manufacturing method of the semiconductor device of Additional remark 1 which is a polyimide resin.

(付記6) 前記第2の絶縁膜は、短冊状に形成され、一方の端部と前記上部駆動電極とを接続し、他方の端部と前記上部容量電極とを接続する付記1に記載の半導体装置の製造方法。 (Supplementary note 6) The second insulating film is formed in a strip shape, and connects one end portion and the upper drive electrode, and connects the other end portion and the upper capacitive electrode. A method for manufacturing a semiconductor device.

本発明の実施例1に係る半導体装置の構成を模式的に示す図で、図1(a)は平面図、図1(b)は図1(a)のA−A線に沿った断面図。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the structure of the semiconductor device which concerns on Example 1 of this invention, Fig.1 (a) is a top view, FIG.1 (b) is sectional drawing along the AA of Fig.1 (a). . 本発明の実施例1に係る半導体装置の製造方法を工程順に模式的に示す構造断面図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural cross-sectional view schematically showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. 本発明の実施例1に係る半導体装置の図2に続く製造方法を工程順に模式的に示す構造断面図。Sectional drawing which shows typically the manufacturing method following FIG. 2 of the semiconductor device which concerns on Example 1 of this invention in order of a process. 本発明の実施例1に係る半導体装置の動作の一形態を模式的に示す断面図。Sectional drawing which shows typically one form of operation | movement of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例2に係る半導体装置の構成を模式的に示す図で、図5(a)は断面図、図5(b)は図5(a)の一部を拡大して示す断面図。FIGS. 5A and 5B are diagrams schematically illustrating a configuration of a semiconductor device according to a second embodiment of the present invention, in which FIG. 5A is a cross-sectional view, and FIG. 5B is an enlarged cross-sectional view of a part of FIG. .

符号の説明Explanation of symbols

1、2 半導体装置
10 半導体基板
11 支持電極
13 下部駆動電極
15 下部容量電極
17 絶縁膜
21 支柱
23 上部駆動電極
25 上部容量電極
26 孔
27、27a、67 シリコン窒化膜
31 犠牲膜
32、40、41 開口
33 導電膜
38、39 フォトレジスト
51 空隙
DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 10 Semiconductor substrate 11 Support electrode 13 Lower drive electrode 15 Lower capacitive electrode 17 Insulating film 21 Post 23 Upper drive electrode 25 Upper capacitive electrode 26 Holes 27, 27a, 67 Silicon nitride film 31 Sacrificial films 32, 40, 41 Opening 33 Conductive film 38, 39 Photo resist 51 Gaps

Claims (5)

半導体基板の表面に、ほぼ直線状に離間して配置された支持電極、下部駆動電極、及び下部容量電極を形成し、前記支持電極、前記下部駆動電極、及び前記下部容量電極の表面に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜を被うように前記半導体基板の表面に犠牲膜を形成して、前記支持電極の表面の前記犠牲膜及び前記第1の絶縁膜に前記支持電極に通ずる開口を形成する工程と、
前記開口を埋め込み、前記犠牲膜の表面を被う導電体を形成し、前記導電体の上に、第2の絶縁膜を形成する工程と、
前記下部駆動電極と前記下部容量電極との隙間に対向する位置に、前記第2の絶縁膜を残すようにパターニングする工程と、
残された前記第2の絶縁膜の中央部の下側を通り、前記下部駆動電極と前記下部容量電極との前記隙間に対向する位置に分離溝を形成し、前記下部駆動電極と前記下部容量電極に対向する位置に前記導電体を残すようにパターニングする工程と、
前記導電体がパターニングされて除去された部分から前記犠牲膜を除去する工程と、
を備えていることを特徴とする半導体装置の製造方法。
A support electrode, a lower drive electrode, and a lower capacitor electrode are formed on the surface of the semiconductor substrate so as to be spaced apart substantially linearly, and a first electrode is formed on the surfaces of the support electrode, the lower drive electrode, and the lower capacitor electrode. Forming an insulating film of
A sacrificial film is formed on the surface of the semiconductor substrate so as to cover the first insulating film, and an opening communicating with the support electrode is formed in the sacrificial film and the first insulating film on the surface of the support electrode. Process,
Forming a conductor that fills the opening, covers the surface of the sacrificial film, and forms a second insulating film on the conductor;
Patterning to leave the second insulating film at a position facing the gap between the lower drive electrode and the lower capacitor electrode;
A separation groove is formed at a position opposite to the gap between the lower drive electrode and the lower capacitor electrode, passing under the central portion of the remaining second insulating film, and the lower drive electrode and the lower capacitor Patterning to leave the conductor in a position facing the electrode;
Removing the sacrificial film from a portion where the conductor has been patterned and removed;
A method for manufacturing a semiconductor device, comprising:
前記第2の絶縁膜は、シリコン窒化膜であることを特徴とする請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film. 前記導電体は、ウェットエッチングで除去されることを特徴とする請求項1または2に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the conductor is removed by wet etching. 前記第2の絶縁膜は、応力を制御して形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed by controlling stress. 半導体基板と、
前記半導体基板上面に形成された支持電極と、
前記半導体基板上面に、前記支持電極とは離間して形成された下部駆動電極と、
前記半導体基板上面に、前記支持電極及び前記下部駆動電極とは離間して、前記支持電極と前記下部駆動電極とを結ぶ方向に配設された下部容量電極と、
前記下部駆動電極と前記下部容量電極とを被覆する第1の絶縁膜と、
前記半導体基板の上面に垂直に、前記支持電極に接続された支柱電極と、
前記下部駆動電極に対向且つ離間して、前記支柱電極にほぼ垂直に接続された梁状の上部駆動電極と、
前記上部駆動電極の上面端部と面接触で接続され且つ並行に延在する第2の絶縁膜と、
前記下部容量電極に対向且つ離間して、前記支柱電極にほぼ垂直に、前記第2の絶縁膜と上面端部で接触して接続された梁状の上部容量電極と、
を備えていることを特徴とする半導体装置。
A semiconductor substrate;
A support electrode formed on the upper surface of the semiconductor substrate;
A lower drive electrode formed on the upper surface of the semiconductor substrate and spaced apart from the support electrode;
A lower capacitor electrode disposed on a top surface of the semiconductor substrate in a direction connecting the support electrode and the lower drive electrode apart from the support electrode and the lower drive electrode;
A first insulating film covering the lower drive electrode and the lower capacitor electrode;
A column electrode connected to the support electrode perpendicular to the top surface of the semiconductor substrate;
A beam-like upper drive electrode connected to the pillar electrode substantially perpendicularly to and opposite to the lower drive electrode; and
A second insulating film connected in surface contact with the upper end of the upper drive electrode and extending in parallel;
A beam-shaped upper capacitor electrode connected to and in contact with the second insulating film at the upper end, substantially perpendicular to the column electrode, facing and spaced from the lower capacitor electrode;
A semiconductor device comprising:
JP2008311273A 2008-12-05 2008-12-05 Method for manufacturing semiconductor device, and semiconductor device Pending JP2010135634A (en)

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US9350073B2 (en) 2011-01-19 2016-05-24 Murata Manufacturing Co., Ltd. MEMS module, variable reactance circuit and antenna device
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JP2014529911A (en) * 2011-09-02 2014-11-13 キャベンディッシュ・キネティックス・インコーポレイテッドCavendish Kinetics, Inc. MEMS variable capacitor with improved RF performance
JP2013089482A (en) * 2011-10-19 2013-05-13 Fujitsu Ltd Mems switch and method for manufacturing the same
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