JP2010130576A - Electric circuit, shift register circuit, driver circuit, and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technologies capable of switching a potential between two transistors while suppressing an increase in power consumption. <P>SOLUTION: An electric circuit comprises a set signal imparting section for imparting a set signal to gate electrodes of both a first transistor and a second transistor to set the first transistor and the second transistor into a conducted state in which a current can flow. Furthermore, the electric circuit comprises a first signal imparting section which causes a first signal to flow to the first transistor in a state that a current can flow through the first transistor, and a second signal imparting section which causes a second signal to flow to the second transistor in a state that a current can flow through the second transistor. Moreover, the electric circuit comprises a control section for sequentially performing switching, in a state that the set signal is imparted, between a first signal state where the first signal flows and an output signal is output, and a second state where the second signal does not flow and the output signal is not output. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electric circuit that switches a potential between two transistors, and a shift register circuit, a driver circuit, and an image display device using the electric circuit.

  In recent years, in a display panel using an organic EL element or the like, a technique for embedding a so-called gate driver integrally in the display panel has been proposed for the purpose of reducing manufacturing costs.

  A shift register circuit in which a set signal from the previous stage is sequentially transmitted to the subsequent stage is disclosed as a driver for selecting and scanning image pickup elements or display elements in which pixel circuits are arranged in a matrix. (For example, Patent Document 1).

  Here, regarding the circuit of each stage constituting the shift register circuit proposed in Patent Document 1, control of the set signal output from the set signal terminal OUT will be described with reference to FIG.

  As shown in FIG. 23, a reference voltage (for example, + 25V) is always applied between the constant voltage input terminal SS and the reference voltage input terminal DD with reference to the constant voltage input terminal SS, so that a TFT (thin film The same potential is applied to the gate and drain of transistor 23). At this time, the TFT 23 is always set to a state (conduction state) in which a current can flow between the drain and the source. Further, depending on whether or not a positive potential is applied to the gate of the TFT 22, the TFT 22 is set to a conductive state or a state in which no current can flow between the drain and the source (non-conductive state).

  When the TFT 22 is in a conductive state, the TFT 24 is set in a conductive state and the TFT 25 is set in a non-conductive state. In such a setting state, a set signal corresponding to a signal applied to the clock signal input terminal clk is output from the set signal terminal OUT. On the other hand, when the TFT 22 is in a non-conductive state, the TFT 24 is set in a non-conductive state and the TFT 25 is set in a conductive state. In such a setting state, the set signal corresponding to the signal applied to the clock signal input terminal clk is not output from the set signal terminal OUT.

JP 2001-160299 A

  However, in the shift register circuit proposed in Patent Document 1, if the TFT 22 is set in a conductive state in order to set the TFT 25 in a non-conductive state, both the two TFTs 22 and 23 are in a conductive state. At this time, a relatively large current (hereinafter referred to as “through current”) flows through the two TFTs 22 and 23 from the reference voltage input terminal DD to the constant voltage input terminal SS, which causes an increase in power consumption. In particular, in all stages of the shift register circuit, in a mode in which the set signal is simultaneously output from the set signal terminal OUT for a certain period, the above-described through current is significantly increased, that is, the power consumption is significantly increased.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of switching a potential between two transistors while suppressing an increase in power consumption.

  In order to solve the above problems, an electric circuit according to a first aspect of the present invention provides a set signal to both gate electrodes of a first transistor and a second transistor, and the first transistor and the second transistor Is provided with a set signal applying unit that sets a conductive state in which current can flow. The electric circuit includes a first signal applying unit that supplies a first signal to the first transistor in a state where a current can flow through the first transistor, and a first signal applying unit that allows a current to flow through the second transistor. A second signal applying unit for supplying a second signal to the two transistors. Further, in the state where the set signal is applied, the electric circuit has a first signal state in which the first signal flows and an output signal is output, and the second signal does not flow and the output signal is not output. A control unit that sequentially switches to the second signal state is provided.

  The electric circuit according to the second aspect of the present invention includes first, second, and third electrodes, and the first electrode and the second electrode are provided in response to application of a potential to the third electrode. A current between the fourth electrode and the fifth electrode in response to application of a potential to the sixth electrode. The second transistor is adjusted. The electrical circuit includes seventh, eighth, and ninth electrodes, and a current between the seventh electrode and the eighth electrode is adjusted according to application of a potential to the ninth electrode. And a fourth transistor having tenth, eleventh, and twelfth electrodes, wherein a current between the tenth electrode and the eleventh electrode is adjusted in accordance with application of a potential to the twelfth electrode; Is provided. In addition, the electric circuit applies a set signal to the third and sixth electrodes so that a current can flow between the first electrode and the second electrode in the first transistor. And a set signal applying unit that sets the second transistor to a conductive state in which a current can flow between the fourth electrode and the fifth electrode, and a first signal to the first electrode. A first signal applying unit for applying, and a second signal applying unit for applying a second signal to the fourth electrode. In the electrical circuit, the second electrode is electrically connected to the ninth and tenth electrodes, and the fifth electrode is electrically connected to the seventh and twelfth electrodes. When the set signal is applied to the third and sixth electrodes, the first signal is applied to the ninth electrode, so that the third transistor The first transistor is set in a conductive state in which a current can flow between the seventh electrode and the eighth electrode, and the second signal is applied to the twelfth electrode, whereby the fourth transistor Are sequentially set to a second setting state in which a current can flow between the tenth electrode and the eleventh electrode.

  An electric circuit according to the third aspect of the present invention is the electric circuit according to the second aspect of the present invention, and includes the thirteenth, fourteenth and fifteenth electrodes, and the electric potential of the fifteenth electrode is A fifth transistor in which a current between the thirteenth electrode and the fourteenth electrode is adjusted according to the application; and a sixteenth, seventeenth, and eighteenth electrode; and according to the application of a potential to the eighteenth electrode. And a sixth transistor for adjusting a current between the sixteenth electrode and the seventeenth electrode. The electric circuit is electrically connected to an input signal applying unit that applies an input signal to the thirteenth electrode and a wiring that electrically connects the fourteenth electrode and the sixteenth electrode. And a signal output unit for outputting an output signal. In the electric circuit, the fifteenth electrode is electrically connected to the second, ninth, and tenth electrodes, and the eighteenth electrode is the fifth, seventh, and twelfth electrodes. Is electrically connected.

  An electric circuit according to a fourth aspect of the present invention is the electric circuit according to the second or third aspect of the present invention, comprising the nineteenth, twentieth and twenty-first electrodes, wherein the twenty-first electrode A seventh transistor in which the current between the nineteenth electrode and the twentieth electrode is adjusted in response to the potential applied to the second electrode, and the twenty-second, twenty-third, and twenty-fourth electrodes. An eighth transistor in which a current between the twenty-second electrode and the twenty-third electrode is adjusted according to the application; and a reset signal applying unit that applies a reset signal to the twenty-first and twenty-fourth electrodes. . Further, in the electric circuit, the nineteenth electrode is electrically connected to a third signal applying unit set to the same potential as the second signal applying unit, and the twentieth electrode is connected to the ninth and tenth electrodes. Electrically connected to the tenth electrode, the twenty-second electrode is electrically connected to a fourth signal applying unit set at the same potential as the first signal applying unit, and the twenty-third electrode is , And electrically connected to the seventh and twelfth electrodes. In the electric circuit, the set signal is applied from the set signal applying unit to the third and sixth electrodes, and the reset signal is applied from the reset signal applying unit to the 21st and 24th electrodes in sequence. To be done. Further, in the electric circuit, in a state where the reset signal is applied to the twenty-first and twenty-fourth electrodes from the reset signal applying unit, the fourth signal applying unit passes through the eighth transistor. By applying the first signal to the twelfth electrode, the fourth transistor is set to the second setting state in which the conduction state is set.

  A shift register circuit according to a fifth aspect of the present invention includes a plurality of electric circuits according to the fourth aspect of the present invention, first and second input signal lines, and each of the plurality of electric circuits. 1st and 4th signal provision part is electrically connected, respectively, The 1st signal line which gives the 1st signal to each of the 1st and 4th signal provision parts, and each 2nd of these electric circuits And a third signal applying unit electrically connected to each other, and a second signal line for applying the second signal to the second and third signal applying units. Further, in the shift register circuit, the plurality of electric circuits are sequentially arranged, and the input signal applying unit of each of the electric circuits arranged in an odd number among the plurality of electric circuits includes the first register. The input signal applying unit of each of the electric circuits electrically connected to the input signal lines and arranged in even-numbered ones of the plurality of electric circuits is connected to the second input signal line. Each is electrically connected. Furthermore, in the shift register circuit, the reset signal applying unit of the electric circuit arranged at one end of the plurality of electric circuits is arranged next to the electric circuit arranged at the one end. The set signal applying unit of the electric circuit that is electrically connected to the signal output unit of the electric circuit and arranged at the other end of the plurality of electric circuits is arranged at the other end. It is electrically connected to the signal output part of the electrical circuit arranged in front of the electrical circuit. In the shift register circuit, in each of the electric circuits excluding the electric circuit arranged at the one end and the other end of the plurality of electric circuits, the set signal applying unit is arranged in front of each other. The signal output unit of the electrical circuit is electrically connected to the signal output unit of the electrical circuit, and the reset signal applying unit is electrically connected to the signal output unit of the electrical circuit arranged next.

  A shift register circuit according to a sixth aspect of the present invention is the shift register circuit according to the fifth aspect of the present invention, wherein the first signal is applied to each of the first electrode and each of the twenty-second electrodes. And the second signal is not applied to each of the fourth electrode and each of the nineteenth electrodes, and the set signal is applied to the set signal applying unit of the electric circuit arranged at the one end. After the signal is applied, the application of the input signal to the electric circuits by the first input signal line and the application of the input signal to the electric circuits by the second input signal line are alternately performed.

  The driver circuit according to the seventh aspect of the present invention further includes a shift register circuit according to the fifth or sixth aspect of the present invention, and first and second mode signal lines. Further, in the driver circuit, each of the electric circuits has 25th, 26th, and 27th electrodes, and the electric circuit between the 25th electrode and the 26th electrode according to application of a potential to the 27th electrode. It has a ninth transistor for adjusting the current, and the 28th, 29th, and 30th electrodes, and the current between the 28th electrode and the 29th electrode is adjusted according to the potential applied to the 30th electrode. A tenth transistor, and thirty-first, thirty-second, and thirty-third electrodes, and a current between the thirty-first electrode and the thirty-second electrode is adjusted in accordance with the application of a potential to the thirty-third electrode. And 11 transistors. Further, in the driver circuit, each of the electric circuits has 34th, 35th, and 36th electrodes, and the electric circuit between the 34th electrode and the 35th electrode is applied in response to application of a potential to the 36th electrode. It has a twelfth transistor whose current is adjusted, and 37th, 38th and 39th electrodes, and the current between the 37th electrode and the 38th electrode is adjusted according to the application of a potential to the 39th electrode. A thirteenth transistor, a forty-first, forty-second, and a forty-second electrode, and the current between the forty-fourth electrode and the forty-first electrode is adjusted according to the application of a potential to the forty-second electrode. 14 transistors. In the driver circuit, in each of the electric circuits, the second electrode and the ninth, tenth, and fifteenth electrodes are electrically connected via the twenty-fifth and twenty-sixth electrodes, The twentieth electrode and the ninth, tenth, and fifteenth electrodes are electrically connected via the twenty-eighth and twenty-ninth electrodes, and the fifth electrode, the seventh, twelfth, and 18 electrodes are electrically connected via the 31st and 32nd electrodes, and the 23rd electrode, the 7th, 12th and 18th electrodes are connected via the 34th and 35th electrodes. Are electrically connected. Further, in the driver circuit, in each of the electric circuits, the 37th electrode is electrically connected to the first signal line, and the 38th electrode is the ninth, tenth, and fifteenth electrodes. The 40th electrode is electrically connected to the second signal line, and the 41st electrode is electrically connected to the 7th, 12th and 18th electrodes. The first mode signal line is electrically connected to the 27th, 30th, 33rd and 36th electrodes, and the second mode signal line is the 39th and 42nd. Electrically connected to the electrode.

  A driver circuit according to an eighth aspect of the present invention is the driver circuit according to the seventh aspect of the present invention, wherein the first mode signal line includes the 27th, 30th, 33rd, and By applying a first mode signal to each of the 36 electrodes, the ninth transistor becomes a conductive state in which a current can flow between the 25th electrode and the 26th electrode, and the 10th transistor A conduction state in which a current can flow between the 28th electrode and the 29th electrode; the eleventh transistor; a conduction state in which a current can flow between the 31st electrode and the 32nd electrode; The conductive state is set such that a current can flow between the 34th electrode and the 35th electrode. In the driver circuit, the second mode signal line applies a second mode signal to the 39th and 42nd electrodes, respectively, so that the 13th transistor is connected to the 37th electrode and the 37th electrode. The conduction state in which a current can flow between the 38th electrode and the fourteenth transistor is set in a conduction state in which a current can flow between the 40th electrode and the 41st electrode, respectively. In the driver circuit, the first mode signal is applied to each electric circuit by the first mode signal line, and the first mode signal is applied to each electric circuit. It is alternately set to the state that is not.

  An image display device according to a ninth aspect of the present invention includes a driver circuit according to the seventh or eighth aspect of the present invention and a plurality of pixels each configured by arranging a plurality of pixel circuits in one direction. The line includes a display unit arranged in another direction different from the one direction. In the image display device, the output terminal of each electric circuit outputs the output signal to each of the plurality of pixel circuits included in the corresponding pixel line among the plurality of pixel lines. .

  A shift register circuit according to a tenth aspect of the present invention is the shift register circuit according to the fifth or sixth aspect, wherein each of the first to eighth transistors included in the electric circuit is , An n-type transistor.

  The present invention suppresses generation of current from the first signal applying unit via the first transistor and the fourth transistor and generation of current from the second signal applying unit through the second transistor and the third transistor. On the other hand, since the potential state between the first transistor and the fourth transistor and the potential state between the second transistor and the third transistor can be switched alternately, an increase in power consumption is suppressed. Can do.

<Terminology>
In this specification, the term “electrically connected” means that one member and the other member are always connected in a conductive manner via wiring or the like, and one member and the other member However, it is used in the meaning including not only the wiring etc. which have electroconductivity but the aspect indirectly connected by the other member. In other words, the term “electrically connected” means that one member and the other member are connected to each other depending on the state of other members (for example, a conductive state in which a current can flow between the source and the drain of the transistor). Is used in a meaning including a mode in which the wiring is conductively connected by wiring and other members.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

<Schematic configuration of image display device>
FIG. 1 is a diagram showing a functional configuration of an image display apparatus 1 according to an embodiment of the present invention. The image display device 1 constitutes a device (organic EL device) using light emission of an organic EL element.

  The image display device 1 mainly includes a control unit 2, an organic EL display unit 3, an X driver circuit 4X, and a Y driver circuit 4Y. In the image display device 1, the image signal is composed of signals related to the three primary colors of red (R), green (G), and blue (B), and the organic EL display unit 3 emits red light. A light emitting element that emits green light and a light emitting element that emits blue light.

  The control unit 2 is a part that performs overall control of the operation of the image display device 1 and includes a CPU, a ROM, a RAM, and the like. For example, programs and various data are stored in the ROM, and various controls and functions in the control unit 2 are realized by the CPU reading and executing the programs in the ROM.

  As shown in FIG. 1, by executing a program in the control unit 2, the γ conversion units 201R, 201G, and 201B and the timing generator (TG) 202 are realized as functional configurations.

γ conversion unit 201R, 201G, 201B, each color value corresponding to each pixel (i.e. the gradation values) receives an input image signal is _{D r, D g, D b} , performs so-called gamma correction. Here, for example, the gradation values D _r , D _g , and D _{b of} the respective colors are converted into values that are raised to the power of about 2.2. Specifically, for example, a 6-bit input image signal (an image signal having a gradation value of 0 to 63) is converted into a 10-bit output image signal (an image signal having a gradation value of 0 to 1023). The converted output image signal is input to the X driver circuit 4X.

  In response to the input image signal input to the control unit 2, the TG 202 outputs a signal for controlling the operation of the X driver circuit 4X and the Y driver circuit 4Y to the X driver circuit 4X and the Y driver circuit 4Y. To do. That is, the operations of the X driver circuit 4X and the Y driver circuit 4Y are synchronized with the input / output of the input image signal and the output image signal.

  The organic EL display unit 3 is an organic EL display (organic electroluminescence display) having a substantially rectangular outline, and includes a self-luminous light emitting element that emits light by flowing current through the organic material. That is, the organic EL display unit 3 constitutes a display unit (self-luminous display unit) including a self-luminous light emitting element.

  A number of pixel circuits 31 are arranged in the organic EL display unit 3, and each pixel circuit 31 includes a light emitting element (here, an organic EL element). And many light emitting elements are arranged in the shape of a lattice, for example. In other words, the organic EL display unit 3 is formed with pixel lines (pixel lines, hereinafter also referred to as “horizontal lines”) formed of a plurality of pixel circuits 31 along one direction (here, the horizontal direction). Yes. Furthermore, a plurality of such horizontal lines are arranged along another direction (here, the vertical direction) different from the one direction. In the present embodiment, it is assumed that n + 1 (n is an arbitrary natural number, for example, n = 479) horizontal lines are arranged on the organic EL display unit 3.

Further, the organic EL display unit 3 is provided with a plurality of image signal lines L _is (see FIG. 2) for supplying an output image signal corresponding to the light emission luminance to each pixel circuit 31. Further, the organic EL display unit 3, a plurality of scanning signal lines L _ss (see FIG. 2) is provided substantially perpendicular to the plurality of image signal lines L _IS. Here, one scanning signal line L _ss is provided for each horizontal line. The scanning signal is a signal for controlling the timing for supplying an output image signal through the image signal line L _IS in each pixel circuit 31. Further, the organic EL display unit 3 is provided with power supply lines L _vd and L _vs (see FIG. 2) for supplying a voltage necessary for light emission between both electrodes of the organic EL element 11 included in each pixel circuit 31. .

X driver circuit 4X is electrically connected to the plurality of image signal lines L _IS, an output image signal is a circuit for controlling the timing of supplying to the image signal line L _IS (image signal line driving circuit).

The Y driver circuit 4Y is a circuit (scanning signal line driving circuit) that controls the timing for supplying the scanning signal to each scanning signal line L _ss . A shift register circuit 400 (see FIG. 14), which will be described later, is applied to the Y driver circuit 4Y, thereby suppressing an increase in power consumption.

Note that various known circuits can be used as the circuit for controlling the timing for adjusting the voltage between the power supply line L _vd and the power supply line L _vs, and thus description thereof is omitted in this specification.

  In the image display device 1, for example, the X driver circuit 4 </ b> X is arranged along one side (for example, a short side or a long side) of the organic EL display unit 3, and the Y driver circuit 4 </ b> Y is connected to the organic EL display unit 3. It arrange | positions along the other side (for example, long side or short side) substantially orthogonal to one side.

  Here, an example in which various functions of the control unit 2 are realized by executing a program by the CPU has been described, but the present invention is not limited thereto. For example, all or part of the configuration of the control unit 2 may be realized by a hardware configuration such as a dedicated electronic circuit.

<Configuration of pixel circuit>
FIG. 2 is a diagram illustrating a configuration example of a pixel circuit (drive circuit) 31 for one pixel constituting the image display device 1.

The pixel circuit 31 includes an organic EL element (OLED) 11, a drive transistor 12, a threshold (V _th ) compensation transistor 13, and a capacitor 14.

  The organic EL element 11 is a light emitting element whose light emission luminance is changed by a current flowing through the light emitting layer. The organic EL element 11 includes an anode electrode 11a and a cathode electrode 11b.

The anode electrode 11a is electrically connected to a V _DD line L _vd as a power supply line that becomes a high potential side when the organic EL element 11 emits light. Further, the cathode electrode 11b is electrically connected via the drive transistor 12 to the V _SS line L _vs as a power supply line that is on the low potential side when the organic EL element 11 emits light. Further, the cathode electrode 11 b is electrically connected to the one electrode 13 ds of the V _th compensation transistor 13.

  The drive transistor 12 is a transistor that is electrically connected in series to the organic EL element 11 and controls the light emission luminance of the organic EL element 11 by adjusting a current in the organic EL element 11. Here, the drive transistor 12 is a thin film transistor (TFT: Thin Film Transistor) which is a type of field effect transistor (FET) that employs a type (n-type) MIS (Metal Insulator Semiconductor) structure in which carriers are electrons. ), I.e., an n-MISFET TFT. The drive transistor 12 has one electrode 12ds, the other electrode 12sd, and a control electrode 12g.

On the other hand, the electrode 12 ds is electrically connected to the cathode electrode 11 b of the organic EL element 11. The one electrode 12ds functions as a drain when current flows in the direction (forward direction) from the anode electrode 11a to the cathode electrode 11b and the organic EL element 11 emits light. Further, when a voltage is applied in the reverse direction to the organic EL element 11, the one electrode 12ds functions as a source. The one electrode 12ds is electrically connected to the one electrode 13ds of the V _th compensation transistor 13.

The other electrode 12sd is electrically connected to the V _SS line L _vs. The other electrode 12 sd functions as a source when a forward current flows through the organic EL element 11. Further, when a voltage is applied in the reverse direction to the organic EL element 11, the other electrode 12sd functions as a drain. Further, the control electrode 12g is a so-called gate, and is electrically connected to the other electrode 13sd of the V _th compensation transistor 13 and the one electrode 14a of the capacitor 14, respectively.

  Further, in the drive transistor 12, a potential applied to the control electrode 12g, more specifically, a voltage value applied between the one electrode 12ds or the other electrode 12sd and the control electrode 12g (that is, between the gate and the source). By adjusting, the current flowing between the one electrode 12ds and the other electrode 12sd is adjusted. The drive transistor 12 has a state in which a current can flow between the drain and the source (hereinafter referred to as a “conductive state”) and a state in which a current cannot flow (hereinafter referred to as “the current state”). (Referred to as “non-conducting state”).

The V _th compensation transistor 13 detects the lower limit value (predetermined threshold voltage V _th ) of the potential of the control electrode 12g with respect to the other electrode 12sd when the drive transistor 12 is in a conductive state (that is, an ON state) and is driven The transistor 12 adjusts the gate voltage of the transistor 12 to a threshold voltage V _th (hereinafter abbreviated as “threshold V _th ”). That is, the “threshold value V _th ” refers to a gate voltage serving as a boundary when the driving transistor 12 changes from an off state (a state where a drain current does not flow) to an on state (a state where the drain current flows). In this case, the V _th compensation transistor 13 is also composed of an n-MISFET TFT like the drive transistor 12. The V _th compensation transistor 13 has one electrode 13ds, the other electrode 13sd, and a control electrode 13g.

On the other hand, the electrode 13ds is electrically connected to the cathode electrode 11b of the organic EL element 11 and the one electrode 12ds of the drive transistor 12, respectively. The other electrode 13sd is electrically connected to the control electrode 12g of the drive transistor 12 and the one electrode 14a of the capacitor 14, respectively. The control electrode 13g is electrically connected to the scanning signal line L _ss .

Further, in the V _th compensation transistor 13, a potential applied to the control electrode 13g, more specifically, applied between the one electrode 13ds or the other electrode 13sd and the control electrode 13g (that is, between the gate and the source). The current flowing between the one electrode 13ds and the other electrode 13sd is adjusted by adjusting the voltage value. The V _th compensation transistor 13 is in a state where current can flow between the drain and source (conducting state) and a state where current cannot flow (non-conducting state) due to the potential applied to the control electrode 13g. And are set selectively.

By the way, since the light emission luminance of the organic EL element 11 is controlled by the current, the light emission luminance fluctuates sensitively to fluctuations in the gate voltage of the drive transistor 12 during light emission. In particular, when the driving transistor 12 is configured using amorphous silicon, the threshold V _th tends to be different for each driving transistor 12. Therefore, if a function for compensating a different threshold V _th for each pixel (V _th compensation function) is not provided, there is a slight difference between the desired light emission luminance and the actual light emission luminance, resulting in light emission between the pixels. Uneven brightness will occur.

Therefore, the V _th compensation transistor 13 realizes a V _th compensation function that compensates for variations in the threshold V _th in the drive transistor 12 by matching the gate voltage of the drive transistor 12 to the threshold V _th for each pixel before light emission. .

The capacitor 14 includes a first electrode 14a and a second electrode 14b. The one electrode 14 a is electrically connected to the control electrode 12 g of the drive transistor 12 and the other electrode 13 sd of the V _th compensation transistor 13. The other electrode 14b is electrically connected to the image signal line L _IS. Here, the retention capacity of the capacitor 14 with a predetermined value C _s.

Incidentally, the organic EL element 11, the voltage of the light emitting time of the reverse is applied to function as a capacitor, to the capacitance (EL element capacitor) with a predetermined value C _o. The drive transistor 12 has a parasitic capacitance C _Gstd between the other electrode 12sd and the control electrode 12g, whereas the parasitic capacitance C _GdTd between the electrode 12ds and the control electrode 12g. Furthermore, V _th compensation transistor 13 has a parasitic capacitance C _GsTth between the other electrode 13sd and the control electrode 13 g, whereas the parasitic capacitance C _GdTth between the electrode 13ds and the control electrode 13 g. The parasitic capacitances C _gsTd , C _gdTd , C _gsTth , and C _gdTth are capacitances having predetermined values determined by the configurations of the drive transistor 12 and the V _th compensation transistor 13, respectively.

3, the circuit configuration of the pixel circuit 31 shown in FIG. 2, the parasitic capacitance _{C gsTth, C gdTth, C gsTd} , the configuration according to the C _GdTd and EL element capacitance C _o (the figure described by the dashed line) It is the added schematic diagram.

As shown in Figure 3, in the pixel circuit 31, between the electrodes of the organic EL element 11 capacitor (element capacitor) C _ol is present having an EL element capacitance C _o, the other electrode 12sd and control of the driving transistor 12 capacitor 12gs having parasitic capacitance C _Gstd exists between the electrode 12g. A capacitor 12gd having a parasitic capacitance C _gdTd exists between the one electrode 12ds of the drive transistor 12 and the control electrode 12g. Furthermore, a capacitor 13gs having parasitic capacitance C _GsTth exists between the other electrode 13sd and the control electrode 13g of the V _th compensation transistor 13. _Further , a capacitor 13gd having a parasitic capacitance C _gdTth exists between the one electrode 13ds of the V _th compensation transistor 13 and the control electrode 13g.

Here, the description has been given focusing on one pixel circuit 31, but the entire organic EL display unit 3 includes a large number (here, n + 1) of pixel circuits 31. For this reason, there are a large number of scanning signal lines L _ss . Therefore, in the following, a large number of scanning signal lines L _ss will be referred to as “nth scanning signal lines (n is an integer of 0 or more) L _ss ” as appropriate.

<Driving method for light emission of organic EL element>
FIG. 4 is a timing chart showing a signal waveform (drive waveform) when the organic EL element 11 emits light. In FIG. 4, the horizontal axis indicates time, and in order from the top, (a) the potential applied to the V _DD line L _vd (potential V _dd ), (b) the potential applied to the V _SS line L _vs (potential V _SS), (c) the potential of the 0 signal applied to the scanning signal line L _SS (potential V _ls0), (d) the potential of the signal applied to the first scanning signal line L _SS (potential V _ls1), ( e) The waveform of the potential of the signal (potential V _lis ) applied to the image signal line Lis _is shown.

Further, FIG. 4 shows a drive waveform for causing the organic EL element 11 to emit light once, and the period related to one light emission is a C _s initialization period P1 (time t _{a to} t _b), the preparation period P2 (time t _b ~t _c), V _th compensation period P3 (time t _c ~t _d), the writing period P4 (time t _d ~t _e), device initialization period P5 (time t _e ~t _f), and configured with the light emission period P6 (time t _f ~). Since the potential V _lis in the writing period P4 is an arbitrary value determined by the light emission luminance of each organic EL element 11, in FIG. 4, hatched hatching is added for convenience in a range where the potential can exist. Yes.

  FIGS. 5 to 9 are diagrams illustrating the flow of current in the pixel circuit 31 that occurs in each period when the image display device 1 is driven, with black arrows. In FIG. 5 to FIG. 9, among the pixel circuits 31, circuits that contribute to the current flow are indicated by bold lines, and circuits that hardly contribute to the current flow are indicated by thin lines. Hereinafter, a method for driving the image display apparatus 1 according to the embodiment of the present invention will be described with reference to FIGS. 4 and 5 to 9 as appropriate.

○ C _s initialization period P1:
FIG. 5 illustrates a current flow in the pixel circuit 31 in the C _s initialization period P1 (hereinafter, abbreviated as “period P1” as appropriate).

In the period P1, a predetermined positive high potential V _DD (for example, 15 V) is applied to the V _DD line L _vd and the V _SS line L _vs. Further, a predetermined positive high potential V _gH (for example, 15 V) is applied to all the scanning signal lines L _ss . Furthermore, a predetermined reference potential to the image signal line L _IS (here, 0V) is applied.

At this time, by the application of high voltage V _gH in the scanning signal line L _ss, positive potential corresponding to the high potential V _gH is applied to the control electrode 13 g, V _th compensation transistor 13 becomes conductive. On the other hand, the V _DD line L _vd and the V _SS line L _vs have substantially the same potential, and the drive transistor 12 is in a non-conduction state (that is, an OFF state). Therefore, in the period P1, as shown in FIG. 5, a current flows from the V _DD line L _vd to the capacitor 14 via one and the other electrodes 13ds and 13sd of the V _th compensation transistor 13, and the capacitor 14 A fixed amount of charge (for example, a charge amount corresponding to 15V) is accumulated.

Note that the amount of charge accumulated in the capacitor 14 increases with the passage of time in the period P1, and a positive potential exceeding a predetermined value is applied to the control electrode 12g, so that the driving transistor 12 may be in a conductive state. However, since the V _DD line L _vd and the V _SS line L _vs are both set to the same potential V _DD , no current flows between the one electrode 12ds and the other electrode 12sd of the drive transistor 12.

○ Preparation period P2:
FIG. 6 illustrates the flow of current in the pixel circuit 31 in the preparation period P2 (hereinafter abbreviated as “period P2” as appropriate).

In the period P2, a negative predetermined potential −V _p (for example, −7 V) is applied to the V _DD line L _vd . Further, a predetermined reference potential (0 V in this case) is applied to the V _SS line L _vs. In addition, a predetermined low potential V _gL (for example, −10 V) is applied to all the scanning signal lines L _ss . Moreover, given the high potential V _dH to the image signal line L _IS (e.g. 10V) is applied.

At this time, by applying the low potential V _{gL to} the scanning signal line L _ss , almost no positive potential is applied to the control electrode 13g, so that the V _th compensation transistor 13 is turned off. On the other hand, when the high potential V _{dH is applied to} the image signal line Lis, a positive potential (for example, 15 + 10 = 25 V) corresponding to the high potential V _dH is applied to the control electrode 12g, and the drive transistor 12 is turned on.

Since the high potential V _p towards the V _SS line L _vs than V _DD line L _vd, as shown in Figure 6, the other and one electrode 12sd of the driving transistor 12 from the V _SS line L _vs, the 12ds A current flows toward the organic EL element 11 sequentially. At this time, a predetermined amount of electric charge (for example, electric charge corresponding to 7 V) corresponding to the potential difference between the V _DD line L _vd and the V _SS line L _vs is accumulated in the element capacitor _Col.

○ _Vth compensation period P3:
FIG. 7 illustrates the flow of current in the pixel circuit 31 in the _Vth compensation period P3 (hereinafter abbreviated as “period P3” where appropriate).

In the period P3, a predetermined reference potential (here, 0 V) is applied to the V _DD line L _vd and the V _SS line L _vs. Further, the high potential V _gH is applied to all the scanning signal lines L _ss . Further, a high potential V _dH (for example, 10 V) _{is applied} to the image signal line Lis.

At this time, by applying the high potential V _{gH to} the scanning signal line L _ss , a positive potential corresponding to the high potential V _gH is applied to the control electrode 13g, and the V _th compensation transistor 13 becomes conductive. Further, in the initial period P3, the potential V _dH granted to charge the image signal line L _IS accumulated in the capacitor 14, the driving transistor 12 becomes conductive.

Therefore, at the beginning of the period P3, as shown in FIG. 7, the current accompanying the charge accumulated in the capacitor 14 is transferred from the capacitor 14 to the other and one electrodes 13sd and 13ds of the _Vth compensation transistor 13, and further to the drive transistor. It flows toward the V _SS line L _vs through the one and other electrodes 12ds and 12sd of 12 in order. The current caused by the charges accumulated in the element capacitor C _ol is one and the other electrode 12ds of the driving transistor 12, flows toward the V _SS line L _vs by sequentially through 12SD.

However, as the current associated with the charge accumulated in the capacitor 14 flows from the capacitor 14 toward the V _SS line L _vs , the charge accumulated in the capacitor 14 decreases. Then, the potential of the control electrode 12g to the other electrode 12sd of the driving transistor 12 (gate voltage) V _g is the reduced to substantially the threshold V _th, the driving transistor 12 becomes nonconductive. At this time, the capacitor 14 is in a state where charges according to the threshold value V _th are accumulated. As described above, in the period P3, the electric charge corresponding to the threshold value _Vth is accumulated in the capacitor 14, and the variation in the threshold value _Vth that is different for each pixel is compensated.

○ Writing period P4:
FIG. 8 illustrates the flow of current in the pixel circuit 31 in the writing period P4 (hereinafter abbreviated as “period P4” as appropriate).

In the period P4, the reference potential 0V is applied to the V _DD line L _vd and the V _SS line L _vs , respectively, and in the target pixel of the process (data writing process) for accumulating charges according to the output image signal, A high potential V _gH is applied to the scanning signal line L _ss , and a potential (V _dH −V _data ) _{is applied} to the image signal line Lis. The potential V _data is a potential of the output image signal and is a potential corresponding to a value corresponding to the luminance gradation of the pixels constituting the image.

At this time, by applying the high potential V _{gH to} the scanning signal line L _ss , a positive potential corresponding to the high potential V _gH is applied to the control electrode 13g, and the V _th compensation transistor 13 becomes conductive. On the other hand, since the potential (V _dH −V _data ) equal to or lower than the potential V _dH in the period P3 _{is applied} to the image signal line L _{is and} the gate voltage V _g of the drive transistor 12 is equal to or lower than the threshold V _th , the drive transistor 12 becomes a non-conduction state.

Therefore, in the period P4, as shown in FIG. 8, from the organic EL element 11 (that is, the element capacitor C _ol ) to the capacitor 14 via the one and other electrodes 13ds and 13sd of the V _th compensation transistor 13 sequentially. Current flows. As a result, the charge corresponding to the potential V _data is added to the charge corresponding to the threshold value V _th already accumulated in the capacitor 14 and accumulated. That is, in the period P4, electric charges corresponding to the light emission luminance of the organic EL element 11 are accumulated in the capacitor 14. In other words, in the period P <b> 4, charges corresponding to the output pixel signal are accumulated in the capacitor 14 in the pixel circuit 31.

Note that the amount of change in the potential of the one electrode 14a of the capacitor 14 (that is, the gate potential of the driving transistor 12) _is the amount of change in the potential of the image signal line Lis, the holding capacitance C _s of the capacitor 14, and the EL of the element capacitor C _ol . It relies on the product of the ratio of the device capacitance C _o (volume ratio). That is, in the present embodiment, when the potential of the image signal line L _IS changes from V _dH to V _data, the gate potential of the driving transistor 12 _{is, (V data -V dH) ×} C s / (C s + C o )Change. For _{example, V dH = 10V, V data} = 5V, C s: C o = 1: When a 2, the potential of the image signal line L _IS is -5V changes, the gate potential V _g of the drive transistor 12, Due to the movement of charge from the organic EL element 11 to the capacitor 14, (5-10) × 1 / (1 + 2) = − 5 / 3V changes. Thus, the change in the potential of the image signal line Lis _is reflected in the gate potential of the drive transistor 12 due to the movement of the charge accumulated in the capacitor 14.

○ Element initialization period P5:
In the element initialization period P5 (hereinafter abbreviated as “period P5” as appropriate), a predetermined negative potential −V _p is applied to the V _DD line L _vd and the V _SS line L _vs. Further, the low potential V _gL is applied to all the scanning signal lines L _ss . Further, the high potential V _{dH is applied} to the image signal line Lis. At this time, the V _th compensation transistor 13 is turned off, and the drive transistor 12 is turned on. Since there is no potential difference between the V _DD line L _vd and the V _SS line L _vs and the V _SS line L _vs is set to the negative potential −V _p , the organic EL element 11 (that is, the element capacitor C _ol ) The charge accumulated in the organic EL element 11 passes through the V _SS line L _vs and the charge accumulated in the organic EL element 11 is wiped out.

○ Light emission period P6:
FIG. 9 illustrates the flow of current in the pixel circuit 31 in the light emission period P6 (hereinafter abbreviated as “period P6” where appropriate).

In the period P6, the positive high potential V _DD is applied to the V _DD line L _vd . Further, a reference potential of 0 V is applied to the V _SS line L _vs. Further, the low potential V _gL is applied to all the scanning signal lines L _ss . Further, the high potential V _{dH is applied} to the image signal line Lis.

At this time, the application of the low potential V _{gL to} the scanning signal line L _ss causes the V _th compensation transistor 13 to become non-conductive. On the other hand, since the high potential V _{dH is applied} to the image signal line Lis, the gate voltage V is equal to the potential corresponding to the amount of charge accumulated in the capacitor 14 (the amount of charge corresponding to the potential V _data ) in the period P4. _g becomes higher than the threshold value V _th , and the driving transistor 12 becomes conductive.

For example, when V _data = 5 V and C _s : C _o = 1: 2, the charge accumulated in the capacitor 14 in the period P4 is 5/3 V lower than the threshold V _th ([V _th -5 / 3] V). Then, in the period P6, V _data (= 5V) content high potential is applied to the image signal line L _IS than the period P4, the control electrodes 12 g, 10 / 3V potential higher than the threshold V _th ([ V _th +10/3] V = [V _th − (5/3) +5] V).

The V _DD line L _vd is higher in potential by the potential V _DD than the V _SS line L _vs , and the drive transistor 12 is in a state in which current flows between the one electrode 12ds and the other electrode 12sd in accordance with the potential V _data. It becomes. For this reason, as shown in FIG. 9, a current corresponding to the potential V _data flows through the organic EL element 11. As a result, a large number of organic EL elements 11 arranged over the entire surface of the organic EL display unit 3 simultaneously emit light at a luminance corresponding to the potential _Vdata . That is, in the period P6, light having a luminance corresponding to the output image signal is emitted from each pixel.

  By repeating such periods P1 to P6, light emission of each organic EL element 11 is repeated, and a moving image corresponding to the output image signal is displayed on the organic EL display unit 3.

<Shift register circuit constituting Y driver>
Hereinafter, the shift register circuit 400 constituting the Y driver circuit 4Y will be described. Here, first, a method of suppressing a current (through current) passing through the circuit in the shift register circuit using a so-called NOT circuit, a problem of the method, and a through current of the shift register circuit 400 according to the present embodiment. The principle of suppressing this will be described sequentially. After that, the configuration of the shift register circuit 400, the configuration of each stage circuit (block circuit) constituting the shift register circuit 400, the transition of the state of each block circuit and the signal flow in the shift register circuit 400, and the shift register circuit 400 The operation will be described sequentially.

<Control of through current using NOT circuit and its problems>
FIG. 10 is a diagram for explaining a technique for suppressing a through current in a shift register circuit. FIG. 10 shows the configuration of each stage circuit (block circuit) BL _X constituting the shift register circuit.

As shown in FIG. 10, the block circuit BL _X includes six n-type transistors Q1 to Q6 and a NOT circuit C _NOT .

The drain of the transistor Q1 is electrically connected to the input side of the NOT circuit _CNOT via a connection portion J1 to which the data signal _SDATA is supplied. Further, the gate of the transistor Q1 is electrically connected to the gate of the transistor Q2 via a connection portion J2 to which a set signal S _SET having a predetermined positive potential is supplied. Further, the source of the transistor Q1 is electrically connected to the gate of the transistor Q5 via the connection portion J5, and sequentially connected to the gate of the transistor Q3 and the drain of the transistor Q4 via the connection portions J5 and J3. Electrically connected.

The drain of the transistor Q2 is electrically connected to the output side of the NOT circuit _CNOT . The source of the transistor Q2 is electrically connected to the gate of the transistor Q6 via the connection portion J6, and is electrically connected to the gate of the transistor Q4 and the drain of the transistor Q3 via the connection portions J6 and J4 in sequence. Connected.

The drain of the transistor Q5 is electrically connected to the connection J7 to which the clock signal _SCLK is supplied. Further, the source of the transistor Q5 is electrically connected to the drain of the transistor Q6 via a connection portion J8 from which an out signal S _OUT as an output signal is output. The sources of the transistors Q3, Q4, and Q6 are grounded.

In such a block circuit BL _X , when a set signal S _SET is applied to the gates of the transistors Q 1 and Q 2, the transistors Q 1 and Q 2 can each flow current between the drain and the source (conductive state), That is, it becomes an ON state.

When the data signal S _DATA having a predetermined positive potential to the input side of the drain and NOT circuit C _NOT transistor Q1 is applied, respectively, a potential corresponding to the data signal S _DATA to the gate of the transistor Q3 is applied The transistor Q3 becomes conductive, and the gate of the transistor Q4 is grounded, and the transistor Q4 is in a state where no current can flow between the drain and the source (non-conductive state), that is, an OFF state. At this time, since the transistor Q1 is conductive and the transistor Q4 is nonconductive, a potential corresponding to the data signal S _DATA is applied to the gate of the transistor Q5, and the transistor Q5 is conductive. Further, since the data signal S _DATA is not applied to the connection portion J6 via the transistor Q2 by the NOT circuit C _NOT , and the transistor Q3 is in a conductive state, the gate of the transistor Q6 is grounded, and the transistor Q6 is not turned on. It becomes a conductive state.

At this time, when the clock signal S _CLK to the drain of the transistor Q5 is applied, out signal S _OUT corresponding from the connection portion J8 to the clock signal S _CLK is output.

On the other hand, a set signal S _SET is applied to the gates of the transistors Q1 and Q2, respectively, and the transistors Q1 and Q2 are applied to the drain of the transistor Q1 and the input side of the NOT circuit _CNOT , respectively. When the potential of the data signal S _DATA becomes a predetermined reference potential (for example, 0 V), the transistors Q3 and Q5 are turned off, and the transistors Q4 and Q6 are turned on. At this time, the connecting portion J8 is grounded, even if the clock signal S _CLK to the drain of the transistor Q5 is applied, out signal S _OUT corresponding to the clock signal S _CLK from the connection J8 is not output.

Thus, in the block circuit BL _X , the potential between the two n-type transistors Q1 and Q4 that are electrically connected in series and the two n-type transistors Q2 that are electrically connected in series. , Q3 are alternately switched so that the out signal S _OUT corresponding to the clock signal S _CLK is output from the connection portion J8 and the out signal S _OUT is not output sequentially. Is done. In the block circuit BL _X , the two transistors Q1 and Q4 that are electrically connected in series are not simultaneously set to the conductive state, and the two transistors Q2 and Q3 that are electrically connected in series are also simultaneously connected. The continuity is not set. For this reason, generation | occurrence | production of the electric current (through-current) which penetrates a circuit via two transistors connected in two electrically in series is suppressed.

However, in the block circuit BL _X , a through current is generated in the NOT circuit C _NOT . This problem will be described below.

FIG. 11 is a diagram showing a general configuration of a NOT circuit C _NOT using n-type transistors.

As shown in FIG. 11, the NOT circuit C _NOT includes two n-type transistors Q11 and Q12. Specifically, the drain and gate of the transistor Q11 are electrically connected to each other via the connection portion J12, and the drain and gate of the transistor Q11 are used to activate the NOT circuit C _NOT . A signal (activation signal) S _ENABLE is input via the connection J11. Further, the source of the transistor Q11 is electrically connected to the drain of the transistor Q12 through the connection portion J13. Furthermore, the gate of the transistor Q12, while being configured so that the data signal S _DATA is input, the source of the transistor Q12 is grounded.

This NOT circuit C _NOT is set to a state in which an activation signal S _ENABLE having a predetermined positive potential is always applied to the drain and gate of the transistor Q11. If the data signal S _DATA having a predetermined positive potential is not applied to the gate of the transistor Q12, the transistor Q11 is set to the conductive state and the transistor Q12 is set to the non-conductive state. The output data signal S _DATAOUT corresponding to S _ENABLE is not output from the connection J13. On the other hand, if the data signal S _DATA is applied to the gate of the transistor Q12, both the transistors Q11 and Q12 are set in a conductive state, so that the output data signal S _DATAOUT corresponding to the activation signal S _ENABLE is connected to the connection portion. Output from J13.

However, when the transistor Q12 is set to the conductive state in order to output the output data signal S _DATAOUT from the connection portion J13, the two transistors Q11 and Q12 electrically connected in series are simultaneously set to the conductive state. Is done. For this reason, in the NOT circuit C _NOT , a through current through the two transistors Q11 and Q12 is generated from the activation signal line L _ENABLE to which the activation signal S _ENABLE is input.

Therefore, the inventors of the present application suppress the generation of through current in two transistors electrically connected in series by creating an electric circuit employing a special configuration instead of the NOT circuit C _NOT. Made it possible to do.

<Principle to suppress through current>
FIG. 12 is a diagram for explaining the principle of suppressing the through current. In Figure 12, configuration for the circuit of each stage constituting the shift register circuit (block circuit) BL _Y is shown.

As shown in FIG. 12, the block circuit BL _Y is configured to include eight first to eighth transistors Tr1 to Tr8 each formed by an n-type TFT.

The drain of the first transistor Tr1 is electrically connected to a first signal line L _DP that supplies a first data signal S _DP as a first signal having a positive high potential at the connection portion C1. Further, the gate of the first transistor Tr1 is electrically connected to the gate of the second transistor Tr2 via the connection portion C2. A set signal S _SET having a predetermined positive potential is supplied to the gates of the first and second transistors Tr1 and Tr2. Further, the source of the first transistor Tr1 is electrically connected to the source of the seventh transistor Tr7 via the connection portion C3, and is sequentially connected to the gate of the fifth transistor Tr5 via the connection portions C3 and C4. They are electrically connected to each other and sequentially connected to the gate of the third transistor Tr3 and the drain of the fourth transistor Tr4 through the connection parts C3 to C5.

The drain of the second transistor Tr2 is electrically connected to a second signal line L _DN that supplies a second data signal S _DN as a second signal having a positive high potential at the connection C6. The source of the second transistor Tr2 is electrically connected to the source of the eighth transistor Tr8 via the connection C7, and is sequentially connected to the gate of the sixth transistor Tr6 via the connections C7 and C8. They are electrically connected to each other and sequentially connected to the drain of the third transistor Tr3 and the gate of the fourth transistor Tr4 through the connection portions C7 to C9.

  Further, the sources of the third and fourth transistors Tr3 and Tr4 are grounded through the connection portions C10 and C11 in sequence.

The drain of the fifth transistor Tr5 is electrically connected to the clock signal line L _CLK that supplies the clock signal S _CLK at the connection portion C12. Further, the source of the fifth transistor Tr5 is electrically connected to the drain of the sixth transistor Tr6 via the connection C13 from which the out signal S _OUT is output. The source of the sixth transistor Tr6 is grounded through the connection portion C11.

The drain of the seventh transistor Tr7 is electrically connected to the second signal line L _{DN at} the connection C14. Further, the gate of the seventh transistor Tr7 is electrically connected to the gate of the eighth transistor Tr8 via the connection portion C15. A reset signal S _RESET having a predetermined positive potential is supplied to the gates of the seventh and eighth transistors Tr7 and Tr8. The drain of the eighth transistor Tr8 is connected first signal line L _DP electrically at a connection C16.

Then, the input of the first data signal S _DP for the block circuit BL _Y from the first signal line L _DP, inputs and the second data signal S _DN to the block circuit BL _Y is not carried out at the same time from the second signal line L _DN To be controlled. That is, the first data signal S _DP and the second data signal S _DN is input to the block circuit BL _Y at different timings.

In such a block circuit BL _Y , when the set signal S _SET is applied from the connection portion C2 to the gates of the first and second transistors Tr1 and Tr2, the first and second transistors Tr1 and Tr2 are turned on, respectively. Set to the state (ON state).

First and when the second transistors Tr1, Tr2 are respectively set to the conductive state, the first data signal S _DP is applied to the block circuit BL _Y, and the second data signal to the block circuit BL _Y if S _DN is applied, a potential corresponding to the first data signal S _DP is applied to the gate of the third transistor Tr3, together with the third transistor Tr3 is set in a conducting state, the gate of the fourth transistor Tr4 is The fourth transistor Tr4 is set to a non-conductive state by being grounded. At this time, the first transistor Tr1 is set to the conductive state, and since the fourth transistor Tr4 is set to a non-conducting state, the potential corresponding to the first data signal S _DP to the gate of the fifth transistor Tr5 is granted As a result, the fifth transistor Tr5 becomes conductive. Further, since the second data signal _SDN is not applied to the second transistor Tr2 and the third transistor Tr3 is in a conducting state, the gate of the sixth transistor Tr6 is grounded and the sixth transistor Tr6 is not conducting. It becomes a state. In this state, when the clock signal S _CLK is applied to the drain of the fifth transistor Tr5, out signal S _OUT corresponding to the clock signal S _CLK from the connection portion C13 is output. In the state where the set signal S _SET is applied, the state in which the first data signal _SDP flows and the out signal S _OUT is output is defined as the first signal state.

Then, after the application of the set signal S _{SET to} the gates of the first and second transistors Tr1, Tr2 is completed, the reset signal S _RESET is applied to the gates of the seventh and eighth transistors Tr7, Tr8. The seventh and eighth transistors Tr7 and Tr8 are each in a conductive state (ON state).

Seventh and when the eighth transistor Tr7, Tr8 are set to the respective conductive state, the first data signal S _DP is applied to the block circuit BL _Y, and the second data signal to the block circuit BL _Y If _SDN is not applied, the third and fifth transistors Tr3 and Tr5 are set in a non-conductive state, and the fourth and sixth transistors Tr4 and Tr6 are in a conductive state. At this time, since the connecting portions C13 are grounded, even if the clock signal S _CLK is applied to the drain of the fifth transistor Tr5, out signal S _OUT corresponding to the clock signal S _CLK is not output from the connecting portion C13. In the state where the set signal S _SET is applied, the state where the second data signal S _DN does not flow and the out signal S _OUT is not output is defined as the second signal state.

Thus, in the block circuit BL _Y, for example, an input of the set signal S _SET, that is the input of the reset signal S _RESET are alternately performed at an appropriate time interval, it is electrically connected in series The second transistor Tr2 (or the eighth transistor Tr8) electrically connected in series with the potential between the first transistor Tr1 (or the seventh transistor Tr7) and the fourth transistor Tr4 (for example, the connection portion C4). ) And the third transistor Tr3 (for example, the connection portion C8) are alternately switched. That is, an electric circuit corresponding to a so-called latch circuit is formed.

Further, a state that the input and the input and the reset signal S _RESET of the set signal S _SET for the block circuit BL _Y is sequentially performed, the out signal S _OUT corresponding from the connecting portion C13 to the clock signal S _CLK is output Sequentially set to a state where no data is output.

In this block circuit BL _Y , all combinations of two transistors electrically connected in series, for example, a combination of the first transistor Tr1 and the fourth transistor Tr4, or a second transistor Tr2 and a third transistor are provided. In combination with Tr3, etc., the two transistors are not set to the conductive state at the same time. For this reason, generation | occurrence | production of the electric current (through-current) which penetrates the circuit via the two transistors electrically connected in series is suppressed.

Here, the first data signal S _DP is applied to the block circuit BL _Y, and in a state where the second data signal S _DN to the block circuit BL _Y is not applied, the set signal S to the block circuit BL _{Y Although} the description has been given of the operation in which the input of the _{SET and} the input of the reset signal S _RESET are alternately performed so that the potential of the connection portion C4 and the potential of the connection portion C8 are alternately switched, the present invention is not limited thereto.

For example, as shown in FIG. 13, a block circuit BL _Z obtained by removing the seventh and eighth transistors Tr7 and Tr8 from the block circuit BL _Y is employed, and the first data signal _SDP input to the block circuit BL _Z and the first The two data signals _SDN may be alternately input. That is, in the state where the set signal S _SET is applied from the connection C2 to the gates of the first and second transistors Tr1 and Tr2, the connection C1 is connected to the gate of the third transistor Tr3 via the first transistor Tr1. first that the data signal S _DP is applied against the fourth transistor via a state of the third transistor Tr3 is set in a conducting state (first setting state), the second transistor Tr2 from the connection C6 by the second data signal S _DN to the gate of Tr4 is applied, there in such a manner are sequentially set in a state where the fourth transistor Tr4 is set to the conductive state (second setting state) May be.

Incidentally, the description of the block circuit BL _Y shown in FIG. 12 described above, has been described first to eighth transistors Tr1~Tr8 as n-type transistor, the first to eighth transistors Tr1~Tr8 is a p-type transistor May be. Even if it is a p-type transistor, generation | occurrence | production of the electric current (through-current) which penetrates the circuit through two transistors electrically connected in series is suppressed. Similarly, the first to sixth transistors Tr1~Tr6 block circuit BL _Z shown in FIG. 13, it may be a p-type transistor.

<Configuration of shift register circuit>
<Outline configuration>
FIG. 14 is a diagram schematically showing a schematic configuration of a shift register circuit 400 applied to the Y driver circuit 4Y of the image display device 1 according to an embodiment of the present invention.

As shown in FIG. 14, the shift register circuit 400 includes _{0th to n-th} block circuits BL _{0 to} BL _n , a first clock signal line L _CLKE , a second clock signal line L _CLKO , a first signal line L _DP , This is an electric circuit including a two-signal line L _DN , a first mode signal line L _SL , a second mode signal line L _PL , and a low potential line L _VL .

The 0th to _n-th block circuits BL _{0 to} BL _n are electrical circuits corresponding to the _{0th to nth} block circuits of the shift register circuit 400, and are arranged in sequence. Each of the block circuits BL _{0 to} BL _n includes _{first to twelfth} terminal portions T _{1 to} T ₁₂ , a clock signal input terminal portion T _IN , an out signal output terminal portion T _OUT , a set signal applying terminal portion T _SET , and a reset signal applying terminal. Part T _RESET , and first to third low potential connection terminal parts T _{L1 to} T _L3 .

The _{0th to n-th} block circuits BL _{0 to} BL _n receive the _0th to n-th out signals S _{OUT0 to} S _OUTn corresponding to the scanning signals for n + 1 horizontal lines arranged in the organic EL display unit 3. Output from each out signal output terminal T _OUT . In other words, the out signal output terminal portions T _{OUT of the} block circuits BL _{0 to} BL _n are connected to the plurality of pixel circuits 31 included in the corresponding horizontal lines, respectively, to the 0th to n-th out signals S _{OUT0 to} S OUT. _OUTn is output.

For example, the out signal output terminal T _{OUT of} the 0th block circuit BL ₀ outputs an out signal (0th out signal) S _OUT0 to the plurality of pixel circuits 31 included in the first horizontal line. The out signal output terminal T _{OUT of} the first block circuit BL ₁ outputs an out signal (first out signal) S _OUT1 to the plurality of pixel circuits 31 included in the second horizontal line. Further, the out signal output terminal T _{OUT of} the second block circuit BL ₂ outputs an out signal (second out signal) S _OUT2 to the plurality of pixel circuits 31 included in the third horizontal line. Further, the out signal output terminal T _OUT of the n-th block circuit BL _n outputs an out signal (n-th out signal) S _OUTn to the plurality of pixel circuits 31 included in the (n + 1) th horizontal line. In the present embodiment, the out signal output terminal portion T _OUT corresponds to the “signal output portion” of the present invention.

The first clock signal line L _CLKE is connected to the odd-numbered block circuits BL ₀ , BL ₂ , BL ₄ ,..., BL _{n− of the 0th to nth} block circuits BL _{0 to} BL _{n. 1} is electrically connected to the clock signal input terminal portion T _IN . The first clock signal line L _CLKE is connected to the odd-numbered block circuits BL ₀ , BL ₂ , BL ₄ ,..., BL _n−1 with respect to the clock signal input terminal portion T _IN . _{Give CLKE} . In the present embodiment, the first clock signal line L _CLKE corresponds to the “first input signal line” of the present invention.

The second clock signal line L _CLKO is connected to the block circuits BL ₁ , BL ₃ , BL ₅ ,..., BL _n arranged in even-numbered ones among the _{0th to n-th} block circuits BL _{0 to} BL _n . It is electrically connected to the clock signal input terminal _TIN . The second clock signal line L _CLKO, each block circuit of the even-numbered _{BL 1, BL 3, BL 5} , ···, a second clock signal S _CLKO to the clock signal input terminal unit T _IN of the BL _n Give. In the present embodiment, the second clock signal line L _CLKO corresponds to the “second input signal line” of the present invention. Furthermore, in this embodiment, the clock signal input terminal portion T _IN corresponds to the “input signal applying portion” of the present invention, and the first and twenty-second clock signals S _CLKE and S _CLKO are the “input signal” of the present invention. It corresponds to.

The first signal line L _DP is electrically connected to the _first , _fourth , and _fifth terminal portions T ₁ , T ₄ , and T ₅ of the _{0th to n-th} block circuits BL _{0 to} BL _n , respectively. The first signal line L _DP applies the first data signal S _DP to the _first , _fourth , and _fifth terminal portions T ₁ , T ₄ , and T ₅ . In the present embodiment, the first terminal portion T ₁ corresponds to the “first signal applying portion” of the present invention, and the fourth terminal portion T ₄ corresponds to the “fourth signal applying portion” of the present invention. The first data signal S _DP corresponds to the “first signal” of the present invention.

The second signal line L _DN is electrically connected to the _second , _third , and _sixth terminal portions T ₂ , T ₃ , and T ₆ of each of the _{0th to n-th} block circuits BL _{0 to} BL _n . The second signal line L _DN applies the second data signal S _DN to the _second , _third , and _sixth terminal portions T ₂ , T ₃ , and T ₆ . In the present embodiment, the second terminal portion T ₂ corresponds to the “second signal applying portion” of the present invention, and the third terminal portion T ₃ corresponds to the “third signal applying portion” of the present invention. The second data signal S _DN corresponds to the “second signal” of the present invention.

The first mode signal line L _SL, is electrically connected respectively 7-10 terminal unit T ₇ through T ₁₀ of each of the 0~n block circuit BL ₀ to BL _n. The first mode signal line L _SL has a first mode signal S _SL given to each 7-10 terminal unit T ₇ through T _10.

The second mode signal line L _PL, are electrically connected respectively first 11, 12 terminal section T _11, T ₁₂ of each of the 0~n block circuit BL ₀ to BL _n. Then, the second mode signal line L _PL, imparts second mode signal S _PL for each eleventh and twelfth terminal portions T _11, T _12.

The low potential line L _VL is electrically connected to the first to third low potential connection terminal portions T _{L1 to} T _L3 of the respective _{0th to nth} block circuits BL _{0 to} BLn. Then, the low potential line L _VL imparts a predetermined low potential (e.g., 0V or slightly negative potential) for each first to third low-potential connection terminal portions T _L1 through T _L3.

Further, the 0~n block circuit BL ₀ to BL reset signal applying terminal unit T _RESET of the 0th block circuit BL ₀ which are arranged at one end of the _n is, are arranged next to the 0th block circuit BL _{0 Is} electrically connected to the out signal output terminal portion T _{OUT of} the first block circuit BL ₁ . In the present embodiment, the reset signal application terminal unit T _RESET corresponds to the “reset signal application unit” of the present invention.

Further, the 0~n block circuit BL ₀ to BL set signal applying terminal unit T _SET of the n block circuit BL _n which are arranged at the other end of the _n is, are arranged in front of the n block circuit BL _n It is electrically connected to the out signal output terminal T _{OUT of} the (n−1) th block circuit BL _n−1 . In the present embodiment, the set signal application terminal unit T _SET corresponds to the “set signal application unit” of the present invention.

Further, in the block circuit BL ₁ ~BL _n-1 except the 0, n block circuit BL _0, BL _n which are arranged in one and the other ends of the first 0~n block circuit BL ₀ to BL _n, Each of the set signal giving terminal portions T _SET is electrically connected to the out signal output terminal portions T _{OUT of the} block circuits BL _{0 to} BL _n-2 arranged in advance. For example, as shown in FIG. 14, the set signal giving terminal portion T _{SET of} the first block circuit BL ₁ is connected to the out signal output terminal portion T _{OUT of} the zeroth block circuit BL ₀ arranged before that. Electrically connected. Further, the set signal giving terminal portion T _{SET of} the second block circuit BL ₂ is electrically connected to the out signal output terminal portion T _{OUT of} the first block circuit BL ₁ arranged in front thereof.

In each of the block circuits BL _{1 to} BL _n−1 , the reset signal giving terminal portion T _RESET is electrically connected to the out signal output terminal portion T _{OUT of} each of the block circuits BL _{2 to} BL _n arranged next. It is connected to the. For example, as shown in FIG. 14, in the first block circuit BL ₁ , the reset signal application terminal unit T _RESET is connected to the out signal output terminal unit T _{OUT of} the second block circuit BL ₂ arranged next. Electrically connected.

Further, a set signal S _SET is externally applied to the set signal application terminal portion T _SET of the 0th block circuit BL _{0 at} a predetermined timing. A reset signal S _RESET is applied from the outside to the reset signal _application terminal unit T _RESET of the nth block circuit BL _{n at} a predetermined timing.

Next, odd-numbered block circuits BL ₀ , BL ₂ , BL ₄ ,..., BL _n−1 among the _{0- th to n-} th block circuits BL _{0 to} BL _n , and even-numbered block circuits The configurations of BL ₁ , BL ₃ , BL ₅ ,..., BL _n will be described sequentially.

<Odd block circuit>
FIG. 15 is a circuit diagram of odd-numbered block circuits BL ₀ , BL ₂ , BL ₄ ,..., BL _n−1 that constitute the shift register circuit 400. Incidentally, the odd-numbered block circuit _{BL 0, BL 2, BL 4} , ···, BL n-1 , since those mutually similar, in Figure 15, as a typical example of the second block circuit BL ₂ A circuit diagram is shown.

As shown in Figure 15, the second block circuit BL ₂ is a 1-14 transistor Tr1～Tr14, the 12 terminal portions T ₁ through T _12, a clock signal input terminal unit T _IN, out signal output terminal portion T _OUT , a set signal giving terminal portion T _SET , a reset signal giving terminal portion T _RESET , and first to third low potential connection terminal portions T _{L1 to} T _L3 are configured.

The first transistor Tr1 includes first, second, and third electrodes E1 to E3, and is provided between the first electrode E1 and the second electrode E2 in response to application of a potential to the third electrode E3 that functions as a gate. This is an n-type TFT whose current is adjusted. The first electrode E1 is electrically connected to the first signal line L _DP via the first terminal portion T _1. The second electrode E2 is electrically connected to the 25th electrode E25 of the ninth transistor Tr9. The third electrode E3 is electrically connected to the set signal application terminal portion _TSET and the sixth electrode E6 of the second transistor Tr2. That is, the set signal S _SET is applied to the third and sixth electrodes E3 and E6 by the set signal applying terminal portion T _SET . In the present embodiment, the first electrode E1 functions as a drain, and the second electrode E2 functions as a source.

The second transistor Tr2 includes fourth, fifth, and sixth electrodes E4 to E6, and is provided between the fourth electrode E4 and the fifth electrode E5 in response to application of a potential to the sixth electrode E6 that functions as a gate. This is an n-type TFT whose current is adjusted. The fourth electrode E4 is electrically connected to the second signal line L _DN via the second terminal portion T _2. The fifth electrode E5 is electrically connected to the 31st electrode E31 of the 11th transistor Tr11. The sixth electrode E6 is electrically connected to the set signal applying terminal portion _TSET and the third electrode E3 of the first transistor Tr1. In the present embodiment, the fourth electrode E4 functions as a drain, and the fifth electrode E5 functions as a source.

The third transistor Tr3 includes seventh, eighth, and ninth electrodes E7 to E9. The third transistor Tr3 is provided between the seventh electrode E7 and the eighth electrode E8 according to application of a potential to the ninth electrode E9 that functions as a gate. This is an n-type TFT whose current is adjusted. The seventh electrode E7 includes a twelfth electrode E12 of the fourth transistor Tr4, an eighteenth electrode E18 of the sixth transistor Tr16, a thirty-second electrode E32 of the eleventh transistor Tr11, a thirty-fifth electrode E35 of the twelfth transistor Tr12, and a fourteenth transistor. Each is electrically connected to the 41st electrode E41 of Tr14. The eighth electrode E8 is electrically connected to the low potential line _LVL via the second low potential connection terminal portion T _L2 . The ninth electrode E9 includes the tenth electrode E10 of the fourth transistor Tr4, the fifteenth electrode E15 of the fifth transistor Tr5, the twenty-sixth electrode E26 of the ninth transistor Tr9, the twenty-ninth electrode E29 of the tenth transistor Tr10, and the thirteenth transistor. Each is electrically connected to the 38th electrode E38 of Tr13. In the present embodiment, the seventh electrode E7 functions as a drain, and the eighth electrode E8 functions as a source.

The fourth transistor Tr4 has tenth, eleventh, and twelfth electrodes E10 to E12, and is provided between the tenth electrode E10 and the eleventh electrode E11 in response to application of a potential to the twelfth electrode E12 that functions as a gate. This is an n-type TFT whose current is adjusted. The tenth electrode E10 includes the ninth electrode E9 of the third transistor Tr3, the fifteenth electrode E15 of the fifth transistor Tr5, the twenty-sixth electrode E26 of the ninth transistor Tr9, the twenty-ninth electrode E29 of the tenth transistor Tr10, and the thirteenth transistor. Each is electrically connected to the 38th electrode E38 of Tr13. The eleventh electrode E11 is electrically connected to the low potential line _LVL via the first low potential connection terminal portion T _L1 . The twelfth electrode E12 includes the seventh electrode E7 of the third transistor Tr3, the eighteenth electrode E18 of the sixth transistor Tr6, the thirty-second electrode E32 of the eleventh transistor Tr11, the thirty-fifth electrode E35 of the twelfth transistor Tr12, and the fourteenth transistor. Each is electrically connected to the 41st electrode E41 of Tr14. In the present embodiment, the tenth electrode E10 functions as a drain, and the eleventh electrode E11 functions as a source.

The fifth transistor Tr5 has thirteenth, fourteenth, and fifteenth electrodes E13 to E15, and is provided between the thirteenth electrode E13 and the fourteenth electrode E14 in response to application of a potential to the fifteenth electrode E15 that functions as a gate. This is an n-type TFT whose current is adjusted. 13 electrode E13 is electrically connected to the first clock signal line L _CLKE via a clock signal input terminal unit T _IN. That is, the first clock signal is applied from the clock signal input terminal portion T _IN to the thirteenth electrode E13. The fourteenth electrode E14 is electrically connected to the sixteenth electrode E16 of the sixth transistor Tr6 and the out signal output terminal T _OUT . That is, the out signal output terminal portion T _OUT that outputs the out signal S _OUT (here, the second out signal S _OUT2 ) to the wiring that electrically connects the fourteenth electrode E14 and the sixteenth electrode E16 is electrically connected. It is connected to the. The fifteenth electrode E15 includes the ninth electrode E9 of the third transistor Tr3, the tenth electrode E10 of the fourth transistor Tr4, the twenty-sixth electrode E26 of the ninth transistor Tr9, the twenty-ninth electrode E29 of the tenth transistor Tr10, and the thirteenth transistor. Each is electrically connected to the 38th electrode E38 of Tr13. In the present embodiment, the thirteenth electrode E13 functions as a drain, and the fourteenth electrode E14 functions as a source.

The sixth transistor Tr6 has sixteenth, seventeenth, and eighteenth electrodes E16 to E18, and is provided between the sixteenth electrode E16 and the seventeenth electrode E17 in response to application of a potential to the eighteenth electrode E18 functioning as a gate. This is an n-type TFT whose current is adjusted. 16 electrode E16 are respectively electrically connected to the fifth transistor Tr5 14th electrode E14 and the out signal output terminal portion T _OUT. The seventeenth electrode E17 is electrically connected to the low potential line _LVL via the third low potential connection terminal portion T _L3 . The eighteenth electrode E18 includes a seventh electrode E7 of the third transistor Tr3, a twelfth electrode E12 of the fourth transistor Tr4, a thirty-second electrode E32 of the eleventh transistor Tr11, a thirty-fifth electrode E35 of the twelfth transistor Tr12, and a fourteenth transistor. Each is electrically connected to the 41st electrode E41 of Tr14. In the present embodiment, the sixteenth electrode E16 functions as a drain, and the seventeenth electrode E17 functions as a source.

The seventh transistor Tr7 has nineteenth, twentieth, and twenty-first electrodes E19 to E21, and is provided between the nineteenth electrode E19 and the twentieth electrode E20 in response to application of a potential to the twenty-first electrode E21 that functions as a gate. This is an n-type TFT whose current is adjusted. 19 electrode E19 is electrically connected to the second signal line L _DN via the third terminal portion T _3. The third terminal portion T ₃ is, is set to the second terminal portion T ₂ the same potential since they are electrically connected to the same manner as the second terminal portion T ₂ second signal line L _DN . The twentieth electrode E20 is electrically connected to the twenty-eighth electrode E28 of the tenth transistor Tr10. 21 electrode E21 is electrically connected to the first 24 electrode E24 of the reset signal applying terminal unit T _RESET and eighth transistor Tr8. That is, the reset signal S _RESET is applied to the 21st and 24th electrodes E21, E24 by the reset signal applying terminal portion T _RESET . In the present embodiment, the nineteenth electrode E19 functions as a drain, and the twentieth electrode E20 functions as a source.

The eighth transistor Tr8 includes the twenty-second, twenty-third, and twenty-fourth electrodes E22 to E24, and is provided between the twenty-second electrode E22 and the twenty-third electrode E23 according to the application of a potential to the twenty-fourth electrode E24 that functions as a gate. This is an n-type TFT whose current is adjusted. 22 electrode E22 is electrically connected to the first signal line L _DP via the fourth terminal portion T _4. Since the fourth terminal portion T ₄ is electrically connected to the first signal line L _DP like the first terminal portion T ₁ , the fourth terminal portion T ₄ is set to the same potential as the first terminal portion T _1. . The 23rd electrode E23 is electrically connected to the 34th electrode E34 of the 12th transistor Tr12. 24 electrode E24 is electrically connected to the first 21 electrode E21 of the reset signal applying terminal unit T _RESET and the seventh transistor Tr7. In the present embodiment, the twenty-second electrode E22 functions as a drain and the twenty-third electrode E23 functions as a source.

The ninth transistor Tr9 includes twenty-fifth, twenty-sixth and twenty-seventh electrodes E25 to E27, and is connected between the twenty-fifth electrode E25 and the twenty-sixth electrode E26 in response to application of a potential to the twenty-seventh electrode E27 functioning as a gate. This is an n-type TFT whose current is adjusted. The 25th electrode E25 is electrically connected to the second electrode E2 of the first transistor Tr1. The twenty-sixth electrode E26 includes a ninth electrode E9 of the third transistor Tr3, a tenth electrode E10 of the fourth transistor Tr4, a fifteenth electrode E15 of the fifth transistor Tr5, a 29th electrode E29 of the tenth transistor Tr10, and a thirteenth transistor. Each is electrically connected to the 38th electrode E38 of Tr13. That is, the second electrode E2 and the ninth, tenth, and fifteenth electrodes E9, E10, and E15 are electrically connected via the twenty-fifth and twenty-sixth electrodes E25 and E26. 27 electrode E27 is electrically connected to the first mode signal line L _SL via the seventh terminal unit T _7. In the present embodiment, the 25th electrode E25 functions as a drain, and the 26th electrode E26 functions as a source.

The tenth transistor Tr10 has 28th, 29th, and 30th electrodes E28 to E30, and is provided between the 28th electrode E28 and the 29th electrode E29 in response to application of a potential to the 30th electrode E30 functioning as a gate. This is an n-type TFT whose current is adjusted. The twenty-eighth electrode E28 is electrically connected to the twentieth electrode E20 of the seventh transistor Tr7. The 29th electrode E29 includes a ninth electrode E9 of the third transistor Tr3, a tenth electrode E10 of the fourth transistor Tr4, a fifteenth electrode E15 of the fifth transistor Tr5, a twenty-sixth electrode E26 of the ninth transistor Tr9, and a thirteenth transistor. Each is electrically connected to the 38th electrode E38 of Tr13. That is, the twentieth electrode E20 and the ninth, tenth, and fifteenth electrodes E9, E10, and E15 are electrically connected through the twenty-eighth and twenty-ninth electrodes E28 and E29. The 30 electrode E30 is electrically connected to the first mode signal line L _SL through the ninth terminal unit T _9. In the present embodiment, the 28th electrode E28 functions as a drain, and the 29th electrode E29 functions as a source.

The eleventh transistor Tr11 includes thirty-first, thirty-second, and thirty-third electrodes E31 to E33, and is provided between the thirty-first electrode E31 and the thirty-second electrode E32 in response to application of a potential to the thirty-third electrode E33 that functions as a gate. This is an n-type TFT whose current is adjusted. The thirty-first electrode E31 is electrically connected to the fifth electrode E5 of the second transistor Tr2. The thirty-second electrode E32 includes a seventh electrode E7 of the third transistor Tr3, a twelfth electrode E12 of the fourth transistor Tr4, an eighteenth electrode E18 of the sixth transistor Tr6, a thirty-fifth electrode E35 of the twelfth transistor Tr12, and a fourteenth transistor. Each is electrically connected to the 41st electrode E41 of Tr14. That is, the fifth electrode E5 and the seventh, twelfth, and eighteenth electrodes E7, E12, and E18 are electrically connected via the thirty-first and thirty-second electrodes E31 and E32. 33 electrode E33 is electrically connected to the first mode signal line L _SL through the eighth terminal portion T _8. In the present embodiment, the 31st electrode E31 functions as a drain, and the 32nd electrode E32 functions as a source.

The twelfth transistor Tr12 includes thirty-fourth, thirty-fifth, and thirty-sixth electrodes E34 to E36, and is provided between the thirty-fourth electrode E34 and the thirty-fifth electrode E35 in response to application of a potential to the thirty-sixth electrode E36 functioning as a gate. This is an n-type TFT whose current is adjusted. The thirty-fourth electrode E34 is electrically connected to the twenty-third electrode E23 of the eighth transistor Tr8. The 35th electrode E35 includes a seventh electrode E7 of the third transistor Tr3, a twelfth electrode E12 of the fourth transistor Tr4, an eighteenth electrode E18 of the sixth transistor Tr6, a thirty-second electrode E32 of the eleventh transistor Tr11, and a fourteenth transistor. Each is electrically connected to the 41st electrode E41 of Tr14. That is, the 23rd electrode E23 and the 7th, 12th, and 18th electrodes E7, E12, E18 are electrically connected via the 34th and 35th electrodes E34, E35. 36 electrode E36 is electrically connected to the first mode signal line L _SL through the tenth terminal unit T _10. In the present embodiment, the 34th electrode E34 functions as a drain, and the 35th electrode E35 functions as a source.

The thirteenth transistor Tr13 includes 37th, 38th, and 39th electrodes E37 to E39, and is provided between the 37th electrode E37 and the 38th electrode E38 in response to application of a potential to the 39th electrode E39 functioning as a gate. This is an n-type TFT whose current is adjusted. 37 electrode E37 is electrically connected to the first signal line L _DP via a fifth terminal unit T _5. The thirty-eighth electrode E38 includes the ninth electrode E9 of the third transistor Tr3, the tenth electrode E10 of the fourth transistor Tr4, the fifteenth electrode E15 of the fifth transistor Tr5, the twenty-sixth electrode E26 of the ninth transistor Tr9, and the tenth transistor. Each is electrically connected to the 29th electrode E29 of Tr10. 39 electrode E39 is electrically connected to the second mode signal line L _PL via an eleventh terminal unit T _11. In the present embodiment, the 37th electrode E37 functions as a drain, and the 38th electrode E38 functions as a source.

The fourteenth transistor Tr14 has forty, forty and forty-second electrodes E40 to E42, and is provided between the forty-eighth electrode E40 and the forty-first electrode E41 according to the application of a potential to the forty-second electrode E42 functioning as a gate. This is an n-type TFT whose current is adjusted. The 40 electrode E40 is electrically connected to the second signal line L _DN via the sixth terminal unit T _6. The forty-first electrode E41 includes the seventh electrode E7 of the third transistor Tr3, the twelfth electrode E12 of the fourth transistor Tr4, the eighteenth electrode E18 of the sixth transistor Tr6, the thirty-second electrode E32 of the eleventh transistor Tr11, and the twelfth transistor. Each is electrically connected to the 35th electrode E35 of Tr12. 42 electrode E42 is electrically connected to the second mode signal line L _PL via the twelfth terminal portions T _12. In the present embodiment, the 40th electrode E40 functions as a drain, and the 41st electrode E41 functions as a source.

<Even-numbered block circuit>
FIG. 16 is a circuit diagram of even-numbered block circuits BL ₁ , BL ₃ , BL ₅ ,..., BL _n constituting the shift register circuit 400. Since the even-numbered block circuits BL ₁ , BL ₃ , BL ₅ ,..., BL _n are similar to each other, FIG. 16 is a circuit diagram of the third block circuit BL ₃ as a representative example. It is shown.

The configuration of the third block circuit BL _{3 is different from} the configuration of the second block circuit BL ₂ (FIG. 15) in the connection destination of the 13th electrode E13 of the fifth transistor Tr5. Specifically, in the second block circuit BL _2, whereas it is electrically connected to the thirteenth electrode E13 via the clock signal input terminal unit T _IN first clock signal line L _CLKE, in the third block circuit BL _3, 13 electrode E13 is electrically connected to the second clock signal line L _CLKO via a clock signal input terminal unit T _iN. The other configuration of the third block circuit BL ₃ is the same as that of the second block circuit BL ₂ . For this reason, in FIG. 16, the same reference numerals are given to the same configuration as the second block circuit BL _{2 in} the configuration of the third block circuit BL ₃ , and here, the description of the similar configuration will be given. Omitted.

<State transition of each block and signal flow in shift register circuit>
FIGS. 17 to 19 are diagrams for explaining the state transition of the block circuits BL _{0 to} BL _n of the shift register circuit 400 and the signal flow in the shift register circuit 400. FIG.

In FIG. 17, the first mode signal S _SL is input to the _{seventh to tenth} terminal portions T _{7 to} T ₁₀ , and the second mode signal S _PL is input to the eleventh and twelfth terminal portions T ₁₁ and T ₁₂ . The first data signal _SDP is input to the first, fourth, and fifth terminal portions T ₁ , T ₄ , T ₅ without being input, and the second, third, and sixth terminal portions T ₂ , T ₂ , Transition of the states of the block circuits BL _{0 to} BL _{n in} the state where the second data signal S _DN is not input to T ₃ and T ₆ (first shift mode), and the signal in the shift register circuit 400 The flow is shown.

In the first shift mode, each block circuit BL ₀ to BL _n, 27, No. 30, with respect to 33, and 36 electrodes E27, E30, E33, E36, the first mode signal S _SL respectively granted Thus, the ninth to twelfth transistors Tr9 to Tr12 are set to the conductive state, and the thirteenth and fourteenth transistors Tr13 and Tr14 are set to the non-conductive state. That is, each of the block circuits BL _{0 to} BL _n is an electric circuit similar to the block circuit BL _Y shown in FIG. More specifically, the second and twentieth electrodes E2, E20 are electrically connected to the ninth, tenth, fifteenth electrodes E9, E10, E15, respectively, and the fifth and twenty-third electrodes E5, E23 are connected. Are electrically connected to the seventh, twelfth, and eighteenth electrodes E7, E12, and E18.

In FIG. 18, the first mode signal S _SL is inputted to the _{seventh to tenth} terminal portions T _{7 to} T ₁₀ , and the second mode signal S _PL is inputted to the eleventh and twelfth terminal portions T ₁₁ and T ₁₂ . The first data signal _SDP is not input to the first, fourth, and fifth terminal portions T ₁ , T ₄ , T ₅ without being input, and the second, third, and sixth terminal portions T ₂ are not input. , T ₃ , T ₆ in the state in which the second data signal S _DN is input (second shift mode), the state transition of each of the block circuits BL _{0 to} BL _n and the signal in the shift register circuit 400 The flow of is shown.

In the second shift mode, as in the first shift mode, the ninth to twelfth transistors Tr9 to Tr12 are set in the conductive state in each of the block circuits BL _{0 to} BL _n , and the thirteenth and fourteenth transistors Tr13, Tr14 is set to a non-conductive state. That is, each of the block circuits BL _{0 to} BL _n is an electric circuit similar to the block circuit BL _Y shown in FIG.

In FIG. 19, the state transition of each of the block circuits BL _{0 to} BL _{n in} a state where the first mode signal S _SL is not input to the _{seventh to tenth} terminal portions T _{7 to} T ₁₀ (simultaneous output mode) The signal flow in the shift register circuit 400 is also shown. In this simultaneous output mode, the ninth to twelfth transistors Tr9 to Tr12 are set in a non-conducting state in each of the block circuits BL _{0 to} BL _n and at a predetermined timing with respect to the thirty-ninth and forty-second electrodes E39 and E42. in by the second mode signal S _PL is applied, thirteenth and fourteenth transistors Tr 13, Tr14 is set in a conducting state.

Hereinafter, referring to FIGS. 17 to 19 as appropriate, the state transition of each of the block circuits BL _{0 to} BL _n in the first shift mode, the second shift mode, and the simultaneous output mode, and the signal flow in the shift register circuit 400, Will be described sequentially.

<First shift mode>
In the first shift mode, the set signal S _SET is applied from the outside to the zeroth block circuit BL ₀ on one end side at a predetermined timing. Then, the odd-numbered blocks circuits _{BL 0, BL 2, BL 4} , ···, while the first clock signal S _CLKE is input from the first clock signal line L _CLKE against BL _n-1 (first a clock signal input state), a state in which the even-numbered blocks circuits _{BL 1, BL 3, BL 5} , ···, the second clock signal S _CLKO from the second clock signal line L _CLKO against BL _n are input And (second clock signal input state) are alternately set.

  Here, a specific operation of the shift register circuit 400 in the first shift mode will be described with reference to FIG.

As shown in FIG. 17, in the first shift mode, the set signal S _SET corresponding to the signal from the TG 202 is applied from the outside to the set signal application terminal portion T _SET of the 0th block circuit BL ₀ on one end side. Then, the set signal S _SET is applied from the set signal applying terminal portion T _SET to the third and sixth electrodes E3 and E6. At this time, the first and second transistors Tr1 and Tr2 are set to a conductive state, respectively. Further, the first signal line L _DP first data signal S _DP respect ninth electrode E9 from the first terminal portion T ₁ via the first transistor Tr1 is given, the third transistor Tr3 is set to a conductive state The Further, the first and second data signals S _DP and S _DN are not applied to the twelfth electrode E12, and the fourth transistor Tr4 is set in a non-conductive state.

In the present embodiment, the state in which the third transistors Tr3 of the block circuits BL _{0 to} BL _n are set to the conductive state corresponds to the “first setting state” of the present invention. In this state, each of the block circuits BL _{0 to} BL _n is in a state where the third transistor Tr3 is set in a conductive state and the fourth transistor Tr4 is set in a non-conductive state (out signal output permission state). Become.

In the out signal output permission state, the fifth transistor Tr5 is set to the conductive state, and the sixth transistor Tr6 is set to the non-conductive state. At this time, the first clock signal line L _CLKE in response to an input of the first clock signal S _CLKE for the 0th block circuit BL _0, the first clock signal from the 0th block circuit BL ₀ out signal output terminal section T _OUT An out signal S _OUT (0th out signal S _OUT0 ) corresponding to the line L _CLKE is output. The 0-out signal S _OUT0 output from 0th block circuit BL ₀ is the zeroth to the first block circuit BL ₁ of the set signal applying terminal unit T _SET arranged in the next block circuit BL _0, the set signal Granted as S _SET .

The first block circuit BL ₁ set signal applying terminal unit T _SET, the set signal S _SET is applied from the 0th block circuit BL _0, the first block circuit BL ₁ is set in the out signal output enable state The Then, from the second clock signal line L _CLKO in response to an input of the second clock signal S _CLKO to the first block circuit BL _1, the second clock signal line from the first block circuit BL ₁ out signal output terminal section T _OUT An out signal S _OUT (first out signal S _OUT1 ) corresponding to L _CLKO is output. The first out signal S _OUT1 output from the first block circuit BL ₁ is set to the set signal application terminal portion T _{SET of} the second block circuit BL ₂ arranged next to the first block circuit BL _1. It is given as signal S _SET .

Further, the first out signal S _OUT1 output from the first block circuit BL ₁ is in response to the reset signal application terminal portion T _{RESET of} the zeroth block circuit BL ₀ arranged before the first block circuit BL ₁ . The reset signal S _RESET is applied. At this time, the reset signal S _RESET respectively, are given to the 21 and the 24 electrodes E21, E24 from the reset signal applied terminal unit T _RESET. As a result, the seventh and eighth transistors Tr7 and Tr8 are set in a conductive state, respectively. Then, the first signal line L _DP first data signal S _DP respect twelfth electrode E12 from the fourth terminal portions T ₄ via the eighth transistor Tr8 is applied, the fourth transistor Tr4 is set to a conductive state The On the other hand, since the first and second data signals S _DP and S _DN are not applied to the ninth electrode E9, the third transistor Tr3 is set in a non-conductive state.

In the present embodiment, the state in which the fourth transistors Tr4 of the block circuits BL _{0 to} BL _n are set to the conductive state corresponds to the “second setting state” of the present invention. In this state, each of the block circuits BL _{0 to} BL _n is in a state where the third transistor Tr3 is set in a non-conductive state and the fourth transistor Tr4 is set in a conductive state (out signal output prohibited state). Become.

In the out signal output prohibited state, the fifth transistor Tr5 is turned off and the sixth transistor Tr6 is turned on. At this time, even if the first clock signal S _CLKE is input from the first clock signal line L _CLKE to the 0th block circuit BL ₀ , the first clock is output from the out signal output terminal T _{OUT of} the 0th block circuit BL _0. The out signal S _OUT (the 0th out signal S _OUT0 ) corresponding to the signal line L _CLKE is not output.

As described above, in the first shift mode, the block circuits BL _{0 to} BL _n are sequentially set to the first clock signal input state and the second clock signal input state. Therefore, the shift register circuit 400 performs the following operation.

First, when the set signal S _SET is input from the outside to the 0th block circuit BL ₀ , the 0th block circuit BL ₀ is set to an out signal output permission state. When the first clock signal S _CLKE relative 0th block circuit BL ₀ is input, the 0-out signal S _OUT0 corresponding to the first clock signal S _CLKE is output from the 0th block circuit BL ₀ .

Then, the 0th-out signal S _OUT0 is input to the first block circuit BL ₁ as a set signal S _SET, the first block circuit BL ₁ is set to the out signal output enable state. When the second clock signal S _CLKO to the first block circuit BL ₁ is input, first-out signal S _OUT1 corresponding to the second clock signal S _CLKO is outputted from the first block circuit BL ₁ .

The next, first-out signal S _OUT1 is, is input to the second circuit block BL ₂ as a set signal S _SET, first-out signal S _OUT1 is, the 0th block circuit BL as a reset signal S _RESET Input for ₀ . At this time, the second circuit block BL ₂ together with the set Out signal output enable state, the 0th block circuit BL ₀ is set to the out signal output disabled state. When the first clock signal S _CLKE the second block circuit BL ₂ is input, the second out signal S _OUT2 in response to the first clock signal S _CLKE is output from the second circuit block BL ₂ . Since the 0th block circuit BL ₀ is set to the out signal output disabled state, even if the first clock signal S _CLKE relative 0th block circuit BL ₀ is inputted, from said 0 block circuit BL ₀ The 0th out signal S _OUT0 is not output.

By repeating such an operation, the first to n block circuits BL _{1 to} BL _n are directed from one end side to the other end side in response to the out signal S _OUT output from the previously arranged block circuits. Are sequentially set to the out signal output permission state. Then, the block circuit set to the out signal output permission state is set to the out signal output prohibition state in response to the out signal S _OUT output from the block circuit arranged next. That is, in the shift register circuit 400, the block circuits BL _{0 to} BL _n are sequentially set to the out signal output permission state and the out signal output prohibition state.

For the n-th block circuit BL _n, there is no block circuit arranged next. Therefore, by the reset signal S _RESET from outside at a predetermined timing in response to a signal from TG202 is input, the n-th block circuit BL _n are set from the out signal output enable state out signal output disabled state. However, the first data signal _SDP is not input to the first, fourth, and fifth terminal portions T ₁ , T ₄ , T ₅ , and the second, third, and sixth terminal portions T ₂ , T ₂ , and changes to T _3, T ₆ in a state where the second data signal S _DN is input, a state in which the first mode signal S _SL against 7-10 terminal unit T ₇ through T ₁₀ is inputted Even when the second mode signal _SPL is switched to the state where the eleventh and twelfth terminal portions T ₁₁ and T ₁₂ are input, the nth block circuit BL _n is changed from the out signal output enable state to the out signal output disable state. Can be set to

Each of the block circuits BL _{0 to} BL _n is moved from the out signal output permission state at a timing when a block circuit arranged next to the next block circuit is set from the out signal output inhibition state to the out signal output permission state. The out signal output disabled state is set. That is, in the 0th to _n-th block circuits BL _{0 to} BL _n , two block circuits arranged in succession and set in the out signal output permission state are sequentially sequentially one block circuit from one end side to the other end side. Shift to. In FIG. 17, the direction of this shift is indicated by an arrow Ar _SHIFT .

In this way, in the shift register circuit 400 set in the first shift mode, the set signal S _{SET is} externally applied to the set signal application terminal portion T _{SET of} the zeroth block circuit BL ₀ arranged on one end side. , The first clock signal input state and the second clock signal input state are alternately set, and the 0th to n-th out signals S _{OUT0 to} S _OUTn are sequentially output. In other words, in the first shift mode, the shift register circuit 400 operates in order of the 0th out signal S _OUT0 , the first out signal S _OUT1 , the second out signal S _{OUT2 ,.} S _{OUT0 to} S _OUTn are sequentially output. In the image display apparatus 1, when the display of one frame of the image, the operation which the first 0~n out signal S _OUT0 to S _OUTn is output sequentially is performed once. Therefore, when images of a plurality of frames constituting a moving image are sequentially displayed, the operation of sequentially outputting the 0th to n-th out signals S _{OUT0 to} S _OUTn is repeatedly performed a plurality of times.

<Second shift mode>
In the second shift mode, similarly to the first shift mode, the first clock signal input state and the second clock signal input state are alternately set. Then, at a predetermined timing, a reset signal S _RESET is applied from the outside to the _n- th block circuit BL _n on the other end side.

However, in the first shift mode, the first data signal S _DP is applied from the first signal line L _DP to each of the block circuits BL _{0 to} BL _n and the second data signal from the second signal line L _DN . _Whereas S _DN is not provided, in the second shift mode, the second data signal S _DN is provided from the second signal line L _DN to each of the block circuits BL _{0 to} BL _n , and the first signal The first data signal S _DP is not applied from the line L _DP . In the first shift mode, the shift register circuit 400 operates in order of the 0th out signal S _OUT0 , the first out signal S _OUT1 , the second out signal S _OUT2 ,..., And the nth out signal S _OUTn. In contrast to sequentially outputting S _{OUT0 to} S _OUTn , in the second shift mode, the shift register circuit 400 causes the n-th out signal S _OUTn , the n−1-th out signal S _OUTn−1 , and the n− _2th out. The respective out signals S _{OUT0 to} S _OUTn are sequentially output in the order of the signals S _OUTn-2 ,..., The 0th out signal S _OUT0 .

  Here, a specific operation of the shift register circuit 400 in the second shift mode will be described with reference to FIG.

As shown in FIG. 18, in the second shift mode, the reset signal S _RESET corresponding to the signal from the TG 202 is given from the outside to the reset signal giving terminal portion T _RESET of the n-th block circuit BL _n on the other end side. When the reset signal S _rESET respectively, are given to the 21 and the 24 electrodes E21, E24 from the reset signal applied terminal unit T _rESET. At this time, the seventh and eighth transistors Tr7 and Tr8 are each turned on. Then, the second signal line L _DN second data signal S _DN against the third terminal portion T ₃ via the seventh transistor Tr7 ninth electrode E9 is applied, the third transistor Tr3 is set to a conductive state The Further, the first and second data signals S _DP and S _DN are not applied to the twelfth electrode E12, and the fourth transistor Tr4 is set in a non-conductive state. That is, the n-th block circuit BL _n are set to out signal output enable state.

At this time, the second clock signal line L _CLKO in response to an input of the second clock signal S _CLKO for the first n block circuit BL _n, the second clock signal from the out-signal output terminal section T _OUT of the n block circuit BL _n An out signal S _OUT (n-th out signal S _OUTn ) corresponding to S _CLKO is output. The n-out signal S _OUTn output from the n-th block circuit BL _n, compared the (n-1) block circuit BL _n-1 of the reset signal applying terminal unit T _RESET arranged in front of the n block circuit BL _n The reset signal S _RESET is applied.

Against the n-1 block circuit BL _n-1 of the reset signal applying terminal unit T _RESET, a reset signal S _RESET from the first n block circuit BL _n is applied, the n-1 block circuit BL _n-1 Is set to the out signal output permission state. Then, the first clock signal line L _CLKE in response to an input of the first clock signal S _CLKE for the first n-1 block circuit BL _n-1, the n-1 block circuit BL _n-1 of the out signal output terminal portion An out signal S _OUT (n− _1th out signal S _OUTn−1 ) corresponding to the first clock signal S _CLKE is output from T _OUT . The (n−1) th out signal S _OUTn−1 output from the (n−1) th block circuit BL _n−1 is the n− _2th block circuit BL arranged before the _n− 1th block circuit BL _{n−1. A} reset signal S _RESET is applied to the _n-2 reset signal application terminal T _RESET .

Further, the n-1-out signal S _OUTn-1 output from the (n-1) block circuit BL _n-1, the said n-1 block circuit BL _n-1 of the n block circuit BL arranged in the following _The set signal S _SET is applied to the _n set signal application terminal T _SET . At this time, the set signal S _SET is applied to the third and sixth electrodes E3 and E6 from the set signal applying terminal portion T _SET . For this reason, the first and second transistors Tr1 and Tr2 are turned on. At this time, the second data signal S _DN is applied from the second terminal portion T ₂ to the twelfth electrode E 12 via the second transistor Tr ₂ by the second signal line L _DN , and the fourth transistor Tr 4 is set to the conductive state. Is done. On the other hand, since the first and second data signals S _DP and S _DN are not applied to the ninth electrode E9, the third transistor Tr3 is set in a non-conductive state.

At this time, the fifth transistor Tr5 is set in a non-conductive state, and the sixth transistor Tr6 is set in a conductive state. Therefore, even if the second clock signal S _CLKO is input from the second clock signal line L _CLKO to the n-th block circuit BL _n , the output corresponding to the second clock signal line L _CLKO is output from the out signal output terminal portion T _OUT . The signal S _OUT (nth out signal S _OUTn ) is not output. That is, the n-th block circuit BL _n are set to out output disabled state.

As described above, in the shift register circuit 400 set to the second shift mode, each of the block circuits BL _{0 to} BL _n is sequentially set to the first clock signal input state and the second clock signal input state. The Therefore, the shift register circuit 400 performs the following operation.

First, when the reset signal S _RESET is externally input to the n-th block circuit BL _n , the n-th block circuit BL _n is set to an out signal output permission state. When the second clock signal S _CLKO is input, the n-out signal S _OUTn corresponding to the second clock signal S _CLKO is outputted from the n block circuit BL _n against the n block circuit BL _n .

Next, the n-th out signal S _OUTn is input as the reset signal S _RESET to the n−1-th block circuit BL _n−1 , and the n−1-th block circuit BL _n−1 enters the out signal output enable state. Is set. When the first clock signal S _CLKE is input to the (n−1) th block circuit BL _n−1 , the (n−1) th out signal S _OUTn−1 corresponding to the first clock signal S _CLKE is nth. -1 block circuit BLn _-1 .

Next, the (n−1) th out signal S _OUTn−1 is input to the _n− 2th block circuit BL _n−2 as the reset signal S _RESET and the n− _1th out signal S _OUTn−1. but is input to the n-th block circuit BL _n as the set signal S _sET. At this time, the n-2 block circuit BL _n-2, along with set to out signal output enable state, the n-th block circuit BL _n are set to out output disabled state. When the second clock signal S _CLKO is input to the n−2 block circuit BL _n−2 , the n− _2th out signal S _OUTn−2 corresponding to the second clock signal S _CLKO is nth. -2 is output from the block circuit BLn _-2 . Further, since the n-th block circuit BL _n are set to out output disabled state, even if the second clock signal S _CLKO against the n block circuit BL _n is inputted, from said n block circuit BL _n The n-th out signal S _OUTn is not output.

By repeating such an operation, the _{0th to ( n-1) th} block circuits BL _{0 to} BL _n−1 are connected from the other end side in response to the out signal S _OUT output from the next arranged block circuit. The out signal output permission state is sequentially set toward one end side. Then, the block circuit set to the out signal output permission state is set to the out signal output prohibition state in response to the out signal S _OUT output from the previously arranged block circuit. That is, in the shift register circuit 400, the block circuits BL _{0 to} BL _n are sequentially set to the out signal output permission state and the out signal output prohibition state.

For the 0th block circuit BL _0, there is no previously arranged block circuit. Therefore, by the reset signal S _SET is inputted from the outside at a predetermined timing in response to a signal from TG202, 0th block circuit BL ₀ is set from the out signal output enable state out signal output disabled state. However, instead of inputting the set signal S _SET from the outside to the 0th block circuit BL ₀ at a predetermined timing, the first mode signal S _SL is input to the _{seventh to tenth} terminal portions T _{7 to} T ₁₀ . Even if the second mode signal _SPL is input to the eleventh and twelfth terminal portions T ₁₁ and T ₁₂ from the state in which the first block circuit BL ₀ is switched from the out signal output permission state to the out signal, The output can be disabled.

Each of the block circuits BL _{0 to} BL _n is moved from the out signal output permission state at a timing when the block circuit arranged further before the previous block circuit is set from the out signal output inhibition state to the out signal output permission state. The out signal output disabled state is set. That is, in the 0th to _n-th block circuits BL _{0 to} BL _n , two block circuits arranged in succession and set in the out signal output permission state are sequentially sequentially one block circuit from the other end side to the one end side. Shift to. In FIG. 18, the direction of this shift is indicated by an arrow Ar _SHIFT .

In this way, in the shift register circuit 400 set to the second shift mode, the reset signal S is externally applied to the reset signal application terminal portion T _{RESET of} the n-th block circuit BL _n arranged on the other end side. _{After the RESET} is applied, the second clock signal input state and the first clock signal input state are alternately set, and the 0th to nth out signals S _{OUT0 to} S _OUTn are sequentially output. That is, in the second shift mode, the shift register circuit 400 includes the nth out signal S _OUTn , the n−1 out signal S _OUTn−1 , the n−2 out signal S _{OUTn− 2,.} sequentially outputs each out signal S _OUT0 to S _OUTn in the order of the signal S _OUT0.

<Simultaneous output mode>
The simultaneous output mode, the first mode signal S _SL against 7-10 terminal unit T ₇ through T ₁₀ is not input, the 9-12 transistor Tr9~Tr12 is set to a non-conductive state. In addition, the second mode signal _SPL is input to the eleventh and twelfth terminal portions T ₁₁ and T _{12 at} a predetermined timing, so that the thirteenth and _twelfth circuits in all the block circuits BL _{0 to} BL _n . The 14 transistors Tr13 and Tr14 are set in a conductive state.

As shown in FIG. 19, in the simultaneous output mode, the ninth to twelfth transistors Tr9 to Tr12 of the block circuits BL _{0 to} BL _n are set in a non-conducting state, and each block circuit BL _{0 is connected} from the first signal line L _DP. In the state _where the first data signal _SDP is applied to .about.BL _n and the second data signal S _DN is not applied from the second signal line L _DN to each of the block circuits BL _{0 to} BL _n . The second mode signal _SPL is input to the terminal portions T ₁₁ and T ₁₂ . At this time, in all the block circuit BL ₀ to BL _n, thirteenth and fourteenth transistors Tr 13, Tr14 is set to the conductive state, the ninth from the first signal line L _DP through the thirteenth transistor Tr 13, 10, and 15 electrode E9, E10, the first data signal S _DP against E15 is assigned, from the second signal line L _DN through the fourteenth transistor Tr14 seventh, twelfth, and eighteenth electrode E7, E12 , E18 is not given the second data signal S _DN . As a result, each third transistor Tr3 is set in a non-conductive state, and each fourth transistor Tr4 is set in a conductive state. For this reason, in all the block circuits BL _{0 to} BL _n , the fifth transistor Tr5 is set to a conductive state and the sixth transistor Tr6 is set to a non-conductive state. That is, all the block circuits BL _{0 to} BL _n are simultaneously set to the out signal output permission state.

At a predetermined timing, the first clock signal S _CLKE is input from the first clock signal line L _CLKE to the odd-numbered block circuits BL ₀ , BL ₂ , BL ₄ ,..., BL _n−1 . The second clock signal S _CLKO is input from the second clock signal line L _CLKO to the even-numbered block circuits BL ₁ , BL ₃ , BL _{5 ,.} At this time, the odd-numbered block circuit _{BL 0, BL 2, BL 4} , ···, out signal corresponding from BL _n-1 to the first clock signal _{S CLKE S OUT0, S OUT2,} S OUT4, ···, S _OUTn-1 is output, the even-numbered block circuit _{BL 1, BL 3, BL 5} , ···, out signal corresponding to the second clock signal S _CLKO from _{BL n S OUT1, S OUT3,} S OUT5, · .., S _OUTn is output. That is, out signals S _{OUT0 to} S _OUTn are simultaneously output from all the block circuits BL _{0 to} BL _n , respectively.

Further, in all the block circuit BL ₀ to BL _n, the second mode signal S _PL is input, the ninth from the first signal line L _DP through the thirteenth transistor Tr 13, 10, and 15 electrode E9, E10 first data signal S _DP is not granted to E15, and the seventh and the second signal line L _DN through the fourteenth transistor Tr14, the relative twelfth, and eighteenth electrode E7, E12, E18 When the 2 data signal S _DN is applied, the third transistor Tr3 is set in a non-conductive state and the fourth transistor Tr4 is set in a conductive state. At this time, in all the block circuits BL _{0 to} BL _n , the fifth transistor Tr5 is set in a non-conductive state and the sixth transistor Tr6 is set in a conductive state. That is, all the block circuits BL _{0 to} BL _n are simultaneously set to the out signal output prohibited state.

Further, in all the block circuit BL ₀ to BL _n, the second mode signal S _PL is input, the ninth from the first signal line L _DP through the thirteenth transistor Tr 13, 10, and 15 electrode E9, E10 first data signal S _DP is not granted to E15, and the seventh and the second signal line L _DN through the fourteenth transistor Tr14, the relative twelfth, and eighteenth electrode E7, E12, E18 when the second data signal S _DN is also not been granted, the potential of the out signal output terminal section T _oUT is in a state of flux (floating state), the potential of the 0~n out signal S _OUT0 to S _OUTn fluid Potential V _HiZ .

Further, the second mode signal _SPL is input to all the block circuits BL _{0 to} BL _n , the first data signal _SDP is not applied, the second data signal _SDN is applied, and the first and By setting the second clock signals S _CLKE and S _CLKO not to be input, it is set to a state in which the out signals S _{OUT0 to} S _OUTn are not output from all the block circuits BL _{0 to} BL _n (stationary state).

Note that the application of the first data signal S _DP from the first signal line L _DP and the application of the second data signal S _DN from the second signal line L _DN to all the block circuits BL _{0 to} BL _n Are not allowed to occur simultaneously. If the first and second data signals S _DP and S _DN are simultaneously applied to all the block circuits BL _{0 to} BL _n , the first and second signal lines L _DP and S _{DN are connected} to the low potential line. A through current flows toward _LVL .

<Operation of shift register circuit>
As described above, by repeating the periods P1 to P6 shown in FIG. 4, the light emission of each organic EL element 11 is repeated, and a moving image corresponding to the output image signal is displayed on the organic EL display unit 3. The Then, the 0~n scanning signal line L _SS potential V _ls0 ~V _lsn, i.e. when focusing on the output from the Y driver circuit 4Y, the potential V of the 0~n scanning signal line L _{SS ls0} ~V _lsn is sequentially and the period P4 that a higher potential V _gH, and period P2, P5, P6 of the potential V _ls0 ~V _lsn of all of the 0~n scanning signal line L _SS becomes a low potential V _gL, all of the 0~n scan _There are periods P1 and P3 in which the potentials V _{ls0 to} V _lsn of the signal line L _SS are at the high potential V _gH . Then, when the shift register circuit 400 that are configured to simultaneously output mode, to set the potential V _ls0 ~V _lsn of all of the 0~n scanning signal line L _SS to the low potential V _gL and high potential V _gH Is possible.

For this reason, in the image display device 1 according to the present embodiment, when the organic EL display unit 3 displays a moving image according to the output image signal, the shift register circuit 400 constituting the Y driver circuit 4Y is in the period P4. Correspondingly, the period (first shift mode period) T _SHIFT in which the first shift mode is set, and the period in which the shift register circuit 400 is set in the simultaneous output mode corresponding to the periods P1 to P3, P5, P6 ( (Simultaneous output mode period) T _PARA is repeated alternately. That is, the shift register circuit 400 includes a state in which the first mode signal S _SL is applied from the first mode signal line L _SL to each of the block circuits BL _{0 to} BL _n and the first mode signal line L _SL. The block circuits BL _{0 to} BL _n are alternately set to a state where the first mode signal S _SL is not applied.

FIG. 20 is a timing chart relating to the operation of the shift register circuit 400 when displaying a moving image according to the output image signal in the organic EL display unit 3. FIG. 20 shows a first shift mode period T _SHIFT (period from time t _{2 to} t ₁₇ ) for one time out of the first shift mode period T _SHIFT and the simultaneous output mode period T _PARA being repeated a plurality of times. This is focused on the simultaneous output mode period T _PARA (period from time t _{20 to} t ₂₅ ).

In FIG. 20, the horizontal axis indicates time, and in order from the top, (a) a set signal S _SET from the outside to the 0th block circuit BL ₀ (hereinafter referred to as “first set signal S _SETL ”), (b) the first clock signal S _CLKE in each block circuit BL ₀ ~BL _n, (c) second clock signal S _CLKO in each block circuit BL ₀ ~BL _n, (d) first data in each block circuit BL ₀ to BL _n signal S _DP, the second data signal S _DN in (e) the block circuit BL ₀ ~BL _n, (f) a first mode signal S _SL in each block circuit BL ₀ ~BL _n, (g) each block circuit BL ₀ second mode signal S _PL in ~BL _n, (h) the zeroth-out signal S _OUT0, (i) first-out signal S _OUT1, (j) second out signal S _OUT2, (k) a third out signal S _OUT3 , (L) the (n-1) th out signal S _OUTn-1 , And (m) The input or output timing of the n-th out signal S _OUTn is shown. In FIG. 20, a state where each signal is input or output (High state) is indicated by “1”, and a state where each signal is not input or output (Low state) is indicated by “0”. Note that the input of each signal is controlled according to the signal from the TG 202.

As shown in FIG. 20, first, at time t ₁ , the head set signal S _SETL is not input to the 0th block circuit BL ₀ , and the first clock signal S _CLKE and the second clock signal are input to the block circuits BL ₀ to _BLn . The clock signal S _CLKO , the first data signal S _DP , and the first mode signal S _SL are not input, and the second data signal S _DN and the second mode signal S _PL are input to the block circuits BL0 to BLn. after that state, the second mode signal S _PL is set to the state not input (Low state) to each block circuit BL0 to BLn. At this time, the input state of other signals is maintained. As for the signal input / output state changes with the passage of time described below, it is assumed that the signal input / output state of the immediately preceding signal is maintained in principle for signals not described.

At time t _2, the together with the first data signal S _DP and the first mode signal S _SL in the block circuit BL0 to BLn are set to a state that is entered (High state), the in each block circuit BL0 to BLn 2 It is set to a state (Low state) in which the data signal S _DN is not input. At this time, the shift register circuit 400 is set to the first shift mode.

From time t _{3 to} t ₄ , the head set signal S _SETL is input to the 0th block circuit BL ₀ (high state). At this time, the 0th block circuit BL ₀ is set to the out signal output permission state.

At time t ₅ ~t _6, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, the 0-out signal S _OUT0 of the 0th block circuit BL ₀ corresponding to the first clock signal S _CLKE is output. Then, set as the 0-out signal S _OUT0 is set signal S _SET for the first block circuit BL _1, is input to the first block circuit BL _1, the first block circuit BL ₁ is in the out-signal output enable state Is done. In the time t _6, the first clock signal S _CLKE is set to a state not input (Low state) to each block circuit BL0 to BLn.

At time t ₇ ~t _8, the second clock signal S _CLKO is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, a first out signal S _OUT1 corresponding to the second clock signal S _CLKO is output from the first block circuit BL ₁ . Then, set as the set signal S _SET first-out signal S _OUT1 is for the second block circuit BL _2, is input to the second block circuit BL _2, second block circuit BL ₂ is the out signal output enable state Is done. Further, set as a reset signal S _RESET first-out signal S _OUT1 is for 0th block circuit BL _0, is input to said 0 block circuit BL _0, said 0 block circuit BL ₀ is the out signal output disabled state Is done. In time t _8, the second clock signal S _CLKO is set to a state not input (Low state) to each block circuit BL0 to BLn.

At time t ₉ ~t _10, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, a second out signal S _OUT2 corresponding to the first clock signal S _CLKE is output from the second block circuit BL ₂ . Then, setting as the second out signal S _OUT2 is set signal S _SET for the third block circuit BL _3, is input to the third block circuit BL _3, the third block circuit BL ₃ Out signal output enable state Is done. Further, set as a reset signal S _RESET second out signal S _OUT2 is for the first block circuit BL _1, is input to the first block circuit BL _1, the first block circuit BL ₁ within out signal output disabled state Is done. At time t ₁₀ , the first clock signal S _CLKE is not input to the block circuits BL0 to _BLn (Low state).

From time t _{11 to} t ₁₂ , the block circuit BL 0 to BLn is set to a state (High state) in which the second clock signal S _CLKO is input. At this time, a third out signal S _OUT3 corresponding to the second clock signal S _CLKO is output from the third block circuit BL ₃ . Then, set as the set signal S _SET third out signal S _OUT3 is for the fourth block circuit BL _4, is input to the fourth block circuit BL _4, fourth block circuit BL ₄ are the out-signal output enable state Is done. Further, set as a reset signal S _RESET third out signal S _OUT3 is for the second block circuit BL _2, is input to the second block circuit BL _2, second block circuit BL ₂ is the out signal output disabled state Is done. At time t ₁₂ , the second clock signal S _CLKO is not input to the block circuits BL0 to BLn (Low state).

Then, operation similar to the operation at time t ₈ ~t ₁₂ is repeated, in the 4 to N-2 block circuit BL ₄ ~BL _n-2, the 4 to N-2-out signal S _OUT4 to S in numerical order _OUTn-2 is output sequentially.

Next, at time t ₁₃ ~t _14, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, the n-1-out signal S _OUTn-1 of the (n-1) th block circuit BL _n-1 corresponding to first clock signal S _CLKE is output. Then, the (n-1) out signal S _OUTn-1 as the set signal S _SET for the first n block circuit BL _n, is input to said n block circuit BL _n, the said n block circuit BL _n-out signal output Set to Allowed state. Further, the (n−1) th out signal S _OUTn−1 is input to the n− _2th block circuit BL _{n−2 as} the reset signal S _RESET for the n−2 block circuit BL _n−2 , -2 block circuit BL _n-2 is set to the out signal output prohibited state. In time t _14, first clock signal S _CLKE is set to a state not input (Low state) to each block circuit BL0 to BLn.

At time t ₁₅ ~t _16, the second clock signal S _CLKO is set to a state that is entered (High state) to each block circuit BL0 to BLn. At this time, an n-th out signal S _OUTn corresponding to the second clock signal S _CLKO is output from the _n- th block circuit BL _n . Then, the n-th-out signal S _OUTn as a reset signal S _RESET for the first n-1 block circuit BL _n-1, is input to said n-1 block circuit BL _n-1, said n-1 block circuit BL _n-1 is set to the out signal output disabled state. At time t ₁₆ , the second clock signal S _CLKO is not input to the block circuits BL0 to BLn (Low state).

At time t _17, together with the first data signal S _DP and the first mode signal S _SL is set to a state of not being input (Low state) in each block circuit BL0 to BLn, first in each block circuit BL0 to BLn 2 The data signal S _DN is set to the input state (High state). At this time, the shift register circuit 400 is released from the state set in the first shift mode.

At time t ₁₈ ~t _19, the second mode signal S _PL is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, the first 0~n out signal S _OUT0 to S _OUTn shift a state of quiescence is not output register circuit 400 from all the block circuit BL ₀ to BL _n are set. In the time t _19, the second mode signal S _PL is set to the state not input (Low state) to each block circuit BL0 to BLn.

At time t _20, together with the first data signal S _DP is set to a state that is entered (High state) in each block circuit BL0 to BLn, the second data signal S _DN is input to the block circuit BL0 to BLn Not set (Low state). At this time, the shift register circuit 400 is set to the simultaneous output mode.

At time t ₂₁ ~t _22, the second mode signal S _PL is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, since it is set to a state in which the first data signal S _DP is input (High state) in each block circuit BL0 to BLn, all block circuit BL ₀ to BL _n, the out signal output enabled state Is set. In the time t _22, the second mode signal S _PL is set to the state not input (Low state) to each block circuit BL0 to BLn.

At time t ₂₃ ~t _24, first and second clock signal S _CLKE each block circuit BL0 to BLn, it is set in a state S _CLKO is input (High state). At this time, _{0th to n-} th out signals S _{OUT0 to} S _{OUTn corresponding} to the first or second clock signals S _CLKE and S _CLKO are output from the _{0th to n-th} block circuits BL _{0 to} BL _n . FIG. 20 shows an example in which the 0th to _n- th out signals S _{OUT0 to} S _OUTn are output once from the 0th to _n-th block circuits BL _{0 to} BL _n in the simultaneous output mode period T _PARA . , when displaying each frame of the moving image corresponding to the output image signal in the organic EL display unit 3, the potential of all of the 0~n scanning signal line L _SS in the period P1, P3 shown in FIG. 4 V _{The 0th} to nth out signals S _{OUT0 to} S _OUTn are output twice from the 0th to _nth block circuits BL _{0 to} BLn so as to correspond to the _{ls0 to} V _lsn becoming the high potential V _gH . At time t _24, the first and second clock signal S _CLKE to each circuit block BL0 to BLn, S _CLKO is set to a state not input (Low state).

At time t _25, together with the first data signal S _DP is set to a state of not being input (Low state) in each block circuit BL0 to BLn, the second data signal to each circuit block BL0 to BLn S _DN and second The mode signal _SPL is set to the input state (High state). At this time, the shift register circuit 400 is released from the state of being set in simultaneous output mode, a state of quiescence first 0~n out signal S _OUT0 to S _OUTn from the 0~n block circuit BL ₀ to BL _n is not output The shift register circuit 400 is set.

By repeating the operation of the shift register circuit 400 at times t _{1 to} t ₂₅ as described above, a moving image corresponding to the output image signal is displayed on the organic EL display unit 3.

  21 and 22 are timing charts showing more detailed operations than the timing charts related to the operation of the shift register circuit 400 shown in FIG.

FIG. 21 is a timing chart relating to the operation in the period including the times t _{1 to} t ₁₈ shown in FIG. 20, and the potentials of the gates of the fifth and sixth transistors Tr5 and Tr6 in the block circuits BL _{0 to} BL _n ( the fifth and sixth gate potential) is _{Tr5 GATE0 ~Tr5 GATEn, Tr6 GATE0 ~Tr6} GATEn timing chart plus the change in the. Further, FIG. 22 is a timing chart according to the operation of the period including the time t ₁₇ ~t ₂₅ shown in FIG. 20, fifth and sixth gate potential Tr5 _GATE0 ~Tr5 _GATEn in each block circuit BL ₀ to BL _n is a timing chart plus the change in Tr6 _GATE0 ~Tr6 _GATEn.

In FIGS. 21 and 22, the state (low potential state) in which the fifth and sixth gate potentials Tr5 _{GATE0 to} Tr5 _GATEn and Tr6 _{GATE0 to} Tr6 _GATEn are low potentials (for example, near 0 V) is indicated by “L”. A state (high potential state) at a high potential (for example, near 10 V) is indicated by “H”, and a state (maximum potential state) at a maximum potential (for example, near 20 V) higher than the high potential is indicated by “SH”. Has been.

As described above, the timing chart shown in FIGS. 21 and 22, as compared with the timing chart shown in FIG. 20, the change of the fifth and sixth gate potential _{Tr5 GATE0 ~Tr5 GATEn, Tr6 GATE0 ~Tr6} GATEn Is added. Therefore, in the following, description of operations similar to those in the timing chart shown in FIG. 20 will be omitted, and changes in the added fifth and sixth gate potentials Tr5 _{GATE0 to} Tr5 _GATEn and Tr6 _{GATE0 to} Tr6 _GATEn will be _omitted . explain.

As shown in FIG. 21, at time t ₃ , the head set signal S _SETL is set to be input to the 0th block circuit BL ₀ (High state). Depending on the setting, the fifth gate potential Tr5 _GATE0 of the 0th block circuit BL _0, together with the transition from low potential to a high potential state, the sixth gate potential Tr6 _GATE0 said 0 block circuit BL ₀ is high Transition from the potential state to the low potential state. That is, the 0th block circuit BL ₀ is set to an out signal output enabled state.

At time t ₅ ~t _6, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, in the 0th block circuit BL ₀ , the fifth gate potential Tr 5 _{GATE 0} shifts from the high potential state to the maximum potential state due to the stray capacitance between the drain and gate of the fifth transistor Tr 5. In addition, this time, the 0-out signal S _OUT0 of the 0th block circuit BL ₀ corresponding to the first clock signal S _CLKE is output.

At time t _5, the 0-out signal S _OUT0 is input to the first block circuit BL ₁ as a set signal S _SET, fifth gate potential Tr5 _GATE1 of the first block circuit BL ₁ is the low potential with shifts to a high potential state, the sixth gate potential Tr6 _GATE1 of the first block circuit BL ₁ is changed from the high potential state to a low potential state. That is, the first block circuit BL ₁ is set in an out signal output enabled state.

At time t ₇ ~t _8, the second clock signal S _CLKO is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, in the first block circuit BL _1, the stray capacitance between the drain and the gate of the fifth transistor Tr5, the fifth gate potential Tr5 _GATE1 transitions from the high potential state a maximum potential state. Further, at this time, a first out signal S _OUT1 corresponding to the second clock signal S _CLKO is output from the first block circuit BL ₁ .

At time t ₇ , the first out signal S _OUT1 is input as the set signal S _SET to the second block circuit BL ₂ , and the fifth gate potential Tr 5 _{GATE 2} of the second block circuit BL ₂ is changed from the low potential state. with shifts to a high potential state, the sixth gate potential Tr6 _GATE2 of the second block circuit BL ₂ is shifted from the high potential state to a low potential state. That is, the second block circuit BL ₂ is set in an out signal output enabled state.

Further, at time t ₇ , the first out signal S _OUT1 is input as the reset signal S _RESET to the 0th block circuit BL ₀ , and the fifth gate potential Tr 5 _{GATE 0} of the 0th block circuit BL ₀ is changed from the high potential state. with shifts to the low potential state, the sixth gate potential Tr6 _GATE0 said 0 block circuit BL ₀ is the transition from the low potential state to a high potential state. That is, the 0th block circuit BL ₀ is set from the out signal output enabled state to the out signal output disabled state.

At time t ₉ ~t _10, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, in the second block circuit BL _2, the stray capacitance between the drain and the gate of the fifth transistor Tr5, the fifth gate potential Tr5 _GATE2 transitions from the high potential state a maximum potential state. Further, at this time, a second out signal S _OUT2 corresponding to the first clock signal S _CLKE is output from the second block circuit BL ₂ .

At time t _9, the second out signal S _OUT2 is input to third block circuit BL ₃ as a set signal S _SET, fifth gate potential Tr5 _GATE3 the third block circuit BL ₃ from the low potential state with shifts to a high potential state, the sixth gate potential Tr6 _GATE3 the third block circuit BL ₃ is shifted from the high potential state to a low potential state. That is, the third block circuit BL ₃ is set to the out signal output enabled state.

Further, at time t _9, the second out signal S _OUT2 is input to the first block circuit BL ₁ as a reset signal S _RESET, fifth gate potential Tr5 _GATE1 of the first block circuit BL ₁ from the high potential state with shifts to the low potential state, the sixth gate potential Tr6 _GATE1 of the first block circuit BL ₁ is shifted from the low potential state to a high potential state. That is, the first block circuit BL ₁ is set from the out signal output enabled state to the out signal output disabled state.

From time t _{11 to} t ₁₂ , the block circuit BL 0 to BLn is set to a state (High state) in which the second clock signal S _CLKO is input. At this time, in the third block circuit BL _3, the stray capacitance between the drain and the gate of the fifth transistor Tr5, the fifth gate potential Tr5 _GATE3 transitions from the high potential state a maximum potential state. Further, at this time, a third out signal S _OUT3 corresponding to the second clock signal S _CLKO is output from the third block circuit BL ₃ .

At time t ₁₁ , the third out signal S _OUT3 is input as the set signal S _SET to the fourth block circuit BL ₄ , and the fifth gate potential Tr 5 _{GATE 4} of the fourth block circuit BL ₄ is changed from the low potential state. with shifts to a high potential state, the sixth gate potential Tr6 _GATE4 the fourth block circuit BL ₄ is shifted from the high potential state to a low potential state. That is, the fourth block circuit BL ₄ is set to the out signal output enabled state.

Furthermore, at time t ₁₁ , the third out signal S _OUT3 is input as the reset signal S _RESET to the second block circuit BL ₂ , and the fifth gate potential Tr 5 _{GATE 2} of the second block circuit BL ₂ is changed from the high potential state. with shifts to the low potential state, the sixth gate potential Tr6 _GATE2 of the second block circuit BL ₂ is shifted from the low potential state to a high potential state. That is, the second block circuit BL ₂ is set from the out signal output enable state to the out signal output disabled state.

Then, operation similar to the operation at time t ₈ ~t ₁₂ is repeated, the 4 to N-2 block circuit BL ₄ ~BL _n-2 is set to out signal output enable state in numerical order, the 4 to N -2 out signals S _{OUT4 to} S _OUTn-2 are sequentially output.

Next, at time t ₁₃ ~t _14, the first clock signal S _CLKE is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, in the n− _1th block circuit BL _n−1 , the fifth gate potential Tr5 _GATEn−1 shifts from the high potential state to the maximum potential state due to the stray capacitance between the drain and gate of the fifth transistor Tr5. . Further, at this time, the n-1-out signal S _OUTn-1 of the (n-1) th block circuit BL _n-1 corresponding to the first clock signal S _CLKE is output.

At time t _13, the n-1-out signal S _OUTn-1 is input to the n-th block circuit BL _n as the set signal S _SET, the fifth gate potential Tr5 _GATEn said n block circuit BL _n with the transition from low potential to a high potential state, the sixth gate potential Tr6 _GATEn said n block circuit BL _n is shifted from the high potential state to a low potential state. That is, the n-th block circuit BL _n are set to out signal output enable state.

Further, at time t ₁₃ , the (n−1) th out signal S _OUTn−1 is input to the n− _2th block circuit BL _n −2 as the reset signal S _RESET , and the n−2th block circuit BL _n−2. fifth gate potential Tr5 _GATEn-2 along with the transition from the high potential state to the low potential state, the sixth gate potential Tr6 _GATEn-2 of the n-2 block circuit BL _n-2 is a high potential state from the low potential Transition. That is, the n-2th block circuit BL _n-2 is set from the out signal output enabled state to the out signal output prohibited state.

At time t ₁₅ ~t _16, the second clock signal S _CLKO is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, in the n block circuit BL _n, the stray capacitance between the drain and the gate of the fifth transistor Tr5, the fifth gate potential Tr5 _GATEn transitions from the high potential state a maximum potential state. Further, at this time, the n-th block signal BL _n outputs the n-th out signal S _OUTn corresponding to the second clock signal S _CLKO .

At time t ₁₅ , the n-th out signal S _OUTn is input as the reset signal S _RESET to the n−1 _- th block circuit BL _n−1 , and the fifth gate of the _n−1-th block circuit BL _n−1 is input. The potential Tr5 _GATEn-1 shifts from the high potential state to the low potential state, and the sixth gate potential Tr6 _GATEn-1 of the _{n- 1th} block circuit BL _n-1 shifts from the low potential state to the high potential state. That is, the (n−1) th block circuit BL _n−1 is set from the out signal output enabled state to the out signal output prohibited state.

At time t _17, while being set to a state in which the first data signal S _DP and the first mode signal S _SL is not inputted (Low state) to each block circuit BL0 to BLn, each block circuit BL0 to BLn The second data signal S _DN is set to the input state (High state). At this time, the shift register circuit 400 is released from the state set in the first shift mode.

Next, as shown in Figure 22, at time t _18, the second mode signal S _PL is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, the fifth gate potential Tr5 _GATEn of the n block circuit BL _n is shifted from the high potential state to the low potential state, the sixth gate potential Tr6 _GATEn a high potential from the low potential state of said n block circuit BL _n Transition to the state. Thus, the n-th block circuit BL _n are set from the out signal output enable state to the out signal output disabled state.

At time t ₂₁ ~t _22, the second mode signal S _PL is set to a state that is entered (High state) in each block circuit BL0 to BLn. At this time, the first data signal _SDP is set to the input state (High state). Therefore, in all the block circuit BL ₀ to BL _n, with each fifth gate potential Tr5 _GATE0 ~Tr5 _GATEn transitions from low potential to a high potential state, the respective sixth gate potential Tr6 _GATE0 ~Tr6 _GATEn high potential Transition from state to low potential state. That is, all the block circuits BL _{0 to} BL _n are set to the out signal output enabled state.

At time t ₂₃ ~t _24, first and second clock signal S _CLKE each block circuit BL0 to BLn, it is set in a state S _CLKO is input (High state). At this time, in all the block circuit BL ₀ to BL _n, the stray capacitance between the drain and the gate of the fifth transistor Tr5, the fifth gate potential Tr5 _GATE0 ~Tr5 _GATEn transitions from the high potential state to the maximum potential state . Further, at this time, the first or second clock signal S _CLKE from the block circuit BL ₀ to BL _n, the first 0~n out signal S _OUT0 to S _OUTn corresponding to S _CLKO are output.

At time t _25, together with the first data signal S _DP in each block circuit BL0~BLn is set to a state not input (Low state), the second data signal S _DN and each block circuit BL0~BLn The second mode signal _SPL is set to a state where it is input (High state). At this time, in all the block circuit BL ₀ to BL _n, together with the fifth gate potential Tr5 _GATE0 ~Tr5 _GATEn transitions from the high potential state to a low potential state, the sixth gate potential Tr6 _GATE0 ~Tr6 _GATEn low potential state Transition to high potential state. That is, all the block circuits BL _{0 to} BL _n are set from the out signal output enabled state to the out signal output disabled state.

As described above, in the image display device 1 according to the embodiment of the present invention, in each of the block circuits BL _{0 to} BL _n , the second electrode E2 of the first transistor Tr1, the ninth electrode E9 of the third transistor Tr3, and The tenth electrode E10 of the fourth transistor Tr4 is electrically connected to each other, and the fifth electrode E5 of the second transistor Tr2, the seventh electrode E7 of the third transistor Tr3, and the twelfth electrode E12 of the fourth transistor Tr4 are connected. Each is electrically connected. Further, a set signal applying terminal portion T _SET for applying a set signal S _SET to the third electrode E3 of the first transistor Tr1 and the sixth electrode E6 of the second transistor Tr2, and a first electrode E1 of the first transistor Tr1 a first terminal portion T ₁ of imparting data signal S _DP, a second terminal portion T ₂ to impart a second data signal S _DN are provided on the fourth electrode E4 of the second transistor Tr2.

Then, a set signal when the S _SET is applied to the third and sixth electrode E3, E6 has a grant of the first data signal S _DP from the first terminal portion T ₁ for the first electrode E1, the second terminal Granting and the second data signal S _DN is not performed simultaneously with respect to the fourth electrode E4 from part T _2. As a result, the generation of current from the first terminal portion T ₁ via the first and fourth transistors Tr1 and Tr4 and the generation of current from the second terminal portion T ₂ via the second and third transistors Tr2 and Tr3 The potential state between the first transistor Tr1 and the fourth transistor Tr4 and the potential state between the second transistor Tr2 and the third transistor Tr3 can be switched alternately. Therefore, the potential between the two n-type transistors can be switched while suppressing an increase in power consumption.

The state shift register circuit 400 when set in the first shift mode, in each circuit block BL ₀ to BL _n, the set signal S _SET is applied to the third and sixth electrode E3, E6 in the ninth from the first terminal portion T ₁ via the first transistors Tr1, by 10, and 15 electrode E9, E10, the first data signal S _DP against E15 is applied, the third transistor Tr3 is set to a conductive state, and the fourth transistor Tr4 is set to a non-conductive state. At this time, the fifth transistor Tr5 is set in a conductive state, and the sixth transistor Tr6 is set in a non-conductive state. That is, the out signal output permission state is set. As a result, out signals S _OUT corresponding to the first and second clock signals S _CLKE and S _CLKO are output from the block circuits BL _{0 to} BL _n . Therefore, it is possible to control the output of the out signal S _OUT corresponding to the first and second clock signals S _CLKE and S _CLKO in the _{0th to n-th} block circuits BL _{0 to} BL _n .

Further, in each of the block circuits BL _{0 to} BL _n , the nineteenth electrode E19 of the seventh transistor Tr7 is electrically connected to the third terminal portion T ₃ set to the same potential as the second terminal portion T _2. The twentieth electrode E20 of the seventh transistor Tr7 is electrically connected to the ninth and tenth electrodes E9, E10. In addition, the 22 electrode E22 of the eighth transistor Tr8 is, is electrically connected to the fourth terminal portions T ₄ is set to the first terminal portion T ₁ have the same potential, the eighth transistor Tr8 23 electrodes E23 Are electrically connected to the seventh and twelfth electrodes E7, E12. Further, a reset signal applying terminal portion T _RESET for applying a reset signal S _RESET to the 21st electrode E21 of the seventh transistor Tr7 and the 24th electrode E24 of the eighth transistor Tr8 is provided.

In such a configuration, for the third and sixth electrode E3, and application of the set signal S _SET for E6, 21 and 24 electrodes from the reset signal applied terminal portion T _RESET E21, E24 from the set signal applying terminal unit T _SET The reset signal S _RESET is sequentially applied. Then, in a state where the reset signal S _RESET is applied to the 21st and 24th electrodes E21, E24 from the reset signal applying terminal portion T _RESET , the fourth terminal portion T ₄ through the eighth transistor Tr8 is used. against 12 electrodes E12 by the first data signal S _DP is applied, is set in a state where the fourth transistor Tr4 is set to the conductive state (second setting state). Therefore, the block circuits BL _{0 to} BL _n are sequentially switched between the first setting state and the second setting state without changing the potentials at the first and second terminal portions T ₁ and T ₂ , that is, out. It is possible to sequentially switch between a signal output permission state and an out signal output prohibition state.

In the shift register circuit 400 according to the embodiment of the present invention, the first and fourth terminal portions T ₁ and T ₄ of the block circuits BL _{0 to} BL _n are commonly used for the first signal line L _DP . The second and third terminal portions T ₂ and T _{3 of} the respective block circuits BL _{0 to} BL _n are electrically connected to the second signal line L _{DN in} common. Further, among the sequentially arrayed plurality of block circuit BL ₀ to BL _n, odd-numbered blocks circuits _{BL 0, BL 2, BL 4} , ···, BL n-1 of the clock signal input terminal unit T _{IN Are} electrically connected to the first clock signal line L _CLKE . Also, among the plurality of block circuits BL _{0 to} BL _n , the clock signal input terminal portion T _IN of each even-numbered block circuit BL ₁ , BL ₃ , BL ₅ ,..., BL _n is connected to the second clock signal line. L _{CLKO is} electrically connected to each. Further, the reset signal applying terminal portion T _{RESET of} the 0th block circuit BL ₀ arranged on the most end side is electrically connected to the out signal output terminal portion T _{OUT of} the first block circuit BL ₁ arranged next. Connected. Further, the set signal giving terminal portion T _{SET of} the n-th block circuit BL _n arranged at the most other end side is the out signal output terminal portion T of the _n−1-th block circuit BL _n−1 arranged before. Electrically connected to _OUT . Further, in each of the first to n-1 block circuits BL _{1 to} BL _n-1 excluding the block circuits BL ₀ and BL _n at both ends of the plurality of block circuits BL _{0 to} BL _n , each set signal giving terminal portion T is provided. _SET is electrically connected to the out signal output terminal T _{OUT of} each of the block circuits BL _{0 to} BL _n-2 arranged in front of each of the block circuits BL _{1 to} BL _n−1 , and each reset The signal giving terminal portion T _RESET is electrically connected to the out signal output terminal portion T _{OUT of} each block circuit BL _{2 to} BL _n arranged next to each block circuit BL _{1 to} BL _n−1. Yes.

In such a configuration, the first data signal _SDP is applied to each first electrode E1 and each twenty-second electrode E22, and the second data signal _SDN is applied to each fourth electrode E4 and each nineteenth electrode E19. The first and second clocks from the first and second clock signal lines L _CLKE and L _CLKO after the set signal S _SET is input to the zeroth block circuit BL ₀ on one end side without being applied to the first block. By alternately supplying the signals S _CLKE and S _CLKO to the respective block circuits BL _{0 to} BL _n , from the 0th block circuit BL ₀ on one end side to the nth block circuit BL _n on the other end side, The block circuits set in the first setting state, that is, the out signal output permission state, are sequentially shifted. Therefore, in the shift register circuit 400, the function of the shift register can be realized while suppressing an increase in power consumption.

  In general, when a TFT is composed of amorphous silicon, CMOS (Complementary Metal Oxide Semiconductor) is difficult to manufacture due to low carrier mobility in amorphous silicon, so-called NMOS (negative channel Metal Oxide Semiconductor) It is necessary to use TFTs that are constructed. A shift register circuit in which the set signal from the previous stage is sequentially transmitted to the subsequent stage tends to attenuate each time the set signal from the previous stage is transmitted to the subsequent stage. In particular, with the demand for higher definition of the image sensor and the display element, the number of stages of the shift register circuit increases, and the set signal is significantly attenuated in the rear stage.

  The shift register circuit 400 according to this embodiment supplies a data signal from the outside in order to sequentially shift the set signal even when the TFT is made of amorphous silicon, and charges are internally generated by the supply of the data signal. Is stored and the TFT is turned on / off to sequentially shift the set signal. As a result, the set signal can continue to be supplied from the front stage to the rear stage with a very small attenuation tendency.

  In the Y driver circuit 4Y including the shift register circuit 400, the second electrode E2 of the first transistor Tr1, the ninth electrode E9 of the third transistor Tr3, the tenth electrode E10 of the fourth transistor Tr4, and the fifth transistor Tr5. The fifteenth electrode E15 is electrically connected via the 25th and 26th electrodes E25, E26 of the ninth transistor Tr9. Further, the twentieth electrode E20 of the seventh transistor Tr7, the ninth electrode E9, the tenth electrode E10, and the fifteenth electrode E15 are electrically connected via the 28th and 29th electrodes E28, E29 of the tenth transistor Tr10. Connected to.

Furthermore, the fifth electrode E5 of the second transistor Tr2, the seventh electrode E7 of the third transistor Tr3, the twelfth electrode E12 of the fourth transistor Tr4, and the eighteenth electrode E18 of the sixth transistor Tr6 are connected to the eleventh transistor Tr11. The thirty-first and thirty-second electrodes E31 and E32 are electrically connected. In addition, the 23rd electrode E23 of the eighth transistor Tr8, the seventh electrode E7, the twelfth electrode E12, and the eighteenth electrode E18 are electrically connected via the 31st and 32nd electrodes E31, E32 of the 11th transistor Tr11. Connected to. In addition, the 37 electrode E37 of the thirteenth transistor Tr13 is electrically connected to the first signal line L _DP, 38th electrode E38 of the thirteenth transistor Tr13 is ninth electrode E9 of the third transistor Tr3, the The tenth electrode E10 of the four transistor Tr4 and the fifteenth electrode E15 of the fifth transistor Tr5 are electrically connected. The 40th electrode E40 of the 14th transistor Tr14 is electrically connected to the second signal line L _DN , and the 41st electrode E41 of the 14th transistor Tr14 is connected to the 7th electrode E7, the 12th electrode E12, and It is electrically connected to the 18th electrode E18. The first mode signal line _LSL is connected to the 27th, 30th, 33rd, and 36th electrodes E27, E30, E33, E36, and the second mode is connected to the 39th and 42nd electrodes E39, E42. Mode signal line _LPL is connected.

In such a configuration, each of the block circuits BL _{0 to} BL _n is determined depending on whether or not the first mode signal S _SL is applied to the 27th, 30th, 33rd, and 36th electrodes E27, E30, E33, E36. The ninth to twelfth transistors Tr9 to Tr12 are alternately set to a conductive state and the ninth to twelfth transistors Tr9 to Tr12 are respectively set to a nonconductive state. Therefore, in the Y driver circuit 4Y, the function of the shift register and the function of simultaneously outputting the out signal S _OUT from the _{0th to n-th} block circuits BL _{0 to} BL _n are realized. Further, even when the out signal S _OUT is simultaneously output from the _{0th to n-th} block circuits BL _{0 to} BL _n , the generation of the through current is suppressed. Therefore, in the Y driver circuit 4Y including the block circuits BL _{0 to} BL _n applied to an image display device of a method in which a plurality of pixel circuits 31 are simultaneously turned on like the image display device 1 according to the embodiment of the present invention. Even when n-type transistors are used, an increase in power consumption can be suppressed.

As described above, in each of the block circuits BL _{0 to} BL _{n according to the} embodiment of the present invention, generation of a through current is suppressed in the electric circuit. Also in the shift register circuit 400, the Y driver circuit 4Y, and the image display device 1 including the block circuits BL _{0 to} BL _n , the generation of through current is suppressed in the electric circuit. As a result, by suppressing the generation of the through current, power consumption can be reduced in each of the block circuits BL _{0 to} BL _n , the shift register circuit 400, the Y driver circuit 4Y, and the image display device 1. In particular, when an n-type transistor using amorphous silicon is employed, in an electric circuit, for example, power consumption can be reduced by about 60% compared to the related art.

<Modification>
The present invention is not limited to the above-described embodiments, and various changes and improvements can be made without departing from the scope of the present invention.

For example, in the shift register circuit 400 according to the above-described embodiment, in the first and second shift modes, the block circuits BL _{0 to} BL _n have the configuration of the block circuit BL _Y shown in FIG. The function of the shift register is realized by setting, but the present invention is not limited to this. For example, the function of the shift register may be realized by setting each of the block circuits BL _{0 to} BL _{n to} have the configuration of the block circuit BL _Z shown in FIG.

  In the above embodiment, the image display device 1 is an organic EL device using light emission of an organic EL element. However, the present invention is not limited to this. For example, the image display apparatus etc. which employ | adopted the light emitting diode (LED) comprised with the inorganic material as a light emitting element may be sufficient.

  In the above embodiment, the Y driver circuit 4Y applied to the image display device 1 has been described as an example, but the present invention is not limited to this. For example, the configuration of the Y driver circuit 4Y according to the embodiment of the present invention may be applied to various driver circuits.

In the above embodiment, the shift register circuit 400 applied to the Y driver circuit 4Y has been described as an example. However, the present invention is not limited to this. For example, the configuration of the shift register circuit 400 according to an embodiment of the present invention may be applied to various shift register circuits. That is, the block circuit BL _Y shown in FIG. 12 can be applied not only to the Y driver circuit 4Y or the shift register circuit 400 but also to various driver circuits or various shift register circuits.

In the above embodiment, the configuration of each of the block circuits BL _{0 to} BL _n applied to the shift register circuit 400 has been described, but the present invention is not limited to this. For example, the configuration of each of the block circuits BL _{0 to} BL _n according to an embodiment of the present invention is such that the potential between two n-type transistors that are electrically connected in series depends on the conduction state of the two transistors. You may apply to the various electric circuits to switch.

It is a figure which shows the functional structure of the image display apparatus which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the pixel circuit for 1 pixel which comprises the image display apparatus which concerns on one Embodiment of this invention. It is a figure which shows typically the parasitic capacitance which generate | occur | produces in a pixel circuit. It is a timing chart which shows the drive waveform of an organic EL display part. It is a figure which illustrates the flow of the electric current in the pixel circuit in a Cs initialization period. It is a figure which illustrates the flow of the electric current in the pixel circuit in a preparation period. It is a figure which illustrates the flow of the electric current in the pixel circuit in a Vth compensation period. It is a figure which illustrates the flow of the electric current in the pixel circuit in the writing period. It is a figure which illustrates the flow of the electric current in the pixel circuit in the light emission period. It is a figure for demonstrating one method of suppressing a through-current in a shift register circuit. It is a figure which shows the NOT circuit using NMOS. It is a figure for demonstrating the principle which suppresses a through current. It is a figure for demonstrating the principle which suppresses a through current. It is a schematic diagram which shows the structure of the shift register circuit applied to Y driver. It is a circuit diagram of an odd-numbered block circuit constituting a shift register circuit. It is a circuit diagram of an even-numbered block circuit constituting a shift register circuit. It is a figure which shows operation | movement of the shift register circuit which concerns on 1st shift mode. It is a figure which shows operation | movement of the shift register circuit which concerns on 2nd shift mode. It is a figure which shows operation | movement of the shift register circuit which concerns on simultaneous output mode. 6 is a timing chart relating to the operation of the shift register circuit. 6 is a timing chart relating to the operation of the shift register circuit. 6 is a timing chart relating to the operation of the shift register circuit. It is a figure which shows the structure for 1 step | paragraph of the shift register which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image display apparatus 2 Control part 3 Organic EL display part 4X X driver circuit 4Y Y driver circuit 11 Organic EL element 31 Pixel circuit 400 Shift register circuit BL0-BLn _{0th- n} block circuit E1-E42 1-42 electrode L _CLKE first clock signal line L _CLKO second clock signal line L _DN second signal line L _DP first signal line L _PL second mode signal line L _SL first mode signal line L _VL low potential line Tr1 to Tr14 first -14 transistor T ₁ through T ₁₂ second 12 terminal portions T _IN a clock signal input terminal unit T _L1 through T _L3 first to third low-potential connection terminal portions T _oUT-out signal output terminal portion T _rESET reset signal applying terminal unit T _SET set signal application terminal

Claims (10)

A set signal applying unit that applies a set signal to the gate electrodes of both the first transistor and the second transistor, and sets the first transistor and the second transistor in a conductive state in which a current can flow;
A first signal applying unit for supplying a first signal to the first transistor in a state where a current can flow to the first transistor;
A second signal applying unit for supplying a second signal to the second transistor in a state where a current can flow to the second transistor;
In a state where the set signal is applied, a first signal state in which the first signal flows and an output signal is output and a second signal state in which the second signal does not flow and the output signal is not output are sequentially A control unit for switching to,
An electrical circuit comprising: A first transistor having first, second, and third electrodes, wherein a current between the first electrode and the second electrode is adjusted in response to application of a potential to the third electrode;
A second transistor having fourth, fifth, and sixth electrodes, wherein a current between the fourth electrode and the fifth electrode is adjusted in response to application of a potential to the sixth electrode;
A third transistor having seventh, eighth, and ninth electrodes, wherein a current between the seventh electrode and the eighth electrode is adjusted in response to application of a potential to the ninth electrode;
A fourth transistor having tenth, eleventh and twelfth electrodes, wherein a current between the tenth electrode and the eleventh electrode is adjusted in response to application of a potential to the twelfth electrode;
By applying a set signal to the third and sixth electrodes, the first transistor is set to a conductive state in which a current can flow between the first electrode and the second electrode, and the first transistor A set signal applying unit that sets two transistors in a conductive state in which a current can flow between the fourth electrode and the fifth electrode;
A first signal applying unit that applies a first signal to the first electrode;
A second signal applying unit that applies a second signal to the fourth electrode;
With
The second electrode is electrically connected to the ninth and tenth electrodes;
The fifth electrode is electrically connected to the seventh and twelfth electrodes;
In the state where the set signal is applied to the third and sixth electrodes, the first signal is applied to the ninth electrode, so that the third transistor is connected to the seventh electrode. When the second signal is applied to the first setting state that is set to a conduction state in which a current can flow between the eighth electrode and the twelfth electrode, the fourth transistor is An electric circuit, wherein the electric circuit is sequentially set to a second setting state set to a conductive state in which a current can flow between the tenth electrode and the eleventh electrode. An electrical circuit according to claim 2,
A fifth transistor having thirteenth, fourteenth and fifteenth electrodes, wherein a current between the thirteenth electrode and the fourteenth electrode is adjusted in response to application of a potential to the fifteenth electrode;
A sixth transistor having sixteenth, seventeenth and eighteenth electrodes, wherein a current between the sixteenth electrode and the seventeenth electrode is adjusted in response to application of a potential to the eighteenth electrode;
An input signal applying unit for applying an input signal to the thirteenth electrode;
A signal output unit that is electrically connected to a wiring that electrically connects the fourteenth electrode and the sixteenth electrode, and that outputs an output signal;
Further comprising
The fifteenth electrode is electrically connected to the second, ninth and tenth electrodes;
The electric circuit, wherein the eighteenth electrode is electrically connected to the fifth, seventh, and twelfth electrodes. An electrical circuit according to claim 2 or claim 3, wherein
A seventh transistor having nineteenth, twentieth and twenty-first electrodes, wherein a current between the nineteenth electrode and the twentieth electrode is adjusted in response to application of a potential to the twenty-first electrode;
An eighth transistor having twenty-second, twenty-third, and twenty-fourth electrodes, wherein a current between the twenty-second electrode and the twenty-third electrode is adjusted in response to application of a potential to the twenty-fourth electrode;
A reset signal applying unit that applies a reset signal to the twenty-first and twenty-fourth electrodes;
Further comprising
The nineteenth electrode is electrically connected to a third signal applying unit set to the same potential as the second signal applying unit;
The twentieth electrode is electrically connected to the ninth and tenth electrodes;
The twenty-second electrode is electrically connected to a fourth signal applying unit set to the same potential as the first signal applying unit;
The twenty-third electrode is electrically connected to the seventh and twelfth electrodes;
Application of the set signal to the third and sixth electrodes from the set signal application unit, and application of the reset signal to the 21st and 24th electrodes from the reset signal application unit are sequentially performed,
In a state where the reset signal is applied to the twenty-first and twenty-fourth electrodes from the reset signal applying unit, the fourth signal applying unit to the twelfth electrode via the eighth transistor. The electric circuit according to claim 1, wherein the fourth signal is set to the second setting state in which the fourth transistor is set to the conductive state when the first signal is applied. A plurality of electrical circuits according to claim 4;
First and second input signal lines;
A first signal line that electrically connects each of the first and fourth signal applying units of the plurality of electric circuits, and applies the first signal to the first and fourth signal applying units;
A second signal line that electrically connects each of the second and third signal applying units of the plurality of electric circuits and applies the second signal to the second and third signal applying units;
With
The plurality of electric circuits are sequentially arranged;
The input signal applying units of the electric circuits arranged in odd numbers among the plurality of electric circuits are electrically connected to the first input signal lines, respectively.
The input signal applying units of the electric circuits arranged in even-numbered electric circuits among the plurality of electric circuits are electrically connected to the second input signal lines, respectively.
The signal output unit of the electric circuit in which the reset signal applying unit of the electric circuit arranged at one end of the plurality of electric circuits is arranged next to the electric circuit arranged at the one end Electrically connected to
The signal of the electric circuit in which the set signal providing unit of the electric circuit arranged at the other end of the plurality of electric circuits is arranged before the electric circuit arranged at the other end Electrically connected to the output,
In each of the electric circuits excluding the electric circuit arranged at the one end and the other end of the plurality of electric circuits, the signal output of the electric circuit in which the set signal applying unit is arranged in front of each other A shift register circuit, wherein the shift register circuit is electrically connected to a signal output section of the electrical circuit in which the reset signal applying section is arranged next. A shift register circuit according to claim 5,
In a state where the first signal is applied to each of the first electrode and the 22nd electrode, and the second signal is not applied to each of the fourth electrode and each of the 19th electrode, After the set signal is applied to the set signal applying unit of the electric circuit arranged at one end, the input signal is applied to each electric circuit by the first input signal line, and the second input signal line The shift register circuit is characterized in that the application of the input signal to each of the electrical circuits is alternately performed. A shift register circuit according to claim 5 or 6,
First and second mode signal lines;
Further comprising
Each said electrical circuit is
A ninth transistor having twenty-fifth, twenty-sixth and twenty-seventh electrodes, wherein the current between the twenty-fifth electrode and the twenty-sixth electrode is adjusted in response to the application of a potential to the twenty-seventh electrode;
A tenth transistor having 28th, 29th, and 30th electrodes, wherein a current between the 28th electrode and the 29th electrode is adjusted according to application of a potential to the 30th electrode;
An eleventh transistor having thirty-first, thirty-second, and thirty-third electrodes, wherein a current between the thirty-first electrode and the thirty-second electrode is adjusted in response to application of a potential to the thirty-third electrode;
A twelfth transistor having thirty-fourth, thirty-fifth and thirty-sixth electrodes, wherein a current between the thirty-fourth electrode and the thirty-fifth electrode is adjusted in response to application of a potential to the thirty-sixth electrode;
A thirteenth transistor having thirty-seventh, thirty-eighth and thirty-ninth electrodes, wherein a current between the thirty-seventh electrode and the thirty-eighth electrode is adjusted in response to application of a potential to the thirty-ninth electrode;
A fourteenth transistor having forty, forty and forty-second electrodes, wherein a current between the forty and forty-first electrodes is adjusted in response to application of a potential to the forty-second electrode;
Further comprising
In each said electrical circuit,
The second electrode and the ninth, tenth, and fifteenth electrodes are electrically connected via the twenty-fifth and twenty-sixth electrodes;
The twentieth electrode and the ninth, tenth and fifteenth electrodes are electrically connected via the 28th and 29th electrodes;
The fifth electrode and the seventh, twelfth, and eighteenth electrodes are electrically connected via the thirty-first and thirty-second electrodes;
The twenty-third electrode and the seventh, twelfth, and eighteenth electrodes are electrically connected via the thirty-fourth and thirty-fifth electrodes;
The 37th electrode is electrically connected to the first signal line;
The thirty-eighth electrode is electrically connected to the ninth, tenth and fifteenth electrodes;
The 40th electrode is electrically connected to the second signal line;
The forty-first electrode is electrically connected to the seventh, twelfth and eighteenth electrodes;
The first mode signal line is electrically connected to the 27th, 30th, 33rd and 36th electrodes;
The driver circuit, wherein the second mode signal line is electrically connected to the 39th and 42nd electrodes. The driver circuit according to claim 7,
The first mode signal line applies a first mode signal to the 27th, 30th, 33rd, and 36th electrodes, respectively, so that the ninth transistor is connected to the 25th electrode and the 25th electrode. A conductive state in which a current can flow between the 26th electrode, the tenth transistor, a conductive state in which a current can flow between the 28th electrode and the 29th electrode, and the eleventh transistor with the 31st electrode. A conduction state in which a current can flow between the thirty-second electrode and the twelfth transistor are set in a conduction state in which a current can flow between the thirty-fourth electrode and the thirty-fifth electrode,
The second mode signal line applies a second mode signal to the 39th and 42nd electrodes, respectively, so that the thirteenth transistor has a current between the 37th electrode and the 38th electrode. Each of the fourteenth transistors is set to a conductive state in which a current can flow between the 40th electrode and the 41st electrode,
The first mode signal line alternately alternates between a state in which the first mode signal is applied to each electric circuit and a state in which the first mode signal is not applied to each electric circuit. A driver circuit characterized by being set. A driver circuit according to claim 7 or claim 8,
A display unit in which a plurality of pixel lines each configured by arranging a plurality of pixel circuits in one direction are arranged in another direction different from the one direction;
With
The output terminal of each of the electric circuits outputs the output signal to each of the plurality of pixel circuits included in the corresponding pixel line among the plurality of pixel lines. . A shift register circuit according to claim 5 or 6,
Each of the first to eighth transistors included in the electric circuit is an n-type transistor.

Images