JP2010130237A - Defect correcting circuit and imaging device with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a defect correcting circuit which does not require a buffer for temporary holding when perpendicularly contiguous pixels of the same color are additively read out, and to provide an imaging device with the defect correcting circuit. <P>SOLUTION: The detect correcting circuit includes: a storage unit for storing the address of a defective pixel of a solid-state imaging element; and a defective pixel correction unit which compares the address of the defective pixel with the address of a pixel corresponding to a pixel signal read out of the solid-state imaging element and corrects the pixel signal that a pixel having the matching address outputs. The solid-state imaging element is enabled to perform addition output with perpendicularly contiguous (k) pixels of the same color, and the storage unit is provided with (k) storage elements 35-1 to 35-k for storing addresses of the defective pixels corresponding to the (k) pixels of the same color. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a defect correction circuit that corrects a pixel signal output from a defective pixel of a solid-state imaging device, and an imaging apparatus including the defect correction circuit.

  2. Description of the Related Art In recent years, imaging apparatuses that can capture and store an image using an imaging element, such as a digital still camera and a digital video camera, have been widely used. As an image pickup element used in such an image pickup apparatus, a CCD type solid-state image pickup element or a CMOS type solid-state image pickup element made of a semiconductor is used.

  In these solid-state image sensors, the resolution has been increased in recent years, and therefore the solid-state image sensor has taken a long time to read all the pixels. This means that the readout frame rate becomes slow.

Therefore, in an imaging device such as a digital still camera, when high resolution is not necessary for applications such as for moving pictures and viewfinders, the frame rate is increased by shortening the readout time by adding and reading out pixels. (For example, refer to Patent Document 1).
JP 2007-150448 A

  However, when pixels of the same color adjacent in the vertical direction are added and read from the solid-state imaging device, it may be necessary to read the pixel signals from the pixels in a different order than when reading all the pixels.

  For example, in the case of the total addition readout in the vertical direction shown in FIG. 32, a horizontal line (second horizontal line) in which a defective pixel exists between the horizontal lines to be added (for example, the first horizontal line and the third horizontal line). Suppose there is. At this time, as shown in FIG. 33, it is necessary to read the defective address first from the memory 101 and temporarily hold it on the circuit.

  Further, in the two-dimensional arrangement order, the defective address on the side of the horizontal line (for example, the third horizontal line when adding between the first horizontal line and the third horizontal line) on which the pixel to be added later read is also stored in the memory 101 in advance. It is necessary to pre-read from and temporarily hold it on the circuit. Then, it becomes necessary to refer at the same timing as that read out earlier in the two-dimensional array order.

  When the pixels of the same color adjacent in the vertical direction are added and read in this way, a buffer for temporarily holding a defective address is required, so that the circuit scale increases and the access control to the memory 101 becomes complicated. There is a problem.

  Therefore, an object of the present invention is to provide a defect correction circuit that does not need a buffer that temporarily holds when pixels of the same color adjacent in the vertical direction are added and read out, and an imaging apparatus including the defect correction circuit.

  In order to achieve such an object, the invention described in claim 1 includes a storage unit that stores an address of a defective pixel of a solid-state image sensor, a pixel address corresponding to a pixel signal read from the solid-state image sensor, and a defective pixel. A defective pixel correction unit that compares addresses and corrects a pixel signal output by a pixel with a matching address, the solid-state imaging device can perform addition output with the same color k pixels in the vertical direction, and the storage unit A defect correction circuit having k storage elements for storing addresses of defective pixels corresponding to the k pixels of the same color is used.

  According to a second aspect of the present invention, in the defect correction circuit according to the first aspect, the solid-state imaging device thins out a plurality of pixels in a horizontal direction or a vertical direction and outputs pixel signals from some pixels. The defective pixel correction unit compares the address of the pixel corresponding to the pixel signal read from the solid-state image sensor and the address of the defective pixel, and if they do not match, the defective pixel is read from the solid-state image sensor. The pixel signal output from the pixel corresponding to the address of the defective pixel is not corrected, and the storage area of the storage unit is divided by a reference point of a certain section, By periodically comparing the address of the defective pixel at the reference point with the address of the pixel to be read out, the defective addresses stored in the storage unit are not sequentially read out, It was decided to skip.

  According to a third aspect of the present invention, in the defect correction circuit according to the first or second aspect, the defective pixel correction unit includes defective pixels of the same color on the basis of a read pixel array from the solid-state imaging device. A determination unit configured to determine whether the pixel is continuous; and a pixel signal output by a defective pixel continuous by the determination unit is a pixel that is not a defect and is adjacent to the continuous defective pixel. And correction means for correcting using the average value of the signal levels of the same color pixels.

  According to a fourth aspect of the present invention, in the defect correction circuit according to the third aspect, the correction means outputs a pixel signal output from a defective pixel determined not to be continuous by the determination means as a defect. Correction is performed using an average value of signal levels of at least two adjacent pixels of the same color adjacent to the defective pixel.

  According to a fifth aspect of the present invention, in the defect correction circuit according to the third or fourth aspect, the determination unit is configured to detect the defect from the solid-state imaging device based on an address of the defective pixel stored in the storage unit. When the pixel corresponding to the pixel signal to be read is a defective pixel, the first signal is output to the correcting unit, and when the pixel is not a defective pixel, the defective pixel of the same color is not continuous with the unit outputting the second signal to the correcting unit. And a means for outputting a first flag to the correcting means and outputting a second flag to the correcting means when defective pixels of the same color are continuous, the correcting means comprising the first signal And the first flag is input, the pixel signal output from the solid-state imaging device is converted to a signal level of at least two adjacent same-color pixels adjacent to the pixel corresponding to the pixel signal. flat When the first signal is input and the second flag is input, the pixel signal read out from the solid-state imaging device is corrected using a value, and the defective pixels including pixels corresponding to the pixel signal Correction was made using an average value of signal levels of at least two adjacent same-color pixels of the same color adjacent to the group.

  The invention according to claim 6 has a solid-state imaging device and a storage unit that stores an address of a defective pixel of the solid-state imaging device, and a pixel address and a defect corresponding to a pixel signal read from the solid-state imaging device. A defective pixel correction unit that compares pixel addresses and corrects a pixel signal output by a pixel with a matching address, and the solid-state imaging device can perform addition output with k pixels of the same color in the vertical direction, and the storage unit The imaging apparatus is provided with k storage elements for storing the addresses of defective pixels corresponding to the k pixels of the same color.

  According to the present invention, it is possible to provide a defect correction circuit that does not need a buffer that temporarily holds when pixels of the same color adjacent in the vertical direction are added and read, and an imaging apparatus including the defect correction circuit.

The best mode for carrying out the invention (hereinafter referred to as “embodiment”) will be described below. The description will be given in the following order.
1. 1. Overall configuration of imaging apparatus 2. Configuration of solid-state image sensor Reading process of pixel signal from solid-state image sensor 4. Defect detection process and defect correction process

[1. Overall configuration of imaging apparatus]
First, the configuration of the imaging apparatus in the present embodiment will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an imaging apparatus according to the present embodiment.

  As shown in FIG. 1, the imaging device 1 includes a solid-state imaging device 10, an A / D (analog / digital) conversion circuit 11, a signal processing circuit 12, a system controller 13, an input unit 14, and an optical block 15. . Further, the imaging apparatus 1 is provided with a driver 16 for driving a mechanism in the optical block 15, a timing generator (TG) 17 for driving the solid-state imaging device 10, and the like.

  The optical block 15 includes a lens for condensing light from the subject onto the solid-state imaging device 10, a drive mechanism for moving the lens to perform focusing and zooming, a mechanical shutter, a diaphragm, and the like. The driver 16 controls driving of the mechanism in the optical block 15 according to a control signal from the system controller 13.

  The solid-state imaging device 10 is driven based on the timing signal output from the TG 17 and converts incident light from the subject into an electrical signal. The TG 17 outputs a timing signal under the control of the system controller 13.

  The A / D conversion circuit 11 performs A / D conversion on the image signal output from the solid-state imaging device 10 and outputs a digital image signal. The image signal is composed of pixel signals output from each pixel of the solid-state imaging device 10.

  The signal processing circuit 12 performs various camera signals such as AF (Auto Focus), AE (Auto Exposure), defective pixel detection processing and correction processing, white balance adjustment, and matrix processing on the digital image signal from the A / D conversion circuit 11. Execute the process.

  The system controller 13 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The CPU executes the program stored in the ROM, thereby controlling each part of the image pickup apparatus 1 and executing various calculations for the control. The input unit 14 includes operation keys, dials, levers, and the like that receive user operation inputs, and outputs a control signal corresponding to the operation inputs to the system controller 13.

  In this imaging device 1, pixel signals received and photoelectrically converted by the respective light receiving elements of the solid-state imaging device 10 are sequentially supplied to the A / D conversion circuit 11 and converted into digital signals, and defect correction is performed by the signal processing circuit 12. Processing and the like are performed and output as image data.

  The image data output from the signal processing circuit 12 is supplied to a graphic interface circuit (not shown) and converted into a display image signal, whereby a camera-through image is displayed on a monitor (not shown). When the system controller 13 is instructed to record an image by a user input operation to the input unit 14 or the like, the image data from the signal processing circuit 12 is supplied to a CODEC (enCOder, DEcoder) and compressed and encoded. The processing is performed and recorded on the recording medium. When recording a still image, image data for one frame is supplied from the signal processing circuit 12 to the CODEC, and when recording a moving image, the processed image data is continuously supplied to the CODEC. .

[2. Configuration of solid-state image sensor]
Next, the configuration of the solid-state imaging device 10 in the present embodiment will be described with reference to the drawings. FIG. 2 is a diagram illustrating a configuration of the solid-state image sensor 10, and FIG. 3 is an explanatory diagram of a pixel arrangement of the solid-state image sensor 10. In this embodiment, for convenience of explanation, the number of pixels is several tens. However, in reality, hundreds to thousands of pixels are arranged in the horizontal direction (H direction) and the vertical direction (V direction). The

  As shown in FIG. 2, the solid-state imaging device 10 includes an imaging region 22, a constant current unit 23, a column signal processing unit 24, a vertical selection unit 25, a horizontal selection unit 26, a horizontal signal line 27, and an output process on a semiconductor substrate 21. A unit 28, a timing generator (TG) 29, and the like are provided.

  The imaging region 22 includes a large number of pixels 22a (see FIG. 3) having light receiving elements, and a pixel signal corresponding to the amount of received light is generated in each pixel 22a. The pixel signal of each pixel 22a is output to the column signal processing unit 24 through a vertical signal line (not shown) for each pixel column. In the constant current section 23, a constant current source (not shown) for supplying a bias current to each pixel 22a is arranged for each pixel column. The vertical selection means 25 selects each pixel 22a in the imaging region 22 one row (one horizontal line) and drives and controls the reading operation of each pixel 22a.

  The column signal processing unit 24 receives pixel signals obtained through the vertical signal lines for each row (for each horizontal line), performs predetermined signal processing, and temporarily holds the signals. For example, CDS (removing fixed pattern noise caused by variations in threshold values of pixel transistors) processing, AGC (auto gain control) processing, and the like are appropriately performed.

  The horizontal selection unit 26 selects the signals of the column signal processing unit 24 one by one and guides them to the horizontal signal line 27. The output processing unit 28 performs predetermined processing on the signal from the horizontal signal line 27 and outputs the signal to the outside, and has a gain control circuit, for example. The timing generator 29 supplies various pulse signals and the like necessary for the operation of each unit based on the reference clock.

  Each pixel 22a provided in the imaging region 22 has a light receiving element such as a photodiode that generates a signal charge corresponding to the amount of received light, and has different spectral characteristics, for example, R (red), G ( Green) and B (blue) color filters are formed. Here, as shown in FIG. 3, a Bayer array is formed in which R, G, and B color filters are arranged in a ratio of 1: 2: 1. Each pixel 22a is provided with a pixel transistor (not shown), and a signal charge corresponding to the amount of light received by the light receiving element is converted into an analog electric signal of a color component corresponding to a color filter formed on the light receiving element. It converts into a signal and outputs it as an image signal of each color of R, G, B. In FIG. 3, for example, “1R1” is the first R pixel 22a of the first horizontal line (R first line), and “2Gb2” is the third of the fourth horizontal line (B second line). G pixel 22a.

[3. Reading process of pixel signal from solid-state image sensor]
Next, pixel signal readout processing from the solid-state imaging device 10 will be described with reference to the drawings. 4 to 11 are explanatory diagrams of the reading process of the pixel signal from the solid-state image sensor 10.

  The system controller 13 outputs a control signal to the solid-state image sensor 10 and reads a pixel signal from the solid-state image sensor 10. The pixel signals can be read out using “All pixel readout”, “Horizontal thinning readout”, “Horizontal addition thinning readout”, “Horizontal addition thinning readout”, “Vertical thinning readout”, “Vertical summation readout”. And “vertical addition thinning readout”. Further, there are “horizontal and vertical direction addition full readout” and “horizontal and vertical direction addition thinning readout”. The system controller 13 outputs a pixel signal from the solid-state imaging device 10 by a readout method according to the operation of the imaging device 1.

  “All-pixel readout” is a readout method for outputting pixel signals from all the pixels 22 a of the solid-state imaging device 10, and the system controller 13 sequentially outputs pixel signals from the pixels 22 a in units of horizontal lines in the same manner as other readout methods. Is output. In this readout method, the pixel 22a array on the imaging region 22 shown in FIG. 3 is used as a readout pixel array, and pixel signals are sequentially output from the pixel 22a from the first horizontal line to the final horizontal line.

  As shown in FIG. 4, “horizontal thinning readout” is a readout method in which a part of pixels 22a is thinned out and a pixel signal is output only from the remaining pixels 22a for each horizontal line. In this readout method, the array excluding a part of the pixels 22a on the imaging region 22 shown in FIG. 4 is a readout pixel array, and pixel signals are sequentially output from the pixels 22a from the first horizontal line to the final horizontal line. Here, “thinning” means not reading. The same applies to the following.

  As shown in FIG. 5, “horizontal addition total readout” is performed by outputting pixel signals from all the pixels 22 a without thinning out the pixels 22 a for each horizontal line, and between adjacent pixels 22 a in the same color and in the horizontal direction. This is a readout method in which pixel signals are added and output as a synthesized pixel signal. In this readout method, the pixel 22a array on the imaging region 22 shown in FIG. 5 (a plurality of pixels 22a of the same color and adjacent in the horizontal direction are simultaneously read) is used as the readout pixel array, and from the first horizontal line to the final horizontal line. Pixel signals are sequentially output from the pixel 22a.

  As shown in FIG. 6, “horizontal addition thinning readout” is performed by thinning out the pixels 22 a for each horizontal line to output pixel signals from some of the pixels 22 a and adding pixel signals of adjacent pixels of the same color. This is a reading method for outputting the data. In this readout method, a pixel array 22a excluding a part on the imaging region 22 shown in FIG. 6 (a plurality of pixels 22a of the same color and adjacent in the horizontal direction are read out simultaneously) is used as a readout pixel array. Then, pixel signals are sequentially output from the pixels 22a from the first horizontal line to the final horizontal line.

  As shown in FIG. 7, “vertical thinning readout” is a readout method in which the pixels 22a are thinned out in units of horizontal lines and only pixel signals are output from the pixels 22a in some horizontal lines. In this readout method, the pixel 22a array excluding a part of the horizontal lines on the imaging region 22 shown in FIG. 7 is used as a readout pixel array, and pixel signals are sequentially output from the pixels 22a on the top horizontal line.

  As shown in FIG. 8, “vertical direction addition full readout” outputs pixel signals from all the pixels 22a without thinning out the pixels 22a, and adds pixel signals of pixels of the same color and adjacent in the vertical direction. This is a readout method for outputting. In this readout method, the pixel 22a array on the imaging area 22 shown in FIG. 8 (a plurality of pixels 22a of the same color and adjacent in the vertical direction are simultaneously read) is used as the readout pixel array, and sequentially from the pixels 22a on the first horizontal line. A pixel signal is output.

  As shown in FIG. 9, “vertical addition thinning readout” is performed by thinning out pixels 22 a in units of horizontal lines to output pixel signals from some of the pixels 22 a, and pixel signals between pixels adjacent in the same color and in the vertical direction. Is a readout method of adding and outputting. In this readout method, the pixel array 22a excluding a part of the horizontal lines on the imaging region 22 shown in FIG. 9 (a plurality of pixels 22a of the same color and adjacent in the vertical direction are read out simultaneously) is used as the readout pixel array, and the top horizontal Pixel signals are sequentially output from the pixels 22a of the line.

  In addition, as shown in FIG. 10, the “horizontal / vertical direction addition full readout” outputs pixel signals from all the pixels 22a without thinning out the pixels 22a, so that the pixels of the same color and adjacent in the horizontal direction or the vertical direction can be output. This is a readout method in which pixel signals are added and output. For example, the pixel signal output from the “1Gr1” pixel 22a is a pixel of “1Gr2” that is the same color as the “1Gr1” pixel 22a and is adjacent in the horizontal direction (hereinafter referred to as “horizontal same-color adjacent pixel”). It is added to the pixel signal output from 22a. The pixel signal output from the “1Gr1” pixel 22a is a pixel of “2Gr1” that is the same color as the “1Gr1” pixel 22a and is adjacent in the vertical direction (hereinafter referred to as “vertical same-color adjacent pixel”). It is added to the pixel signal output from 22a. In this reading method, the pixel array 22a on the imaging region 22 shown in FIG. 10 (a plurality of pixels 22a of the same color and adjacent in the horizontal direction or the vertical direction are read simultaneously) is used as the read pixel array. Then, pixel signals are sequentially output from the pixels 22a on the first horizontal line.

  Further, “horizontal and vertical direction addition thinning readout” is a readout method in which the pixels 22a are thinned out for each horizontal line unit and each vertical line, and only pixel signals are output from some of the pixels 22a, as shown in FIG. In this readout method, a pixel 22a array excluding a part of horizontal lines and vertical lines on the imaging region 22 shown in FIG. 11 (a plurality of pixels 22a of the same color and adjacent in the horizontal direction or the vertical direction are read out simultaneously) is read out. It is an array. Then, pixel signals are sequentially output from the pixels 22a on the first horizontal line.

  As described above, in the imaging apparatus 1 according to the present embodiment, the pixel signal is read from the solid-state imaging device 10 in addition to “all pixel readout”, “horizontal thinning readout”, and the like (hereinafter “other than all pixel readout”). It is possible to read by the reading method of “. In “other than reading all pixels”, the time for outputting a pixel signal for one frame from the solid-state imaging device 10 can be shortened, and thereby the frame rate can be increased.

  In the imaging apparatus 1 according to the present embodiment, the reading method is switched according to the application. For example, “All-pixel readout” is a mode for obtaining an image to be originally recorded, and “All-pixel readout” is for continuously monitoring with a moving image by an electronic viewfinder to select a composition and a subject. Mode.

[4. Defect detection processing and defect correction processing]
Next, the defect detection process and the defect correction process in the imaging apparatus 1 according to the present embodiment will be described. FIG. 12 is a diagram illustrating a configuration for performing defect detection and defect correction processing in the signal processing circuit 12 of the imaging apparatus 1, and FIG. 13 is a configuration diagram of an address detector in the signal processing circuit 12.

  As shown in FIG. 12, the signal processing circuit 12 includes a first defect detection unit 31, a second defect detection unit 32, an address generator 33, an address detector 34, a volatile memory unit 35, a non-volatile memory 36, and a correction comparator. 37, a defect correction unit 38 is provided. The signal processing circuit 12 functions as a defect detection circuit and a defect correction circuit. The correction comparator 37 and the defect correction unit 38 constitute a defective pixel correction unit 39.

  In the following, first, the defect detection process is specifically described, and then the defect correction process is specifically described.

[4.1. Defect detection process]
First, the defect detection process will be specifically described with reference to the drawings.

(Overview of defect detection process)
In a solid-state imaging device such as a COMS type, defective pixels that output abnormal pixel signals are generated due to local crystal defects of semiconductors or adhesion of minute dust to the pixel surface. In such a case, it is known that the defective pixel causes the image quality to deteriorate. Therefore, conventionally, in an imaging apparatus using a solid-state image sensor, it is possible to improve image quality degradation caused by a defective pixel by detecting a defective pixel of the solid-state image sensor and correcting a pixel signal output from the defective pixel. I have to.

  In general, the detection of a defective pixel is determined by whether or not the signal level difference between the defect detection target pixel and its adjacent pixel exceeds a threshold value. When the signal level difference exceeds the threshold value, the defect detection target pixel is determined as a defective pixel. Then, an address (hereinafter referred to as “defective address”) which is the position information of the defective pixel is held in a volatile storage unit (hereinafter referred to as “volatile memory”) such as SRAM, and further, non-volatile such as EEPROM. Is stored in a storage unit (hereinafter referred to as “nonvolatile memory”). In addition, in the correction of the pixel signal output from the defective pixel, the defective address previously stored in the non-volatile memory at the start-up is expanded in the volatile memory, and the address of the pixel being read and the volatile memory Compare with defective address. If the addresses match, the pixel signal output from the defective pixel is corrected based on the average value of a plurality of pixels of the same color adjacent to the defective pixel (hereinafter referred to as “same color adjacent pixels”) (Japanese Patent Laid-Open No. 06-2006). No. -22322).

  In recent years, as the resolution and size of a solid-state image sensor increase, the pixels become finer and minute dust adheres across a plurality of pixels. This greatly reduces the yield of the solid-state image sensor. It has an influence. Therefore, not only the above-mentioned single defective pixel (single defect) but also the detection of a continuous defect extending over a plurality of pixels, that is, a case where adjacent pixels of the same color are continuously defective pixels has become important. A detection method has been proposed (see Japanese Patent Application Laid-Open No. 07-15670).

  However, in the conventional continuous defect detection, it is necessary to set a threshold value assuming that neighboring pixels are also defective, and adjustment is very difficult.

  In view of this, the imaging apparatus 1 according to the present embodiment can easily detect a single defect or a continuous defect.

  The defect detection process will be specifically described below.

  When the defect detection process is started, the system controller 13 of the imaging apparatus 1 according to the present embodiment first outputs a control signal to the solid-state imaging device 10 and reads out pixel signals from the solid-state imaging device 10 by reading all pixels. That is, the system controller 13 uses the two-dimensional arrangement order of the solid-state imaging device 10 as a readout pixel arrangement, and starts from the pixel 22a from the first pixel on the first horizontal line (pixel “1R1”) to the last pixel on the last horizontal line in the horizontal line order. A pixel signal is output.

  The pixel signal read from the solid-state imaging device 10 is converted into a digital signal by the A / D conversion circuit 11 and input to the first defect detection unit 31 and the second defect detection unit 32. Each of the defect detection units 31 and 32 compares the signal level of the input pixel signal with a reference threshold value for defect detection, and outputs a defect correction signal corresponding to the comparison result. For example, when the signal level of the input pixel signal exceeds the reference threshold and it is determined that the pixel is a defective pixel, a high-level defect correction enable signal (first signal) is generated as the defect correction signal, and the address detector 34. Output to. On the other hand, when it is determined that the signal level of the input pixel signal does not exceed the reference threshold value and is not a defective pixel, a low level defect disable signal (second signal) is generated as a defect correction signal, and the address detector 34.

  The address detector 34 receives the address generated by the address generator 33 and the defect correction signal output from each of the defect detectors 31 and 32. The address detector 34 determines that the address output from the address generator 33 when the defect correction signal is an enable signal is an address corresponding to the defective pixel, and uses this address (hereinafter referred to as “defective address”) as volatile. The data is sequentially stored in the memory unit 35. The volatile memory unit 35 is a number of storage elements corresponding to the number k of adjacent pixels of the same color in the vertical direction to be added at the time of vertical addition reading such as “vertical addition total readout” and “vertical addition thinning readout”. Volatile memories 35-1 to 35-k are included. In other words, the volatile memories 35-1 to 35 -k are memory elements for storing the addresses of defective pixels corresponding to the respective pixels of the same color k pixels adjacent in the vertical direction to be added at the time of vertical direction addition reading. It is.

  Thereafter, the defective address stored in the volatile memory unit 35 is written in the nonvolatile memory 36 inside, thereby completing a series of operations. Note that the nonvolatile memory 36 may be provided outside the signal processing circuit 12.

  Hereinafter, each of the first defect detection unit 31, the second defect detection unit 32, the address generator 33, the address detector 34, the volatile memory unit 35, the nonvolatile memory 36, the correction comparator 37, and the defect correction unit 38 will be described in detail. Explained. 14 is a diagram for explaining the detection operation of the first defect detection unit 31, FIG. 15 is a diagram for explaining the detection operation of the second defect detection unit 32, and FIG. 16 is a diagram illustrating the first defect detection unit 31 and the second defect detection unit 31. 6 is a diagram for explaining a detection operation of a defect detection unit 32. FIG. In the following description, it is assumed that a black spot defect due to dust adhering across a plurality of pixels 22a in the horizontal direction is detected. However, the present invention can also be applied to the detection of a white spot defect. Further, even when white spot defects and black spot defects are mixed, these defects can be detected.

(First defect detection unit 31)
The first defect detection unit 31 detects a defective pixel using one pixel 22a among the plurality of pixels 22a in the solid-state imaging device 10 as a defect detection target. That is, it is a defect detection unit aimed at detecting a single defect. The first defect detection unit 31 includes a pixel signal from a defect detection target pixel (hereinafter referred to as “defect detection target pixel”) and at least two or more pixels of the same color adjacent to the defect detection target pixel in the horizontal direction (hereinafter referred to as “defect detection target pixel”). The signal level difference from the pixel signal from “horizontal adjacent same color pixel” is detected. When the signal level difference exceeds the reference threshold value α, the first defect detection unit 31 determines that the defect detection target pixel is a defective pixel.

  For example, as illustrated in FIG. 14, it is assumed that “1 Gb2” and “1B3” pixels 22 a among the pixels 22 a of the second horizontal line are defective pixels. When the “1 Gb2” pixel 22 a is a defect detection target pixel, the first defect detection unit 31 starts from the “1 Gb1” and “1 Gb3” pixels 22 a that are horizontal adjacent same color pixels of the same color as the defect detection target pixel. The signal level of each output pixel signal is detected.

  Thereafter, the first defect detection unit 31 calculates the average value of the signal levels of the pixel signals output from these horizontally adjacent pixels of the same color, and calculates the average value and the signal level of the pixel signal output from the defect detection target pixel. It is determined whether the difference between the two exceeds a reference threshold value α. When the level difference exceeds the reference threshold value α, the first defect detection unit 31 determines that the defect detection target pixel is a defective pixel.

  The example illustrated in FIG. 14 illustrates a state in which the “1 Gb2” pixel 22a that is a defect detection target pixel is a defective pixel. That is, the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel (“1Gb1” and “1Gb3” pixel 22a) and the pixel signal output from the defect detection target pixel (“1Gb2” pixel 22a). This shows a state where the difference from the signal level exceeds the reference threshold value α.

  Here, “adjacent” does not mean physically adjacent to the defect detection target pixel, but is a pixel of the same color and the same horizontal line as the defect detection target pixel, It means the nearest pixel. In other words, a pixel that is physically adjacent to the defect detection target pixel when a pixel having a color different from that of the defect detection target pixel is excluded is a horizontally adjacent same color pixel.

(Second defect detection unit 32)
The second defect detection unit 32 uses the two pixels 22a adjacent in the horizontal direction of the same color among the plurality of pixels 22a of the solid-state imaging device 10 (hereinafter referred to as “defect detection target pixel group”) as a defect detection target. Pixel detection is performed. That is, it is a defect detection unit aimed at detection of two horizontal defects of the same color. The second defect detection unit 32 includes a signal level of a pixel signal from each pixel 22a of the defect detection target pixel group and pixel signals from two or more horizontally adjacent same color pixels of the same color adjacent to the defect detection target pixel group in the horizontal direction. The signal level of is detected. A defect in which the difference between the signal level of the pixel signal output from the plurality of pixels 22a in the defect detection target pixel group and the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel exceeds the reference threshold β. The pixel 22a in the detection target pixel group is determined as a defective pixel.

  For example, as illustrated in FIG. 15, when “1 Gb2” and “1 Gb3” pixels 22 a are used as the defect detection target pixels, the second defect detection unit 32 outputs the signal levels of the pixel signals output from the defect detection target pixels. Is detected. In addition, the second defect detection unit 32 detects the level of the pixel signal output from each of the “1Gb1” and “1Gb4” pixels 22a, which are adjacent pixels of the same color adjacent to the same color as the defect detection target pixel.

  Thereafter, the second defect detection unit 32 calculates an average value of the levels of the pixel signals output from these horizontally adjacent pixels of the same color, and calculates the average value and the signal level of the pixel signal output from the defect detection target pixel. It is determined whether or not the difference exceeds a reference threshold value β. Then, when the level difference exceeds the reference threshold value β, the second defect detection unit 32 determines that the defect detection target pixel is a defective pixel.

  The example illustrated in FIG. 15 illustrates a state in which the “1 Gb2” pixel 22a that is a defect detection target pixel is a defective pixel. At this time, the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel (“1Gb1” and “1Gb3” pixel 22a) and the pixel signal output from the defect detection target pixel (“1Gb2” pixel 22a) Of the signal level exceeds the reference threshold value β.

  On the other hand, the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel (“1Gb1” and “1Gb3” pixel 22a) and the pixel signal output from the defect detection target pixel (“1Gb3” pixel 22a) The difference from the signal level does not exceed the reference threshold β. Accordingly, the “1Gb2” pixel 22a among the defect detection target pixels is determined as a defective pixel, and the “1Gb3” pixel 22a among the defect detection target pixels is determined not to be a defective pixel.

  As described above, the imaging device 1 according to the embodiment includes not only the first defect detection unit 31 but also the second defect detection unit 32, and therefore detects defective pixels that cannot be detected by the first defect detection unit 31. Will be able to.

  For example, as illustrated in FIG. 16, “1 Gb2” and “1 Gb3” pixels 22 a that are defect detection target pixels are defective pixels. At this time, if the defect detection target pixel is the “1 Gb2” pixel 22a in the first defect detection unit 31, the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel and the defect detection target pixel are output. The difference from the signal level of the pixel signal does not exceed the reference threshold value α. As shown in FIG. 16, the pixel of the “1Gb3” pixel 22a is also a defective pixel, and the signal of the pixel signal output from the two horizontally adjacent pixels of the same color (“1Gb1” and “1Gb3” pixel 22a) This is because the average level is lowered.

  On the other hand, in the second defect detection unit 32, assuming that the defect detection target pixel is the “1 Gb2” and “1 Gb3” pixel 22 a, the “1 Gb2” pixel 22 a is determined as a defective pixel. This is because the difference between the average signal level of the pixel signals output from the horizontally adjacent same color pixels (the “1Gb1” and “1Gb4” pixels 22a) and the signal level of the pixel signal output from the “1Gb2” pixels is the same. This is because the reference threshold value β is exceeded. This is because, as shown in FIG. 16, the “1 Gb4” pixel 22a, which is a horizontally adjacent same color pixel, is not a defective pixel, and the average value of the signal level of the pixel signal output from the horizontally adjacent same color pixel does not decrease. .

  As described above, the second defect detection unit 32 can detect defective pixels that cannot be detected by the first defect detection unit 31. In the present embodiment, two pixels 22a of the same color adjacent in the horizontal direction among the plurality of pixels 22a of the solid-state imaging device 10 are set as the defect detection target pixel group, but n pixels (n Is an integer of 2 or more) as long as the pixel 22a is a defect detection target pixel group. In addition to the second defect detection unit 32, a third defect detection unit that performs defect detection using the three pixels 22a as a defect detection target pixel group, and performs defect detection using the four pixels 22a as a defect detection target pixel group. A fourth defect detection unit or the like may be provided.

  In addition, both the processing of the first defect detection unit 31 and the processing of the second defect detection unit 32 are the pixels from the signal level of the pixel signal of the x (x is a natural number) defect detection target pixel (group) and the horizontally adjacent same color pixel. It is the same in that a defective pixel is determined based on whether or not the difference from the average value of the signal level of the signal exceeds the reference threshold value. Therefore, it is not necessary to set a threshold value assuming that the peripheral pixels are defective as in the conventional case, and the processing is not complicated.

(Address generator 33)
The address generator 33 generates an address (position information of the pixel 22 a in the solid-state image sensor 10) of the pixel 22 a that outputs the pixel signal read from the solid-state image sensor 10. In the present embodiment, information on the horizontal position and the vertical position of the pixel 22a is used as the address of the pixel 22a. For example, in the imaging region 22 shown in FIG. 3, the pixel 22a of “2B1” is the second position from the left in the horizontal direction and the fourth position from the top in the vertical direction, and is set to the address “x2v4”.

  The address generator 33 generates an address of a pixel that has output the pixel signal output from the solid-state imaging device 10 to the signal processing circuit 12 and outputs the generated address to the address detector 34. As a result, the address of the pixel 22 a to which the detection result is output from the defect detection units 31 and 32 is output to the address detector 34.

(Address detector 34)
The address detector 34 has a select circuit 34a and an address fetch circuit 33b.

  The selection circuit 34a inputs the detection result information from the first defect detection unit 31 and the detection result information from the second defect detection unit 32, and takes in an output corresponding to the parameter set in the address detector 34. This is performed for the circuit 33b. This parameter can be changed from the system controller 13 and can be changed by an input to the input unit 14 provided in the imaging apparatus 1.

  For example, when the parameter is set to the first parameter, the select circuit 34a outputs a signal corresponding to the information of the detection result by the first defect detection unit 31 to the address capturing circuit 33b. Specifically, when the information of the detection result by the first defect detection unit 31 is information indicating a defective pixel, the select circuit 34a outputs a high-level control signal, and the detection result of the first defect detection unit 31 When the information is not information indicating a defective pixel, a low level control signal is output.

  When the parameter is set to the second parameter, the select circuit 34a outputs a signal corresponding to the information of the detection result by the second defect detector 32 to the address fetch circuit 33b. Specifically, when the information of the detection result by the second defect detection unit 32 is information indicating a defective pixel, the select circuit 34a outputs a high-level control signal, and the detection result of the second defect detection unit 32 When the information is not information indicating a defective pixel, a low level control signal is output.

  Further, when the parameter is set to the third parameter, the select circuit 34a takes in the signal corresponding to the detection result information from the first defect detection unit 31 and the detection result information from the second defect detection unit 32. Output to the circuit 33b. Specifically, when both the information on the detection result by the first defect detection unit 31 and the information on the detection result by the second defect detection unit 32 are information indicating a defective pixel, the select circuit 34a controls the high level control signal. Is output. When the information on the detection result by the first defect detection unit 31 and the information on the detection result by the second defect detection unit 32 are different, the selection circuit 34a displays information on the detection result by one of the defect detection units 31 and 32. When the information indicates a defective pixel, a high level control signal is output.

  When the parameter is set to the fourth parameter, the priority of the first defect detection unit 31 is increased, and when the parameter is set to the fifth parameter, the priority of the second defect detection unit 32 is increased. To do. The select circuit 34a outputs a signal that places importance on the detection result of the priority defect detection unit when the detection result information of the defect detection units 31 and 32 is different. That is, the defect detection units 31 and 32 output the difference from the reference threshold to the select circuit 34a. In the selection circuit 34a, the difference output from the defect detection unit with high priority is weighted heavily, the difference output from the defect detection unit with low priority is weighted down, and if the added value is positive, the pixel is a defective pixel. Determination is made and a high level control signal is output. If the added value is negative, it is determined that the pixel is not a defective pixel, and a low level control signal is output.

  As described above, either one of the first defect detection unit 31 and the second defect detection unit 32 can be selectively operated. In addition, at least one of the first defect detection unit 31 and the second defect detection unit 32 can detect a pixel determined as a defective pixel as a defective pixel. Therefore, a desired defect detection process according to the operation mode of the imaging device 1 can be performed.

  The address fetch circuit 33b receives an address from the address generator 33 and a control signal from the select circuit 34a. When the control signal output from the select circuit 34a is a high level signal, the address input from the address generator 33 is output to the volatile memory unit 35, and the address of the defective pixel is stored in the volatile memory unit 35. Store as a defective address.

(Volatile memory unit 35)
Next, the volatile memory unit 35 will be described. As described above, the volatile memory unit 35 includes a plurality of volatile memories 35-1 to 35-k. A plurality of volatile memories as storage elements are provided in this way when the method of reading pixel signals from the solid-state imaging device 10 is “vertical direction addition full readout” or “vertical direction addition thinning readout”. This is to improve the reading speed from the unit 35. Here, since “vertical direction addition full readout” and “vertical direction addition thinning readout” are performed by adding two pixels of the same color adjacent in the horizontal direction in the readout pixel array, k = 2, but the same color When adding three adjacent pixels, k = 3. Further, when four adjacent pixels of the same color are added, k = 4.

  First, the reason why the volatile memory unit 35 is configured by a plurality of volatile memories 35-1 to 35-k will be described.

  In the conventional imaging apparatus, the defect detection of the pixel 22a of the solid-state imaging device 10 is performed by reading all pixels. Accordingly, the storage method in the volatile memory unit 35 also sequentially holds the defect address from the first pixel of the first horizontal line to the final pixel of the last horizontal line.

  As described above, since defective addresses are held in order from the first pixel to the last pixel in the imaging region 22, when some pixels 22a are thinned out and read out, or the reading order of the pixels 22a is changed. It is necessary to change the order of the defective addresses to be referred to.

  However, the number of defective pixels differs for each solid-state image sensor 10. In addition, since the number is different for each horizontal line, it is difficult to instantly find where in the volatile memory unit 35 a necessary defect address is located.

  For example, when pixels of the same color adjacent in the vertical direction are added and read from the CMOS solid-state imaging device 10 (see FIGS. 8, 9, and 10), the pixel signals are output from the pixels 22a in an order different from that for reading all the pixels. May need to be read.

  For example, in the case of the total addition readout in the vertical direction shown in FIG. 17, a horizontal line (second horizontal line) where a defective pixel exists between the horizontal lines to be added (for example, the first horizontal line and the third horizontal line). Suppose there is. At this time, as shown in FIG. 18, it is necessary to read the defective address first from the volatile memory unit 35 and temporarily hold it on the circuit.

  Further, in the two-dimensional arrangement order, the defect address on the side of the horizontal line (for example, the third horizontal line when adding between the first horizontal line and the third horizontal line) where the pixel 22a to be added later read is also volatilized in advance. It is necessary to read ahead from the memory 35 and temporarily hold it on the circuit. Then, it becomes necessary to refer at the same timing as that read out earlier in the two-dimensional array order.

  In this way, when pixels of the same color adjacent in the vertical direction are added and read out, a buffer for temporarily holding a defective address is required, so that the circuit scale increases and access control to the volatile memory unit 35 is performed. There are also complicated problems.

  In view of this, the volatile memory unit 35 in the present embodiment stores the defective addresses of the pixels 22a added in the vertical direction in separate storage elements in advance for each horizontal line in order to enable various readouts from the solid-state imaging device 10. A plurality of volatile memories 35-1 to 35-k are provided so that they can be stored.

  That is, when the number of horizontal lines to be added is k, the imaging area 22 is divided into k areas in advance, and the defect addresses of the divided same areas are sequentially held in the same volatile memory. Although an example of k = 2 is shown here, the number of horizontal lines to be added may be k = 3 or k = 4.

  As a result, the defect addresses of the pixels 22a added in the vertical direction are sequentially held in the divided volatile memories 35-1 and 35-2 (see FIGS. 19 and 20). It is possible to sequentially read from the volatile memories 35-1, 35-2. Therefore, at the time of “vertical addition reading”, defective addresses are alternately read from the volatile memory 35-1 and the volatile memory 35-2 in units of horizontal lines. With this configuration, a buffer that is temporarily held at the time of defect correction is not required, and access control to the volatile memory unit 35 is facilitated.

[4.2. Defect correction process]
Next, the defect correction processing will be specifically described with reference to the drawings.

(Overview of defect correction processing)
In the conventional solid-state imaging device, the resolution has been increased in recent years. Therefore, the solid-state imaging device has taken much time to read out all the pixels. This means that the read frame rate becomes slow.

  Therefore, in an imaging device such as a digital still camera, when high resolution is not necessary for applications such as moving pictures and viewfinders, the frame rate is set by shortening the readout time by thinning out pixels or adding readout. There is a lot to do faster.

  However, when reading by thinning out or adding pixels, there is a problem that an appropriate correction process cannot be performed if the process is executed by the same algorithm as that applied when reading all the pixels.

  In view of this, Japanese Patent Application Laid-Open No. 2003-51990 proposes a technique for switching the correction method in accordance with the reading mode. Japanese Patent Application Laid-Open No. 2007-53634 proposes a technique for detecting by all-pixel reading and corresponding to the pixel arrangement at the time of correction.

  However, conventionally, a correction method must be provided corresponding to the reading mode, and further switching between them must be performed appropriately, which complicates the processing.

  Therefore, in the present embodiment, without distinguishing the readout method of a solid-state imaging device such as a CMOS type, it is locally determined whether or not defects of the same color pixel are continuous in the readout pixel array, and an appropriate defective pixel is obtained. Correction processing can be performed.

  The defect correction process will be specifically described below.

  When starting the defect correction process, the system controller 13 of the imaging apparatus 1 according to the present embodiment reads the defect address written in the nonvolatile memory 36 inside and performs the process of rewriting it in the volatile memory unit 35.

  When the defect detection processing is started, the system controller 13 first outputs a control signal to the solid-state image sensor 10 and sequentially reads pixel signals from the solid-state image sensor 10. The address generator 33 sequentially outputs the address of the pixel 22a that has output the pixel signal being read, and the correction comparator 37 outputs the address output by the address generator 33 and the defective address read by the volatile memory unit 35. And compare.

  When the address output from the address generator 33 matches the defective address read from the volatile memory unit 35, the correction comparator 37 recognizes the pixel at that address as a defect and generates a defect correction enable signal. Transition to reading the next defective address.

  The defect correction enable signal is input to the defect correction unit 38. When the defect correction enable signal is input, the defect correction unit 38 performs defect correction processing on the pixels output from the solid-state imaging device 10. In this defect correction processing, it is determined whether or not there are m consecutive pixels having the same horizontal color with reference to the readout pixel array, and correction is performed using the average value of the signal levels of two adjacent pixels of the same horizontal color that are not defective. .

  On the other hand, when the address output from the address generator 33 does not match the defective address read by the volatile memory unit 35, the address of the pixel 22a read from the solid-state imaging device 10 and the address holding of the volatile memory unit 35 are retained. The size of the defect address is compared.

When the address of the pixel 22a read out from the solid-state image sensor 10 is larger, the upper target defective address is discarded and the next defective address is read out from the storage memory.

(Defect Correction Unit 38)
As shown in FIG. 21, the defect correction unit 38 includes a determination unit 40 and a correction unit 41. The defect correcting unit 38 outputs m defective pixels (m is a natural number) that are adjacent to the read pixel array in the horizontal direction and two pixels of the same color that are adjacent in the horizontal direction (hereinafter referred to as “horizontal same color adjacent two pixels”). The pixel signal of the defective pixel is corrected using the average value of the signal level of the pixel signal to be processed.

  The discriminating means 40 has delay circuits 50 to 52, 54 and a logical product (AND) circuit 53, discriminates whether or not the horizontal same color defective pixels are continuous with reference to the readout pixel array, and flag signals {K, J} is output to the selector 69. The delay circuits 50 to 52, 54 are circuits that delay the input pixel signal by two clocks.

  The flag signal {K, J} is obtained when the pixel signal (the signal at position B in FIG. 21) output from the delay circuit 62 in the correcting means 41 is output from a defective pixel. This is a signal that instructs the selector 69 what correction signal to replace.

  When the pixel signal output from the delay circuit 62 in the correction means 41 is output from the defective pixel, is the pixel signal (the signal at position A in FIG. 21) that is input two times later output from the defective pixel? Determine whether or not. That is, when the defect correction signal (the signal at the I position in FIG. 21) output from the delay circuit 52 in the determination unit 40 is at a high level, the defect correction signal (H in FIG. 21) output from the delay circuit 51. It is determined whether the position signal is at a low level or a high level. In the following description, the high level is “H” and the low level is “L”.

  When the defect correction signal output from the delay circuit 52 is at a high level and the defect correction signal output from the delay circuit 51 is “L”, the pixel signal input two times later is output from the defective pixel. It is determined that the signal is not “L”, and an “L” signal is output from the AND circuit 53. On the other hand, when the defect correction signal output from the delay circuit 51 is “H”, it is determined that the pixel signal input two times later is output from the defective pixel, and an “H” signal is output from the AND circuit 53. Output. The signal output from the AND circuit 53 is the signal “J” of the flag signals {K, J}, and the signal obtained by delaying the output of the AND circuit 53 by the delay circuit 54 is the flag signal {K, J}. It is our “K” signal. The flag signal {K, J} consists of four types {L, L}, {L, H}, {H, L}, {1, 1}, and {L, L} indicates single defect correction. The first flag signal {L, H}, {H, L}, {H, H} is a second flag for instructing continuous defect correction. “Single defect correction” means correcting a defective pixel in which the same color pixel adjacent in the horizontal direction is not a defective pixel, and “continuous defect correction” means a plurality of defective pixels of the same color adjacent in the horizontal direction. Means to correct.

  In addition, the delay circuit 52 of the determination unit 40, simultaneously with the pixel signal (the signal at position B in FIG. 21) output from the delay circuit 62 in the correction unit 41, the defect correction signal (see FIG. 21) input to the determination unit 40. 21) is input to the selector 70. The selector 70 of the correcting means 41 outputs a signal input from the selector 69 when the input defect correction signal is a defect correction enable signal (first signal). The selector 70 outputs a signal input from the delay circuit 62 when the input defect correction signal is a defect correction disable signal (second signal).

  The correction unit 41 includes delay circuits 60 to 64, adders 65 and 66, 1/2 amplifiers 67 and 68, and selectors 69 and 70, and receives the pixel signal output from the A / D conversion circuit 11. Then, based on the flag signal {K, J} input from the discriminating means 40, the pixel signal output from the defective pixel is corrected using the average value of the signal levels of the pixel signals from the two adjacent pixels of the same color that are not defective. To do. The delay circuits 60 to 64 are circuits that delay the input pixel signal by two clocks.

The following three signals are input to the selector 69.
(A) A signal obtained by adding the output of the delay circuit 61 and the output of the delay circuit 63 by the adder 65 and halving the signal level by the ½ amplifier 67 (the signal at the position C in FIG. 1 correction signal ”)
(B) A signal obtained by adding the output of the delay circuit 60 and the output of the delay circuit 63 by the adder 66 and halving the signal level by the ½ amplifier 68 (the signal at position D in FIG. 2) "
(C) A signal obtained by adding the output of the delay circuit 60 and the output of the delay circuit 63 by the adder 66 and further delaying the signal whose signal level is halved by the ½ amplifier 68 by the delay circuit 64 (see FIG. (21 position E signal: hereinafter referred to as “third correction signal”)

  The selector 69 selects any one of the first to third correction signals input based on the flag signal {K, J} input from the determination unit 40. Specifically, when the flag signal is {0, 0}, the first correction signal is selected and output, and when the flag signal {K, J} is {0, 1} and {1, 1}, the second correction signal is output. A signal is selected and output. When the flag signal {K, J} is {1, 0}, the third correction signal is selected and output.

The selector 70 selectively outputs one of the two input signals based on the signal output from the delay circuit 52 of the determination unit 40. That is, the selector 70 outputs a signal input from the selector 69 when the defect correction enable signal (first signal) is output as a defect correction signal from the delay circuit 52. On the other hand, when a defect correction disable signal (second signal) is output from the delay circuit 52 as a defect correction signal, a signal input from the delay circuit 62 is output.

  Since the correcting means 41 is configured as described above, when there are m consecutive defective pixels (m is a natural number), the average value of the signal levels of the pixel signals output from the two adjacent pixels of the same color is used. The pixel signal of the defective pixel can be corrected. That is, when the same color pixel (horizontal adjacent same color pixel) that is adjacent in the horizontal direction in the readout pixel array with respect to the defective pixel that has output the pixel signal is not a defective pixel, the pixel signal output from the defective pixel is the horizontal adjacent same color pixel. Is replaced with a correction signal having a signal level that is an average value of the signal levels of the pixel signals output from. In addition, when there are two consecutive defective pixels of the same color (hereinafter referred to as “adjacent same-color defective pixel group”) in the readout pixel array, the pixel signal output from each defective pixel of the adjacent same-color defective pixel group is used as the adjacent same color. Correction is performed with a correction signal having a signal level that is an average value of signal levels of pixel signals output from pixels of the same color horizontally adjacent to the defective pixel group (horizontal adjacent same color pixels).

  Hereinafter, the operation of the correction means 41 will be described with reference to the drawings. 22 to 28 are diagrams for explaining the operation of the correction means 41. In the following description, it is assumed that the solid-state imaging device 10 has a defect as shown in FIG.

(Defect correction when reading all pixels)
First, a defect correction process when the system controller 13 reads all pixels from the solid-state imaging device 10 will be described with reference to FIG. FIG. 23 (a) is a diagram showing the state of the position A shown in FIG. 21, FIG. 23 (b) is a diagram showing the state of the position B shown in FIG. 21, and FIG. 23 (c) is a diagram of G shown in FIG. It is a figure which shows the state of a position.

  In the example shown in FIG. 23A, pixel signals output from the solid-state imaging device 10 from the pixels 22a of “1R1”,..., “1Gr10”,. Is input. Further, a signal corresponding to the pixel signal output from the solid-state imaging device 10 is sequentially input from the correction comparator 37 to the defect correction unit 38.

  As shown in FIG. 23C, the defect correction unit 38 outputs pixel signals output from “1Gr4” and “1Gr5” defective pixels to pixel signals output from the “1Gr3” and “1Gr6” pixels 22 a. The defect signal is replaced with a correction signal having an average value of the signal level, and continuous defect correction is performed. Also, the pixel signal output from the defective pixel “1R7” is replaced with a correction signal of the average value of the signal level of the pixel signal output from the pixel 22a of “1R6” and “1R8”, and single defect correction is performed. Further, the pixel signal output from the defective pixel of “1R9” is replaced with a correction signal of the average value of the signal level of the pixel signal output from the pixel 22a of “1R8” and “1R10”, and single defect correction is performed. In this manner, single defect correction and continuous defect correction can be performed at the time of reading all pixels.

(Defect correction during horizontal thinning readout)
Next, defect correction processing when the system controller 13 performs horizontal thinning readout from the solid-state imaging device 10 will be described with reference to FIG. 24A is a diagram showing the state of the position A shown in FIG. 21, FIG. 24B is a diagram showing the state of the position B shown in FIG. 21, and FIG. 24C is a diagram showing the state of G shown in FIG. It is a figure which shows the state of a position.

  In the example shown in FIG. 24A, pixel signals output from the pixels 22a of “1R1”,..., “1Gr10”,. Input to the correction unit 38. Further, a signal corresponding to the pixel signal output from the solid-state imaging device 10 is sequentially input from the correction comparator 37 to the defect correction unit 38.

  As shown in FIG. 24C, the defect correction unit 38 converts the pixel signals output from the defective pixels “1R7” and “1R9” to the pixel signals output from the pixels “1R5” and “1R11”. Replace with the correction signal of the average value of the signal level and perform continuous defect correction. In addition, the pixel signal output from the defective pixel of “1Gr5” is replaced with a correction signal of the average value of the signal level of the pixel signal output from the pixels of “1Gr3” and “1Gr7”, and single defect correction is performed.

  Thus, the normal “1R8” pixel 22a is thinned out, and the “1R7” pixel 22a and the “1R9” pixel 22a are adjacent to each other in the readout pixel array with the same color. Even in such a case, continuous defect correction can be performed, and the accuracy of defect correction can be improved. For example, when only single defect correction is performed, as shown in FIG. 25, when “1R3” and “1R5” are defective pixels, correction is performed using the pixel signal output by the defective pixel. Can not do. On the other hand, the defect correction unit 38 according to the present embodiment can perform correction using a pixel signal output from a normal pixel, and can improve the accuracy of defect correction.

(Defect correction during horizontal readout)
Next, defect correction processing when the system controller 13 performs horizontal direction addition reading from the solid-state imaging device 10 will be described with reference to FIGS. 26 and 27. FIG. 26 (a) and 27 (a) are diagrams showing the state of the position A shown in FIG. 21, FIGS. 26 (b) and 27 (b) are diagrams showing the state of the position B shown in FIG. 26 (c) and 27 (c) are diagrams showing the state of the position G shown in FIG.

  In the example shown in FIG. 26A, pixels of “1R (1 + 2)”, “1Gr (1 + 2)”,..., “1Gr (11 + 12)”,. The pixel signal output from 22 a is output and sequentially input to the defect correction unit 38. Further, a signal corresponding to the pixel signal output from the solid-state imaging device 10 is sequentially input from the correction comparator 37 to the defect correction unit 38. In FIG. 26A, for example, “1Gr (1 + 2)” means a combined pixel signal output from the “1Gr1” pixel and the “1Gr2” pixel, and “1R (1 + 2)” , “1R1” and “1R2” are output from the pixel and added to each other to mean a combined pixel signal.

  As shown in FIG. 26C, the defect correction unit 38 synthesizes the synthesized pixel signals of “1Gr (3 + 4)” and “1Gr (5 + 6)” into “1Gr (1 + 2)” and “1Gr (7 + 8)”. Substituting a correction signal for the average value of the signal level of the pixel signal, and performing continuous defect correction. Further, the defect correcting unit 38 converts the combined pixel signals of “1R (7 + 8)” and “1R (9 + 10)” into the average value of the signal levels of the combined pixel signals of “1R (5 + 6)” and “1Gr (11 + 12)”. In this case, continuous defect correction is performed.

  In the first horizontal line, Gr defective pixels are continuous in all pixel readout. In addition, since the pixels are divided and added to different pixels, the defects continue after the addition. Therefore, in the readout arrangement, they are adjacent in the same color, and are recognized as the same color continuous defect, and can be replaced by the continuous defect correction method.

  When the second horizontal line is read in the horizontal direction, the following operation is performed. That is, as shown in FIG. 27A, “1Gb (1 + 2)”, “1B (1 + 2)”,..., “1B (11 + 12) from the solid-state imaging device 10 to the first horizontal line (B first line). ) ”,... Are output from the pixel 22a and sequentially input to the defect correction unit 38. Further, a signal corresponding to the pixel signal output from the solid-state imaging device 10 is sequentially input from the correction comparator 37 to the defect correction unit 38. In FIG. 27A, for example, “1 Gb (1 + 2)” means a pixel signal output from the “1 Gb 1” pixel and the “1 Gb 2” pixel and added, and “1B (1 + 2)” is It means a pixel signal output from the “1B1” pixel and the “1B2” pixel and added.

  As shown in FIG. 27C, the defect correction unit 38 converts the pixel signal of “1B (5 + 6)” to the average value of the signal levels of the pixel signals of “1B (3 + 4)” and “1B (7 + 8)”. Replace with the correction signal to perform continuous defect correction. The composite pixel signal of “1 Gb (9 + 10)” is replaced with a correction signal of an average value of the signal levels of the composite pixel signals of “1B (7 + 8)” and “1B (11 + 12)”, and continuous defect correction is performed.

  As shown in FIG. 22, in the second horizontal line, the B-type defective pixels are continuous in the read pixel array at the time of reading all pixels. In addition, since the pixels are divided and added to different pixels, the defects continue after the addition. Therefore, in the readout pixel array at the time of horizontal addition readout, they are adjacent with the same color, and are recognized as the same color continuous defect, and can be replaced by the continuous defect correction method. In the Gb system, defective pixels are not continuous in the read pixel array during all pixel readout and horizontal direction addition readout, and replacement can be performed by a single defect correction method.

(Defect correction during horizontal readout)
Next, defect correction processing when the system controller 13 performs vertical direction addition reading from the solid-state imaging device 10 will be described with reference to FIG. FIG. 28 (a) is a diagram showing the state of the position A shown in FIG. 21, FIG. 28 (b) is a diagram showing the state of the position B shown in FIG. 21, and FIG. 28 (c) is a diagram of G shown in FIG. It is a figure which shows the state of a position.

  In the example shown in FIG. 28A, “(1 + 2) Gb1”, “(1 + 2) B1”,..., “,” Obtained by adding the pixels of the second and fourth horizontal lines from the solid-state imaging device 10. (1 + 2) B11 ”,... Are output and sequentially input to the defect correction unit 38. Further, a signal corresponding to the combined pixel signal output from the solid-state imaging device 10 is sequentially input from the correction comparator 37 to the defect correction unit 38. In FIG. 28A, for example, “(1 + 2) Gb1” is a pixel signal output from the “1Gb1” pixel and the “2Gb1” pixel and added, and “(1 + 2) B1” is It means a combined pixel signal output from the “1B1” pixel and the “2B1” pixel and added.

  As shown in FIG. 28C, the defect correcting unit 38 synthesizes the synthesized pixel signals “(1 + 2) B5” and “(1 + 2) B6” into “(1 + 2) B4” and “(1 + 2) B7”. Substituting a correction signal for the average value of the signal level of the pixel signal, and performing continuous defect correction. In addition, the defect correcting unit 38 converts the combined pixel signals “(1 + 2) Gb9” and “(1 + 2) Gb10” into the average value of the signal levels of the combined pixel signals “(1 + 2) Gb8” and “(1 + 2) Gb10”. In this case, continuous defect correction is performed.

  In this way, in the B system, the “B5” pixel 22a and the “B6” pixel 22a are continuous on the same horizontal line, and thus are continuous defects, and are replaced by the continuous defect correction method. On the other hand, the Gb system is a single defect in all pixels, but by performing pixel addition in the vertical direction, the defect continues in the read pixel array at the time of correction. Is going.

  In the above description, the decimation method and the addition method are limited. However, the reading method is basically a combination of all pixel readout, addition full readout, decimation readout, and addition decimation readout independently in the vertical and horizontal directions. Can also be adapted and can be changed as appropriate according to the specifications.

(How to read from the volatile memory unit 35)
When the thinning process is performed as described above, an unnecessary defective address exists in the volatile memory unit 35, and it is necessary to skip the defective address in units of horizontal lines.

  Defect address reading in units of horizontal lines is skipped during the horizontal blanking period, and unnecessary defects up to the defective address used after the pixel signal output period of the next horizontal line (hereinafter referred to as “effective period”) are used. The address is skipped sequentially, and when it reaches the data to be used, it waits for the start of the valid period. Here, the “horizontal blanking period” is a period from the end of the output of the pixel signal of one horizontal line in the readout pixel array to the start of the output of the pixel signal of the next horizontal line in the readout pixel array. It is.

  Since this skipping is performed one data at a time during the horizontal blanking period, the number of cycles of horizontal blanking is conventionally larger than the number of words (number of stored defective addresses) of the volatile memory unit 35 holding the defective address. I had to. If the number of horizontal blanking cycles is not larger than the number of words in the volatile memory unit 35, skipping is not completed within the horizontal blanking period, and reading stops and breaks in the middle, and correction is made in the middle. This is because it may not be possible.

  Therefore, in the imaging device 1 according to the present embodiment, by dividing the inside of the volatile memory unit 35 that holds the defect address by a reference point of an arbitrary section, a part is not sequentially read out, but from the reference point to the reference point. The data is skipped.

  First, when the correction function is set to ON, the defect address at each reference point is read out. The read defect address at each reference point is held, and compared with the pixel address being processed, it is determined whether reading can be skipped. When reading can be skipped, the reading address (memory address) is skipped to the position of the possible reference point, and reading is sequentially resumed from there.

  By skipping the reading, there is no conventional limitation on the relationship between the number of horizontal blanking cycles and the number of words in the storage memory for holding the defective address. Therefore, an increase in the number of defective addresses that can be held is expected, and more pixel defects can be corrected.

  Further, since it is not necessary to read out all unnecessary defective pixel position address signals, it is possible to reduce the power required for reading (maximum “reference point number / reference point number + 1”).

  Here, an example of processing when the reference point in the volatile memory unit 35 is set at the 128th word will be described with reference to FIGS. 29 and 30. FIG. FIG. 29 is a conceptual diagram of a storage state of a defective address in the volatile memory unit 35, and FIG. 30 is a diagram for explaining a reading process from the volatile memory unit 35. In the following description, it is assumed that the volatile memory unit 35 can store 256 defective addresses, and the addresses are 0 to 255.

  As shown in FIG. 30, when the correction function is set to ON, the signal processing circuit 12 reads in advance the defect address at the 128th word, which is the reference point, from the volatile memory unit 35 and holds it in a storage unit (not shown). deep. Further, RADR, which is the read address of the volatile memory unit 35 in which the defective address is stored, is set to “0” (step S10).

  Next, the signal processing circuit 12 determines whether or not the SG address is larger than the 128th defective address (step S11). Here, the SG address is an address output from the address generator 33 and is an address of a pixel that outputs a pixel signal being processed.

  If it is determined in step S11 that the SG address is not larger than the 128 word defective address (step S11: No), the signal processing circuit 12 increments RADR by +1 (step S12). On the other hand, if it is determined that the SG address is larger than the 128-word defective address (step S11: Yes), the signal processing circuit 12 determines whether RADR is larger than 128 (step S13).

  If it is determined in step S13 that RADR is greater than 128 (step S13: Yes), the signal processing circuit 12 proceeds to step S12. On the other hand, if it is determined that RADR is not greater than 128 (step S13: No), the signal processing circuit 12 sets RADR to 129 (step S14).

  When the processes in steps S12 and S14 are completed, the signal processing circuit 12 determines whether there is no defective address to be read from the volatile memory unit 35 (RDATA == All1), and further whether RADR is 255 or more. Determination is made (step S15).

  When it is determined in step S15 that there is a defective address to be read from the volatile memory unit 35, or when it is determined that RADR is not 255 or more (step S15: No), the signal processing circuit 12 performs the process. Return to S11. On the other hand, when it is determined that there is no defective address read from the volatile memory unit 35, or when it is determined that RADR is 255 or more (step S15: Yes), the signal processing circuit 12 ends the processing.

  In FIG. 29, the reference point is set only at the 128th word, but as shown in FIG. 31, it can be set at the 64th, 128th, and 192words, and can be set more finely.

  As described above, the defective pixel correction unit 39 in the present embodiment compares the address of the pixel corresponding to the pixel signal read from the solid-state imaging device 10 with the address of the defective pixel (defective address). At this time, if they do not match, it is determined that the defective pixel has been thinned out when the solid-state imaging device 10 is read, and the pixel signal output from the pixel corresponding to the defective address is not corrected. . Further, the storage area of the volatile memory unit 35 is divided by a reference point of a certain section, and the defect address at the reference point and the pixel address read from the reference point are periodically compared to store in the volatile memory unit 35. Some defective addresses are not read sequentially, but are partially skipped.

  Therefore, there is no restriction as in the conventional case in the relationship between the number of horizontal blanking cycles and the number of words in the volatile memory unit 35 for holding a defective address. Therefore, an increase in the number of defective addresses that can be held is expected, and more pixel defects can be corrected. Further, since it is not necessary to read out all unnecessary defective pixel position address signals, it is possible to reduce the power required for reading.

  The volatile memory unit 35 includes volatile memories 35-1 and 35-2. As described above, each volatile memory 35-1 and 35-2 has a defective address alternately in units of horizontal lines. Is memorized. Therefore, for example, in the case of vertical addition reading, the defective address can be read alternately from the volatile memory 35-1 and the volatile memory 35-2 in units of horizontal lines. With this configuration, a buffer that is temporarily held at the time of defect correction is not required, and access control to the volatile memory unit 35 is facilitated.

  Although several embodiments of the present invention have been described in detail with reference to the drawings, these are merely examples, and the present invention can be implemented in other forms that are variously modified and improved based on the knowledge of those skilled in the art. It is possible to implement.

  For example, in the above-described embodiment, a CMOS solid-state image sensor is described as an example of the solid-state image sensor. However, the present invention is not limited thereto, and a CCD solid-state image sensor may be used.

It is a figure which shows the structure of the imaging device in one Embodiment of this invention. It is a figure which shows the structure of the solid-state image sensor in one Embodiment of this invention. It is explanatory drawing of the pixel arrangement | sequence of a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is explanatory drawing of the read-out process of the pixel signal from a solid-state image sensor. It is a figure which shows the structure which performs the process of a defect detection and defect correction in the signal processing circuit of an imaging device. It is a block diagram of the address detector in a signal processing circuit. It is a figure for demonstrating the detection operation of a 1st defect detection part. It is a figure for demonstrating the detection operation of a 2nd defect detection part. It is a figure for demonstrating the detection operation of a 1st defect detection part and a 2nd defect detection part. It is a figure for demonstrating the storage method to a volatile memory part. It is a figure for demonstrating the storage method to a volatile memory part. It is a figure for demonstrating the storage method to a volatile memory part. It is a figure for demonstrating the storage method to a volatile memory part. It is a block diagram of a defect correction circuit. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is a figure for demonstrating operation | movement of a correction | amendment means. It is an image figure of the recording state of the defective address of a volatile memory part. It is explanatory drawing of the read-out process of a volatile memory part. It is explanatory drawing of the read-out process of a volatile memory part. It is a figure for demonstrating the storage method to the conventional volatile memory part. It is a figure for demonstrating the storage method to the conventional volatile memory part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Imaging device 10 Solid-state image sensor 11 A / D conversion circuit 12 Signal processing circuit 13 System controller 14 Input part 15 Optical block 16 Driver 31 First defect detection part 32 Second defect detection part 33 Address generator 34 Address detector 35 Volatilization Volatile memory 36 volatile memory 36 nonvolatile memory 37 correction comparator 38 defect correction circuit 39 defective pixel correction unit 40 discrimination means 41 correction means

Claims (6)

Compares the storage unit that stores the address of the defective pixel of the solid-state image sensor with the address of the pixel corresponding to the pixel signal read from the solid-state image sensor and the address of the defective pixel, and corrects the pixel signal output by the pixel with the matching address A defective pixel correction unit,
The solid-state imaging device is capable of adding and outputting with k pixels of the same color in the vertical direction,
The storage unit is a defect correction circuit provided with k storage elements that store addresses of defective pixels corresponding to the k pixels of the same color. The solid-state imaging device can output pixel signals from some pixels by thinning out a plurality of pixels in a horizontal direction or a vertical direction,
The defective pixel correction unit includes:
Compare the address of the pixel corresponding to the pixel signal read from the solid-state image sensor and the address of the defective pixel, and if they do not match, determine that the defective pixel has been thinned out when reading the solid-state image sensor, The pixel signal output from the pixel corresponding to the address of the defective pixel is not corrected, and further, the storage area of the storage unit is divided by a reference point of a certain section, and the address of the defective pixel at the reference point is read from this The defect correction circuit according to claim 1, wherein by periodically comparing pixel addresses, the defect addresses stored in the storage unit are not read sequentially but partially read. The defective pixel correction unit includes:
Discriminating means for discriminating whether or not defective pixels of the same color are continuous with reference to an array of read pixels from the solid-state imaging device
The pixel signal output from the defective pixel that is continuous by the determination unit is corrected using an average value of signal levels of at least two adjacent same-color pixels that are non-defective pixels and are adjacent to the continuous defective pixel. The defect correction circuit according to claim 1, further comprising: a correction unit that performs correction. The correction means includes
A pixel signal output from a defective pixel determined not to be continuous by the determination unit is used as an average value of signal levels of at least two adjacent same-color pixels that are not defective and are adjacent to the defective pixel. The defect correction circuit according to claim 3, wherein the defect correction circuit corrects the error. The discrimination means includes
Based on the address of the defective pixel stored in the storage unit, when the pixel corresponding to the pixel signal read from the solid-state imaging device is a defective pixel, the first signal is output to the correcting unit, and when the pixel is not a defective pixel, the correcting unit Means for outputting a second signal to
Means for outputting a first flag to the correction means when defective pixels of the same color are not continuous, and outputting a second flag to the correction means when defective pixels of the same color are continuous;
The correction means includes
When the first signal is input and the first flag is input, the pixel signal output from the solid-state imaging device is converted into at least two adjacent same-color pixels of the same color adjacent to the pixel corresponding to the pixel signal. Correct using the average value of the signal level of
When the first signal is input and the second flag is input, the pixel signal read from the solid-state imaging device is at least of the same color adjacent to a continuous defective pixel group including pixels corresponding to the pixel signal. The defect correction circuit according to claim 3, wherein correction is performed using an average value of signal levels of two adjacent same color pixels. A solid-state imaging device and a storage unit that stores the address of the defective pixel of the solid-state imaging device, and the address of the defective pixel is compared with the address of the pixel corresponding to the pixel signal read from the solid-state imaging device. A defective pixel correction unit that corrects a pixel signal output from the pixel,
The solid-state imaging device is capable of adding and outputting with k pixels of the same color in the vertical direction,
The storage unit is an imaging apparatus provided with k storage elements that store addresses of defective pixels corresponding to the k pixels of the same color.