JP2010129085A - Information processing system, system controller and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten required time of STR processing in an information processing system using XDR DRAM. <P>SOLUTION: The XDR DRAM 13 performs data reset according to input of an RST (reset) signal. A system controller 11 outputs a reset signal to the XDR DRAM 13 according to the RST signal to be input from a memory controller 12 via a levels shifter 24 to reset the XDR DRAM 13 in first power application of a system. When power of the system is turned off with holding data stored in the XDR DRAM, the system controller 11 turns the power of the memory controller 12 off while maintaining power application of the XDR DRAM 13 according to the RST signal to be input from the memory controller 12 via the level shifter 24. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an STR processing technique in an information processing system having XDR DRAM (registered trademark) as a main memory.

  STR (Suspend-To-RAM) as a means for realizing high-speed start-up of a system such as a computer, etc., in which the main memory (generally SDRAM) is always in a power supply state and the previous system state is left on the main memory when the system is degenerated. ). STR is a mode in which power supply to most devices such as a CPU and a hard disk is stopped while the current state is stored in a memory. Since the memory holds data in a state where the OS is started, the OS is not restarted when returning, and returns to the state before suspension.

  The STR is in a suspend mode in which the power consumption at the time of suspend and the time required for return are well balanced. For example, “STD (Suspend-To-Disk)”, which saves data to the hard disk and turns off almost all devices, has almost the same principle, but the access speed of the memory is overwhelmingly faster than the hard disk. It takes less time to return. In addition, power is supplied to the memory in STR and not supplied in STD. However, the power consumption of the memory is relatively small, which does not cause a big problem.

  In the system described in Patent Document 1 below, the memory controller determines whether it is in the STR state before resetting. The memory controller can also clear the data in response to a determination that the processor is not in the STR state before reset.

Special table 2007-504553 gazette

  Recently, there is SPE (Spurs Engin) (registered trademark) as a processor that is the center of a platform for enjoying real-time content including high-resolution moving images and multi-channel audio through an advanced human interface. This processor is optimized for multimedia processing and distributed computing environments. In multimedia processing, the performance is about 10 times that of a conventional processor installed in a personal computer.

  Also, recent DRAM data rates are significantly faster, with some reaching several gigahertz. As such a high-speed data rate DRAM, there is an XDR DRAM. In the processor as described above, STR processing to XDR DRAM is defined as a concept. However, unlike previous implementations of STR in SDRAM (DDR2 DRAM), in the case of XDR DRAM, system startup such as RSTn control in cold boot (Cold Boot) and SCK / CMD control in warm boot (Warm Boot) In the time control, the control state on the memory controller side that operates the XIO memory interface must be recognized by the system controller side that controls the STR control circuit, but such means is not specifically defined.

  In the STR processing of a memory system using a conventional XDR DRAM, the time required for startup such as warm boot is remarkably long, and it is desired to increase the processing speed.

  An object of the present invention is to shorten the time required for STR processing in an information processing system using XDR DRAM.

  In the present invention, in the STR processing of an information processing system using XDR DRAM, the meaning corresponding to the system startup (power-on) processing and the degeneration (partial power-off) processing is performed on the RST signal of the memory controller. Made. By this RST signal, the processing state on the memory controller side necessary for the STR processing is transmitted to the system controller side. In response to the RST signal, the system controller executes system startup processing and degeneration processing.

  In the STR processing of the memory system using the XDR DRAM, it is possible to reduce the processing overhead necessary for transmitting the processing state on the memory controller side to the system controller side, and to shorten the time required for the startup processing and the degeneration processing. .

It is a block diagram which shows the structure of the information processing system which concerns on one Example of this invention. 3 is a diagram showing detailed circuits around a system controller 11, a memory controller 12, an XDR DRAM 13, and a STR control circuit 14. FIG. It is a flowchart which shows STR control at the time of cold boot. It is a flowchart which shows STR control in the case of turning off a power supply by the setting of suspend. It is a flowchart which shows STR control at the time of warm boot. It is a figure which shows the circuit which implement | achieves the high-speed of XDR DRAM reset control at the time of cold boot.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention.

  This system includes a system controller 11, a memory controller 12, an XDR DRAM 13, a STR control circuit 14, and a host system 15.

  The system controller 11 performs overall control of the system. For example, the system controller 11 initializes the memory controller 12, initializes the host system 15, sets Vref_FETE, RSTn, SCK_BJT, etc. of the STR control circuit 14, and sets a mail-box 15a of the host system 15 during system operation. Communication with the memory controller 12 and system monitoring are performed. In this embodiment, as will be described later, the system controller 11 monitors the STR processing state of the memory controller 12 via an RST (reset) terminal output signal of the memory controller 12 (XIO memory interface 12a).

  The memory controller 12 is a memory controller provided in a general-purpose processor composed of a multi-core processor or a single processor as described above, for example. Here, such a general-purpose processor is referred to as the memory controller 12. The memory controller 12 includes an XIO memory interface 12a, a control processor 12b, a data transfer PCI Express 12c (high-speed bus for communication with the host system), an initialization / communication serial bus 12d, and the like. The memory controller 12 is in charge of operations such as image processing in order to realize the system function.

  An XDR DRAM (Extreme Data Rate DRAM) 13 is a main memory of the memory controller 12. As will be described later, the STR control circuit 14 includes a Vref control FET, an RSTn control voltage dividing resistor, and an SCK control NPN-BJT.

  The host system 15 is a South Bridge of the memory controller 12, that is, a SoC (System on Chip) in which I / Os are aggregated. The host system 15 includes a mailbox, a memory controller 12 and an SRAM (not shown) for communication between the system controller and an initialization / communication serial bus 15b.

  FIG. 2 shows detailed circuits around the system controller 11, the memory controller 12, the XDR DRAM 13, and the STR control circuit 14. In order to simplify the description, the data bus, address bus, and other signal lines are omitted.

  In this example, four XDR DRAMs 13a to 13d are provided as the XDR DRAM 13. Each DRAM can arbitrarily set a bit configuration such as 4 bits and 8 bits, and a number (0 to 3) for identifying each is set. In the figure, “Term” is a terminal resistance (pull-up resistance). Reference numeral 21 denotes a memory cell power supply line (also referred to as a core power supply), for example, 1.8V. Reference numeral 22 denotes an I / O power supply line (also referred to as an I / O power supply), for example, 1.2V. The STR control circuit 14 includes a resistor 25, an NPN bipolar transistor 26, an NchFET transistor 30, a resistor 31, an NchFET transistor 32, and the like.

  The RST (reset) terminal of the memory controller 12 is connected to the I / O power supply 1.2V 22 via the resistor 23 and is connected to GPI0 (General Purpose Input 0) of the system controller 11 via the level shifter 24. . The level shifter 24 converts the RST output amplitude (1.2 V / 0 V) of the memory controller 12 into an appropriate input amplitude (3.3 V / 0 V) of the system controller 11.

  A GPO0 (General Purpose Output 0) terminal of the system controller 11 is connected to the gate of the Nch-FET transistor 30. One current terminal of the transistor 30 is connected to the 5.0 V power supply line through the resistor 31 and is connected to the gate of the Nch-FET transistor 32, and the other current terminal is connected to GND. One current terminal of the transistor 32 is connected to the power supply line 21 through the resistor 33 and is connected to GND through the resistor 34. The other current terminal of the transistor 32 is connected to the Vref terminal of the XDR DRAMs 13a to 13d, is connected to GND through the capacitor 38, and is connected to the VREF terminal of the memory controller 12 through the resistor 37. The other current terminal of the transistor 32 is connected to the 1.2 V power supply line 22 through a resistor 35 and is connected to GND through a resistor 36.

  The GPO1 terminal of the system controller 11 is connected to the RST terminals of the XDR DRAMs 13a to 13d. The GPO1 terminal is connected to the 1.8V power supply line 21 through the resistor 28, and is connected to GND through the resistor 29.

  The GPO2 terminal of the system controller 11 is connected to the base of the bipolar transistor 26 via the resistor 25. The collector of the transistor 26 is connected to the SCK terminals of the XDR DRAMs 13 a to 13 d and the SCK terminal of the memory controller 12, and is connected to the 1.2 V power supply line 22 through the resistor 27.

  Next, the operation of this embodiment will be described.

  First, STR control of the XDR DRAM 13 at the time of cold boot will be described with reference to the flowchart of FIG. At the time of cold boot, that is, when the power is turned on for the first time after shipment from the factory, the STR control of the XDR XDR DRAM 13 is performed according to the following procedure.

  When the power is turned on as in step C1, the system controller [Sys-Con] 11 turns on the XDR DRAM core power supply (1.8V_XDR VDD) 21, and the memory controller 12 and the IO power supply (1.2V_XIOVDD) 22 .

  In step C2, POR (Power On Reset) processing of the memory controller 12 and the host system [HS] 15 is performed.

  In step C3, the firmware (F / W) of the memory controller 12 is booted, that is, the firmware is executed from the beginning (hereinafter, the firmware of the memory controller 12 is described as the memory controller 12F / W).

  In Step C4, the Vref_FET and SCK_BJT of the STR control circuit 14 are initialized. That is, the system controller 11 sets the GPO0 terminal (Vref_FET) to the high level and the GPO2 terminal (SCK_BJT) to the low level.

  In step C5, initialization of the memory controller and XDR DRAM and XDR DRAM reset control are performed. Hereinafter, details of step C5 will be described as steps C5a to C5g.

  Step C5a: The memory controller 12F / W initializes the memory controller 12.

  C5b: The memory controller 12F / W performs XDR DRAM reset control (enable). That is, the memory controller 12F / W sets the RST (reset) terminal of the memory controller 12 to the low level. This RST signal is input as a Low level signal to the GPI 0 terminal of the system controller 11 via the level shifter 34.

  C5c: The system controller 11 performs XDR DRAM reset control (enable). That is, the system controller 11 sets the GPO1 terminal (RST) to the low level in response to the low level of the GPI0 terminal. This RST signal is input to the RST terminals of the XDR DRAMs 13a to 13d, and the XDR DRAM is reset. At this time, the data bit configuration, number (address), etc. of the XDR DRAMs 13a to 13d are reset, and the XDR DRAMs 1313a to 13d become unusable, but the data stored in the RAM main body is not erased.

  Here, the system controller 11 needs to complete the process of setting the GPO1 terminal (RST) to the Low level within a predetermined time (for example, 1 msec) after the memory controller 12RST terminal changes from the High level to the Low level. This is because if this process takes more time, the memory controller 12 starts operating, and for example, erroneous data may be written to the XDR DRAM 13.

  C5d: Software of the memory controller 12 (hereinafter referred to as memory controller 12S / W) performs SCK control of the XDR DRAM.

  C5e: The memory controller 12S / W performs XDR DRAM reset control (disable). That is, the memory controller 12S / W changes the RST terminal of the memory controller 12 from Low level to High impedance (High level). This signal is input to the GPI0 terminal of the system controller 11 through the level shifter 34 as a high level signal.

  C5f: The system controller 11 performs XDR DRAM reset control (disable). That is, the system controller 11 sets the GP01 terminal (RST) to High impedance in response to the High level of the GPI0 terminal. Here, as described above, the system controller 11 sets the GPO1 terminal (RST) to high impedance within a predetermined time (for example, 1 msec) after the RST terminal of the memory controller 12 changes from low level to high level. Need to be completed.

  C5g: The memory controller 12S / W initializes the XIO memory interface 12a.

  Next, the STR control when the power is turned off with the suspend setting (Enter to Suspend), that is, when the system is turned off while retaining the data stored in the DRAM, will be described with reference to the flowchart of FIG.

  In step S1, the XDR DRAM 13 is set. That is, the memory controller 12F / W executes a power down sequence of the XDR DRAM 13. As a result, the XDR DRAM 13 enters a self-refresh mode with low power consumption.

  In step S2, the SCK (serial clock) / CMD (command) degeneration process of the STR control circuit 14, that is, the memory controller is disconnected from the XDR DRAM, and the power OFF process of the memory controller is performed. Hereinafter, details of step S2 will be described as steps S2a to S2d.

  Step S2a: The memory controller 12F / W notifies the system controller 11 of the start of the degeneration process by changing the RST terminal of the memory controller 12 from the high impedance to the low level.

  Step S2b: The memory controller 12F / W fixes the CMD logic of the XDR DRAM 13 to zero.

  Step S2c: The memory controller 12F / W fixes the logic of SCK of the XDR DRAM 13 to 1. Thus, by fixing the logic of CMD and SCK, the output levels of the CMD terminal and the SCK terminal are fixed, and noise generation in the subsequent processing can be prevented.

  Step S2d: The memory controller 12F / W notifies the system controller 11 of the end of the degeneration process by setting the RST terminal of the memory controller 12 from Low level to High impedance (High level). Thus, when the power is turned off with the suspend setting, the RST signal of the memory controller 12 means the start and end of the degeneration process of the memory controller 12.

  Next, in step S3, SCK_BJT degeneration processing of the STR control circuit 14 is performed. That is, the system controller 11 sets the GPO2 terminal (SCK_BJTn) from low to high level in response to the high level of the GPI0 input terminal. As a result, the bipolar transistor 26 is turned ON, and noise mixing in the SCK signal line can be prevented.

  In step S4, Vref_FET degeneration processing of the STR control circuit 14 is performed. That is, the system controller 11 sets the GPO0 (Vref_FET) terminal from High to Low level. As a result, the FET transistor 30 is turned off and the FET transistor 32 is also turned off.

  In step S5, a power shutdown process is performed. That is, the system controller 11 cuts off the IO power supply (1.2V_XIOVDD) 22 of the memory controller 12 and the XDR DRAM 13. Here, the system controller 11 maintains the XDR DRAM core power supply 21 (1.8V_XDRVDD). As a result, the data recorded in the XDR DRAM 13 is suspended.

  Next, the STR control of the XDR DRAM in the so-called resume at the time of warm boot will be described with reference to the flowchart of FIG.

  When power is turned on during a warm boot, that is, in a suspended state (a state where the XDR DRAM core power supply 21 is maintained), STR control of the XDR DRAM is performed according to the following procedure.

  When power is turned on, the system controller 11 turns on the memory controller 12 and the XDR DRAM IO power supply (1.2V_XIOVDD) 22 in step R1. Here, the memory controller 12 and the core power supply 21 of the XDR DRAM are always maintained.

  In step R2, POR (Power On Reset) initialization processing (resetting of each register, etc.) of the memory controller 12 and the host system 15 is performed.

  In step R3, the Vref_FET operation of the STR control circuit is performed. That is, the system controller 11 changes the GPO0 terminal (Vref_FET) from Low level to High impedance. As a result, the FET transistor 30 is turned on and the FET transistor 32 is also turned on. In step R4, the boot of the memory controller 12F / W, that is, the program is executed from the beginning.

  In step R5, the SCK / CMD restart process (1/2) of the STR control circuit 14 is performed. Hereinafter, details of Step R5 will be described as Steps Ra to Rd.

  Step R5a: The memory controller 12F / W notifies the system controller 11 of the start of the restart process by changing the RST terminal of the memory controller 12 from High impedance to Low level.

  Step R5b: The memory controller 12F / W fixes the logic of SCK of the XDR DRAM 13 to 1.

  Step R5c: The memory controller 12F / W fixes the CMD logic of the XDR DRAM 13 to zero.

  Step R5d: The memory controller 12F / W notifies the system controller 11 of the end of resumption by setting the RST terminal of the memory controller 12 from Low level to High impedance (High level). Thus, at the time of warm boot, the RST signal of the memory controller 12 means the start and end of the restart process of the memory controller 12.

  Next, in step R6, the SCK_BJT operation of the STR control circuit is performed. That is, the system controller 11 sets the GPO2 terminal from High to Low level in response to the High level of the GPI0 terminal, and the bipolar transistor 26 is turned off. As described above, the system controller 11 needs to complete this process within a predetermined time (for example, 1 msec) after the RST terminal of the memory controller 12 changes from the High level to the Low level.

  In step R7, the SCK / CMD restart process (2/2) of the STR control circuit is performed. That is, the memory controller 12F / W fixes the SCK logic of the XDR DRAM 13 to 0. The serial bus between the XIO memory interface 12a and the XDR DRAM 13 returns to the normal operation.

  In step R8, the memory controller 12 / XDR DRAM 13 is initialized. That is, the memory controller 12F / W performs initialization of the XDR DRAM I / F 12a.

  As described above, an information processing system according to an embodiment of the present invention includes an XDR DRAM 13 that performs data reset in response to a reset signal input, a memory controller 12 that controls the XDR DRAM 13 to read and write data, and an XDR And a system controller 11 that performs STR processing of the DRAM 13. The memory controller 12 outputs an RST signal (Low) at any time of cold boot (first power-on), power-off by the suspend setting, and warm boot (normal power-on). During a cold boot, the system controller 11 determines that the RST signal input from the memory controller is a reset signal, outputs a reset signal to the XDR DRAM 13, and resets the XDR DRAM 13. When the power is turned off due to the suspend setting, the system controller 11 determines that the RST signal input from the memory controller 12 is a notification of the degeneration mode, and turns off the memory controller while maintaining the power on of the XDR DRAM 13. Therefore, in a system having a DRAM such as an XDR DRAM having a reset function, the STR process can be performed in a short time.

  Next, speeding up the XDR DRAM reset control will be described.

  In order to speed up the XDR reset control at the time of cold boot, the system controller 11 may directly reset the XDR DRAM 13 instead of resetting the XDR DRAM 13 from the GPO1 terminal. FIG. 6 is a circuit for realizing high speed XDR reset control. In this circuit, an FET transistor 37 is added as compared with the circuit of FIG. The FET transistor 37 is connected between the RST terminal of the memory controller 12 and the RST terminals of the XDR DRAMs 13a to 13d, and the gate thereof is connected to the GPO1 terminal of the system controller 11.

  At the time of cold boot, the GPO1 terminal of the system controller 11 is at a low level. A low level signal is output as a reset signal from the RST terminal of the memory controller 12. As a result, the memory controller 12 can directly reset the XDR DRAMs 13a to 13d via the RST terminal, and the XDR reset control can be speeded up. In this example, the GPO1 terminal of the system controller 11 maintains the high level when the power is turned off by the suspend setting and at the time of warm boot.

  The above description is an embodiment of the present invention, and does not limit the apparatus and method of the present invention, and various modifications can be easily implemented.

  DESCRIPTION OF SYMBOLS 11 ... System controller, 12 ... Memory controller, 13a-13d ... XDR DRAM, 24 ... Level shifter.

Claims (10)

DRAM that performs data reset in response to a reset signal input;
A memory controller that controls the DRAM and reads and writes data;
A system controller for controlling the DRAM and the memory controller, and an information processing system comprising:
The system controller is
Means for outputting the reset signal to the DRAM in response to a reset signal input from the memory controller when the system is powered on for the first time;
Means for turning off the power of the memory controller while maintaining power on of the DRAM in response to a reset signal input from the memory controller when the power of the system is turned off while retaining data stored in the DRAM When,
An information processing system comprising:   2. The level shifter provided between the memory controller and the system controller, and the reset signal is transmitted from the memory controller to the system controller via the level shifter. system.   The system of claim 1, wherein the DRAM is an XDR DRAM. A system controller used in a system including a DRAM that performs data reset in response to a reset signal input and a memory controller that controls the DRAM to read and write data,
Means for outputting the reset signal to the DRAM in response to a reset signal input from the memory controller when the system is powered on for the first time;
Means for turning off the power to the memory controller while maintaining power on of the DRAM in response to a reset signal input from the memory controller when the system is turned off while retaining data stored in the DRAM; ,
A system controller comprising: A method for controlling an information processing system including a DRAM, a memory controller, and a system controller,
When the system is powered on for the first time, the system controller outputs the reset signal to the DRAM in response to a reset signal input from the memory controller,
When the system power is turned off while retaining the data stored in the DRAM, the system controller maintains the power on of the DRAM in response to a reset signal input from the memory controller, The memory control method characterized by cutting off.   6. The method of claim 5, wherein the reset signal is transmitted from the memory controller to the system controller via a level shifter.   6. The method of claim 5, wherein the DRAM is an XDR DRAM. DRAM that performs data reset in response to a reset signal input;
A memory controller that controls the DRAM to read and write data;
A system controller for performing STR (Suspend-To-RAM) processing of the DRAM,
The system controller is
Means for outputting the reset signal to the DRAM in response to a reset signal input from the memory controller when the system is powered on for the first time;
Means for turning off the power of the memory controller while maintaining power on of the DRAM in response to a reset signal input from the memory controller when the power of the system is turned off while retaining data stored in the DRAM When,
An information processing system comprising: A system controller that performs STR (Suspend-To-RAM) processing of a system including a DRAM that performs data reset in response to a reset signal input and a memory controller that controls the DRAM to read and write data.
Means for outputting the reset signal to the DRAM in response to a reset signal input from the memory controller when the system is powered on for the first time;
Means for turning off the power to the memory controller while maintaining power on of the DRAM in response to a reset signal input from the memory controller when the system is turned off while retaining data stored in the DRAM; ,
A system controller comprising: A STR (Suspend-To-RAM) control method in an information processing system including a DRAM, a memory controller, and a system controller,
When the system is powered on for the first time, the system controller outputs the reset signal to the DRAM in response to a reset signal input from the memory controller,
When the system power is turned off while retaining the data stored in the DRAM, the system controller maintains the power on of the DRAM in response to a reset signal input from the memory controller, The memory control method characterized by cutting off.

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