JP2010123854A - Method of manufacturing semiconductor device and wire bonding equipment - Google Patents

Method of manufacturing semiconductor device and wire bonding equipment Download PDF

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Publication number
JP2010123854A
JP2010123854A JP2008297913A JP2008297913A JP2010123854A JP 2010123854 A JP2010123854 A JP 2010123854A JP 2008297913 A JP2008297913 A JP 2008297913A JP 2008297913 A JP2008297913 A JP 2008297913A JP 2010123854 A JP2010123854 A JP 2010123854A
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Japan
Prior art keywords
wire
capillary
bonding
pad
semiconductor device
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JP2008297913A
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Japanese (ja)
Inventor
Takeshi Kaneda
剛 金田
Tominori Takahashi
富視 高橋
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2008297913A priority Critical patent/JP2010123854A/en
Publication of JP2010123854A publication Critical patent/JP2010123854A/en
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To securely supervise an undesired protrusion of wire from a bonding capillary by monitoring the presence of contact of a bonding wire and a semiconductor chip using a loop circuit when deceleration is started in the course of lowering the bonding capillary to a bonding pad. <P>SOLUTION: Wire bonding equipment monitors the presence of undesired contact of the wire and semiconductor chip using a loop circuit constituted by the wire and the like before the wire contacts a pad after deceleration is started in the course of lowering a capillary to the pad when a ball portion 7 of the leading end of the wire 6 is connected to the pad 5 on the semiconductor chip 1 using the capillary 31. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置（または半導体集積回路装置）の製造方法におけるワイヤ・ボンディング技術に適用して有効な技術に関する。   The present invention relates to a technique effective when applied to a wire bonding technique in a method of manufacturing a semiconductor device (or a semiconductor integrated circuit device).

日本特開平１１−２６５１７号公報（特許文献１）には、半導体チップ側のボンディング・パッドにワイヤをボンディング（いわゆる「第１ボンディング」）した後に、ボンディングされたワイヤ、半導体チップ、およびワイヤ・ボンディング装置等から構成されるループ状回路を利用して、ワイヤ・ボンディング接続不良を検査する技術が開示されている。   In Japanese Patent Laid-Open No. 11-26517 (Patent Document 1), after bonding a wire to a bonding pad on the semiconductor chip side (so-called “first bonding”), the bonded wire, the semiconductor chip, and the wire bonding A technique for inspecting a wire bonding connection failure by using a loop circuit constituted by an apparatus or the like is disclosed.

特開平１１−２６５１７号公報JP-A-11-26517

ワイヤの接続（ワイヤ・ボンディング）は、まず、キャピラリの先端部から突出するワイヤの一端部に放電（スパーク）によりボール部を形成し、キャピラリの先端部から突出したボール部を引き上げる。そして、接合する対象物（例えば、パッド）に向かってキャピラリを下降させ、ワイヤのボール部とパッドを圧着することにより、行われる。   For wire connection (wire bonding), first, a ball portion is formed by discharge (sparking) at one end portion of the wire protruding from the tip portion of the capillary, and the ball portion protruding from the tip portion of the capillary is pulled up. Then, the capillary is lowered toward an object (for example, a pad) to be joined, and the ball portion of the wire and the pad are pressure-bonded.

また、製造ＴＡＴ（Ｔｕｒｎ Ａｒｏｕｎｄ Ｔｉｍｅ）の低減を考慮して、キャピラリの最初の下降速度は、ボール部を対象物に接触させる直前の下降速度よりも速くしている。すなわち、対象物の直上において、ボール部がキャピラリに接触する前に、キャピラリの下降速度を減速させ（キャピラリの下降動作に急ブレーキをかけ）、その後、ボール部が対象物に接触するまで、キャピラリを低速で下降させている。   Further, in consideration of a reduction in manufacturing TAT (Turn Around Time), the initial lowering speed of the capillary is higher than the lowering speed immediately before the ball portion is brought into contact with the object. That is, immediately below the object, before the ball part contacts the capillary, the capillary descending speed is decelerated (rapid braking is applied to the descending action of the capillary), and then the capillary until the ball part contacts the object. Is lowered at low speed.

今回、本願発明者は、前記したような動作を有するワイヤ・ボンディング装置に対して、以下の問題を見出した。   This time, this inventor discovered the following problems with respect to the wire bonding apparatus which has the above operation | movement.

すなわち、ワイヤにバック・テンションを掛けてワイヤの弛み等を防止するバック・テンション付加装置の内部（内面）には、使用頻度により、ワイヤとの摩擦抵抗により発生した異物が付着してしまい、ワイヤを引き上げる際、十分にボール部を引き上げることができなくなることが分かった。そして、ボール部が十分に引き上げられていない状態で、キャピラリの下降動作に急ブレーキをかけると、引き上げきれなかったワイヤが、ブレーキの衝撃（慣性の法則）によりキャピラリの先端部から対象物に向かって飛び出してしまうことが分かった。   That is, foreign matter generated due to frictional resistance with the wire adheres to the inside (inner surface) of the back tension applying device that applies back tension to the wire to prevent loosening of the wire. It was found that the ball part could not be sufficiently lifted when lifting the ball. If the capillary is braked suddenly while the ball is not sufficiently pulled up, the wire that could not be pulled up will move from the tip of the capillary to the object due to the impact of the brake (law of inertia). I knew it would jump out.

このとき、対象物が半導体チップのパッドの場合、キャピラリから飛び出したワイヤの一端部（ボール部）が、隣のパッドに跨って半導体チップの主面（表面）に付着する問題、隣のパッドに付着する問題、更には、先に形成された隣のワイヤと接触するという問題が発生する。これは、半導体装置の小型化の影響により、隣り合うパッド間のピッチが狭くなったことも、理由の一つである。   At this time, when the object is a pad of a semiconductor chip, there is a problem that one end portion (ball portion) of the wire protruding from the capillary adheres to the main surface (front surface) of the semiconductor chip across the adjacent pad. The problem of adhesion occurs, and further, the problem of contact with the adjacent wire formed earlier occurs. One of the reasons for this is that the pitch between adjacent pads is reduced due to the downsizing of the semiconductor device.

尚、前記特許文献１には、ワイヤを対象物に接触させる際に生じる、ワイヤの飛び出し不良については示唆がなく、前記特許文献１の技術では、このワイヤの飛び出しを監視することは困難である。
そこで、本願発明では、ワイヤの一端部が対象物に向かって飛び出したことが分かる検査機構について検討した。 In addition, the above-mentioned Patent Document 1 does not suggest a wire pop-out defect that occurs when a wire is brought into contact with an object, and it is difficult to monitor the wire pop-out with the technique of Patent Document 1. .
In view of this, the present invention has examined an inspection mechanism that reveals that one end of the wire has jumped out toward the object.

本願発明は、これらの課題を解決するためになされたものである。   The present invention has been made to solve these problems.

本発明の目的は、信頼性の高い半導体装置の製造プロセスを提供することにある。   An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

本発明の前記並びにその他の目的と新規な特徴は本明細書の記述及び添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば下記の通りである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

すなわち、本願発明は半導体チップ上のパッドにキャピラリにより、ワイヤの先端部であるボール部を接続する際、パッドに向けてキャピラリを降下させる途中において、その降下速度の減速を開始した後であって、ワイヤがパッドと接触する前に、ワイヤ、半導体チップ、およびワイヤ・ボンディング装置等から構成されるループ状回路を利用して、ワイヤと半導体チップとの不所望な接触の有無をモニタするものである。   That is, in the present invention, when connecting the ball part, which is the tip of the wire, to the pad on the semiconductor chip with the capillary, after the capillary is lowered toward the pad, the speed of the descending is started. Before a wire comes into contact with a pad, a loop circuit composed of a wire, a semiconductor chip, a wire bonding apparatus, etc. is used to monitor the presence of unwanted contact between the wire and the semiconductor chip. is there.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

すなわち、ボンディング・パッドに向けてボンディング・キャピラリを降下させる途中において、その降下速度の減速を開始した後であって、ボンディング・ワイヤがボンディング・パッドと接触する前に、ボンディング・ワイヤ、半導体チップ、およびワイヤ・ボンディング装置等から構成されるループ状回路を利用して、ワイヤ・ボンディングと半導体チップとの不所望な接触の有無をモニタすることにより、ボンディング・キャピラリからのワイヤの不所望な飛び出しを確実に監視することができる。   That is, in the middle of lowering the bonding capillary toward the bonding pad, after starting to decrease the descent speed and before the bonding wire comes into contact with the bonding pad, the bonding wire, the semiconductor chip, In addition, by using a loop circuit composed of a wire bonding device, etc., by monitoring the presence of undesired contact between the wire bonding and the semiconductor chip, undesired jumping out of the wire from the bonding capillary It can be reliably monitored.

〔実施の形態の概要〕
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。 [Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

１．以下の工程を含む半導体装置の製造方法：
（ａ）ワイヤ・ボンディング装置内において、先端にボール部を有するボンディング・ワイヤを貫通させたボンディング・キャピラリを、半導体チップの第１の主面上のボンディング・パッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを、前記第１の降下速度をより遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記ボンディング・パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリにより前記ボール部を前記ボンディング・パッドに押し付けることによって、前記ボンディング・ワイヤを前記ボンディング・パッドにボンディングする工程；
（ｅ）前記工程（ｂ）および（ｃ）を含む区間内であって、前記ボール部が前記ボンディング・パッドに接触する前の第１検査期間内に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・キャピラリからの前記ボンディング・ワイヤの不所望な突出の有無を検出する第１の検査を実行する工程。 1. A semiconductor device manufacturing method including the following steps:
(A) In the wire bonding apparatus, a bonding capillary that has a bonding wire having a ball portion at the tip thereof is directed toward the bonding pad on the first main surface of the semiconductor chip, and the first descending speed Step of lowering with;
(B) After the step (a), in the wire bonding apparatus, the step of decelerating the bonding capillary to a lower second descent rate;
(C) After the step (b), in the wire bonding apparatus, the bonding capillary is lowered at the second lowering speed to bring the ball portion into contact with the bonding pad;
(D) After the step (c), the step of bonding the bonding wire to the bonding pad by pressing the ball portion against the bonding pad by the bonding capillary in the wire bonding apparatus. ;
(E) In the section including the steps (b) and (c), the bonding is performed in the wire bonding apparatus within a first inspection period before the ball portion contacts the bonding pad. First inspection for detecting presence or absence of undesired protrusion of the bonding wire from the bonding capillary using a loop circuit including a part of each of the wire, the semiconductor chip, and the wire bonding apparatus The process of performing.

２．前記１項の半導体装置の製造方法において、更に以下の工程を含む：
（ｆ）前記工程（ｄ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記ボンディング・ワイヤに沿って、前記ボンディング・パッドから後退させる工程；
（ｇ）前記工程（ｆ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記半導体チップの外部のリード部に向けて移動させる工程；
（ｈ）前記工程（ｇ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤの側面を前記ボンディング・キャピラリによって、前記ボンディング・パッドに押し付けることによって、前記ボンディング・ワイヤを前記リード部にボンディングする工程；
（ｉ）前記工程（ｄ）の後であって、前記工程（ｈ）の前に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・ワイヤの前記ボンディング・パッドに対するボンディング状態を検出する第２の検査を実行する工程。 2. The method for manufacturing a semiconductor device according to the item 1, further includes the following steps:
(F) After the step (d), in the wire bonding apparatus, the step of retracting the bonding capillary along the bonding wire from the bonding pad;
(G) After the step (f), in the wire bonding apparatus, the step of moving the bonding capillary toward the lead portion outside the semiconductor chip;
(H) After the step (g), by pressing the side surface of the bonding wire against the bonding pad with the bonding capillary in the wire bonding apparatus, the bonding wire is applied to the lead portion. Bonding process;
(I) After the step (d) and before the step (h), in the wire bonding apparatus, a part of each of the bonding wire, the semiconductor chip, and the wire bonding apparatus Performing a second inspection for detecting a bonding state of the bonding wire with respect to the bonding pad using a loop-shaped circuit including:

３．前記２項の半導体装置の製造方法において、
（ｊ）前記工程（ｈ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリをワイヤ・クランパが開かれた状態で、前記ボンディング・ワイヤに沿って、前記リード部から後退させる工程；
（ｋ）前記工程（ｊ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリをワイヤ・クランパが開かれた状態で、前記ボンディング・ワイヤに沿って、前記リード部から後退させることにより、前記ボンディング・ワイヤを前記リード部の近傍で切断する工程；
（ｌ）前記工程（ｋ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを貫通した前記ボンディング・ワイヤの先端部に放電によりボール部を形成する工程；
（ｍ）前記工程（ｋ）の後であって、前記工程（ｌ）の前に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・ワイヤが正常に切断されたか否かを検査する第３の検査を実行する工程。 3. In the method of manufacturing a semiconductor device according to the item 2,
(J) After the step (h), in the wire bonding apparatus, the bonding capillary is retracted from the lead portion along the bonding wire in a state where the wire clamper is opened;
(K) After the step (j), in the wire bonding apparatus, the bonding capillary is retracted from the lead portion along the bonding wire with the wire clamper opened. Cutting the bonding wire in the vicinity of the lead portion;
(L) After the step (k), in the wire bonding apparatus, a step of forming a ball portion by discharge at the tip of the bonding wire penetrating the bonding capillary;
(M) After the step (k) and before the step (l), in the wire bonding apparatus, a part of each of the bonding wire, the semiconductor chip, and the wire bonding apparatus And performing a third inspection for inspecting whether or not the bonding wire has been normally cut using a loop circuit including:

４．前記１から３項のいずれか一つの半導体装置の製造方法において、前記半導体チップは金属製のリード・フレーム上に固定されている。   4). 4. In the method of manufacturing a semiconductor device according to any one of items 1 to 3, the semiconductor chip is fixed on a metal lead frame.

５．前記１から３項のいずれか一つの半導体装置の製造方法において、前記半導体チップは配線基板上に固定されている。   5. 4. In the method for manufacturing a semiconductor device according to any one of items 1 to 3, the semiconductor chip is fixed on a wiring board.

６．前記１から５項のいずれか一つの半導体装置の製造方法において、前記第１の検査は直流電流又は電圧を印加して実行される。   6). 6. In the method of manufacturing a semiconductor device according to any one of 1 to 5, the first inspection is performed by applying a direct current or a voltage.

７．前記１から５項のいずれか一つの半導体装置の製造方法において、前記第１の検査中において、電流又は電圧方向を切り替える。   7). 6. In the method of manufacturing a semiconductor device according to any one of 1 to 5, the current or voltage direction is switched during the first inspection.

８．前記１から５項のいずれか一つの半導体装置の製造方法において、前記第１の検査は交流電流又は電圧を印加して実行される。   8). 6. In the method for manufacturing a semiconductor device according to any one of items 1 to 5, the first inspection is performed by applying an alternating current or a voltage.

９．前記１から５項のいずれか一つの半導体装置の製造方法において、前記第１の検査は高周波電流又は電圧を印加して実行される。   9. 6. In the method of manufacturing a semiconductor device according to any one of 1 to 5, the first inspection is performed by applying a high frequency current or voltage.

１０．前記１から５項のいずれか一つの半導体装置の製造方法において、前記第１の検査はパルス状の電流又は電圧を印加して実行される。   10. 6. In the method for manufacturing a semiconductor device according to any one of items 1 to 5, the first inspection is performed by applying a pulsed current or voltage.

１１．前記１から１０項のいずれか一つの半導体装置の製造方法において、前記工程（ｂ）は、以下の下位工程を含む：
（ｂ１）前記ボンディング・キャピラリを、前記第１の降下速度をより遅く、前記第２の降下速度より速い第３の降下速度まで減速させる工程；
（ｂ２）前記工程（ｂ１）の後、前記ボンディング・キャピラリを、前記第３の降下速度で降下させる工程；
（ｂ３）前記工程（ｂ２）の後、前記第３の降下速度で降下させる工程。 11. 11. In the method for manufacturing a semiconductor device according to any one of 1 to 10, the step (b) includes the following substeps:
(B1) decelerating the bonding capillary to a third lowering speed that is slower than the first lowering speed and faster than the second lowering speed;
(B2) After the step (b1), lowering the bonding capillary at the third lowering speed;
(B3) A step of lowering at the third lowering speed after the step (b2).

１２．前記１から１１項のいずれか一つの半導体装置の製造方法において、前記工程（ｃ）において、前記ボール部が前記ボンディング・パッドに接触する際には、前記ボンディング・キャピラリへの超音波およびボンディング荷重の印加が開始されている。   12 12. In the method of manufacturing a semiconductor device according to any one of 1 to 11, in the step (c), when the ball portion contacts the bonding pad, an ultrasonic wave and a bonding load applied to the bonding capillary. Has been started.

１３．前記１から１２項のいずれか一つの半導体装置の製造方法において、前記ボンディング・ワイヤは、金を主要な成分とする。   13. In the method for manufacturing a semiconductor device according to any one of Items 1 to 12, the bonding wire includes gold as a main component.

１４．前記１から１３項のいずれか一つの半導体装置の製造方法において、前記ボンディング・パッドの主要部は、アルミニウムを主要な成分とする。   14 14. In the method of manufacturing a semiconductor device according to any one of 1 to 13, the main part of the bonding pad includes aluminum as a main component.

１５．前記１から１４項のいずれか一つの半導体装置の製造方法において、前記第１の検査は、前記工程（ｂ）の開始後であって、前記工程（ｃ）における前記ボール部の前記ボンディング・パッドへの正常な接触の前に、前記ボール部を含む前記ボンディング・ワイヤの一部が、前記半導体チップの前記第１の主面上の導電部に接触したか否かを検査する。   15. 15. The manufacturing method of a semiconductor device as described above in any one of 1 to 14, wherein the first inspection is after the start of the step (b) and the bonding pad of the ball portion in the step (c). Before normal contact with the semiconductor chip, it is inspected whether a part of the bonding wire including the ball portion has contacted the conductive portion on the first main surface of the semiconductor chip.

１６．前記１から１５項のいずれか一つの半導体装置の製造方法において、前記第１検査期間内に、連続的、断続的に、または離散的に複数回、前記第１の検査を実行する。   16. 16. In the method for manufacturing a semiconductor device according to any one of 1 to 15, the first inspection is executed a plurality of times continuously, intermittently, or discretely within the first inspection period.

１７．前記１から５、および、８から１６項のいずれか一つの半導体装置の製造方法において、前記第１の検査は、１０００Ｈｚから１ＭＨｚの範囲内の高周波電流又は電圧を印加して実行される。   17. In the method of manufacturing a semiconductor device according to any one of 1 to 5 and 8 to 16, the first inspection is performed by applying a high-frequency current or voltage within a range of 1000 Hz to 1 MHz.

１８．前記１７項の半導体装置の製造方法において、高周波電流又は電圧は、実質的に正弦波交流である。   18. In the method for manufacturing a semiconductor device according to the item 17, the high-frequency current or voltage is substantially sinusoidal alternating current.

１９．以下の工程を含む半導体装置の製造方法：
（ａ）ワイヤ・ボンディング装置内において、先端にボール部を有するボンディング・ワイヤを貫通させたボンディング・キャピラリを、半導体チップの第１の主面上のボンディング・パッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを、前記第１の降下速度をより遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記ボンディング・パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリにより前記ボール部を前記ボンディング・パッドに押し付けることによって、前記ボンディング・ワイヤを前記ボンディング・パッドにボンディングする工程、
ここで、前記工程（ｂ）の開始の後であって、前記ボール部が前記ボンディング・パッドに接触する前の第１検査期間内に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・キャピラリからの前記ボンディング・ワイヤの不所望な突出の有無を検出する第１の検査を実行する。 19. A semiconductor device manufacturing method including the following steps:
(A) In the wire bonding apparatus, a bonding capillary that has a bonding wire having a ball portion at the tip thereof is directed toward the bonding pad on the first main surface of the semiconductor chip, and the first descending speed Step of lowering with;
(B) After the step (a), in the wire bonding apparatus, the step of decelerating the bonding capillary to a lower second descent rate;
(C) After the step (b), in the wire bonding apparatus, the bonding capillary is lowered at the second lowering speed to bring the ball portion into contact with the bonding pad;
(D) After the step (c), the step of bonding the bonding wire to the bonding pad by pressing the ball portion against the bonding pad by the bonding capillary in the wire bonding apparatus. ,
Here, after the start of the step (b) and within a first inspection period before the ball portion contacts the bonding pad, the bonding wire, A first inspection is performed to detect the presence or absence of an undesired protrusion of the bonding wire from the bonding capillary using a loop circuit including a part of each of the semiconductor chip and the wire bonding apparatus.

２０．前記１９項の半導体装置の製造方法において、更に以下の工程を含む：
（ｆ）前記工程（ｄ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記ボンディング・ワイヤに沿って、前記ボンディング・パッドから後退させる工程；
（ｇ）前記工程（ｆ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを前記半導体チップの外部のリード部に向けて移動させる工程；
（ｈ）前記工程（ｇ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤの側面を前記ボンディング・キャピラリによって、前記ボンディング・パッドに押し付けることによって、前記ボンディング・ワイヤを前記リード部にボンディングする工程；
（ｉ）前記工程（ｄ）の後であって、前記工程（ｈ）の前に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・ワイヤの前記ボンディング・パッドに対するボンディング状態を検出する第２の検査を実行する工程。 20. The method for manufacturing a semiconductor device according to the item 19, further includes the following steps:
(F) After the step (d), in the wire bonding apparatus, the step of retracting the bonding capillary along the bonding wire from the bonding pad;
(G) After the step (f), in the wire bonding apparatus, the step of moving the bonding capillary toward the lead portion outside the semiconductor chip;
(H) After the step (g), by pressing the side surface of the bonding wire against the bonding pad with the bonding capillary in the wire bonding apparatus, the bonding wire is applied to the lead portion. Bonding process;
(I) After the step (d) and before the step (h), in the wire bonding apparatus, a part of each of the bonding wire, the semiconductor chip, and the wire bonding apparatus Performing a second inspection for detecting a bonding state of the bonding wire with respect to the bonding pad using a loop-shaped circuit including:

２１．前記２０項の半導体装置の製造方法において、
（ｊ）前記工程（ｈ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリをワイヤ・クランパが開かれた状態で、前記ボンディング・ワイヤに沿って、前記リード部から後退させる工程；
（ｋ）前記工程（ｊ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリをワイヤ・クランパが開かれた状態で、前記ボンディング・ワイヤに沿って、前記リード部から後退させることにより、前記ボンディング・ワイヤを前記リード部の近傍で切断する工程；
（ｌ）前記工程（ｋ）の後、前記ワイヤ・ボンディング装置内において、前記ボンディング・キャピラリを貫通した前記ボンディング・ワイヤの先端部に放電によりボール部を形成する工程；
（ｍ）前記工程（ｋ）の後であって、前記工程（ｌ）の前に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・ワイヤが正常に切断されたか否かを検査する第３の検査を実行する工程。 21. In the manufacturing method of the semiconductor device according to the item 20,
(J) After the step (h), in the wire bonding apparatus, the bonding capillary is retracted from the lead portion along the bonding wire in a state where the wire clamper is opened;
(K) After the step (j), in the wire bonding apparatus, the bonding capillary is retracted from the lead portion along the bonding wire with the wire clamper opened. Cutting the bonding wire in the vicinity of the lead portion;
(L) After the step (k), in the wire bonding apparatus, a step of forming a ball portion by discharge at the tip of the bonding wire penetrating the bonding capillary;
(M) After the step (k) and before the step (l), in the wire bonding apparatus, a part of each of the bonding wire, the semiconductor chip, and the wire bonding apparatus And performing a third inspection for inspecting whether or not the bonding wire has been normally cut using a loop circuit including:

２２．前記１９から２１項のいずれか一つの半導体装置の製造方法において、前記半導体チップは金属製のリード・フレーム上に固定されている。   22. 22. In the method for manufacturing a semiconductor device according to any one of 19 to 21, the semiconductor chip is fixed on a metal lead frame.

２３．前記１９から２１項のいずれか一つの半導体装置の製造方法において、前記半導体チップは配線基板上に固定されている。   23. In the method for manufacturing a semiconductor device according to any one of the items 19 to 21, the semiconductor chip is fixed on a wiring board.

２４．前記１９から２３項のいずれか一つの半導体装置の製造方法において、前記第１の検査は直流電流又は電圧を印加して実行される。   24. 24. In the method of manufacturing a semiconductor device as described above in any one of 19 to 23, the first inspection is performed by applying a direct current or a voltage.

２５．前記１９から２３項のいずれか一つの半導体装置の製造方法において、前記第１の検査中において、電流又は電圧方向を切り替える。   25. 24. In the method for manufacturing a semiconductor device as described above in any one of 19 to 23, the current or voltage direction is switched during the first inspection.

２６．前記１９から２３項のいずれか一つの半導体装置の製造方法において、前記第１の検査は交流電流又は電圧を印加して実行される。   26. 24. In the method of manufacturing a semiconductor device as described above in any one of 19 to 23, the first inspection is performed by applying an alternating current or a voltage.

２７．前記１９から２３項のいずれか一つの半導体装置の製造方法において、前記第１の検査は高周波電流又は電圧を印加して実行される。   27. 24. In the method for manufacturing a semiconductor device as described above in any one of 19 to 23, the first inspection is performed by applying a high-frequency current or voltage.

２８．前記１９から２３項のいずれか一つの半導体装置の製造方法において、前記第１の検査はパルス状の電流又は電圧を印加して実行される。   28. 24. In the method of manufacturing a semiconductor device as described above in any one of 19 to 23, the first inspection is performed by applying a pulsed current or voltage.

２９．前記１９から２８項のいずれか一つの半導体装置の製造方法において、前記工程（ｂ）は、以下の下位工程を含む：
（ｂ１）前記ボンディング・キャピラリを、前記第１の降下速度をより遅く、前記第２の降下速度より速い第３の降下速度まで減速させる工程；
（ｂ２）前記工程（ｂ１）の後、前記ボンディング・キャピラリを、前記第３の降下速度で降下させる工程；
（ｂ３）前記工程（ｂ２）の後、前記第３の降下速度で降下させる工程。 29. 29. In the method for manufacturing a semiconductor device as described above in any one of 19 to 28, the step (b) includes the following substeps:
(B1) decelerating the bonding capillary to a third lowering speed that is slower than the first lowering speed and faster than the second lowering speed;
(B2) After the step (b1), lowering the bonding capillary at the third lowering speed;
(B3) A step of lowering at the third lowering speed after the step (b2).

３０．前記１９から２９項のいずれか一つの半導体装置の製造方法において、前記工程（ｃ）において、前記ボール部が前記ボンディング・パッドに接触する際には、前記ボンディング・キャピラリへの超音波およびボンディング荷重の印加が開始されている。   30. 30. In the method of manufacturing a semiconductor device as described above in any one of 19 to 29, in the step (c), when the ball portion comes into contact with the bonding pad, an ultrasonic wave and a bonding load applied to the bonding capillary. Has been started.

３１．前記１９から３０項のいずれか一つの半導体装置の製造方法において、前記ボンディング・ワイヤは、金を主要な成分とする。   31. 31. In the method of manufacturing a semiconductor device according to any one of 19 to 30, the bonding wire includes gold as a main component.

３２．前記１９から３０項のいずれか一つの半導体装置の製造方法において、前記ボンディング・パッドの主要部は、アルミニウムを主要な成分とする。   32. 31. In the method of manufacturing a semiconductor device according to any one of 19 to 30, the main part of the bonding pad includes aluminum as a main component.

３３．前記１９から３２項のいずれか一つの半導体装置の製造方法において、前記第１の検査は、前記工程（ｂ）の開始後であって、前記工程（ｃ）における前記ボール部の前記ボンディング・パッドへの正常な接触の前に、前記ボール部を含む前記ボンディング・ワイヤの一部が、前記半導体チップの前記第１の主面上の導電部に接触したか否かを検査する。   33. 33. In the method of manufacturing a semiconductor device as described above in any one of 19 to 32, the first inspection is after the start of the step (b), and the bonding pad of the ball portion in the step (c) Before normal contact with the semiconductor chip, it is inspected whether a part of the bonding wire including the ball portion has contacted the conductive portion on the first main surface of the semiconductor chip.

３４．前記１９から３３項のいずれか一つの半導体装置の製造方法において、前記第１検査期間内に、連続的、断続的に、または離散的に複数回、前記第１の検査を実行する。   34. 34. In the method of manufacturing a semiconductor device as described above in any one of 19 to 33, the first inspection is executed a plurality of times continuously, intermittently, or discretely within the first inspection period.

３５．前記１９から２３、および、２６から３４項のいずれか一つの半導体装置の製造方法において、前記第１の検査は、１０００Ｈｚから１ＭＨｚの範囲内の高周波電流又は電圧を印加して実行される。   35. In the method for manufacturing a semiconductor device according to any one of Items 19 to 23 and 26 to 34, the first inspection is performed by applying a high-frequency current or voltage within a range of 1000 Hz to 1 MHz.

３６．前記３５項の半導体装置の製造方法において、高周波電流又は電圧は、実質的に正弦波交流である。   36. In the method for manufacturing a semiconductor device according to the item 35, the high-frequency current or voltage is substantially sinusoidal alternating current.

３７．少なくとも以下の工程を実行することができるワイヤ・ボンディング装置：
（ａ）先端にボール部を有するボンディング・ワイヤを貫通させたボンディング・キャピラリを、半導体チップの第１の主面上のボンディング・パッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記第１の降下速度をより遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記ボンディング・キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記ボンディング・パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記ボンディング・キャピラリにより前記ボール部を前記ボンディング・パッドに押し付けることによって、前記ボンディング・ワイヤを前記ボンディング・パッドにボンディングする工程；
（ｅ）前記工程（ｂ）および（ｃ）を含む区間であって、前記ボール部が前記ボンディング・パッドに接触する前に、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ボンディング・キャピラリからの前記ボンディング・ワイヤの不所望な突出の有無を検出する第１の検査を実行する工程。 37. Wire bonding apparatus capable of performing at least the following steps:
(A) a step of lowering a bonding capillary through which a bonding wire having a ball portion at the tip passes, toward a bonding pad on the first main surface of the semiconductor chip at a first lowering speed;
(B) after the step (a), decelerating the first descending speed to a slower second descending speed;
(C) after the step (b), lowering the bonding capillary at the second lowering speed to bring the ball portion into contact with the bonding pad;
(D) After the step (c), the step of bonding the bonding wire to the bonding pad by pressing the ball portion against the bonding pad with the bonding capillary;
(E) a section including the steps (b) and (c), and before the ball portion contacts the bonding pad, each of the bonding wire, the semiconductor chip, and the wire bonding apparatus; Performing a first test for detecting the presence or absence of undesired protrusion of the bonding wire from the bonding capillary using a loop-shaped circuit including a part thereof;

〔本願における記載形式・基本的用語・用法の説明〕
１．本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。 [Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

２．同様に実施の態様等の記載において、材料、組成等について、「ＡからなるＸ」等といっても、特にそうでない旨明示した場合および文脈から明らかにそうでない場合を除き、Ａ以外の要素を主要な構成要素のひとつとするものを排除するものではない。たとえば、成分についていえば、「Ａを主要な成分として含むＸ」等の意味である。たとえば、「シリコン部材」等といっても、純粋なシリコンに限定されるものではなく、ＳｉＧｅ合金やその他シリコンを主要な成分とする多元合金、その他の添加物等を含む部材も含むものであることはいうまでもない。   2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

また、「金ワイヤ」、「アルミニウム・ボンディング・パッド」等といっても、純粋な金またはアルミニウムから構成されたもののみを指すのではなく、特に、そうでない旨明示した場合および原理的にそうでないことが明らかである場合を除き、「金を主要な成分とするワイヤ」または「その主要部分がアルミニウム主要な成分とするボンディング・パッド」等を指すものとする。   In addition, “gold wire”, “aluminum bonding pad”, etc. do not only refer to those composed of pure gold or aluminum, but in particular if clearly stated otherwise and in principle Except where it is not clear, it shall refer to “a wire containing gold as a main component” or “bonding pad whose main portion is a main component of aluminum” or the like.

３．同様に、図形、位置、属性等に関して、好適な例示をするが、特にそうでない旨明示した場合および文脈から明らかにそうでない場合を除き、厳密にそれに限定されるものではないことは言うまでもない。   3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

４．さらに、特定の数値、数量に言及したときも、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、その特定の数値を超える数値であってもよいし、その特定の数値未満の数値でもよい。   4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

５．「ウエハ」というときは、通常は半導体装置（半導体集積回路装置、電子装置も同じ）をその上に形成する単結晶シリコンウエハを指すが、エピタキシャルウエハ、ＳＯＩ基板、ＬＣＤガラス基板等の絶縁基板と半導体層等の複合ウエハ等も含むことは言うまでもない。   5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

〔実施の形態の詳細〕
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。 [Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

１．本願の一実施の形態の半導体装置の製造方法における組み立て工程全体の説明（主に図２０から２４）
図２０から図２４に基づいて、ＭＡＰ（Ｍｏｌｄ Ａｒｒａｙ Ｐｒｏｃｅｓｓ）方式によるダイ・ボンディングからパッケージ・ダイシングまでの組立工程の概要を説明する。図２０に示すように、まず、たとえば、銅を主要な成分とする銅系金属等で構成されたリードフレーム２（または有機配線基板、有機配線薄膜等の配線基板の基体部）を準備する。リードフレーム２上においては、複数の単位領域１７（個々の半導体装置に対応する部分）が外枠部１５と中枠部１６によって保持されている。各単位領域１７内には、それぞれ半導体チップ１（図２１参照）を搭載するためのダイ・パッド部（チップ搭載部）３、ダイ・パッド部３を外枠部１５または中枠部１６に連結するダイ・パッド支持部１４、多数のリード部４等が設けられている。 1. Description of the entire assembly process in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 20 to 24)
The outline of the assembly process from die bonding to package dicing by the MAP (Mold Array Process) method will be described with reference to FIGS. As shown in FIG. 20, first, for example, a lead frame 2 (or a base portion of a wiring board such as an organic wiring board or an organic wiring thin film) made of a copper-based metal having copper as a main component is prepared. On the lead frame 2, a plurality of unit regions 17 (portions corresponding to individual semiconductor devices) are held by the outer frame portion 15 and the middle frame portion 16. In each unit region 17, a die pad portion (chip mounting portion) 3 for mounting the semiconductor chip 1 (see FIG. 21) and the die pad portion 3 are connected to the outer frame portion 15 or the middle frame portion 16, respectively. There are provided a die pad support portion 14 and a large number of lead portions 4.

次に、図２１に示すように、各ダイ・パッド部３に、たとえば銀ペースト等の接着剤層（有機配線基板等の場合は、たとえばエポキシ樹脂系非導電性ペースト、ＤＡＦその他）を介して、半導体チップ１をボンディング・パッド（パッド、電極パッド）５がある面を上にして固定する（半導体チップ１の裏面をダイ・パッド部の上面に固着する）。   Next, as shown in FIG. 21, an adhesive layer such as a silver paste (for example, an epoxy resin non-conductive paste, DAF or the like in the case of an organic wiring board or the like) is passed through each die pad portion 3. The semiconductor chip 1 is fixed with the surface having the bonding pad (pad, electrode pad) 5 facing upward (the back surface of the semiconductor chip 1 is fixed to the upper surface of the die pad portion).

次に、図２２に示すように、各ボンディング・パッド５と対応するリード部４間を、たとえばサーモソニック・ボンディング・プロセス（Ｔｈｅｒｍｏ−Ｓｏｎｉｃ Ｂｏｎｄｉｎｇ Ｐｒｏｃｅｓｓ）を用いたボール・ウエッジ・ボンディング形式（ボンディング・パッド側の第１ボンドがキャピラリを用いたボール・ボンディングで、リード部側の第２ボンドがウエッジ・ボンディングである）によって、金を主要な成分とするワイヤ６（ボンディング・ワイヤ）等で連結する。このワイヤ・ボンディング・プロセスについては、セクション４等で詳述する。   Next, as shown in FIG. 22, between the bonding pads 5 and the corresponding lead portions 4, for example, a ball wedge bonding type (bonding bonding) using a thermosonic bonding process (Thermo-Sonic Bonding Process) is performed. The first bond on the pad side is ball bonding using a capillary, and the second bond on the lead side is wedge bonding), and is connected by a wire 6 (bonding wire) or the like containing gold as a main component. . This wire bonding process will be described in detail in section 4 and the like.

次に、図２３に示すように、ワイヤ・ボンディングが完了したリードフレーム２をモールド金型内に収容して、リードフレーム２の上面を封止レジンによりレジン封止することで、半導体チップ１の上面およびボンディング・ワイヤをその内部に封止するレジン封止体２１を形成する。これにより、リードフレーム２、複数の半導体チップ１、多数のボンディング・ワイヤ６、レジン封止体２１等から構成されるリードフレーム・レジン封止体複合体が形成される。   Next, as shown in FIG. 23, the lead frame 2 in which wire bonding is completed is accommodated in a mold, and the upper surface of the lead frame 2 is resin-sealed with a sealing resin, so that the semiconductor chip 1 A resin sealing body 21 that seals the upper surface and the bonding wire therein is formed. As a result, a lead frame / resin sealing body composite composed of the lead frame 2, the plurality of semiconductor chips 1, a large number of bonding wires 6, the resin sealing body 21, and the like is formed.

次に、図２４に示すように、このリードフレーム・レジン封止体複合体をＸ方向ダイシング・ライン２２およびＹ方向ダイシング・ライン２３に沿って、たとえば回転ブレードによってパッケージ・ダイシング処理することで、個々の半導体装置に分割する。この個々の半導体装置については、セクション２等で詳述する。   Next, as shown in FIG. 24, the lead frame / resin encapsulant composite is package-diced by, for example, a rotating blade along the X-direction dicing line 22 and the Y-direction dicing line 23. Divide into individual semiconductor devices. This individual semiconductor device will be described in detail in section 2 and the like.

２．本願の一実施の形態の半導体装置の製造方法によって製造された半導体装置の説明（主に図２５から図２８および図１８）
ここで例示して説明する半導体装置は、基本的にＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構成またはＣＭＩＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構成を有している。すなわち、ＰチャネルＭＩＳＦＥＴ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ ＳｅｍｉｃｏｎｄｕｃｔｏｒｎＦｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）群およびＮチャネルＭＩＳＦＥＴ群から要素回路が構成されている。 2. Description of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 25 to 28 and FIG. 18)
A semiconductor device illustrated and described here basically has a complementary metal oxide semiconductor (CMOS) configuration or a complementary metal insulator semiconductor (CMIS) configuration. That is, an element circuit is composed of a P-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) group and an N-channel MISFET group.

図２５に示すように、完成した半導体装置２４（図２８参照）のパッケージの上面１１は、ほぼ正方形または長方形等の矩形を呈したレジン封止部２０となっている。また、図２６に示すように、完成した半導体装置のパッケージの下面１２の封止レジン部２０の間には、ダイ・パッド部３、ダイ・パッド支持部１４、リード部４の各下面が露出している。図２７は、図２５の封止レジンを透過して内部を見たパッケージ上面図である。図２７に示すように、各アルミニウム・ボンディング・パッド５と対応するリード部４との間に、金線６が接続されている。図２７のＸ−Ｘ’断面を図２８に示す。図２８に示すように、完成した半導体装置２４のレジン封止部２０の内部のダイ・パッド３の上面には、半導体チップ１が固着されており、その上面１ａ（デバイス面）の各ボンディング・パッド５には、キャピラリによって押しつぶされたボンディング・ワイヤ先端のボール部７がある。   As shown in FIG. 25, the upper surface 11 of the package of the completed semiconductor device 24 (see FIG. 28) is a resin sealing portion 20 having a substantially square or rectangular shape. Further, as shown in FIG. 26, the lower surfaces of the die pad portion 3, the die pad support portion 14, and the lead portion 4 are exposed between the sealing resin portions 20 on the lower surface 12 of the package of the completed semiconductor device. is doing. FIG. 27 is a top view of the package as seen through the sealing resin of FIG. As shown in FIG. 27, a gold wire 6 is connected between each aluminum bonding pad 5 and the corresponding lead portion 4. FIG. 28 shows an X-X ′ cross section of FIG. As shown in FIG. 28, the semiconductor chip 1 is fixed to the upper surface of the die pad 3 inside the resin sealing portion 20 of the completed semiconductor device 24, and each bonding surface on the upper surface 1a (device surface) is fixed. The pad 5 has a ball portion 7 at the tip of the bonding wire that is crushed by the capillary.

図１８は、ワイヤ・ボンディングにおいて、ワイヤの状態を検査するという観点から、ＣＭＩＳ構成の半導体チップ１およびその周辺の構造を模式的、類型的に説明したものである。回路的には、ボンディング・パッド５は、大雑把に３種類に分類することができる。第１類は、接地電源用ボンディング・パッド５Ｇｎｄ、Ｖｄｄ電源用ボンディング・パッド５Ｖｄｄ等の電源パッドである。第２類は、入力用ボンディング・パッド５Ｉｎ等の入力パッドである。第３類は、出力用ボンディング・パッド５Ｏｕｔ等の出力パッドである。   FIG. 18 schematically illustrates the CMIS-structured semiconductor chip 1 and its peripheral structure from the viewpoint of inspecting the wire state in wire bonding. In terms of circuit, the bonding pads 5 can be roughly classified into three types. The first type is a power supply pad such as a bonding pad 5Gnd for ground power supply and a bonding pad 5Vdd for Vdd power supply. The second type is an input pad such as an input bonding pad 5In. The third type is an output pad such as an output bonding pad 5Out.

通常、ＣＭＩＳ構成の半導体チップ１は、Ｐ型単結晶シリコン半導体基板１を用いて形成される。そして、半導体基板１の第１主面１ａ（デバイス面）のＰ型単結晶シリコン半導体基板領域１ｐに、ＮチャネルＭＩＳＦＥＴ２５ｎが設けられる。一方、半導体基板１の第１主面１ａ（デバイス面）のＰ型単結晶シリコン半導体基板領域１ｐに形成されたＮ型ウエル領域ＮＷに、ＰチャネルＭＩＳＦＥＴ２５ｐが設けられる。   Usually, the semiconductor chip 1 having a CMIS structure is formed using a P-type single crystal silicon semiconductor substrate 1. An N-channel MISFET 25n is provided in a P-type single crystal silicon semiconductor substrate region 1p on the first main surface 1a (device surface) of the semiconductor substrate 1. On the other hand, a P-channel MISFET 25p is provided in the N-type well region NW formed in the P-type single crystal silicon semiconductor substrate region 1p on the first main surface 1a (device surface) of the semiconductor substrate 1.

半導体基板１の第２主面１ｂ（裏面）の下方には、リード・フレーム品の場合は接着部剤層１０である銀ペースト等の導電性接着部剤層（配線基板の場合は、エポキシ系非導電性接着剤層等となる）がある。更に、接着部剤層１０の下には、リード・フレーム２（または配線基板等の基体部）があり、これを通して、検査電流が、下地の基体部２が直接触れるワイヤ・ボンディング装置の導電部４５に流れる。ただし、基体部２が有機配線基板等の場合は、直流電流は実質的に流れない。   Below the second main surface 1b (back surface) of the semiconductor substrate 1, there is a conductive adhesive layer such as a silver paste which is an adhesive layer 10 in the case of a lead frame product (in the case of a wiring board, an epoxy type). A non-conductive adhesive layer or the like). Further, under the adhesive agent layer 10, there is a lead frame 2 (or a base part such as a wiring board), through which a test current is directly conducted by a conductive part of a wire bonding apparatus with which the base base part 2 touches. It flows to 45. However, when the base part 2 is an organic wiring board or the like, the direct current does not substantially flow.

ＮチャネルＭＩＳＦＥＴ２５ｎは、Ｎ型ゲート電極２５ｎｇ、Ｎ型ソース領域２５ｎｓ、Ｎ型ドレイン領域２５ｎｄ、Ｎ型コンタクト領域ＮＣ等を有する。一方、ＰチャネルＭＩＳＦＥＴ２５ｐは、Ｐ型ゲート電極２５ｐｇ、Ｐ型ソース領域２５ｐｓ、Ｐ型ドレイン領域２５ｐｄ、Ｐ型コンタクト領域ＰＣ等を有する。その外、半導体基板１の第１主面１ａ（デバイス面）のＰ型単結晶シリコン半導体基板領域１ｐには、Ｎ型保護素子ＮＰ（Ｎ型不純物領域）が設けられている。一方、半導体基板１の第１主面１ａ（デバイス面）のＰ型単結晶シリコン半導体基板領域１ｐに形成されたＮ型ウエル領域ＮＷには、P型保護素子PＰ（P型不純物領域）が設けられている。   The N channel MISFET 25n includes an N type gate electrode 25ng, an N type source region 25ns, an N type drain region 25nd, an N type contact region NC, and the like. On the other hand, the P-channel MISFET 25p includes a P-type gate electrode 25pg, a P-type source region 25ps, a P-type drain region 25pd, a P-type contact region PC, and the like. In addition, an N-type protection element NP (N-type impurity region) is provided in the P-type single crystal silicon semiconductor substrate region 1p on the first main surface 1a (device surface) of the semiconductor substrate 1. On the other hand, a P-type protection element PP (P-type impurity region) is provided in the N-type well region NW formed in the P-type single crystal silicon semiconductor substrate region 1p on the first main surface 1a (device surface) of the semiconductor substrate 1. It has been.

これらを考慮すると、接地電源用ボンディング・パッド５Ｇｎｄは半導体チップの裏面１ｂに至るまでＰＮ接合がないことがわかる。Ｖｄｄ電源用ボンディング・パッド５Ｖｄｄの方は、Ｐ型単結晶シリコン半導体基板領域１ｐとＮ型ウエル領域ＮＷの間にＰＮ接合があるので、ＰＮ接合の逆方向耐圧以上の電圧を印加しない場合（以下同じ）には、直流的な検査における電流方向は、順方向ＰＮ接合を介した一方（Ｐ型単結晶シリコン半導体基板領域１ｐを高電位側とする電流方向）に限定される。   Considering these, it can be seen that the grounding power supply bonding pad 5Gnd has no PN junction until it reaches the back surface 1b of the semiconductor chip. The Vdd power supply bonding pad 5Vdd has a PN junction between the P-type single crystal silicon semiconductor substrate region 1p and the N-type well region NW. In the same manner, the current direction in the DC inspection is limited to one through the forward PN junction (current direction with the P-type single crystal silicon semiconductor substrate region 1p on the high potential side).

次に、入力用ボンディング・パッド５Ｉｎについて考察する。入力用ボンディング・パッド５ＩｎはＮ型ゲート電極２５ｎｇおよびＰ型ゲート電極２５ｐｇに接続されると同時に、Ｎ型保護素子ＮＰ（Ｎ型不純物領域）およびP型保護素子PＰ（P型不純物領域）に接続されているので、Ｎ型保護素子ＮＰを経由する電流通路は、一方向（Ｐ型単結晶シリコン半導体基板領域１ｐを高電位側とする電流方向）のみであるが（順方向ＰＮ接合を介して）確保されている。   Next, the input bonding pad 5In will be considered. The input bonding pad 5In is connected to the N-type gate electrode 25ng and the P-type gate electrode 25pg and simultaneously connected to the N-type protection element NP (N-type impurity region) and the P-type protection element PP (P-type impurity region). Therefore, the current path through the N-type protection element NP is only in one direction (current direction in which the P-type single crystal silicon semiconductor substrate region 1p is on the high potential side) (through a forward PN junction). ) Is secured.

同様に、出力用ボンディング・パッド５Ｏｕｔについて考察する。出力用ボンディング・パッド５Ｏｕｔは、Ｎ型ドレイン領域２５ｎｄおよびＰ型ドレイン領域２５ｐｄに接続されているので、Ｎ型ドレイン領域２５ｎｄを経由する電流通路は、一方向（Ｐ型単結晶シリコン半導体基板領域１ｐを高電位側とする電流方向）のみであるが（順方向ＰＮ接合を介して）確保されている。   Similarly, the output bonding pad 5Out will be considered. Since the output bonding pad 5Out is connected to the N-type drain region 25nd and the P-type drain region 25pd, the current path passing through the N-type drain region 25nd is unidirectional (P-type single crystal silicon semiconductor substrate region 1p). (Current direction with a high potential side) is ensured (through a forward PN junction).

従って、全てのボンディング・パッドについて検査（たとえば第１の検査）を実行するには、ＰＮ接合の逆方向耐圧以上の電圧を印加しない直流的な検査では、Ｐ型単結晶シリコン半導体基板領域１ｐを高電位側とする電流方向とするテスト電圧を印加するか、または、ミリ秒オーダの時間で電流又は電圧の方向を反転して、両方向で検査を実行する必要がある。ただし、摂氏２００度以上でワイヤ・ボンディングを実行する場合は、ＰＮ接合の逆方向電流を十分に確保することができるので、いずれかの方向での直流電流の有無を検査できるようにテスト電圧を印加すればよい。   Therefore, in order to execute the inspection (for example, the first inspection) for all the bonding pads, the P-type single crystal silicon semiconductor substrate region 1p is formed in the DC inspection in which a voltage higher than the reverse breakdown voltage of the PN junction is not applied. It is necessary to apply a test voltage having a current direction on the high potential side, or to reverse the direction of the current or voltage in a time on the order of milliseconds and to perform inspection in both directions. However, when wire bonding is performed at 200 degrees Celsius or higher, the reverse current of the PN junction can be sufficiently secured, so the test voltage must be set so that the presence or absence of DC current in any direction can be inspected. What is necessary is just to apply.

３．本願の一実施の形態の半導体装置の製造方法に使用するワイヤ・ボンディング装置等の説明（主に図１５および図１６）
ここでは、セクション４で説明するワイヤ・ボンディング・プロセスの理解を容易にするために、ワイヤ・ボンディング装置３０（図１５）の要部であるワイヤ・ボンディング・ヘッド４０の関係が深い部分について、簡単に説明する。 3. Description of wire bonding apparatus used for manufacturing method of semiconductor device of one embodiment of the present application (mainly FIGS. 15 and 16)
Here, in order to facilitate the understanding of the wire bonding process described in Section 4, a portion having a deep relationship with the wire bonding head 40, which is a main part of the wire bonding apparatus 30 (FIG. 15), is simply described. Explained.

図１５に示すように、ワイヤ・ボンディング・ヘッド４０は、ＸＹテーブル上に置かれており、ＸＹ方向に移動できるほか、Ｚ軸方向にも上下できるようになっている。ワイヤ送り出し部５０には、ボンディング・ワイヤ６を巻いたスプール４４が回転できるように取り付けられている。ボンディング・ワイヤ６は、スプール４４からワイヤ繰り出しローラ４３を介して、ワイヤ繰り出しテンション・ガイド４２に送られる。ワイヤ繰り出しテンション・ガイド４２では、ガス流をワイヤ６の側面に当てることで、ワイヤ６のスムースな送り出しを可能にしている。ワイヤ繰り出しテンション・ガイド４２から送り出されたワイヤ６は、その後、中継ローラ４８を介して、バック・テンション付加装置３３を貫通する。このバック・テンション付加装置３３によって、これより先のワイヤ６に対して、常に所定のバック・テンションがかけられることとなる。もっとも、クランパ３２が閉じているときのクランパ３２より先の部分には、このバック・テンションは及ばない。バック・テンション付加装置３３を貫通したワイヤ６は、ワイヤ・クランパ３２の一対のアーム間を通過して、ボンディング・アーム４７の先端部に取り付けられたボンディング・キャピラリ３１を貫通する。従って、ボンディング・ワイヤ先端部８は、常に、ボンディング・キャピラリ３１の下端（先端）から突出している。なお、中継ローラ４８、バック・テンション付加装置３３、ワイヤ・クランパ３２、ボンディング・アーム４７、ボンディング・キャピラリ３１等は、ボンディング・アーム制御部４９によって、制御又は駆動されている。   As shown in FIG. 15, the wire bonding head 40 is placed on an XY table and can move in the XY direction and can also move up and down in the Z-axis direction. A spool 44 around which the bonding wire 6 is wound is attached to the wire delivery unit 50 so as to be rotatable. The bonding wire 6 is sent from the spool 44 to the wire feeding tension guide 42 via the wire feeding roller 43. In the wire feed tension guide 42, the gas flow is applied to the side surface of the wire 6 so that the wire 6 can be smoothly fed out. Thereafter, the wire 6 fed from the wire feeding tension guide 42 passes through the back tension applying device 33 via the relay roller 48. By this back tension applying device 33, a predetermined back tension is always applied to the wire 6 beyond this. However, this back tension does not reach the portion ahead of the clamper 32 when the clamper 32 is closed. The wire 6 that has passed through the back tension applying device 33 passes between the pair of arms of the wire clamper 32 and passes through the bonding capillary 31 attached to the tip of the bonding arm 47. Accordingly, the bonding wire tip 8 always protrudes from the lower end (tip) of the bonding capillary 31. The relay roller 48, the back tension applying device 33, the wire clamper 32, the bonding arm 47, the bonding capillary 31 and the like are controlled or driven by a bonding arm control unit 49.

次に、バック・テンション付加装置３３の働きについて説明する。図１６に示すように、その中をワイヤ６が貫通する筒状構造をしており、常圧部５３と負圧部５４の間に狭隘部５５があり、狭隘部５５の直上のガス導入口５６からガス（導入ガス流５７）が流入して、上方に抜ける（排出ガス流５８）構造となっている。このため、負圧部５４に負圧（常圧部５３の圧力を基準とする）が発生して、ワイヤ先端側５１を引き込むワイヤ終端側５２へのバック・テンション（矢印）が形成されることとなる。   Next, the operation of the back tension applying device 33 will be described. As shown in FIG. 16, it has a cylindrical structure through which the wire 6 penetrates, and there is a narrow portion 55 between the normal pressure portion 53 and the negative pressure portion 54, and a gas introduction port directly above the narrow portion 55. Gas (introduced gas flow 57) flows in from 56 and escapes upward (exhaust gas flow 58). For this reason, a negative pressure (referenced to the pressure of the normal pressure portion 53) is generated in the negative pressure portion 54, and a back tension (arrow) to the wire end side 52 that draws the wire tip side 51 is formed. It becomes.

４．本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程のデバイス・装置断面フォロー等の説明（主に図１から図１４、図１７および図１９）
図１７又は図１９を参照しながら図１から図１４に基づいて、本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程の単位サイクル（ワイヤ１本をボンディングするサイクル）の流れを説明する。単位サイクルは、標準的には２００ミリ秒程度（図１９参照）である。 4). Description of device / apparatus cross-section follow-up of wire bonding process in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIG. 1 to FIG. 14, FIG. 17 and FIG. 19)
A flow of a unit cycle (a cycle of bonding one wire) of a wire bonding process in the method of manufacturing a semiconductor device according to the embodiment of the present application is described with reference to FIGS. explain. The unit cycle is typically about 200 milliseconds (see FIG. 19).

先ず、水平移動開始時点ｔ１（図１９）の後、図１に示すように、ボール形成時のキャピラリ・レベル（高さ）ｈ１（キャピラリの下端の高さを言う）において、クランパ３２を閉じた状態で、ワイヤ６の先端８ａと放電電極３４の間に放電を発生させ、それによりワイヤ６の先端８ａにボール部７を形成する。ボール部７を形成する際には、溶融ボールは、ワイヤ６を這い上がり、キャピラリ３１の先端部に若干接近する。ボール形成後、図２に示すように、クランパ３２を開いた状態で、目的とするボンディング・パッドに向けて更に水平移動を行う。このサイクルはじめから、降下開始までは、通常、３５ミリ秒程度である。   First, after the horizontal movement start time t1 (FIG. 19), as shown in FIG. 1, the clamper 32 is closed at the capillary level (height) h1 (referring to the height of the lower end of the capillary) during ball formation. In this state, a discharge is generated between the tip 8 a of the wire 6 and the discharge electrode 34, thereby forming the ball portion 7 at the tip 8 a of the wire 6. When forming the ball portion 7, the molten ball scoops up the wire 6 and slightly approaches the tip of the capillary 31. After the formation of the ball, as shown in FIG. 2, the horizontal movement is further performed toward the target bonding pad with the clamper 32 opened. The time from the beginning of this cycle to the start of descent is usually about 35 milliseconds.

次に、図３に示すように、第１ボンドへ向けての降下開始時点ｔ２（図１９）において、クランパ３２を開いた状態で、目的とするボンディング・パッドへ向けて第１の降下速度で降下を開始する。図中において、一対の一点破線は、それぞれ減速レベルｈ２（減速を開始する高さ）およびサーチ・レベルｈ３（最終着地速度になる高さ）を表す。この降下開始から、減速開始までは、通常、２０ミリ秒程度である。   Next, as shown in FIG. 3, at the time point t2 when descent toward the first bond starts (FIG. 19), the clamper 32 is opened and the first descent speed toward the target bonding pad is reached. Start descent. In the figure, a pair of dashed lines represent a deceleration level h2 (a height at which deceleration starts) and a search level h3 (a height at which the final landing speed is reached). The time from the start of descent to the start of deceleration is usually about 20 milliseconds.

次に、図４に示すように、第１ボンドへ向けての降下減速開始時点ｔ３（図１９）において、降下減速開始レベルｈ２に達すると、クランパ３２を開いた状態で、第１ボンドのサーチ・レベルｈ３に達するまでに、前記第１の降下速度よりも遅い第２の降下速度になるように、減速を開始する。すなわち、第１ボンドへの降下減速開始時点ｔ３（降下減速開始レベルｈ２）からボールの最終着地速度での降下開始時点ｔ４（第１ボンドのサーチ・レベルｈ３）間の平均降下速度は、ほぼ前記第１の降下速度よりも遅く、前記第２の降下速度よりも速い第３の降下速度となる。   Next, as shown in FIG. 4, at the descent / deceleration start time t3 (FIG. 19) toward the first bond, when the descent / deceleration start level h2 is reached, the clamper 32 is opened and the search for the first bond is performed. -Deceleration is started so that the second descending speed slower than the first descending speed is reached until the level h3 is reached. That is, the average descent speed from the descent deceleration start time t3 (descent deceleration start level h2) to the first bond to the descent start time t4 (first bond search level h3) at the final landing speed of the ball is substantially the same as that described above. The third descending speed is lower than the first descending speed and faster than the second descending speed.

次に、図６に示すように、ボールの最終着地速度での降下開始時点ｔ４（図１９）において、第１ボンドのサーチ・レベルｈ３に達すると、クランパ３２を開いた状態で、目的とするボンディング・パッド５へ向けて、前記第２の降下速度での降下を開始するとともに、ボンディング・キャピラリ３１に超音波と所定のボンディング荷重の印加を開始する。   Next, as shown in FIG. 6, when the descent start time t4 (FIG. 19) at the final landing speed of the ball reaches the search level h3 of the first bond, the target is maintained with the clamper 32 opened. The descent at the second descent speed is started toward the bonding pad 5 and the application of ultrasonic waves and a predetermined bonding load to the bonding capillary 31 is started.

次に、図７に示すように、ボールの着地時点ｔ５（図１９）において、ボンディング・キャピラリ３１に超音波と所定のボンディング荷重を印加しながら、且つ、クランパ３２を開いた状態で、第１ボンドのボール着地レベルｈ４（実際のボール７のボンディング・パッド５への着地高さ）に達する。この減速開始から、着地までは、通常、５ミリ秒程度である。   Next, as shown in FIG. 7, at the ball landing time t5 (FIG. 19), the ultrasonic wave and a predetermined bonding load are applied to the bonding capillary 31 and the clamper 32 is opened. The ball landing level h4 of the bond (the actual landing height of the ball 7 on the bonding pad 5) is reached. The time from the start of deceleration to the landing is usually about 5 milliseconds.

その後も、図８に示すように、第１ボンドのボール着地レベルｈ４を超えて、ボンディング・キャピラリ３１に超音波と所定のボンディング荷重を印加しながら、且つ、クランパ３２を開いた状態で、キャピラリ３１は降下を続けて、ボール部７を扁平にする。   After that, as shown in FIG. 8, the capillary landing level h4 is exceeded, the ultrasonic wave and the predetermined bonding load are applied to the bonding capillary 31, and the clamper 32 is opened. 31 continues to descend to flatten the ball portion 7.

その後、第１ボンドにおけるキャピラリ降下停止時点ｔ６（図１９）において、第１ボンドの終点レベルｈ５に達すると、ボンディング・キャピラリ３１に超音波と所定のボンディング荷重を印加しながら、且つ、クランパ３２を開いた状態で、キャピラリ３１の降下が停止する。この間にボンディング・パッド５とボール部７の結合が確実なものとなる。この着地から、降下停止までは、通常、１０ミリ秒程度である。   Thereafter, when the first bond end point level h5 is reached at the capillary drop stop time t6 (FIG. 19) in the first bond, the ultrasonic wave and a predetermined bonding load are applied to the bonding capillary 31 and the clamper 32 is moved. In the open state, the descent of the capillary 31 stops. During this time, the bonding pad 5 and the ball portion 7 are securely connected. The time from landing to stop descent is usually about 10 milliseconds.

ここで、若干先のステップに戻って、問題点を説明する。図１でボール部７を形成した後、図２に示すように、バック・テンション付加装置３３によりワイヤ６にバック・テンションをかけて、ボール部７がキャピラリ３１の先端に接触する位置まで、ワイヤ６を引き戻すようにしている。しかし、バック・テンション付加装置３３の内部汚れ等に起因して、間歇的にボール部７が図１のような状態で、図３以降の降下を開始する事態が発生することがある。そうすると、第１ボンドへ向けての降下減速開始時点ｔ３からボールの着地時点ｔ５（正常なボール部の着地時点）の前までの間においては、比較的質量が大きいボール部に下向きの慣性力が作用して、ボール部７が更に突出する。この結果、図５に示すように、ボール部７を含むワイヤ６が、目標とするボンディング・パッド５やその他の隣接するボンディング・パッドに早期に接触することがある。このような状態でそのまま第１ボンドを実行すると、ボールが隣接する一対のボンディング・パッドを跨いで接合されたり、目標とするボンディング・パッド５の所定の位置から大きくずれて接合される等の種々の不良（「ワイヤ突出起因不良」という）の原因となる。この際、ボール部７が完全にキャピラリ３１の守備範囲から外にシフトした結果、第１ボンドがされない場合は、後の第１ボンド結果の検査（第２の検査）で検出することができる。しかし、中途半端にシフトして、一応、見かけ上は第１ボンドがされた場合には、通常の検査では見逃されることとなる。このため、不良を大量に作る結果となりほか、製品の信頼性を著しく低下させる恐れがある。   Here, let us return to the slightly previous step and explain the problem. After the ball portion 7 is formed in FIG. 1, as shown in FIG. 2, the back tension is applied to the wire 6 by the back tension applying device 33 until the ball portion 7 contacts the tip of the capillary 31. 6 is pulled back. However, due to internal dirt or the like of the back / tension applying device 33, a situation may occur in which the ball portion 7 starts to descend as shown in FIG. As a result, a downward inertia force is applied to the ball portion having a relatively large mass between the time point d3 at which the descent and deceleration toward the first bond starts and the time point t5 before the ball landing time (normal landing time of the ball portion). By acting, the ball portion 7 further protrudes. As a result, as shown in FIG. 5, the wire 6 including the ball portion 7 may come into early contact with the target bonding pad 5 and other adjacent bonding pads. If the first bond is executed as it is in such a state, the ball is bonded across a pair of adjacent bonding pads, or the ball is bonded greatly deviated from a predetermined position of the target bonding pad 5. Cause a defect (referred to as “defect caused by wire protrusion”). At this time, if the first bond is not formed as a result of the ball portion 7 being completely shifted out of the defensive range of the capillary 31, it can be detected by a subsequent inspection (second inspection) of the first bond result. However, if it shifts halfway and the first bond is apparently made, it will be overlooked in the normal inspection. For this reason, in addition to the result of producing a large number of defects, the reliability of the product may be significantly reduced.

そこで、本実施の形態においては、ボール部７がキャピラリ３１の下端から過剰に突出していると、第１ボンドへ向けての降下減速開始時点ｔ３以降であって、ボールの正常な着地時点ｔ５の以前に、ボール部７を含むワイヤ６が、目標とするボンディング・パッド５またはそれに隣接するボンディング・パッド等の半導体チップ１の第１の主面１ａ上の導電部分に接触する可能性が高い点に着目した。すなわち、第１ボンドへ向けての降下減速開始時点ｔ３以降であって、ボールの正常な着地時点ｔ５の以前の第１検査期間ＴＰ（始点は降下減速開始時点ｔ３であり、終点はボールの実際の着地時点の直前である第１検査終点ｔｅである）内に、ボール部７を含むワイヤ６が、目標とするボンディング・パッド５またはそれに隣接するボンディング・パッド等の半導体チップ１の第１の主面１ａ上の導電部分に接触していないか否かを電気的に検査することにより、ワイヤ突出起因不良をモニタする。   Therefore, in the present embodiment, if the ball portion 7 protrudes excessively from the lower end of the capillary 31, it is after the descent deceleration start time t3 toward the first bond and at the normal landing time t5 of the ball. Previously, there is a high possibility that the wire 6 including the ball portion 7 is in contact with a conductive portion on the first main surface 1a of the semiconductor chip 1 such as the target bonding pad 5 or a bonding pad adjacent thereto. Focused on. That is, after the descent / deceleration start time t3 toward the first bond and before the normal landing time t5 of the ball, the first inspection period TP (the start point is the descent / deceleration start time t3 and the end point is the actual ball position). The wire 6 including the ball portion 7 is within a first bonding end 5 of the semiconductor chip 1 such as a target bonding pad 5 or a bonding pad adjacent thereto. The wire protrusion defect is monitored by electrically inspecting whether or not the conductive portion on the main surface 1a is in contact.

次に、図８以降のプロセスを説明する。図９に示すように、第２ボンドへの上昇開始時点ｔ７（図１９）において、ボンディング・キャピラリ３１への超音波と所定のボンディング荷重の印加を停止させて、クランパ３２を開いた状態で、ボール部７からボンディング・キャピラリ３１の先端までのワイヤ６の長さが第２ボンドに必要な長さになるまで、ボンディング・キャピラリ３１をワイヤ６に沿って上昇させる。この降下停止から、キャピラリ上昇までは、通常、１０ミリ秒程度である。   Next, the processes after FIG. 8 will be described. As shown in FIG. 9, at the start time t7 of rising to the second bond (FIG. 19), the application of ultrasonic waves and a predetermined bonding load to the bonding capillary 31 is stopped and the clamper 32 is opened. The bonding capillary 31 is raised along the wire 6 until the length of the wire 6 from the ball portion 7 to the tip of the bonding capillary 31 becomes a length necessary for the second bond. The time from the descent stop to the capillary rise is usually about 10 milliseconds.

この上昇開始時点ｔ７（図１９）の直後に、第１ボンドが確実に行われた否かを確認するための検査（第２の検査）を電気的に実行する。   Immediately after the rise start time t7 (FIG. 19), an inspection (second inspection) for confirming whether or not the first bond is surely performed is performed electrically.

次に、図１０に示すように、第２ボンドへのルーピング動作開始時点ｔ８（図１９）において、ボール部７からボンディング・キャピラリ３１の先端までのワイヤ６の長さが第２ボンドに必要な長さになると、それ以上ワイヤ６が送り出されないように、クランパ３２が閉じられる。この状態で、所定の経路で（たとえば、第２ボンドへの降下開始時点ｔ９までは水平移動して、その後、降下を開始する）第２ボンディング点（リード部４）へ接近するルーピング動作が開始される。第２ボンドへの降下減速開始時点ｔ１０（図１９）において、ボンディング・キャピラリ３１がリード部４の上面近傍まで降下すると、降下速度を減速するとともに、ボンディング・キャピラリ３１への超音波と所定のボンディング荷重の印加が開始する。   Next, as shown in FIG. 10, the length of the wire 6 from the ball portion 7 to the tip of the bonding capillary 31 is necessary for the second bond at the start time t8 of the looping operation to the second bond (FIG. 19). When the length is reached, the clamper 32 is closed so that no further wire 6 is fed out. In this state, a looping operation to approach the second bonding point (lead portion 4) is started on a predetermined path (for example, the horizontal movement is started until the descent start time t9 to the second bond and then the descent starts). Is done. When the bonding capillary 31 descends to the vicinity of the upper surface of the lead part 4 at the start of deceleration descent to the second bond t10 (FIG. 19), the descending speed is reduced and the ultrasonic waves to the bonding capillary 31 and predetermined bonding are performed. Application of load begins.

その後、図１１に示すように、クランパ３２を閉じた状態で、低速降下をしてワイヤ６の側面が着地する（リード部４の上面に接触する）。ボンディング・キャピラリ３１は、そのまま着地レベルを超えて、降下して、第２ボンドにおけるキャピラリ降下停止時点ｔ１１（図１９）において、第２ボンドの終点レベルｈ６に達すると、降下を停止する。その後、クランパ３２を閉じた状態で、ボンディング・キャピラリ３１への超音波と所定のボンディング荷重の印加を、次のサイクルのためのワイヤ繰り出し開始時点ｔ１２（図１９）まで継続する。これで、第２ボンドが完了したことになる。この第１ボンド完了直後のキャピラリ上昇から、この第２ボンドの完了までは、通常、８５ミリ秒程度である。   Thereafter, as shown in FIG. 11, with the clamper 32 closed, the side surface of the wire 6 is landed at a low speed (contacts the upper surface of the lead portion 4). The bonding capillary 31 descends beyond the landing level as it is, and when it reaches the end point level h6 of the second bond at the capillary descent stop time t11 (FIG. 19) in the second bond, the descent stops. Thereafter, with the clamper 32 closed, the application of ultrasonic waves and a predetermined bonding load to the bonding capillary 31 is continued until the wire feeding start time t12 (FIG. 19) for the next cycle. This completes the second bond. It usually takes about 85 milliseconds from the rise of the capillary immediately after the completion of the first bond to the completion of the second bond.

次に、図１２に示すように、次のサイクルのためのワイヤ繰り出し開始時点ｔ１２（図１９）において、ボンディング・キャピラリ３１への超音波と所定のボンディング荷重の印加を停止し、クランパ３２を開いた状態で、次のサイクルのワイヤ繰り出しのためのボンディング・キャピラリ３１の上昇を開始する。ワイヤ・クランプのための上昇停止又は減速時点ｔ１３（図１９）において、一旦、上昇を停止又は減速した状態で、クランパ３２を閉じる。その後、ワイヤ・カットおよび次の水平移動のための上昇開始時点ｔ１４（図１９）において、再びクランパ３２を閉じた状態で、ボンディング・キャピラリ３１の上昇を開始する。この直後に、図１３に示すように、ワイヤ・カットのタイミングｔｃ（図１９）において、ワイヤ６がカットされて、ワイヤの部分６ａとワイヤの部分６ｂに分離される。その後も、図１４に示すように、クランパ３２を閉じた状態で、次の水平移動のための上昇完了時点ｔ１５（次のサイクルの開始点ｔ１に対応）まで上昇を続ける。これで単位ボンディング・サイクルが完結する。なお、ワイヤ・カットのタイミングｔｃ（図１９）の直後に、ワイヤ６が正しくカットされたか否かを確認するための検査（第３の検査）を電気的に実行する。この第２ボンドの完了から、このサイクルの完了までは、通常、６０ミリ秒程度である。   Next, as shown in FIG. 12, at the time t12 (FIG. 19) at the start of wire feeding for the next cycle, the application of ultrasonic waves and a predetermined bonding load to the bonding capillary 31 is stopped, and the clamper 32 is opened. In this state, the assembling of the bonding capillary 31 for feeding the wire in the next cycle is started. At the time point t13 (FIG. 19) of ascending or decelerating for wire clamping, the clamper 32 is closed while the ascending is once stopped or decelerated. Thereafter, at the rising start time t14 (FIG. 19) for the wire cut and the next horizontal movement, the bonding capillary 31 starts to rise with the clamper 32 closed again. Immediately after this, as shown in FIG. 13, at the wire cut timing tc (FIG. 19), the wire 6 is cut and separated into a wire portion 6a and a wire portion 6b. Thereafter, as shown in FIG. 14, with the clamper 32 closed, the ascending is continued until the ascending completion time t15 (corresponding to the starting point t1 of the next cycle) for the next horizontal movement. This completes the unit bonding cycle. Immediately after the wire cut timing tc (FIG. 19), an inspection (third inspection) for confirming whether or not the wire 6 has been cut correctly is electrically executed. The time from the completion of this second bond to the completion of this cycle is typically about 60 milliseconds.

次に、これまでに説明した第１の検査、第２の検査、第３の検査等のワイヤ状態検査について、図１７に基づいて、更に説明する。図１７に示すように、半導体チップ１、リード・フレーム２（または配線基板等の基体部）、ボンディング・ワイヤ６、ワイヤ・ボンディング装置３０等からなる系は、電気的に見ると、ループ状回路３９（クローズド・ループまたはオープン・ループ）を形成している。検査回路４１からループをたどると、以下のようになる。検査回路４１からワイヤ・スプール４４、ワイヤ・スプール４４からワイヤ６へ、そして、ワイヤ６は、ワイヤ繰り出しローラ４３、ワイヤ繰り出しテンション付加用ガス流４６により側方のテンションを与えているワイヤ繰り出しテンション・ガイド４２、バック・テンション付加装置３３、ワイヤ・クランパ３２、ボンディング・キャピラリ３１等を経由して、ボール部７に至る。ここで、ボール部７を含むワイヤ６がボンディング・パッド５に接触又は連結されているときは、このループまたは電流通路は、更に延びて、ボンディング・パッド５から半導体チップ本体１の裏面１ｂを経て、リードフレーム２、リードフレーム等の基体部２が直接触れるワイヤ・ボンディング装置の導電部４５等を介して、検査回路４１の設置電極に戻る。ここで、ワイヤ６がボンディング・パッド５に接触も連結もしていないときは、完全なオープン・ループとなり、検査回路４１の両端子から見たループ状回路３９の抵抗値は非常に大きな値となる。また、基体部２が配線基板の場合（接着部材層１０が絶縁性の場合）には、その部分が容量素子のように作用するので、交流、高周波（たとえば１０ｋＨｚ程度、好適な範囲として１０００Ｈｚから１ＭＨｚ）またはパルス状の電圧又は電流（検査信号）を印加して、その際の検査回路４１の両端子から見たループ状回路３９の当該部分のリアクタンス等（具体的には、ワイヤがパッドに接触しているときのチップ裏面１ｂとヒート・ブロック４５等の間に介在する通常の電気容量値か、あるいは、オープンループに対応するほとんど「０」に近い容量値かを判定する）を測定する必要がある。また、直流的に測定する場合も、図１８について説明したように、ＣＭＩＳ構成のデバイスのように不純物構造が複雑なデバイスでは、通常、測定に適した微弱な電圧又は電流条件においては、一方向しか導通しないボンディング・パッドが必ず存在するので、検査期間内に少なくとも１度は、電圧又は電流方向を切り替える（順方向及び逆方向）ようにすれば、測定の信頼度を上げることができる。たとえば、検査期間を４ミリ秒から５ミリ秒程度とすると、順方向検査期間または逆方向検査期間は、２ミリ秒程度となる。なお、このとき、たとえば、先に正方向で導通が取れた場合は、逆方向に切り替えることは必要ではない。また、異常が検出された場合には、アラームを表示するとともに、ボンディング動作を適宜停止する。ここで、検査回路は、直流電圧又は電流、あるいは前記のような検査信号を供給でき、その際の検査回路４１の両端子から見たループ状回路３９の導通・非導通またはインピーダンス特性（交流的な導通・非導通という意味で）等を検出できるものであればよい。なお、直流測定は、比較的簡単な回路で済む反面、通常、２度以上測定する必要がある場合もある。一方、交流（高周波その他を含む）測定は、一回の測定で済む反面、通常、測定回路がやや複雑となる。以上は各検査に共通する事項である。   Next, wire state inspections such as the first inspection, the second inspection, and the third inspection described so far will be further described with reference to FIG. As shown in FIG. 17, a system comprising a semiconductor chip 1, a lead frame 2 (or a base part such as a wiring board), a bonding wire 6, a wire bonding apparatus 30 and the like is a loop circuit when viewed electrically. 39 (closed loop or open loop) is formed. Following the loop from the inspection circuit 41 is as follows. From the inspection circuit 41 to the wire spool 44, from the wire spool 44 to the wire 6, and to the wire 6, the wire feeding tension 43 is applied with a side tension by the wire feeding roller 43 and the wire feeding tension application gas flow 46. The ball part 7 is reached via the guide 42, the back tension applying device 33, the wire clamper 32, the bonding capillary 31 and the like. Here, when the wire 6 including the ball portion 7 is in contact with or connected to the bonding pad 5, this loop or current path further extends from the bonding pad 5 through the back surface 1 b of the semiconductor chip body 1. Returning to the installation electrode of the inspection circuit 41 through the conductive part 45 of the wire bonding apparatus or the like directly touching the base part 2 such as the lead frame 2 or the lead frame. Here, when the wire 6 is not in contact with or connected to the bonding pad 5, it becomes a complete open loop, and the resistance value of the loop circuit 39 viewed from both terminals of the inspection circuit 41 becomes a very large value. . Further, when the base portion 2 is a wiring board (when the adhesive member layer 10 is insulative), the portion acts like a capacitive element, so that alternating current, high frequency (for example, about 10 kHz, a suitable range from 1000 Hz) 1 MHz) or pulsed voltage or current (inspection signal) is applied, and reactance of the portion of the loop circuit 39 viewed from both terminals of the inspection circuit 41 (specifically, the wire is applied to the pad) It is determined whether it is a normal electric capacity value interposed between the chip back surface 1b and the heat block 45 or the like when in contact, or a capacity value almost close to “0” corresponding to the open loop). There is a need. Also, in the case of direct current measurement, as described with reference to FIG. 18, in a device having a complicated impurity structure such as a device having a CMIS structure, one-way operation is usually performed under a weak voltage or current condition suitable for measurement. Since there is always a bonding pad that conducts only, the reliability of measurement can be improved by switching the voltage or current direction (forward direction and reverse direction) at least once during the inspection period. For example, if the inspection period is about 4 to 5 milliseconds, the forward inspection period or the reverse inspection period is about 2 milliseconds. At this time, for example, if conduction is first obtained in the forward direction, switching in the reverse direction is not necessary. If an abnormality is detected, an alarm is displayed and the bonding operation is stopped as appropriate. Here, the inspection circuit can supply a DC voltage or current, or the above-described inspection signal, and the conduction / non-conduction of the loop circuit 39 viewed from both terminals of the inspection circuit 41 at that time or impedance characteristics (AC-like) It is only necessary to be able to detect such as continuity / non-conduction. Note that DC measurement requires a relatively simple circuit, but there are cases where it is usually necessary to measure two or more times. On the other hand, alternating current (including high frequency and others) measurement can be performed only once, but the measurement circuit is usually somewhat complicated. The above is a matter common to each inspection.

次に、第１の検査について説明する。この検査は、ボールの正常な着地時点ｔ５の前に、一回でも異常な着地がないか否かを確認するものであるから、第１検査期間ＴＰ内に連続的、断続的、または離散的（間歇的）に一回あるいは複数回、実行する。   Next, the first inspection will be described. Since this inspection is to confirm whether or not there is an abnormal landing even once before the normal landing time t5 of the ball, it is continuous, intermittent or discrete within the first inspection period TP. Run (intermittently) once or multiple times.

次に、第２の検査について説明する。この検査は、第１ボンドが正しく行われたか、あるいは、接合されなかったか、または一度接合された後、剥離したかを確認するものであるから、１本のワイヤ（第１ボンドから第２ボンドまで）に対して一度だけ実施すればよい。この検査は、（完全なオープン・ループの時と比較して）導通あり（直流測定）又はループ内の容量成分が比較的大きい（交流測定）等のとき、正常値である。また、この第２の検査を行う期間（第２検査期間）は、ボンディング・パッド５からボンディング・キャピラリ３１を引き上げてから、ボンディング・ワイヤ６の一部（側面）がリード部４にボンディングされる前までである。これは、リード部４にボンディング・ワイヤ６を接続した後も検査すると、1本のワイヤに対するワイヤ・ボンディング工程が完了するまでに、ボンディング・パッド５に接続されたボンディング・ワイヤ６の一端部側が剥がれたとしても、リード部４に接続されたワイヤ６を介して直流電流が流れてしまい、ワイヤ６の接合不良を検出することが困難となるためである。尚、本実施の形態では、図１９に示すように、第２ボンドへの上昇開始時点ｔ７の直後である。   Next, the second inspection will be described. Since this inspection is to confirm whether the first bond has been performed correctly, has not been bonded, or has been bonded once and then peeled off, one wire (from the first bond to the second bond) Up to once). This test is normal when there is continuity (compared to a fully open loop) (DC measurement) or the capacitance component in the loop is relatively large (AC measurement). Further, during this second inspection period (second inspection period), after the bonding capillary 31 is pulled up from the bonding pad 5, a part (side surface) of the bonding wire 6 is bonded to the lead portion 4. Until now. If the inspection is performed after the bonding wire 6 is connected to the lead portion 4, one end portion side of the bonding wire 6 connected to the bonding pad 5 is not processed until the wire bonding process for one wire is completed. Even if it peels off, it is because a direct current flows through the wire 6 connected to the lead part 4 and it becomes difficult to detect a bonding failure of the wire 6. In the present embodiment, as shown in FIG. 19, it is immediately after the rising start time t7 to the second bond.

次に、第３の検査について説明する。この検査は、ワイヤが正しくカットされているか否かを確認するものであり、１本のワイヤ（第１ボンドから第２ボンドまで）に対して一度だけ実施すればよい。この検査は、（完全なクローズド・ループと時と比較して）非導通（直流測定）又は非導通に対応する程度にループ内の容量成分が比較的小さいとき、正常値である。また、この第３の検査を行う機関（第３検査期間）は、ワイヤ・クランパが開かれた状態で、ボンディング・キャピラリ３１をボンディング・ワイヤ６に沿ってリード部４から後退させることによりボンディング・ワイヤ６をリード部４の近傍で切断してから、ボンディング・キャピラリ３１を貫通したワイヤの先端部に放電によりボール部を形成する前までである。尚、本実施の形態では、図１９に示すように、ワイヤ・カットのタイミングｔｃの直後である。   Next, the third inspection will be described. This inspection is to confirm whether or not the wire is cut correctly, and it is only necessary to perform it once for one wire (from the first bond to the second bond). This test is normal when the capacitive component in the loop is relatively small to the extent that it corresponds to non-conduction (DC measurement) or non-conduction (compared to time with a fully closed loop). In addition, the engine that performs the third inspection (third inspection period) moves the bonding capillary 31 back from the lead portion 4 along the bonding wire 6 while the wire clamper is opened. From the time when the wire 6 is cut in the vicinity of the lead portion 4 to the time before the ball portion is formed by discharge at the tip portion of the wire penetrating the bonding capillary 31. In the present embodiment, as shown in FIG. 19, it is immediately after the wire cut timing tc.

５．サマリ
以上本発明者によってなされた発明を実施の形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。 5). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. .

例えば、前記実施の形態では、半導体基板内の構造が比較的複雑なシリコン系のＣＭＩＳ ＦＥＴ集積回路を有する半導体チップ上のボンディング・パッドにワイヤをボンディングする例を具体的に説明したが、本願発明はこれに限定されるものではなく、シリコン系のその他の集積回路および単体デバイス、並びに、シリコン系以外の集積回路および単体デバイス等にも適用できることは言うまでもない。   For example, in the above-described embodiment, an example in which a wire is bonded to a bonding pad on a semiconductor chip having a silicon-based CMIS FET integrated circuit having a relatively complicated structure in the semiconductor substrate has been specifically described. However, the present invention is not limited to this, and needless to say, the present invention can be applied to other silicon-based integrated circuits and single devices, and non-silicon-based integrated circuits and single devices.

また、前記実施の形態では、金系のボンディング・ワイヤを使用した技術を具体的に説明したが、本願発明はこれに限定されるものではなく、銅系のボンディング・ワイヤを使用した技術にも、そのまま適用できることは言うまでもない。   In the above embodiment, the technique using a gold-based bonding wire has been specifically described. However, the present invention is not limited to this, and the technique using a copper-based bonding wire is also applicable. Needless to say, it can be applied as it is.

また、前記実施の形態では、最も一般的に使用されているサーモソニック・ボンディング技術を具体的に説明したが、本願発明はこれに限定されるものではなく、その他の方式のワイヤ・ボンディングにも適用できることは言うまでもない。すなわち、キャピラリを用いたボール＆ウエッジ・ボンディング等に広く適用できる。   In the above-described embodiment, the most commonly used thermosonic bonding technique has been specifically described. However, the present invention is not limited to this, and other types of wire bonding are also used. Needless to say, it can be applied. That is, the present invention can be widely applied to ball & wedge bonding using a capillary.

更に、前記実施の形態では、半導体チップ１のボンディング・パッド５にボンディング・ワイヤ６の一端部側を接続してから、ワイヤの他端部（終端部）側をリード部４に接続する、所謂、正ボンディング方式に対して本願発明を適用することについて説明したが、これに限定されるものではない。すなわち、リード部４にボンディング・ワイヤ６の一端部側を接続してから、ワイヤの他端部（終端部）側を半導体チップ１のボンディング・パッド５に接続する、所謂、逆ボンディング方式（すなわち、リード側）に対しても、本願発明を適用できる。   Further, in the above embodiment, after connecting one end portion side of the bonding wire 6 to the bonding pad 5 of the semiconductor chip 1, the other end portion (terminal portion) side of the wire is connected to the lead portion 4. The application of the present invention to the positive bonding method has been described, but the present invention is not limited to this. That is, after connecting one end portion of the bonding wire 6 to the lead portion 4, the other end portion (terminal portion) side of the wire is connected to the bonding pad 5 of the semiconductor chip 1. The present invention can also be applied to the lead side.

本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（ボール形成）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (ball formation) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンドのための水平移動）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (horizontal movement for the 1st bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンドのための初期降下）のデバイス・装置断面フォロー図である。It is a device and apparatus cross-sectional follow figure of the wire bonding process (initial fall for the 1st bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンドのための減速）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (deceleration for the 1st bond) in the manufacturing method of the semiconductor device of one embodiment of this application. ワイヤ・ボンディング工程（第１ボンドのための減速等）における技術的問題点を説明するためのデバイス・装置断面図である。It is a device and device sectional view for explaining a technical problem in a wire bonding process (deceleration for the first bond, etc.). 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンドのための着地直前の降下状態）のデバイス・装置断面フォロー図である。FIG. 3 is a device / apparatus cross-sectional follow-up view of a wire bonding step (a lowered state immediately before landing for a first bond) in a method of manufacturing a semiconductor device according to an embodiment of the present application; 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンドのための着地時点）のデバイス・装置断面フォロー図である。It is a device and apparatus cross-sectional follow figure of the wire bonding process (at the time of landing for the 1st bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第１ボンド終了時点）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (at the time of the 1st bond end) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第２ボンドのためのキャピラリ後退）のデバイス・装置断面フォロー図である。It is a device and apparatus cross-sectional follow figure of the wire bonding process (capillary retreat for 2nd bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第２ボンドのためのルーピング動作時）のデバイス・装置断面フォロー図である。It is a device and apparatus cross-sectional follow figure of the wire bonding process (at the time of the looping operation | movement for a 2nd bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第２ボンド完了時）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (at the time of the 2nd bond completion) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第２ボンド完了後のキャピラリ後退）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (capillary retreat after completion of the 2nd bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（第２ボンド完了後のワイヤ・カット）のデバイス・装置断面フォロー図である。It is a device and apparatus cross section follow figure of the wire bonding process (wire cut after the completion of the 2nd bond) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程（次のワイヤボンディング・サイクルのための上昇）のデバイス・装置断面フォロー図である。It is a device and apparatus cross-sectional follow figure of the wire bonding process (rise for the next wire bonding cycle) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法に使用するワイヤ・ボンディング装置のボンディング・ヘッド部の斜視図である。It is a perspective view of the bonding head part of the wire bonding apparatus used for the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法に使用するワイヤ・ボンディング装置のボンディング・ヘッド部のバック・テンション付加装置の模式断面図である。1 is a schematic cross-sectional view of a back tension applying device for a bonding head portion of a wire bonding device used in a method for manufacturing a semiconductor device according to an embodiment of the present application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ接触検査（ワイヤ飛び出し検査）に使用するループ状回路の説明図である。It is explanatory drawing of the loop-shaped circuit used for the wire contact test | inspection (wire pop-out test | inspection) in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法におけるワイヤ接触検査（ワイヤ飛び出し検査）の対象デバイス（半導体チップ）の各種のボンディング・パッドと内部構造とに関係を模式的に示すデバイス断面図である。It is device sectional drawing which shows typically the relationship between the various bonding pads and internal structure of the object device (semiconductor chip) of the wire contact test | inspection (wire protrusion test | inspection) in the manufacturing method of the semiconductor device of one embodiment of this application. . 本願の一実施の形態の半導体装置の製造方法におけるワイヤ・ボンディング工程の単位サイクルのプロセス・タイミング・チャートである。It is a process timing chart of the unit cycle of the wire bonding process in the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法における組み立て工程（リードフレーム準備）を説明するためのデバイス上面図（図２０（ａ））およびＸ−Ｘ’断面図（図２０（ｂ））である。FIG. 20A is a device top view (FIG. 20A) and an XX ′ cross-sectional view (FIG. 20B) for explaining an assembly process (lead frame preparation) in the semiconductor device manufacturing method according to the embodiment of the present application; is there. 本願の一実施の形態の半導体装置の製造方法における組み立て工程（ダイ・ボンディング）を説明するためのデバイス上面図（図２１（ａ））およびＸ−Ｘ’断面図（図２１（ｂ））である。FIG. 21A is a device top view (FIG. 21A) and an XX ′ cross-sectional view (FIG. 21B) for explaining an assembly process (die bonding) in the method for manufacturing a semiconductor device according to an embodiment of the present application; is there. 本願の一実施の形態の半導体装置の製造方法における組み立て工程（ワイヤ・ボンディング）を説明するためのデバイス上面図（図２２（ａ））およびＸ−Ｘ’断面図（図２２（ｂ））である。FIG. 22A is a device top view (FIG. 22A) and an XX ′ cross-sectional view (FIG. 22B) for explaining an assembly process (wire bonding) in the semiconductor device manufacturing method according to the embodiment of the present application; is there. 本願の一実施の形態の半導体装置の製造方法における組み立て工程（レジン封止）を説明するためのデバイス上面図（図２３（ａ））およびＸ−Ｘ’断面図（図２３（ｂ））である。FIG. 23A is a device top view (FIG. 23A) and a cross-sectional view taken along line XX ′ (FIG. 23B) for illustrating an assembly process (resin sealing) in the method for manufacturing a semiconductor device according to an embodiment of the present application. is there. 本願の一実施の形態の半導体装置の製造方法における組み立て工程（パッケージ・ダイシング）を説明するためのデバイス上面図（図２３（ａ））およびＸ−Ｘ’断面図（図２３（ｂ））である。FIG. 23A is a device top view (FIG. 23A) and an XX ′ cross-sectional view (FIG. 23B) for explaining an assembly process (package dicing) in the semiconductor device manufacturing method according to the embodiment of the present application; is there. 本願の一実施の形態の半導体装置の製造方法によって製造された半導体装置の上面図である。It is a top view of the semiconductor device manufactured by the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法によって製造された半導体装置の下面図である。It is a bottom view of the semiconductor device manufactured by the manufacturing method of the semiconductor device of one embodiment of this application. 本願の一実施の形態の半導体装置の製造方法によって製造された半導体装置の上面透視図（封止レジンを除去したもの）である。1 is a top perspective view (with a sealing resin removed) of a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present application; FIG. 本願の一実施の形態の半導体装置の製造方法によって製造された半導体装置の図２７のＸ−Ｘ’断面図である。FIG. 28 is a cross-sectional view of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the embodiment of the present application, taken along line X-X ′ in FIG. 27.

符号の説明Explanation of symbols

１ 半導体チップ（半導体基板）
１ａ 半導体チップの第１主面（デバイス面）
１ｂ 半導体チップの第２主面（裏面）
１ｐ Ｐ型単結晶シリコン半導体基板領域
２ リード・フレーム（または配線基板等の基体部）
３ ダイ・パッド部（チップ搭載部）
４ リード部
５ ボンディング・パッド（パッド、電極パッド）
５Ｇｎｄ 接地電源用ボンディング・パッド
５Ｖｄｄ Ｖｄｄ電源用ボンディング・パッド
５Ｉｎ 入力用ボンディング・パッド
５Ｏｕｔ 出力用ボンディング・パッド
６，６ａ，６ｂ ボンディング・ワイヤ（金線）
７ ボンディング・ワイヤ先端のボール部
８ ボンディング・ワイヤ先端部
８ａ ボンディング・ワイヤの元の先端部
９ ウエッジ・ボンディング部
１０ 接着部材層
１１ パッケージの上面
１２ パッケージの下面
１４ ダイ・パッド支持部
１５ 外枠部
１６ 中枠部
１７ 単位領域
２０ 封止レジン部
２１ レジン封止体
２２ Ｘ方向ダイシング・ライン
２３ Ｙ方向ダイシング・ライン
２４ 半導体装置
２５ｎ ＮチャネルＭＩＳＦＥＴ
２５ｎｄ （ＮチャネルＭＩＳＦＥＴの）Ｎ型ドレイン領域
２５ｎｇ （ＮチャネルＭＩＳＦＥＴの）Ｎ型ゲート電極
２５ｎｓ （ＮチャネルＭＩＳＦＥＴの）Ｎ型ソース領域
２５ｐ ＰチャネルＭＩＳＦＥＴ
２５ｐｄ （ＰチャネルＭＩＳＦＥＴの）Ｐ型ドレイン領域
２５ｐｇ （ＰチャネルＭＩＳＦＥＴの）Ｐ型ゲート電極
２５ｐｓ （ＰチャネルＭＩＳＦＥＴの）Ｐ型ソース領域
３０ ワイヤ・ボンディング装置
３１ ボンディング・キャピラリ
３２ ワイヤ・クランパ
３３ バック・テンション付加装置
３４ 放電電極
３５ 放電
３９ ループ状回路
４０ ワイヤ・ボンディング・ヘッド
４１ 検査回路
４２ ワイヤ繰り出しテンション・ガイド
４３ ワイヤ繰り出しローラ
４４ ワイヤ・スプール
４５ 基体部が直接触れるワイヤ・ボンディング装置の導電部
４６ ワイヤ繰り出しテンション付加用ガス流
４７ ボンディング・アーム
４８ 中継ローラ
４９ ボンディング・アーム制御部
５０ ワイヤ送り出し部
５１ ワイヤ先端側
５２ ワイヤ終端側
５３ 常圧部
５４ 負圧部
５５ 狭隘部
５６ ガス導入口
５７ 導入ガス流
５８ 排出ガス流
ｈ１ ボール形成時のキャピラリ・レベル（高さ）
ｈ２ 降下減速開始レベル
ｈ３ 第１ボンドのサーチ・レベル
ｈ４ 第１ボンドのボール着地レベル
ｈ５ 第１ボンドの終点レベル
ｈ６ 第２ボンドの終点レベル
ＮＣ Ｎ型コンタクト領域
ＮＰ Ｎ型保護素子
ＮＷ Ｎ型ウエル領域
ＰＣ Ｐ型コンタクト領域
ＰＰ Ｐ型保護素子
ＴＰ 第１検査期間
ｔ１ 水平移動開始時点
ｔ２ 第１ボンドへ向けての降下開始時点
ｔ３ 第１ボンドへ向けての降下減速開始時点
ｔ４ ボールの最終着地速度での降下開始時点
ｔ５ ボールの着地時点（ボールの正常な着地時点）
ｔ６ 第１ボンドにおけるキャピラリ降下停止時点
ｔ７ 第２ボンドへの上昇開始時点
ｔ８ 第２ボンドへのルーピング動作開始時点
ｔ９ 第２ボンドへの降下開始時点
ｔ１０ 第２ボンドへの降下減速開始時点
ｔ１１ 第２ボンドにおけるキャピラリ降下停止時点
ｔ１２ 次のサイクルのためのワイヤ繰り出し開始時点
ｔ１３ ワイヤ・クランプのための上昇停止又は減速時点
ｔ１４ ワイヤ・カットおよび次の水平移動のための上昇開始時点
ｔ１５ 次の水平移動のための上昇完了時点（次のサイクルの開始点ｔ１に対応）
ｔｃ ワイヤ・カットのタイミング
ｔｅ 第１検査終点 1 Semiconductor chip (semiconductor substrate)
1a First main surface (device surface) of a semiconductor chip
1b Second main surface (back surface) of semiconductor chip
1p P-type single crystal silicon semiconductor substrate region 2 Lead frame (or base portion of wiring board or the like)
3 Die pad part (chip mounting part)
4 Lead part 5 Bonding pad (pad, electrode pad)
5Gnd Bonding pad for ground power supply 5Vdd Bonding pad for Vdd power supply 5In Bonding pad for input 5Out Bonding pad for output 6,6a, 6b Bonding wire (gold wire)
7 Bonding wire tip ball portion 8 Bonding wire tip portion 8a Bonding wire original tip portion 9 Wedge bonding portion 10 Adhesive member layer 11 Upper surface of package 12 Lower surface of package 14 Die pad support portion 15 Outer frame portion 16 Middle frame portion 17 Unit region 20 Sealing resin portion 21 Resin sealing body 22 X direction dicing line 23 Y direction dicing line 24 Semiconductor device 25n N channel MISFET
25 nd (N channel MISFET) N type drain region 25 ng (N channel MISFET) N type gate electrode 25 ns (N channel MISFET) N type source region 25 p P channel MISFET
25 pd (P-channel MISFET) P-type drain region 25 pg (P-channel MISFET) P-type gate electrode 25 ps (P-channel MISFET) P-type source region 30 Wire bonding apparatus 31 Bonding capillary 32 Wire clamper 33 Back tension Additional Device 34 Discharge Electrode 35 Discharge 39 Loop Circuit 40 Wire Bonding Head 41 Inspection Circuit 42 Wire Feeding Tension Guide 43 Wire Feeding Roller 44 Wire Spool 45 Conducting Portion of Wire Bonding Device Directly Touching Base Unit 46 Wire Feeding Gas flow for tension application 47 Bonding arm 48 Relay roller 49 Bonding arm control unit 50 Wire delivery unit 51 Wire tip side 52 Wire end side 53 Normal pressure part 54 Negative pressure part 55 Narrow part 56 Gas introduction port 57 Introduction gas flow 58 Exhaust gas flow h1 Capillary level (height) at the time of ball formation
h2 descent deceleration start level h3 first bond search level h4 first bond ball landing level h5 first bond end point level h6 second bond end point level NC N-type contact region NP N-type protection element NW N-type well region PC P-type contact region PPP P-type protective element TP First inspection period t1 Horizontal movement start time t2 Descent start time toward the first bond t3 Descent deceleration start time toward the first bond t4 At the final landing speed of the ball D5 descent start time t5 Ball landing time (normal ball landing time)
t6 Capillary descent stop time at the first bond t7 Rise start time to the second bond t8 Looping operation start time to the second bond t9 Descent start time to the second bond t10 Descent deceleration start time to the second bond t11 Second Capillary descent stop time at bond t12 Wire feed start time for next cycle t13 Rise stop or deceleration time for wire clamp t14 Lift start time for wire cut and next horizontal movement t15 Next horizontal movement time Completion point for completion (corresponding to the start t1 of the next cycle)
tc Wire cut timing te First inspection end point

Claims (20)

以下の工程を含む半導体装置の製造方法：
（ａ）ワイヤ・ボンディング装置内において、先端にボール部を有するワイヤを貫通させたキャピラリを、半導体チップの第１の主面上のパッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを、前記第１の降下速度より遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリにより前記ボール部を前記パッドに押し付けることによって、前記ワイヤを前記パッドにボンディングする工程；
（ｅ）前記工程（ｂ）および（ｃ）を含む区間内であって、前記ボール部が前記パッドに接触する前の第１検査期間内に、前記ワイヤ・ボンディング装置内において、前記ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記キャピラリからの前記ワイヤの不所望な突出の有無を検出する第１の検査を実行する工程。 A semiconductor device manufacturing method including the following steps:
(A) in the wire bonding apparatus, a step of lowering a capillary having a wire having a ball part at the tip thereof toward the pad on the first main surface of the semiconductor chip at a first lowering speed;
(B) after the step (a), decelerating the capillary to a second lowering speed slower than the first lowering speed in the wire bonding apparatus;
(C) after the step (b), the step of lowering the capillary at the second lowering speed in the wire bonding apparatus to bring the ball portion into contact with the pad;
(D) After the step (c), the step of bonding the wire to the pad by pressing the ball portion against the pad by the capillary in the wire bonding apparatus;
(E) In a section including the steps (b) and (c), and within the first inspection period before the ball portion contacts the pad, the wire, the wire, Performing a first test for detecting the presence or absence of undesired protrusion of the wire from the capillary using a loop circuit including a semiconductor chip and a part of each of the wire bonding apparatus; 前記１項の半導体装置の製造方法において、更に以下の工程を含む：
（ｆ）前記工程（ｄ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを前記ワイヤに沿って、前記パッドから後退させる工程；
（ｇ）前記工程（ｆ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを前記半導体チップの外部のリード部に向けて移動させる工程；
（ｈ）前記工程（ｇ）の後、前記ワイヤ・ボンディング装置内において、前記ワイヤの側面を前記キャピラリによって、前記リード部に押し付けることによって、前記ワイヤを前記リード部にボンディングする工程；
（ｉ）前記工程（ｄ）の後であって、前記工程（ｈ）の前に、前記ワイヤ・ボンディング装置内において、前記ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ワイヤの前記ボンディング・パッドに対するボンディング状態を検出する第２の検査を実行する工程。 The method for manufacturing a semiconductor device according to the item 1, further includes the following steps:
(F) After the step (d), the step of retracting the capillary from the pad along the wire in the wire bonding apparatus;
(G) After the step (f), the step of moving the capillary toward the lead portion outside the semiconductor chip in the wire bonding apparatus;
(H) After the step (g), in the wire bonding apparatus, the side surface of the wire is pressed against the lead portion by the capillary to bond the wire to the lead portion;
(I) After the step (d) and before the step (h), the wire bonding apparatus includes a part of each of the wire, the semiconductor chip, and the wire bonding apparatus. Performing a second test for detecting a bonding state of the wire to the bonding pad using a loop circuit; 前記２項の半導体装置の製造方法において、
（ｊ）前記工程（ｈ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリをワイヤ・クランパが開かれた状態で、前記ワイヤに沿って、前記リード部から後退させる工程；
（ｋ）前記工程（ｊ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリをワイヤ・クランパが開かれた状態で、前記ワイヤに沿って、前記リード部から後退させることにより、前記ワイヤを前記リード部の近傍で切断する工程；
（ｌ）前記工程（ｋ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを貫通した前記ワイヤの先端部に放電によりボール部を形成する工程；
（ｍ）前記工程（ｋ）の後であって、前記工程（ｌ）の前に、前記ワイヤ・ボンディング装置内において、前記ボンディング・ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記ワイヤが正常に切断されたか否かを検査する第３の検査を実行する工程。 In the method of manufacturing a semiconductor device according to the item 2,
(J) After the step (h), in the wire bonding apparatus, the capillary is retracted from the lead portion along the wire with the wire clamper opened;
(K) After the step (j), in the wire bonding apparatus, the capillary is retracted from the lead portion along the wire in a state where the wire clamper is opened. Cutting in the vicinity of the lead portion;
(L) After the step (k), in the wire bonding apparatus, a step of forming a ball portion by discharge at the tip of the wire penetrating the capillary;
(M) After the step (k) and before the step (l), in the wire bonding apparatus, a part of each of the bonding wire, the semiconductor chip, and the wire bonding apparatus Performing a third inspection for inspecting whether or not the wire is normally cut using a loop-shaped circuit including: 前記１項の半導体装置の製造方法において、前記半導体チップは金属製のリード・フレーム上に固定されている。     In the method for manufacturing a semiconductor device according to the item 1, the semiconductor chip is fixed on a metal lead frame. 前記１項の半導体装置の製造方法において、前記半導体チップは配線基板上に固定されている。     In the method of manufacturing a semiconductor device according to the item 1, the semiconductor chip is fixed on a wiring board. 前記１項の半導体装置の製造方法において、前記第１の検査は直流電流又は電圧を印加して実行される。     In the method of manufacturing a semiconductor device according to the item 1, the first inspection is performed by applying a direct current or a voltage. 前記１項の半導体装置の製造方法において、前記第１の検査中において、電流又は電圧方向を切り替える。     In the method of manufacturing a semiconductor device according to the item 1, the current or voltage direction is switched during the first inspection. 前記１項の半導体装置の製造方法において、前記第１の検査は交流電流又は電圧を印加して実行される。     In the method of manufacturing a semiconductor device according to the item 1, the first inspection is performed by applying an alternating current or a voltage. 前記１項の半導体装置の製造方法において、前記第１の検査は高周波電流又は電圧を印加して実行される。     In the method for manufacturing a semiconductor device according to the item 1, the first inspection is performed by applying a high-frequency current or voltage. 前記１項の半導体装置の製造方法において、前記第１の検査はパルス状の電流又は電圧を印加して実行される。     In the method for manufacturing a semiconductor device according to the item 1, the first inspection is performed by applying a pulsed current or voltage. 前記１項の半導体装置の製造方法において、前記工程（ｂ）は、以下の下位工程を含む：
（ｂ１）前記キャピラリを、前記第１の降下速度より遅く、前記第２の降下速度より速い第３の降下速度まで減速させる工程；
（ｂ２）前記工程（ｂ１）の後、前記キャピラリを、前記第３の降下速度で降下させる工程；
（ｂ３）前記工程（ｂ２）の後、前記第３の降下速度で降下させる工程。 In the method for manufacturing a semiconductor device according to the item 1, the step (b) includes the following sub-steps:
(B1) decelerating the capillary to a third lowering speed that is slower than the first lowering speed and faster than the second lowering speed;
(B2) After the step (b1), lowering the capillary at the third lowering speed;
(B3) A step of lowering at the third lowering speed after the step (b2). 前記１項の半導体装置の製造方法において、前記工程（ｃ）において、前記ボール部が前記パッドに接触する際には、前記キャピラリへの超音波およびボンディング荷重の印加が開始されている。     In the method of manufacturing a semiconductor device according to the item 1, application of ultrasonic waves and a bonding load to the capillary is started when the ball part contacts the pad in the step (c). 前記１項の半導体装置の製造方法において、前記ワイヤは、金を主要な成分とする。     In the method of manufacturing a semiconductor device according to the item 1, the wire contains gold as a main component. 前記１項の半導体装置の製造方法において、前記パッドの主要部は、アルミニウムを主要な成分とする。     In the method of manufacturing a semiconductor device according to the item 1, the main part of the pad contains aluminum as a main component. 前記１項の半導体装置の製造方法において、前記第１の検査は、前記工程（ｂ）の開始後であって、前記工程（ｃ）における前記ボール部の前記パッドへの正常な接触の前に、前記ボール部を含む前記ワイヤの一部が、前記半導体チップの前記第１の主面上の導電部に接触したか否かを検査する。     In the method of manufacturing a semiconductor device according to the item 1, the first inspection is performed after the start of the step (b) and before the normal contact of the ball portion with the pad in the step (c). Then, it is inspected whether a part of the wire including the ball portion is in contact with the conductive portion on the first main surface of the semiconductor chip. 前記１項の半導体装置の製造方法において、前記第１検査期間内に、連続的、断続的、または離散的に複数回、前記第１の検査を実行する。     In the method of manufacturing a semiconductor device according to the item 1, the first inspection is executed a plurality of times continuously, intermittently or discretely within the first inspection period. 前記１項の半導体装置の製造方法において、前記第１の検査は、１０００Ｈｚから１ＭＨｚの範囲内の高周波電流又は電圧を印加して実行される。     In the method for manufacturing a semiconductor device according to the item 1, the first inspection is performed by applying a high-frequency current or voltage within a range of 1000 Hz to 1 MHz. 前記１７項の半導体装置の製造方法において、高周波電流又は電圧は、実質的に正弦波交流である。     In the method for manufacturing a semiconductor device according to the item 17, the high-frequency current or voltage is substantially sinusoidal alternating current. 以下の工程を含む半導体装置の製造方法：
（ａ）ワイヤ・ボンディング装置内において、先端にボール部を有するワイヤを貫通させたキャピラリを、半導体チップの第１の主面上のパッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを、前記第１の降下速度より遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記ワイヤ・ボンディング装置内において、前記キャピラリにより前記ボール部を前記パッドに押し付けることによって、前記ワイヤを前記パッドにボンディングする工程、
ここで、前記工程（ｂ）の開始の後であって、前記ボール部が前記パッドに接触する前の第１検査期間内に、前記ワイヤ・ボンディング装置内において、前記ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記キャピラリからの前記ボンディング・ワイヤの不所望な突出の有無を検出する第１の検査を実行する。 A semiconductor device manufacturing method including the following steps:
(A) in the wire bonding apparatus, a step of lowering a capillary having a wire having a ball part at the tip thereof toward the pad on the first main surface of the semiconductor chip at a first lowering speed;
(B) after the step (a), decelerating the capillary to a second lowering speed slower than the first lowering speed in the wire bonding apparatus;
(C) after the step (b), the step of lowering the capillary at the second lowering speed in the wire bonding apparatus to bring the ball portion into contact with the pad;
(D) After the step (c), the step of bonding the wire to the pad by pressing the ball portion against the pad by the capillary in the wire bonding apparatus;
Here, after the start of the step (b) and within a first inspection period before the ball portion contacts the pad, the wire, the semiconductor chip, and the A first test for detecting the presence or absence of undesired protrusion of the bonding wire from the capillary is performed using a loop circuit including a part of each of the wire bonding apparatuses. 以下の工程を実行することができるワイヤ・ボンディング装置：
（ａ）先端にボール部を有するワイヤを貫通させたキャピラリを、半導体チップの第１の主面上のパッドに向けて、第１の降下速度で降下させる工程；
（ｂ）前記工程（ａ）の後、前記第１の降下速度より遅い第２の降下速度まで減速させる工程；
（ｃ）前記工程（ｂ）の後、前記キャピラリを前記第２の降下速度で降下させて、前記ボール部を前記パッドに接触させる工程；
（ｄ）前記工程（ｃ）の後、前記キャピラリにより前記ボール部を前記パッドに押し付けることによって、前記ワイヤを前記パッドにボンディングする工程；
（ｅ）前記工程（ｂ）および（ｃ）を含む区間であって、前記ボール部が前記パッドに接触する前に、前記ワイヤ、前記半導体チップおよび前記ワイヤ・ボンディング装置のそれぞれの一部を含むループ状回路を用いて、前記キャピラリからの前記ワイヤの不所望な突出の有無を検出する第１の検査を実行する工程。 Wire bonding equipment that can perform the following steps:
(A) a step of lowering a capillary through which a wire having a ball part at the tip is directed toward a pad on the first main surface of the semiconductor chip at a first lowering speed;
(B) after the step (a), decelerating to a second lowering speed slower than the first lowering speed;
(C) After the step (b), lowering the capillary at the second lowering speed to bring the ball portion into contact with the pad;
(D) After the step (c), the step of bonding the wire to the pad by pressing the ball portion against the pad with the capillary;
(E) A section including the steps (b) and (c), and includes a part of each of the wire, the semiconductor chip, and the wire bonding apparatus before the ball portion contacts the pad. Performing a first test for detecting the presence or absence of an undesired protrusion of the wire from the capillary using a loop circuit;
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104772417A (en) * 2014-01-15 2015-07-15 库利克和索夫工业公司 Short tail recovery techniques in wire bonding operations
WO2015122410A1 (en) * 2014-02-14 2015-08-20 株式会社新川 Wire bonding apparatus and semiconductor device manufacturing method
CN109003909A (en) * 2017-06-07 2018-12-14 三菱电机株式会社 The manufacturing method of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104772417A (en) * 2014-01-15 2015-07-15 库利克和索夫工业公司 Short tail recovery techniques in wire bonding operations
WO2015122410A1 (en) * 2014-02-14 2015-08-20 株式会社新川 Wire bonding apparatus and semiconductor device manufacturing method
CN106165076A (en) * 2014-02-14 2016-11-23 株式会社新川 Throwing device and the manufacture method of semiconductor device
JPWO2015122410A1 (en) * 2014-02-14 2017-03-30 株式会社新川 Wire bonding apparatus and semiconductor device manufacturing method
US9899348B2 (en) 2014-02-14 2018-02-20 Shinkawa Ltd. Wire bonding apparatus and method of manufacturing semiconductor device
CN106165076B (en) * 2014-02-14 2019-01-01 株式会社新川 The manufacturing method of throwing device and semiconductor device
CN109003909A (en) * 2017-06-07 2018-12-14 三菱电机株式会社 The manufacturing method of semiconductor device
CN109003909B (en) * 2017-06-07 2023-01-06 三菱电机株式会社 Method for manufacturing semiconductor device

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