JP2010122820A - Compile device and compile method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce unnecessary recovery codes while using a pop instruction with a recovery code of a callee-save register. <P>SOLUTION: A compile device has capabilities of: detecting a recovery unnecessary register at an exit of a function; determining a saving order and a recovery order of the callee-save register taking the recovery unnecessary register into consideration; reflecting a total size of the registers which have become unnecessary of recovery in update size of a stack register without generating the recovery code of recovery unnecessary register. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a compiling device, a compiling method, and a compiler that reduce the code size and execution time of an object program in a computer utilization technique. In particular, with respect to a recovery code reduction method for a call-save register using a stack operation instruction such as a push / pop instruction, a code string for recovering only a call-save register necessary at a function exit is generated without increasing the number of instructions. The present invention relates to a compiling device, a compiling method, and a compiler that reduce a recovery code of a callee-save register, reduce a recovery code of a callee-save register that generates an object program having a small code size and good execution performance.

  In a compiler that converts source code into executable code, register saving and recovery are required at the function call destination when a function call is made. A register that needs to be saved and restored at a function call destination is generally called a “calle-save register”. The save / restore location of the callee-save register is usually secured on a stack set in advance in the memory. Also, a register for storing a value (stack pointer) indicating the top position of the stack immediately after the function call is prepared, and this register is referred to as a stack register (hereinafter referred to as SP) in this specification. To do.

  An example of data saving and recovery processing that is generally performed is as follows. As shown in FIG. 12A, the function entry code saves the callee-save register and subtracts the address corresponding to the SP register size. In order to secure a work area (corresponding to -α in the figure) used in the function after executing with an instruction (push instruction) for storing the data in the callee-save register on the stack pointed to by the SP after subtraction The stack register update instruction is executed by the add instruction.

  On the other hand, as shown in FIG. 12B, the function exit code executes the update instruction of the stack register SP with the add instruction, and then restores the callee-save register from the stack pointed to by the SP to the callee-save register. Is loaded with an instruction (pop instruction) for adding an address corresponding to the register size to SP.

A technique disclosed in Patent Document 1 is known for saving and restoring a callee-save register as described above.
JP 2008-71065 A

  Here, a recovery code (pop instruction) in the case where there are a plurality of function exits and only a part of the saved call-save register is defined on a path from the function entry to a function exit will be considered. In this case, since only the defined call-save register needs to be recovered at the function exit, it is assumed that the recovery code of only the necessary register is generated by the pop instruction. However, the pop instruction is an instruction including a mechanism for updating the stack address in addition to a mechanism for recovering a value from the stack to the register. Therefore, if the recovery code is simply reduced, the value of the register to be recovered is recovered from a stack address different from that at the time of saving, and illegal code is executed.

  Therefore, an object of the present invention is to provide means for reducing unnecessary recovery codes while using a pop instruction in the recovery code of a callee-save register.

  The present invention includes a first processor that performs arithmetic processing, and a storage unit that stores information used by the processor, and that compiles a source program including a function and generates an object program including a stack operation instruction In the apparatus, a syntax analysis unit that reads the source program and generates an intermediate code, and a register allocation that allocates a register of a second processor that constitutes a computer that reads the intermediate code and executes the object program to the intermediate code And a code generation unit that generates an object code from the intermediate code allocated to the register and outputs an object program, and the storage unit includes target information storing information on the register of the second processor; Before being assigned to the function First register information for storing register information, and second register information for storing the save order and recovery order of the registers, and the code generation unit is assigned to the entry and exit of the function A definition register information collection unit that collects information on the registers and stores the information in the first register information; and a saving order of the registers assigned to the function entry and exit by reading the first register information A save / recovery order determination unit that determines a recovery order, and a save / recovery code generation unit that generates a save code and a recovery code of the register according to the save order and the recovery order determined by the save / recovery order determination unit. And a save / recovery code generation unit generates a save code for the register at the entry of the function according to the save order of the registers, and stores the first register information. And a register that is generated on the path from the entry to the exit of the function from the save order and the recovery order and generates a recovery code for each exit of the function, and is not defined on the path The stack address update instruction for correcting the stack address by the sum of the register sizes is generated at the exit of the function.

  Therefore, according to the present invention, when generating an object code of a function having a plurality of exits, unnecessary recovery code of the callee-save register can be reduced, so that the code size of the object program is not increased. It is possible to generate an object program (execution code) with good execution performance.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a configuration diagram of a computer system (compiler) in which a compiler according to the present invention operates. The computer system 200 includes a CPU (or processor) 201 that performs arithmetic processing, a display device 202 that displays information, a keyboard 203 that inputs information, a main storage device 204 that stores information used by the CPU 201, And an external storage device 205 for storing information. The keyboard 203 accepts a compiler activation command from the user. The compiler end message and error message are displayed on the display device 202. The external storage device 205 is configured by an HDD or a nonvolatile memory, and stores a source program 206 and an object program 207. The main memory 204 stores a compiler 208 that reads the source program 206 and generates an object program 207, an intermediate code 209, a definition register information table 210, a register information table 211, and a target information table 212 that are necessary in the compilation process. Is done. Compile processing is performed by the CPU 201 executing a compiler (program) 208.

  The target information table 212 stores in advance information related to the configuration of a computer system (target system) 250 (see FIG. 2) that executes the object program 207. In the target information table 212, for example, the CPU type of the target system 250, the types and numbers of available registers, the type of OS running on the target system, and the like are stored in advance. The compiler 208 executes a compile process for reading the configuration of the target system from the target information table 212 and generating the object program 207.

  The compiler 208 creates a definition register information table 210 that holds the allocation (definition) state of the registers of the target system 250 as will be described later in the course of performing the compilation process, and the target stored in the definition register information table 210. A register information table 211 that sets the importance of the registers of the system is generated as described later.

  The external storage device 205 functions as a storage medium that stores the compiler 208. When the CPU 201 receives a compiler activation command from the keyboard 203, the CPU 201 reads the compiler 208 from the external storage device 205 into the main storage device 204, reads the source program 206, and executes compilation processing. At this time, it is assumed that the target information table 212 is read into the main storage device 204 in advance.

  Note that an OS (not shown) may be read into the main storage device 204 of FIG. 1 and executed by the CPU 201, and the compiler 208 may be executed on the OS.

  FIG. 2 is a configuration diagram of a computer system (hereinafter referred to as a target system) 250 that executes the object program 207 generated by the compiler 208 of the present invention. The target system 250 includes a CPU (or processor) 251 that performs arithmetic processing, a display device 252 that displays information, a keyboard 253 that inputs information, and a main storage device 254 that stores information used by the CPU 251. And an external storage device 255 for storing information. The keyboard 253 accepts an activation command for the object program 207 from the user. An execution result, an end message, or an error message of the object program 207 is displayed on the display device 252. The external storage device 255 is composed of an HDD or a non-volatile memory, and stores the object program 207 generated by the compiling device 200. The main storage device 254 stores an OS 270 and an object program 207. The OS 270 secures a stack area 260 on the main storage device 254.

  In this example, R1, R2, R3,..., Rn, SP (stack registers) exist as registers of the CPU 251, and the stack pointer stored in the SP indicates the address of the stack area 260. Note that R1 to R3,..., Rn indicate general-purpose registers, for example.

  When the CPU 251 receives an activation command for the object program 207 from the keyboard 253, the CPU 251 reads the object program 207 from the external storage device 255 into the main storage device 254 and executes it. Note that the object program 207 is transferred from the compiling device 200 to the target system 250 via a network (not shown).

  FIG. 3 shows a processing procedure of the compiler 208 operating in the computer system 200 of FIG.

  The processing of the compiler 208 is performed in the order of syntax analysis 301 of the source program 206, code optimization 302, register allocation 303, and code generation 304 that generates object code as the object program 207.

  In the syntax analysis 301, the compiler 208 performs a syntax analysis with the source program 206 as an input, and outputs an intermediate code 209. In the code optimization 302, the compiler 208 inputs the intermediate code 209, applies optimization such as loop structure conversion and partial redundancy deletion, and outputs the result as the converted intermediate code 209.

  In the register allocation 303, the compiler 208 allocates the registers R1 to R3,..., Rn of the processor 251 of the target system 250 to each node (each processing element) of the intermediate code 209. In the code generation 304, the compiler 208 converts the intermediate code 209 into the object program 207 and outputs it as the object program 207. For the parsing 301, code optimization 302, and register allocation 303, a known or well-known technique may be applied.

  A save-save register (hereinafter referred to as “calle register”) save code and recovery code reduction process 305 is a save code (Push instruction) or recovery code (Pop) required at the entry or exit of a function described in the source program 206. This is a process for reducing the code size of the object program 207 to be generated and generated in the code generation 304.

  The save code is an instruction code that saves the contents of the callee registers (for example, R1 to R3) of the target system 250 in the stack area 260 of the target system 250 and updates the stack pointer. In particular, the push instruction is an instruction for subtracting the stack address by the size of the register to be saved and then storing the data of the register in the area indicated by the stack address after the subtraction.

  The recovery code is an instruction code for restoring the contents of the call register (for example, R1 to R3) of the target system 250 from the stack area 260 of the target system 250 and updating the stack pointer. In particular, the pop instruction is an instruction for adding the stack address by the size of the register after loading data from the area indicated by the stack address to the register.

  FIG. 4 shows an example of the definition register information table 210. It is generated on the main memory 204 by the compiler 208. The definition register information table includes columns such as an exit block 801, a definition register set 802, a weight 803, a processed flag 804, and the like.

  The exit block 801 registers exit block information that exists in a function described by the source program 206. The exit block refers to the basic block that is executed last in the called function. On the other hand, the entry block indicates a basic block that is executed first in the called function. In the source program 206 shown in FIG. 11, the entry block indicates the process on the third line where the actual processing of the function is performed, and the exit block performs the process on the fifth line or the eleventh line that returns to the caller. The example of FIG. 11 shows an example in which there are two function exit blocks depending on the conditional branch instruction “if”.

  The definition register set 802 registers a set of callee registers defined in the intermediate code 209 on the path (processing process) from the function entry block to the exit block. Here, the set of callee registers means that the compiler 208 allocates (defines) the registers of the CPU 251 of the target system for each block for a certain function in the process of register allocation 303 in FIG. The register numbers (names) or identifiers defined (allocated) on the path from the entry block to the exit block are listed.

  The weight 803 registers the importance of each exit block. Here, the importance is an index showing how much each exit block is executed, and the higher the importance, the higher the execution frequency of the exit block. As a technique for obtaining this importance, a method that the compiler 208 obtains at the time of compilation (referred to as a static technique) or a method that obtains by executing the object program 207 generated by the compiler 208 (this is referred to as a dynamic technique). ) Etc. are considered. The processed flag 804 is a flag used when determining whether or not the processing of the corresponding exit block has been completed in various processes in the compiler 208.

  FIG. 5A shows an example of the register information table 211. The register information table 211 is generated on the main storage device 204 by the compiler 208. The register information table 211 includes columns such as a register number 901, a weight 902, a processed flag 903, and the like.

  The register number 901 registers a callee register number (or identifier) defined by the intermediate code 209 among the register numbers (or identifiers) of the CPU 251 of the target system 250. The weight 902 registers the importance of each register. The importance is an index indicating how much the recovery code of the register is executed. The higher the importance, the higher the execution frequency of the recovery code of the register. This importance can be calculated from the definition register set 802 and the weight 803 in the definition register information table 210. Details will be described with reference to FIG. The processed flag 903 is a flag used when determining whether or not the processing of the corresponding register is completed in various processes. 5A shows a state before sorting of the register information table 211, and FIG. 5B shows a state after sorting by the callee register save code and recovery code reduction process 305. FIG.

  FIG. 6 shows a processing procedure of the callee register save code and recovery code reduction process 305 shown in FIG. In step 101, the compiler 208 collects register information defined on the path from the entry block of the source program 206 to the exit block. Note that the processing of step 101 can be performed for each function or for each subroutine.

  In step 102, the compiler 208 determines the save order or the recovery order of the callee register. In step 103, the compiler 208 generates a save register save code (for example, a Push instruction) in the entry block of the function. In step 104, the recovery code (for example, Pop instruction) of the callee register in consideration of the recovery order obtained in step 102 is generated in the function exit block by the compiler 208. By considering this recovery order, unnecessary recovery codes can be reduced from the object program 207. Details of the processes shown in the flowchart of FIG. 6 will be described with reference to FIGS. 7, 8, 9, and 10.

  FIG. 7 shows a processing procedure of the definition register information collection 101 shown in FIG. In step 401, the compiler 208 reads the intermediate code 209 and registers all exit blocks in the function in the exit block set. Note that the compiler 208 secures a predetermined area on the main storage device 204 as a variable for the exit block set. Similarly, a basic block set, a processed basic block set, and the like described below are also used as variables by the compiler 208 to secure a predetermined area on the main storage device 204.

  In step 402, the compiler 208 determines whether the exit block set is empty. If it is not empty, it means that there is an exit block for which processing has not been completed, and the process proceeds to step 403. In step 403, the definition register set 802 corresponding to the exit block that has not been processed is emptied for initialization. In step 404, the processed basic block set is emptied for initialization. This is provided so that the same basic block is not processed many times. The basic block indicates a series of arithmetic processing among one function (or subroutine). For example, one line described in the source program 206 in FIG. 11 is handled as a basic block.

  In step 405, the exit block set is registered in the basic block set. In step 406, it is determined whether the basic block set is empty. If the basic block set is empty, the process proceeds to step 411. If the basic block set is not empty, the process proceeds to step 407. In step 407, the head element is extracted from the basic block set. The extracted top element is deleted from the basic block set.

  In step 408, the compiler 208 traces all instructions in the basic block with respect to the basic block extracted in step 407, and registers the registers defined by the respective instructions in the definition register set 802 of the definition register information table 210. Go. In step 409, the processed basic block is registered in the processed basic block set. In step 410, the basic block executed immediately before the basic block extracted in step 407 is traced. If the basic block executed immediately before is not registered in the processed basic block set, the basic block is set as the basic block set. Register and return to step 406.

  By repeating the processing of step 406 to step 410, a definition register set defined on the path from the entry block to a certain exit block can be obtained.

  Since the basic block set should be empty after the definition register set is obtained, the process proceeds to step 411 based on the determination in step 406. In step 411, a set of an exit block and a definition register set is registered in the definition register information table 210.

  When the compiler 208 registers the definition register information 802 in the definition register information table 210, the register information defined on the path from the entry block to the exit block becomes clear as shown in FIG. The registers defined in the definition register information table 210 are registers that need to be recovered in the exit block. Therefore, even if a register is saved in the entry block, a register that is not registered in the definition register set can be regarded as a recovery unnecessary register. By extracting the registers that do not need to be recovered, the recovery code inserted into the object program 207 can be reduced. That is, when compiling is performed according to the processing procedure described in the source program 206, a recovery code that does not actually function is extracted from the recovery codes generated in the object program 207, and the recovery code is extracted from the object program. 207 can be blocked.

  In step 412, the exit block that has been processed is deleted from the exit block set, and the process returns to step 402. In step 402, if the exit block set is empty, that is, if all exit blocks have been processed, the process proceeds to step 413. In step 413, a value called a weight expressing the importance of the block is set for the exit block registered in the definition register information table. The heavier (larger) the weight, the higher the importance of the register registered in the definition register set of the exit block.

  As a method for setting the weight, there are a static setting method as described above, a dynamic setting method, and the like. In the static setting method, the compiler 208 itself determines the weight of each exit block. The method of dynamically setting is to execute an object program in which a code for counting the number of executions of a function exit is embedded in advance, acquire the execution count information of the function exit, and then read and execute the acquired execution count information. The compiler 208 calculates and sets the weight from the number of times. In the case of this dynamic function exit weighting, the function exit execution frequency information may be set for each function in the target information table 212. The method of setting statically has an advantage that the object program 207 need not be executed because the weight is determined by one compilation, but the weight determined by the compiler 208 and the operation of the actual program (object program 207) are advantageous. Have the disadvantage that they can be very different.

  On the other hand, the method of dynamically setting the weight has the disadvantage that it takes time to execute the object program 207 once by the target system 250, but has the advantage that the obtained information is consistent with the actual program operation. .

  FIG. 8 shows a processing procedure for determining the save order and recovery order 102 of the callee register. In step 501, the compiler 208 clears and initializes the weight of the register information table 211. In step 502, the compiler 208 clears and initializes the processed flag in the definition register information table 210.

  In step 503, the compiler 208 reads the processed flag 804 of the definition register information table 210, and determines whether all the exit blocks have been processed. Whether or not the exit block has been processed is determined by whether or not all the processed flags 804 for the exit blocks registered in the definition register information table 210 are set. If all exit blocks have been processed, go to step 509. On the other hand, if all the exit blocks have not been processed, the process proceeds to step 504.

  In step 504, the processed flag of the definition register information table 210 corresponding to the exit block to be processed by the compiler 208 is set. In step 505, the definition register set corresponding to the exit block not yet processed by the compiler 208 is extracted from the definition register information table 210, and the process proceeds to step 506.

  In step 506, it is determined whether all the extracted definition register sets have been processed. If all the extracted definition register sets have been processed, the process returns to step 503 to process the next exit block. On the other hand, if the extracted definition register set has not yet been processed, the process proceeds to step 507. In step 507, one register is extracted from the definition register set, and the weight of this register is set in step 508.

  In step 508, the weight 803 registered in the definition register information table 210 is extracted from the exit block information. Further, the weight extracted in step 508 is added to the register information table 211 of the register to be processed.

  By repeating steps 503 to 508, the weight 803 set by the compiler 208 for the definition register set in the definition register information table 210 is added to the register information table 211 as a weight for each register. After the weights of all the registers are set, the process proceeds to step 509 and the register information table 211 is sorted so that the weights are in descending order. After sorting, as shown in FIG. 5B, the registers determined to be important are arranged from the top of the register information table 211 (the uppermost entry in the figure).

  FIG. 9 shows a processing procedure of the save code generation code 103 of the callee register. In step 601, the compiler 208 reads the intermediate code 209 and registers the entry block in the entry block set. Note that the compiler 208 secures a predetermined area on the main memory 204 as a variable for the entry block set. In addition, as shown in FIG. 11, the entry block is a basic block that performs the first calculation process of one function (or subroutine), and performs the first calculation process of the function in the source program 206 of FIG. Point to a line.

  In step 602, it is determined whether the entry block set is empty. If it is empty, the process is terminated. If the entrance block set is not empty, the process proceeds to step 603. In step 603, the head element is extracted from the entry block set. Then, the extracted top element is deleted from the basic block set.

  In step 604, an instruction serving as a reference point for inserting a save code is registered in the entry block to be processed. In this embodiment, an instruction (for example, an add instruction) for updating the stack register SP that holds the stack address (stack pointer) of the target system 250 is registered as a reference point.

  In step 605, the compiler 208 clears and initializes all processed flags 903 in the register information table 211. In step 606, it is determined whether save codes for all registers have been generated. This determination is made based on whether all the processed flags 903 in the register information table 211 are set. If all the processed flags 903 are set, the process returns to step 602. If all the processed flags 903 are not set, the process proceeds to step 607.

  In step 607, the compiler 208 traces the table from the beginning (the uppermost entry in the figure) to the rear (the lowermost entry in the figure) of the register information table 211, and saves the register for which the processed flag 903 is not set. Is generated. As the save code, for example, a push instruction is used. The save code generated in step 607 is inserted immediately before the insertion reference instruction set in step 604.

  In step 608, the processed flag 903 of the register information table 211 corresponding to the register for which the compiler 208 has finished generating the save code is set.

  By repeating the processing from step 606 to step 608, the save code of the callee register necessary for the entry block of the basic block described by the source program 206 can be generated.

  FIG. 10 shows a processing procedure of the recovery code generation 104 of the callee register. In step 701, the compiler 208 clears and initializes all processed flags 804 in the definition register information table 210. In step 702, it is determined whether all exit blocks have been processed. This determination is made based on whether all the processed flags 804 of the definition register information table 210 are set. If all the processed flags 804 are set, the process ends.

  On the other hand, if all the processed flags 804 are not set, the process proceeds to step 703. In step 703, the processed flag 804 of the definition register information table 210 corresponding to the exit block to be processed is set. In step 704, an instruction serving as a reference point for inserting a recovery code is registered in the exit block to be processed. The instruction serving as the reference point is an instruction (for example, a Pop instruction) for updating the stack register SP, similarly to the reference point of the entry block described above.

  In step 705, the compiler 208 initializes the recovery code reduction size. By determining whether or not the recovery code reduction size is 0, it is possible to determine whether or not the recovery code has been reduced in a certain exit block. The recovery code reduction size is secured on the main memory 204 by the compiler 208 as a variable.

  In step 706, the compiler 208 clears all processed flags 903 in the register information table 211. In step 707, it is determined whether all the registers have been processed. This determination is made based on whether all the processed flags 903 in the register information table 211 are set. If all the processed flags 903 are set, the process proceeds to step 712. If all the processed flags 903 are not set, the process proceeds to step 708.

  In step 708, while tracing the table from the beginning of the register information table 211 to the back, it is determined whether or not a recovery code is required in the exit block for the register number for which the first processed flag 903 is not set. . This determination is made based on whether or not the register is registered in the definition register set 802 of the definition register information table 210 corresponding to the exit block. If the register is not registered in the definition register set 802 of the definition register information table 210 corresponding to the exit block, this register is not defined on the path from the entry block to the exit block. Since it is determined, it is not necessary to generate a recovery code, and the process proceeds to step 710.

  In step 710, in order to store the reduced register size, the size of the register determined by the compiler 208 that the recovery code is not necessary in step 708 is added to the recovery code reduction size.

  On the other hand, if the register is registered in the definition register set 802 of the definition register information table 210, a recovery code is required. Therefore, a recovery code is generated in step 709 and immediately after the insertion reference point set in step 704. Insert into. As the recovery code, for example, a pop instruction is used.

  In step 711, the processed flag 903 of the register information table 211 corresponding to the register for which the compiler 208 has finished processing the recovery code is set, and the process returns to step 707. In step 712, it is determined whether or not the recovery code reduction size at the exit block is zero. If the recovery code reduction size is 0, it is determined that the recovery code has not been reduced, and the process returns to step 702. If the recovery code reduction size is other than 0, it is determined that the recovery code has been reduced, and the process proceeds to step 713.

  In step 713, the compiler 208 reflects the reduced size in the update instruction of the stack register SP of the exit block for the exit block in which the recovery code has been reduced. With this reflection processing, a correct code can be generated even if the recovery code is reduced when the push / pop instruction is used.

  With the above processing, a recovery code is inserted for each function exit. However, if there are multiple function exits, it is necessary to recover all registers corresponding to the save code inserted at the function entry at each function exit. Rather, the recovery code is generated only for the registers allocated on the path from the function entry to the function exit. As a result, in the conventional example, for the registers saved at the function entry, recovery codes are generated for all the registers at the function exit, whereas in the present invention, they are defined on the path from the function entry to the function exit. For the registers that do not exist, the size of the object program 207 can be reduced without generating save code. For a register with a reduced recovery code, it is possible to generate a normal object program 207 while omitting the generation of the recovery code by correcting the stack address corresponding to the register size.

  A recovery code reduction processing procedure in the present embodiment will be described with reference to the example of the program (source program 206) in FIG.

  The program example of FIG. 11 is described in C language. The source program 206 calculates the total of array elements from the array passed as an argument and the number of elements. If the array does not exist in the 4th row, 0 is returned as the sum of the array elements in the 5th row. If the array exists, the array elements are summed up by the repeated statements in the 8th to 10th rows. Calculate and return the total in line 11. Therefore, in the source program 206, there are two function exits on the fifth and eleventh lines. The two function exits are processed by the compiler 208 as the above-described exit blocks, and the third line serving as the entry of the function is processed by the compiler 208 as an entry block. Note that the first line and the like are definitions for the compiler 208 and are not handled as basic blocks in the code generation 304.

  As a result of the register assignment by the compiler 208 for the source program 206, the registers defined on the path from the entry to the exit 1 of the 11th line are the registers R1, R2 of the CPU 251 of the target system 250 shown in FIG. , R3, and the register defined on the path from the entrance to the exit 2 of the fifth row is R3, and the weight of each exit block is 0.8 at exit 1 and 0.2 at exit 2 Suppose there was. When the definition register information collection process of step 101 is applied in this state, the definition register information table 210 of FIG. 4 is obtained.

  Next, FIG. 5A shows the result of applying the processing for determining the save / restore order of the callee register in step 102 to the definition register information table of FIG.

  In the definition register information table 210 of FIG. 4, first, in the exit 1, registers R1, R2, and R3 are defined in the definition register set 802, and the weight of the exit block is registered as 0.8. 0.8 is set to the weights of R1, R2, and R3 in the register information table 211 in (a). In the exit 2 of the definition register information table 210 of FIG. 4, only the register R3 is defined in the definition register set 802 and the weight of the exit block is registered as 0.2, so only the register R3 of the register information table 211 is registered. Add a weight of 0.2. As a result, the register information table 211 in the state shown in FIG. The result of sorting the register information table 211 in FIG. 5A in descending order according to the weight 902 is the register information table 211 in FIG.

  In FIG. 5B, the register R3 is determined to be more important than the register R1 and the register R2 because the register recovery code is required both when exiting from the exit 1 and exiting from the exit 2. That is, at the exit 1, all the registers R1 to R3 saved at the entrance need to be restored, whereas at the exit 2, only the register R3 is defined on the path from the entrance to the exit 2. Therefore, the compiler 208 can generate a save code for only the register R3 at the exit 2 and omit the save codes for the registers R1 and R2.

  FIG. 12 shows an example in which the save code and the recovery code of the source program 206 in FIG. 11 are generated in the prior art. In the save code in FIG. 12A, the registers R1, R2, and R3 are sequentially saved on the stack by a push instruction, and then a stack address update instruction (add SP, -α) is executed to secure a work area. Has been. In the recovery code of FIG. 12B according to the prior art, first, a stack address update instruction (add SP, α) is executed to release the work area, and then the registers R3, R2, R1 are placed on the stack in the order. Has been recovered with the pop instruction.

  Next, examples of the save code and the recovery code according to the present embodiment generated from the definition register information table of FIG. 4 and the register information tables of FIGS. 5A and 5B are shown in FIGS. .

  FIGS. 13A and 13B show an example in which the save code and the recovery code are generated at the exit 1 without the reduction of the recovery register according to the present invention.

  In the save code of FIG. 13A, the registers R3, R1, and R2 are saved on the stack area by a push instruction in the order according to the weighting, and then a stack address update instruction (add SP, -Α) is being executed. In the recovery code of FIG. 13B, first, a stack address update instruction (add SP, α) is executed to release the work area, and then the registers R2, R1, and R3 are stacked in the order according to the weighting. It has been recovered from above with the pop instruction. In the recovery code shown in FIG. 12B of the conventional example, the registers are recovered in the reverse order of the saved registers. In contrast to this conventional example, in the present invention, as shown in FIG. 13B, the order of the registers that execute the POP instruction is restored in the order of R2, R1, and R3 according to the weight. Note that the rank of the function exit register uses the rank of the function exit weight.

  FIG. 14B shows the recovery code at exit 2 with recovery register reduction. Even when the recovery codes of the registers R1 and R2 are reduced by the recovery code of FIG. 14B by determining the saving order and the recovery order of the registers in consideration of the importance of the register, the pop instruction which is the recovery code By reflecting the stack address update size (= reduced register size) at the update size α + 8 of the stack register update instruction, the recovery code can be reduced without inserting extra instructions as in the conventional example. Can do.

  That is, in the save code shown in FIG. 14A, as in the case of the exit 1, the registers R3, R1, and R2 are saved in the stack area in the order corresponding to the weight by the push instruction, and then the work area is secured. The stack address update instruction (add SP, -α) is executed.

  In the recovery code of FIG. 14B, a stack address update instruction is first executed to release the work area. At this time, the stack address is corrected according to the number of registers from which the recovery code is deleted. . In this example, since the recovery codes of the registers R1 and R2 are deleted, if the size of each of the registers R1 to R3 is 4 bytes, 8 bytes for two registers become the deletion register size. Therefore, the stack address update instruction is (add SP, α + 8), and the stack addresses corresponding to two registers are shifted.

  After the stack address update instruction is executed, only the register R3 selected according to the weight is restored from the stack area with the pop instruction.

  As described above, at the function exit 2, the compiler 208 determines that it is not necessary to recover the continuous registers R1 and R2, and only the register R3 needs to be recovered. Therefore, the compiler 208 executes one stack address update instruction (add SP + 8) instead of two pop instructions, corrects the stack address according to the number of registers to be deleted, and then issues the POP instruction in the register R3. Generate. As a result, when the object program 207 is executed by the target system 250, the contents of each register are saved in the stack area 260 in the order of the registers R3, R1, and R2 using the save code shown in FIG. Secure.

  Function exit 2 releases the α-byte work area and adds 8 bytes corresponding to the sizes of the two registers R1 and R2 from which the recovery code is deleted to the stack address, and then restores register R3 with the POP instruction. . Thus, the object program 207 can be executed normally by reducing the stack address of the stack register SP to the state before the saving of the registers R1 to R3 while reducing two recovery codes.

  As described above, according to the first embodiment, when generating an object code of a function having a plurality of function exits, unnecessary recovery code in the callee-save register can be reduced, and the object program can be reduced. It is possible to reduce the code size of 207 and generate an object program (execution code) with good execution performance.

  Further, although the stack address is corrected by deleting unnecessary recovery code generation, if the stack register update instruction is generated for each recovery code not created at this time, the object code cannot be reduced. As described above, since the weights are set in the function exit registers and sorted in descending order of the weights, a plurality of register update instructions are combined into one, so that the size of the object code generated by the compiler 208 is reduced. It becomes possible.

<Second Embodiment>
15 and 16 show a second embodiment of callee register save / restore code reduction processing.

  FIG. 15 is a flowchart showing a second processing procedure of the callee register saving code and recovery code reduction processing 305 shown in FIG. 3 of the first embodiment.

  In step 101, the compiler 208 reads the intermediate code 209 as in the first embodiment and collects register information defined on the path from the entry block to the exit block. In step 103, the compiler 208 generates a save code for the callee register in the function entry block. In step 1504, the compiler 208 generates a recovery code for the callee register.

  FIG. 16 shows a processing procedure of the recovery code generation 1504 of the callee register shown in FIG. In this recovery code generation processing 1504, an instruction for updating the stack address is inserted in place of the pop instruction for the register determined to be unnecessary for recovery. The stack address update instruction is to add a constant for the register size to the stack register (SP) holding the stack address. When instructions for updating the stack address are continuously inserted, the recovery instructions are reduced by combining the continuous instructions into one instruction. For example, when two consecutive instructions are combined into one instruction, the constant part of the stack address update instruction is register size × 2. Hereinafter, the processing procedure of the recovery code generation processing 1504 will be described.

  In step 1601, the compiler 208 clears and initializes all processed flags 804 in the definition register information table 210. In step 1602, it is determined whether all exit blocks have been processed. This determination is made based on whether all the processed flags 804 of the definition register information table 210 are set. If all the processed flags 804 are set, the process ends. On the other hand, if all the processed flags 804 are not set, the process proceeds to step 1603. In step 1603, the processed flag 804 of the definition register information table 210 corresponding to the exit block to be processed is set. In step 1604, an instruction serving as a reference point for inserting a recovery code is registered in the exit block to be processed. As described in the first embodiment, the instruction serving as the reference point is an instruction for updating the stack register, like the reference point of the entry block.

  In step 1605, an area used when the compiler 208 combines consecutive stack address update instructions into one is initialized, and the stack address update instruction is set to an unregistered state. In step 1606, all the processed flags 903 in the register information table 211 are cleared and initialized. In step 1607, it is determined whether all the registers have been processed. This determination is made based on whether all the processed flags 903 in the register information table 211 are set. If all the processed flags 903 are set, the process returns to step 1602. On the other hand, if all the processed flags 903 are not set, the process proceeds to step 1608. In step 1608, while tracing the table from the beginning of the register information table 211 to the back, it is determined whether or not a recovery code is necessary in the exit block for the register number for which the first processed flag 903 is not set. . This determination is made based on whether or not the register is registered in the definition register set 802 of the definition register information table 210 corresponding to the exit block. If the register is registered in the definition register set 802, a recovery code is required. Therefore, a recovery code is generated in step 1609 and inserted immediately after the insertion reference point set in step 1604. As the recovery code, for example, a pop instruction is used.

  In step 1610, the registration state (variable) of the stack address update instruction is initialized, and the stack address update instruction is set to an unregistered state. Since the stack address update instruction is used to combine consecutive stack address instructions into one, when a pop instruction is generated with a recovery code, it is necessary to initialize the registration state. In step 1608, if the register is not registered in the definition register set 802, the compiler 208 determines that this register is not defined on the path from the entry block to the exit block. There is no need to generate a recovery code, and the process proceeds to step 1611.

  In step 1611, it is determined whether or not the stack address update instruction has been registered. This determination may be made by referring to the registration state (variable) of the stack address update instruction to determine whether or not it is already registered. If the stack address update instruction has been registered, the compiler 208 determines that the stack address update instruction has been continuously generated with the recovery code, and therefore performs instruction reduction processing. The number of instructions can be reduced by not generating an address update instruction for the register and reflecting the size of the register in the constant addition portion of the instruction registered as the stack address update instruction.

  In step 1612, the process of correcting the constant addition value is performed. If it is not registered in the registration state of the stack address update instruction in step 1611, the process proceeds to step 1613. In step 1613, a stack address update instruction is created for those for which it is determined that the recovery code is unnecessary, and is inserted immediately after the insertion reference point set in step 1604. In step 1614, a stack address update instruction is registered. After these processes are completed, the processed flag 903 of the register information table 211 is set in step 1615, and the process returns to step 1607.

  If it is determined by the above processing that recovery codes of consecutive registers are unnecessary, the recovery code size can be reduced by manipulating the stack address with one stack address update instruction without using the pop instruction.

  Next, FIG. 17B shows an example of the recovery code according to the second embodiment generated from the definition register information table of FIG. 4 and the register information tables of FIGS. 5A and 5B. FIG. 12B of the conventional example shows a recovery code at the exit 1 where there is no reduction in the recovery register. FIG. 17B of the second embodiment shows a recovery code at the exit 2 where there is a reduction in the recovery register. In the exit 2 shown in FIG. 17B, it is determined that recovery of the continuous registers R1 and R2 is unnecessary, so that one address update instruction (add SP, 8) is generated instead of two pop instructions. Therefore, the recovery code size can be reduced. In this example, since one register size is 4 bytes, the constant part of the stack address update instruction is 8 (= 4 × 2).

  As described above, even in the second embodiment, unnecessary recovery code in the callee-save register can be reduced, the object program code size can be reduced, and an object program (execution code) with good execution performance can be generated. It becomes possible to do.

  In each of the above embodiments, an example is shown in which the computer that generates the object program 207 from the source program 206 and the computer that executes the object program 207 (target system 250) are different. The object program 207 may be executed. In this case, the target information table 212 may describe the resources of the computer 200.

  As described above, the present invention is applied to a compiling device and a compiler that generate a callee-save register save code and a recovery code using a stack operation instruction (push / pop instruction) in a process of converting a source program into an object program. it can.

1 is a block diagram of a computer system in which a compiler according to the present invention operates. FIG. 2 is a block diagram of a target system that executes an object program generated by the compiler of FIG. 1. The flowchart which shows 1st Embodiment and shows the processing procedure of a compiler. Explanatory drawing which shows 1st Embodiment and shows an example of a definition register information table. FIG. 2 is an explanatory diagram illustrating the first embodiment and an example of a register information table, where (a) illustrates a state before sorting and (b) illustrates a state after sorting. FIG. 4 is a flowchart showing a processing procedure for generating a callee register save code and a recovery code shown in FIG. 3. The flowchart which shows 1st Embodiment and shows the process sequence of the definition register information collection 101 shown in FIG. 7 is a flowchart illustrating a processing procedure for determining a save order and a recovery order of the callee register illustrated in FIG. 6 according to the first embodiment. The flowchart which shows 1st Embodiment and shows the process sequence of the save code generation of the callee register shown in FIG. The flowchart which shows 1st Embodiment and shows the process sequence of the recovery code production | generation of the callee register shown in FIG. Explanatory drawing which shows 1st Embodiment and shows an example of a source program. An example of generation of a save code and a recovery code according to the prior art is shown, (a) shows a save code, and (b) shows a recovery code corresponding to the save code. The first embodiment shows an example of generation of a save code and a recovery code when the recovery code is not reduced, (a) shows the save code, and (b) shows the recovery code corresponding to the save code. . The 1st embodiment is shown and the example of the production | generation of the save code and recovery code in the case of reducing a recovery code is shown, (a) shows a save code, (b) shows the recovery code corresponding to a save code . The flowchart which shows 2nd Embodiment and shows the processing procedure of calle register saving code and recovery code generation The flowchart which shows 2nd Embodiment and shows the process sequence of the recovery code production | generation 1504 of the callee register shown in FIG. The second embodiment shows an example of generating a save code and a recovery code when reducing the recovery code, (a) showing the save code, and (b) showing the recovery code corresponding to the save code. .

Explanation of symbols

101 definition register information collection process 102 save / recovery order determination process 103 save code generation process 104 recovery code generation process 200 computer system (compile device)
206 Source Program 207 Object Program 208 Compiler 210 Definition Register Information Table 211 Register Information Table 212 Target Information Table 250 Computer System (Target System)

Claims (7)

In a compiling apparatus that includes a first processor that performs arithmetic processing and a storage unit that stores information used by the processor, and that reads a source program including a function and generates an object program including a stack operation instruction.
A parsing unit that reads the source program and generates intermediate code;
A register allocating unit that reads the intermediate code and allocates a register of a second processor constituting a computer that executes the object program to the intermediate code;
A code generation unit that generates an object code from the intermediate code assigned to the register and outputs an object program;
The storage unit
Target information storing register information of the second processor;
First register information for storing information of the register allocated to the function;
Second register information for storing the save order and recovery order of the registers;
Have
The code generator is
A definition register information collection unit that collects information of the registers allocated to the entry and exit of the function and stores the information in the first register information;
A save / restore order determining unit that reads the first register information and determines a save order and a restore order of the registers assigned to the entry and exit of the function;
A save / recovery code generation unit that generates a save code and a recovery code of the register according to the save order and the recovery order determined by the save / recovery order determination unit;
The evacuation / recovery code generator
A register save code is generated at the entry of the function according to the save order of the registers, and the first register information and the registers allocated on the path from the save order to the exit from the save order and the recovery order On the other hand, a stack that generates a recovery code for each exit of the function, calculates a sum of register sizes that are not defined on the path, and corrects a stack address at the exit of the function by the sum of the register sizes. A compiling device for generating an address update instruction. The compiling device according to claim 1,
The evacuation / recovery order determination unit
A compiling apparatus that weights a register assigned to an exit of the function and determines a rank of a register that generates a recovery code based on the rank of the weight. The compiling device according to claim 2,
The target information stores in advance the number of executions of the function exit when the object program is executed by the second processor,
The evacuation / recovery order determination unit
A compiling device, wherein the number of executions of a function exit is read from the target information, and the weight is obtained from the size of the execution times. The compiling device according to claim 1,
The save code, after subtracting the stack address by the number of bytes corresponding to the size of the register, stores the data of the register in the area pointed to by the stack address after the subtraction,
The compile apparatus, wherein after the data is loaded from the area indicated by the stack address to the register, the recovery code adds the number of bytes corresponding to the size of the register to the stack address. In a compiling apparatus that includes a first processor that performs arithmetic processing and a storage unit that stores information used by the processor, and that reads a source program including a function and generates an object program including a stack operation instruction.
A parsing unit that reads the source program and generates intermediate code;
A register allocating unit that reads the intermediate code and allocates a register of a second processor constituting a computer that executes the object program to the intermediate code;
A code generation unit that generates an object code from the intermediate code assigned to the register and outputs an object program;
The storage unit
Target information storing register information of the second processor;
First register information for storing information of the register allocated to the function;
Have
The code generator is
A definition register information collection unit that collects information of the registers allocated to the entry and exit of the function and stores the information in the first register information;
A save / recovery code generation unit that generates a save code and a recovery code of the register allocated by the definition register information collection unit;
The evacuation / recovery code generator
Reading the first register information, generating a save code for the register allocated to the function entry, and for each register exit assigned to the register allocated on the path from the function entry to the exit A compiling device that generates a recovery code and corrects a stack address according to the size of the register for a register that is not defined on the path. The compiling device according to claim 5,
A detection unit for detecting that the update instruction of the stack address is continuously generated;
An update value correction unit that corrects the value of the update instruction of the stack address according to the detection result,
The update value correction unit
When the detection unit continuously generates stack address update instructions, it does not generate the second and subsequent stack address update instructions, and the value of the stack address update instruction generated first is set to a plurality of stack addresses. A compiling device for correcting to a correction value. A first computer including a first processor that performs arithmetic processing and a storage unit that stores information used by the processor reads a source program including a function and generates an object program including a stack operation instruction. In the compilation method,
The first processor reads the source program and generates intermediate code;
The first processor reads the intermediate code and allocates a register of a second processor constituting a second computer that executes the object program to the intermediate code;
The first processor generates an object code from the intermediate code allocated to the register and outputs the object code as an object program;
The step of generating an object code from the intermediate code assigned to the register and outputting it as an object program,
Collecting information on the registers allocated to the entry and exit of the function and storing them in the first register information set in the storage unit;
Reading the first register information and determining a save order and a recovery order of the registers assigned to the entry and exit of the function;
Generating a save code and a recovery code of the register according to the determined save order and recovery order, and
The step of generating the save code and the recovery code of the register according to the determined save order and the recovery order,
A register save code is generated at the entry of the function according to the save order of the registers, and the first register information and the registers allocated on the path from the save order to the exit from the save order and the recovery order On the other hand, a stack that generates a recovery code for each exit of the function, calculates a sum of register sizes that are not defined on the path, and corrects a stack address at the exit of the function by the sum of the register sizes. A compiling method characterized by generating an address update instruction.

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