JP2010118930A - Frequency converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency converter capable of obtaining a high conversion gain at a low power supply voltage and obtaining excellent saturation characteristics and distortion characteristics. <P>SOLUTION: The frequency converter comprises: a transistor pair 3 comprised of first and second transistors; a first transmission line 5a whose one terminal is connected to the common emitter terminal of the transistor pair 3 and whose other terminal is grounded; a second transmission line 5b whose one terminal is connected to the common collector terminal of the transistor pair 3 and whose other terminal is grounded via a capacitor 6; an output load circuit 7 whose one terminal is connected to the terminal grounded via the second via the capacitor 6 of the second transmission line 5b and whose other terminal is connected to a power supply terminal 1; and a bias circuit 4 which is connected to base terminals of the first and second transistors for supplying bias. A high frequency signal input terminal 8 is provided to the common emitter terminal of the transistor pair 3, LO signal input terminals 9a and 9b are provided to the base terminals of the first and second transistors, and an output signal terminal 10 for extracting a mixed signal is provided to the output load circuit 7. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a frequency converter that multiplies or mixes signals in a high frequency band such as UHF, microwaves, and millimeter waves.

  As a conventional frequency converter, a base terminal includes a first transistor to which a positive phase signal of the first signal is input and a second transistor to which a negative phase signal of the first signal is input to the base terminal, A transistor pair having a common emitter terminal and a common collector terminal, a second signal is input to the base terminal, an emitter terminal is connected to a constant current source, and a collector terminal is the common emitter terminal of the transistor pair. And a third transistor connected to the output terminal and a common collector of the pair of transistors connected to a constant voltage level via an output load, and an output circuit that extracts a third signal from the common collector (for example, a patent) Reference 1).

Japanese Patent No. 4056739 (FIG. 1)

  However, in the conventional frequency converter as described above, the saturation characteristics and distortion characteristics as a frequency converter are determined mainly by the large signal characteristics of the RF signal input transistor, which is an active element, so that satisfactory saturation characteristics are obtained. In addition, it is difficult to obtain distortion characteristics, and there is a problem that deterioration of these characteristics is remarkable particularly when operating at a low voltage and / or low current. Also, depending on the power supply voltage and the operating current, the load resistance value is limited within the range in which the transistor can operate. It has been difficult to obtain a high conversion gain due to high output load impedance.

  The present invention has been made in order to solve the above-mentioned problems. Instead of using a transistor as an active element in the RF signal input section, a transmission line is used, and a load circuit is formed from a transmission line and a transistor without using a resistor. It is an object of the present invention to realize a frequency converter that can obtain a high conversion gain at a low power supply voltage and a good saturation characteristic and distortion characteristic by using the output load circuit.

  The frequency converter according to the present invention includes a transistor pair composed of a first NPN transistor and a second NPN transistor for local signal input, each having a common emitter terminal and collector terminal, and one terminal common to the transistor pair. A first transmission line connected to the emitter terminal and having the other terminal grounded, and a second transmission having one terminal connected to the common collector terminal of the transistor pair and the other terminal grounded via a capacitor A line, an output load circuit having one terminal connected to a grounded terminal via a capacitor of the second transmission line, and the other terminal connected to a power supply terminal, the first NPN transistor, and the second A bias circuit connected to a base terminal of the transistor for supplying a bias, and a first common emitter terminal of the transistor pair A high-frequency signal input terminal for inputting a single-phase signal is provided, and a LO signal input terminal for inputting a first differential signal is provided at the base terminals of the first and second NPN transistors, and the output load circuit And an output signal terminal for extracting a mixed signal of the first single-phase signal and the first differential signal.

  According to the present invention, by using a transmission line instead of using a transistor as an active element for an RF signal input unit, and using an output load circuit composed of a transmission line and a transistor without using a resistor as a load circuit, a low power supply voltage can be obtained. In addition, a high conversion gain can be obtained and good saturation characteristics and distortion characteristics can be obtained.

Embodiment 1 FIG.
1 is a circuit diagram showing a frequency converter according to Embodiment 1 of the present invention. The frequency converter shown in FIG. 1 includes a transistor pair 3 composed of a first NPN transistor 2a and a second NPN transistor 2b for local oscillation (LO) signal input each having a common emitter terminal and collector terminal, and one terminal. Is connected to the common emitter terminal of the transistor pair 3, the other terminal is grounded, one terminal is connected to the common collector terminal of the transistor pair 3, and the other terminal is connected via the capacitor 6. The second transmission line 5b that is grounded and one terminal connected to the grounded terminal via the capacitor 6 of the second transmission line 5b and the other terminal connected to the power source (Vcc) terminal 1 A circuit 7 and a bias circuit 4 connected to the base terminals of the first NPN transistor 2a and the second transistor 2b to supply a bias. A high frequency (RF) signal input terminal 8 for inputting a first single-phase signal is provided at the common emitter terminal of the pair of transistors 3, and the first terminals of the first NPN transistor 2 a and the second NPN transistor 2 b are connected to the first terminals. LO signal input terminals 9a and 9b for inputting a differential signal are provided, and an output signal terminal 10 for extracting a mixed signal of the first single-phase signal and the first differential signal from the output load circuit 7 is provided.

The operation and effect will be described below. In the frequency converter according to the first embodiment, a transistor pair is _generated by an RF signal (f _RF ) input through the RF signal input terminal 8 and an LO signal (f _LO ) input through the LO signal input terminals 9a and 9b. 3 is mixed with a signal (f _2LO ) having a frequency twice the LO signal frequency generated when the LO signal input transistors 2a and 2b are alternately turned on / off in FIG. It is extracted as a frequency (f _IF = f _2LO ± f _RF ) signal.

  The DC voltage Vcc is supplied to the LO signal input transistors 2a and 2b through the output load circuit 7, the output load circuit 7 and the transmission line 5b to the power supply terminal 1 of the frequency converter in the first embodiment. A base bias is supplied from the bias circuit 4 to the base terminals of the LO signal input transistors 2a and 2b. The RF signal is input to the common emitter terminal of the transistor pair 3 via the RF signal input terminal 8 with the transmission line 5a as a load. On the other hand, for the LO signal, a positive phase signal is input to the base terminal of the LO signal input transistor 2a via the LO signal input terminal 9a, and a negative phase signal is input to the LO signal input transistor via the LO signal input terminal 9b. 2b is input to each base terminal.

Here, by setting the line length of the transmission line 5a to approximately λ / 4 (λ: wavelength) with respect to the frequency of the input RF signal, the common emitter terminal (point A in FIG. 1) to which the RF signal is input is Since the transmission line has a line length of λ / 4 and the other terminal is grounded, it is electrically open at the RF signal frequency. For this reason, it becomes high input impedance with respect to RF signal, and the input RF signal can keep the amplitude high. On the other hand, the transmission line 5b has a line length of approximately λ / 4 (λ: wavelength) with respect to a frequency (f _2LO ) that is twice the input LO signal frequency, and the capacitor 6 has a frequency that is twice the LO signal frequency. The capacitance value is sufficiently large so that it can be regarded as a short circuit at (f _2LO ).

As a result, the common collector terminal (point B in FIG. 1) of the transistor pair 3 is grounded by a capacitor whose transmission line length is λ / 4 and the other terminal is sufficiently short-circuited. It is electrically open at double the frequency (f _2LO ). For this reason, since it becomes a high output load with respect to the double LO signal generated in the transistor pair 3 and a large amplitude can be obtained, efficient frequency conversion can be performed.

  Since such a frequency converter does not use a transistor which is an active element in the RF input circuit, high saturation and distortion characteristics can be obtained. Furthermore, by using a transmission line as the load of the transistor pair 3, the voltage drop with respect to the operating current is ideally 0 as compared with the case where a resistor is used as the load, so that the power supply voltage and the current value are limited. High load impedance can be obtained.

Embodiment 2. FIG.
FIG. 2 is a circuit diagram showing a frequency converter according to Embodiment 2 of the present invention. In FIG. 2, 1 is a power supply (Vcc) terminal, 2a, 2b, 2c, 2d are local (LO) signal input transistors, 3a, 3b are transistor pairs comprising LO signal input transistors 2a, 2b and 2c, 2d. 4 is a bias circuit for supplying a bias to the LO signal input transistors 2a, 2b, 2c and 2d, 5a, 5b, 5c and 5d are transmission lines, 6a and 6b are capacitors, 7a and 7b are output load circuits, 8a, 8b is a radio frequency (RF) signal input terminal, 9a and 9b are LO signal input terminals, and 10a and 10b are output signal terminals.

  The frequency converter according to the second embodiment uses two frequency converters according to the first embodiment, that is, the frequency converter according to the first embodiment is used as the first frequency converter. The second frequency converter having the same configuration as that of the first frequency converter, the first NPN transistor 2a of the transistor pair 3a of the first frequency converter and the second of the transistor pair 3b of the second frequency converter. The base terminals of the NPN transistor 2d of the first frequency converter and the second NPN transistor 2b of the transistor pair 3a of the first frequency converter and the first NPN transistor 2c of the transistor pair 3b of the second frequency converter, Common base terminals. The base terminals of the first NPN transistor 2a of the transistor pair 3a of the first frequency converter and the first NPN transistor 2c of the transistor pair 3b of the second frequency converter are connected in common, and the first terminal The base terminals of the second NPN transistor 2b of the transistor pair 3a of the frequency converter and the second NPN transistor 2d of the transistor pair 3b of the second frequency converter may be connected in common.

  Further, the power supply terminal 1 and the LO signal input terminals 9a and 9b of the two frequency converters are common, and the RF signal input terminal and the output signal terminal of the two frequency converters are not common, and the first and second frequency converters are not common. The frequency converter is independently provided as RF signal input terminals 8a and 8b and output signal terminals 10a and 10b, and a common connection base terminal of the first NPN transistor 2a and the second NPN transistor 2d, and a second NPN transistor LO signal input terminals 9a and 9b for inputting the first differential signal are provided at the common connection base terminal of 2b and the first NPN transistor 2c, and the common emitter terminal of the transistor pair 3a and the common emitter of the transistor pair 3b are provided. RF signal input terminals 8a and 8b for inputting a second differential signal to the terminals, and an output load circuit of the first frequency converter The mixed signal of the first differential signal and the second differential signal is extracted as the third differential signal from the output signal terminals 10a and 10b of the output load circuit 7b of the a and second frequency converter. ing.

  As a result, the same effects as in the first embodiment can be obtained, and the balance operation is performed with respect to the RF input and the IF output. Therefore, the IF output such as the frequency twice the LO signal and the frequency twice the RF signal can be obtained. It is possible to suppress unwanted waves in.

Embodiment 3 FIG.
FIG. 3 is a circuit diagram showing a frequency converter according to the third embodiment of the present invention, and shows a specific configuration of the output load circuit 7 (7a and 7b) in the first and second embodiments. . In FIG. 3, the same parts as those in FIG. In the frequency converter shown in FIG. 3, the output load circuit 7a of the first frequency converter includes a first PNP transistor 11a having a common base and collector terminal, and the first PNP transistor 11a and an emitter connected in common. The common emitter terminal of the first and second PNP transistors 11a and 11b is connected to the power supply terminal 1, and the commonly connected base and collector terminals of the first PNP transistor 11b are the first PNP transistor 11b. The transmission line 5b of the second transmission line 5b is connected to the grounded terminal side, and the collector terminal of the second PNP transistor 11b is connected to the output signal terminal 10a so that the mixed signal is taken out from the output signal terminal 10a. Has been made.

  Similarly, the output load circuit 7b of the second frequency converter includes a first PNP transistor 11c having a common base and collector terminal, and a second PNP transistor having the emitter connected in common with the first PNP transistor 11c. 11d, the common emitter terminal of the first and second PNP transistors 11c and 11d is connected to the power supply terminal 1, and the commonly connected base and collector terminals of the first PNP transistor 11c are the second transmission line 5d. The collector terminal of the second PNP transistor 11d is connected to the grounded terminal side via the capacitor 6b, and the output signal terminal 10b is connected to extract the mixed signal from the output signal terminal 10b.

Here, the transistors 11a and 11c and the transistors 11b and 11d are in a current mirror relationship, and the ratio of the flowing current is determined by the area ratio of the transistors. An IF signal (f _IF = f _2LO ± f _RF ), which is a mixture of the LO double signal (f _2LO ) and the RF signal (f _RF ), is generated from the transistors 11a and 11c to the transistors 11b and 11d due to the current mirror relationship. Then, it is taken out via the output terminals 10a and 10b.

  Such an active load circuit using a PNP transistor has less restrictions on the power supply voltage and current value than an output load circuit using a resistor, and uses the output resistance of the PNP transistor as a load. And a high conversion gain can be realized. Note that the area ratio of the transistors, that is, the current mirror ratio, is appropriately set depending on the required output power and load conditions.

Embodiment 4 FIG.
FIG. 4 is a circuit diagram showing a frequency converter according to the fourth embodiment of the present invention, and is a specific example of the output load circuit 7 (7a and 7b) in the first and second embodiments different from the third embodiment. The structure is shown. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. In the frequency converter shown in FIG. 4, the output load circuit 7a includes a first PNP transistor 11e, and a first PNP transistor 11e and a second PNP transistor 12 having an emitter and a base connected in common. And the common emitter terminal of the second PNP transistors 11e and 12 are connected to the power supply terminal 1, and the collector terminal of the first PNP transistor 11e is connected to the terminal side grounded via the capacitor 6a of the second transmission line 5b. The collector terminal of the second PNP transistor 12 is connected in common with the base and connected to the constant current source 13, the output signal terminal 10a is provided at the collector terminal of the first PNP transistor 11e, and the output signal terminal 10a The mixed signal is taken out from.

  Similarly, the output load circuit 7b of the second frequency converter includes a first PNP transistor 11f and a second PNP transistor 12 having an emitter and a base commonly connected to the first PNP transistor 11f. The common emitter terminal of the first and second PNP transistors 11f and 12 is connected to the power supply terminal 1, and the collector terminal of the first PNP transistor 11f is connected to the terminal side grounded via the capacitor 6b of the second transmission line 5d. The collector terminal of the second PNP transistor 12 is connected in common with the base and connected to the constant current source 13, the output signal terminal 10b is provided at the collector terminal of the first PNP transistor 11f, and the output signal terminal The mixed signal is extracted from 10b.

  The frequency conversion operation and effect of the frequency converter in the fourth embodiment are the same as those in the first and second embodiments, and the operation of the output load circuit will be described below. The output load circuit includes PNP transistors 11 e and 11 f and a PNP transistor 12. The PNP transistors 11e and 11f and the PNP transistor 12, which is a current mirror reference transistor whose base terminal and collector terminal are short-circuited, have a current mirror relationship in which the base terminals are connected in common. By setting the current value flowing through the transistor pair determined by the setting of 4 and the current values flowing through the transistors 11e and 11f determined by the relationship of the current mirror to be equal, the transistors 11e and 11f each operate as an active load circuit.

  Such an active load circuit using a PNP transistor has less restrictions on the power supply voltage and current value than an output load circuit using a resistor, and uses the output resistance of the PNP transistor as a load. And a high conversion gain can be realized.

Embodiment 5 FIG.
5 is a circuit diagram showing a frequency converter according to Embodiment 5 of the present invention. 5, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The frequency converter according to the fifth embodiment has a collector terminal connected to the power source 1 and an emitter terminal connected to the common emitter terminal of the transistor pairs 3a and 3b, to the first and second frequency converters according to the second embodiment. The reference transistors 14a and 14b, and the power supply 15 connected to the base terminals of the reference transistors 14a and 14b and serving as bias supply means for determining the bias current flowing through the reference transistors 14a and 14b are added. The frequency conversion operation is the same as that of the second embodiment.

  In the frequency converter according to the fifth embodiment, instead of the bias current flowing through the transistor pair 3 in the second embodiment, the current flowing through the output load circuits 7a and 7b is reduced by flowing through the reference transistors 14a and 14b. Since the bias current flowing through the transistor pair 3a and 3b can be reduced without reducing the low-frequency noise generated by the current flowing through the transistor pair 3a and 3b in addition to the effect of the second embodiment. Can

  Therefore, a good noise figure can be obtained even when the frequency of the IF signal is low. In the fifth embodiment, the configuration and operation with respect to the second embodiment are described, but the same effect can be obtained when applied to the first, third, and fourth embodiments.

Embodiment 6 FIG.
6 is a circuit diagram showing a frequency converter according to Embodiment 6 of the present invention. In FIG. 6, the same parts as those in FIG. In the frequency converter according to the sixth embodiment, the collector terminal of the reference transistor 14a shown in FIG. 5 is connected to the output load circuit 7b side, and the collector terminal of the reference transistor 14b is connected to the output load circuit 7a side. .

  That is, in the frequency converter according to the second embodiment shown in FIG. 2, the collector terminal is connected to the output load circuit 7b side of the second frequency converter, and the emitter terminal is the transistor pair 3a of the first frequency converter. The first reference NPN transistor 14a connected to the common emitter terminal of the first frequency converter, the collector terminal connected to the output load circuit 7a side of the first frequency converter, and the emitter terminal of the transistor pair 3b of the second frequency converter A second reference NPN transistor 14b connected to the common emitter terminal, and a power supply 15 as bias supply means connected to the base terminals of the first and second reference transistors 14a and 14b. .

  Thereby, the same effect as the frequency converter in the fifth embodiment can be obtained, and leakage of the LO double signal to the output signal terminals 10a and 10b can be suppressed.

Embodiment 7 FIG.
In the first to sixth embodiments, the transistors constituting the transistor pair 3 (3a and 3b) have been described as junction bipolar transistors (NPN). However, these transistors have the same operation and similar operation as field effect transistors (NMOS). An effect is obtained. In this case, the collector may be replaced with the drain, the emitter with the source, and the base with the gate.

  In the third to sixth embodiments, the transistors constituting the output load circuits 7a and 7b are described as junction bipolar transistors (PNP). However, the same operation and similar operation can be achieved even when these are field effect transistors (PMOS). An effect is obtained. In this case, the collector may be replaced with the drain, the emitter with the source, and the base with the gate.

  Further, in the third to sixth embodiments, the transistors constituting the transistor pairs 3a and 3b are described as junction bipolar transistors (NPN), and the transistors constituting the output load circuits 7a and 7b are described as junction bipolar transistors (PNP). However, the same operation and similar effect can be obtained by using these as a field effect transistor (NMOS) and a field effect transistor (PMOS), respectively. In this case, the collector may be replaced with the drain, the emitter with the source, and the base with the gate.

It is a circuit diagram which shows the frequency converter which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the frequency converter which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the frequency converter which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the frequency converter which concerns on Embodiment 4 of this invention. It is a circuit diagram which shows the frequency converter which concerns on Embodiment 5 of this invention. It is a circuit diagram which shows the frequency converter based on Embodiment 6 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Power supply terminal, 2a 1st NPN transistor, 2b 2nd NPN transistor, 3, 3a, 3b transistor pair, 4 bias circuit, 5a 1st transmission line, 5b 2nd transmission line, 6, 6a capacitor, 7, 7a, 7b output load circuit, 8, 8a, 8b high frequency signal input terminal, 9a, 9b LO signal input terminal, 10, 10a, 10b output signal terminal, 11a first PNP transistor, 11b second PNP transistor, 11e 1st PNP transistor, 12 2nd PNP transistor, 13 constant current source, 14a, 14b reference transistor, 15 power supply.

Claims (9)

A transistor pair consisting of a first NPN transistor and a second NPN transistor for local oscillation signal input, each having a common emitter terminal and collector terminal;
A first transmission line having one terminal connected to the common emitter terminal of the transistor pair and the other terminal grounded;
A second transmission line having one terminal connected to the common collector terminal of the transistor pair and the other terminal grounded via a capacitor;
An output load circuit in which one terminal is connected to a terminal grounded via a capacitor of the second transmission line, and the other terminal is connected to a power supply terminal;
A bias circuit connected to a base terminal of the first NPN transistor and the second transistor to supply a bias;
A high-frequency signal input terminal for inputting a first single-phase signal is provided at the common emitter terminal of the transistor pair, and a first differential signal is input to the base terminals of the first and second NPN transistors. A frequency converter comprising a signal input terminal and an output signal terminal for extracting a mixed signal of the first single-phase signal and the first differential signal in the output load circuit. The frequency converter according to claim 1 is a first frequency converter, and further includes a second frequency converter having the same configuration as the first frequency converter,
The power source terminal and the LO signal input terminal of the first and second frequency converters are shared,
The base terminal of the first NPN transistor of the transistor pair of the first frequency converter and the base terminal of either the first or second NPN transistor of the transistor pair of the second frequency converter are connected in common. And the other base terminals of the second NPN transistor of the first frequency converter transistor pair and the first or second NPN transistor of the second frequency converter transistor pair are connected in common,
The RF signal input terminal and the output signal terminal of the first and second frequency converters are not shared, and the RF signal input terminal and the output signal terminal are provided independently in the first and second frequency converters. With
A first differential signal is input to the LO signal input terminal, while an RF signal input terminal is provided at each common emitter terminal of the transistor pair of the first and second frequency converters to output a second differential signal. Input,
Extracting a mixed signal of the first differential signal and the second differential signal as a third differential signal from an output signal terminal of each output load circuit of the first and second frequency converters; Feature frequency converter. The frequency converter according to claim 1 or 2,
The output load circuit includes a first PNP transistor having a common base and collector terminal, and a second PNP transistor having the first PNP transistor emitter connected in common,
A common emitter terminal of the first and second PNP transistors is connected to the power supply terminal;
The commonly connected base and collector terminals of the first PNP transistor are connected to the grounded terminal side of the second transmission line via the capacitor,
A frequency converter, wherein a collector terminal of the second PNP transistor is connected to the output signal terminal, and a mixed signal is extracted from the output signal terminal. The frequency converter according to claim 1 or 2,
The output load circuit includes a first PNP transistor and a second PNP transistor having an emitter and a base commonly connected to the first PNP transistor,
A common emitter terminal of the first and second PNP transistors is connected to the power supply terminal;
A collector terminal of the first PNP transistor is connected to a grounded terminal side through a capacitor of a second transmission line;
A collector terminal of the second PNP transistor is connected in common with the base and connected to a constant current source;
An output signal terminal is provided at a collector terminal of the first PNP transistor, and a mixed signal is extracted from the output signal terminal. The frequency converter according to any one of claims 1 to 4, wherein:
A reference transistor having a collector terminal connected to the power source and an emitter terminal connected to a common emitter terminal of the transistor pair; and a power source as bias supply means connected to a base terminal of the reference transistor. A frequency converter characterized by that. The frequency converter according to claim 2, wherein
A first reference NPN transistor having a collector terminal connected to the output load circuit side of the second frequency converter and an emitter terminal connected to a common emitter terminal of the transistor pair of the first frequency converter;
A second reference NPN transistor having a collector terminal connected to the output load circuit side of the first frequency converter and an emitter terminal connected to a common emitter terminal of the transistor pair of the second frequency converter;
A frequency converter further comprising: a power supply as bias supply means connected to base terminals of the first and second reference transistors. The frequency converter according to any one of claims 1 to 6,
An NPN transistor constituting the transistor pair is an NMOS transistor, a base terminal is replaced with a gate terminal, an emitter terminal is replaced with a source terminal, and a collector terminal is replaced with a drain terminal. The frequency converter according to any one of claims 3 to 6,
A frequency converter comprising a PNP transistor constituting the output load circuit as a PMOS transistor, a base terminal replaced with a gate terminal, an emitter terminal replaced with a source terminal, and a collector terminal replaced with a drain terminal. The frequency converter according to any one of claims 3 to 6,
An NPN transistor constituting the transistor pair is an NMOS transistor, a PNP transistor constituting the output load circuit is a PMOS transistor, and an emitter terminal is replaced with a source terminal and a collector terminal is replaced with a drain terminal, respectively. .

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