JP2010114165A - Semiconductor device, laminated semiconductor device, and method for manufacturing laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably join bumps to each other by low pressure without application of excessive pressure when laminating an SOI (silicon on insulator) substrate having TSV (through silicon via). <P>SOLUTION: The semiconductor device includes: a substrate having an insulating layer and an SIO layer formed in contact with the insulating layer; a through-hole extending between the main surface and backside of the substrate; a through connection part for electrically connecting the main surface to the backside, which is formed in the through-hole; a dent part for exposing an end portion of the through connection part on the main surface or backside; and a contact member as a member to be electrically contact with the other substrate, which is formed in the dent part in contact with the end portion of the through connection part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a stacked semiconductor device, and a method for manufacturing the stacked semiconductor device.

Conventionally, a through silicon via is formed in a silicon substrate such as a silicon wafer, and a laminated semiconductor device is formed using the through silicon via as a contact. For example, Patent Document 1 saves the cost of forming an insulating film when manufacturing a stacked package, ensures the insulating characteristics of the insulating film, ensures the uniformity and low roughness of the insulating film, and causes device defects due to defects in the insulating film itself. Disclosed is a method for forming a through silicon via to prevent. The method includes forming a groove in each chip of a wafer composed of a plurality of semiconductor chips, forming a liquid polymer on the wafer so as to fill the groove, and patterning the polymer to form grooves. Forming an insulating film made of a polymer on the side wall; forming a metal film so as to fill a groove in which the insulating film is formed on the side wall; and exposing the metal film embedded in the groove. And backgrinding the rear surface of the wafer. A typical device formed on a silicon substrate is a CMOSFET (Complementary Metal Oxide Semiconductor Field-Effect Transistor), but a CMOS on an SOI (Silicon on Insulator) substrate for the purpose of preventing latch-up and improving response speed. A device is formed.
JP 2008-91857 A

  According to Patent Document 1, a through silicon via (hereinafter sometimes abbreviated as “TSV”) may be formed on a silicon substrate, and a plurality of semiconductor devices having TSVs may be stacked to form a stacked semiconductor device. However, when TSV is formed on an SOI substrate, it is necessary to consider that the SOI layer which is an active layer of the SOI substrate has a very thin film thickness. In other words, when stacking SOI substrates having TSVs, it is desired that bonding between bumps can be reliably performed without applying as much extra pressure as possible and with low pressure.

  In order to solve the above problems, in the first aspect of the present invention, a substrate having an SOI layer formed in contact with the insulating layer and the insulating layer, a through-hole penetrating between the front surface and the back surface of the substrate, A through-coupling portion that is electrically connected between the front surface and the back surface, formed in the through-hole, a recessed portion that exposes an end portion of the through-coupling portion on the front surface or the back surface, and a recess that is in contact with the end portion of the through-coupling portion There is provided a semiconductor device provided with a contact member formed on the portion and serving as a member that comes into electrical contact with another substrate.

  In the semiconductor device described above, the contact member may include cream solder. The cream solder may be formed by a printing method. Further, the cream solder may have an amount necessary and sufficient to fill the recess when melted by reflow.

  In order to solve the above problems, in the second aspect of the present invention, a substrate having an SOI layer formed in contact with the insulating layer and the insulating layer, a through-hole penetrating between the front surface and the back surface of the substrate, A through-coupling portion that is electrically connected between the front surface and the back surface, formed in the through-hole, a recessed portion that exposes an end portion of the through-coupling portion on the front surface or the back surface, and a recess that contacts the end portion of the through-coupling portion A plurality of semiconductor devices each having a contact member formed on the portion, and by combining the contact member of one semiconductor device and the contact member of another semiconductor device, A laminated semiconductor device formed by laminating the layers is provided.

  In the laminated semiconductor device described above, the contact member may include cream solder, and the bonding of the contact member between one semiconductor device and another semiconductor device may be performed by reflow of the contact member. Further, the contact member has cream solder, and the cream solder may be filled in the space formed by the recess of one semiconductor device and the recess of another semiconductor device without excess or deficiency.

  In order to solve the above-described problem, in the third aspect of the present invention, a step of preparing a substrate having an insulating layer and an SOI layer formed in contact with the insulating layer and a space between the front surface and the back surface of the substrate are provided. A step of forming a through hole, a step of forming a through coupling part for electrically coupling between the front surface and the back surface in the through hole, and forming a recess by exposing the end of the through coupling portion on the front surface or the back surface. Forming a contact member in the recess in contact with the end of the through-coupling portion, and joining the contact member of one semiconductor device and the contact member of another semiconductor device Thus, there is provided a method for manufacturing a stacked semiconductor device including a step of stacking one semiconductor device and another semiconductor device.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a cross-sectional example of a semiconductor device 100 of the present embodiment. The semiconductor device 100 includes a substrate 102, an insulating layer 104, an SOI layer 106, an element isolation 108, a MOSFET 110, an interlayer wiring 112, an interlayer insulating layer 114, a through hole 116, a through via 122, a recess 124, a back bump 126 and a surface bump 128. Is provided.

  The substrate 102 includes an insulating layer 104 and an SOI layer 106 formed in contact with the insulating layer 104. The substrate 102 may be a silicon wafer, for example.

  The insulating layer 104 is formed near the surface of the substrate 102. The SOI layer 106 may be a silicon crystal layer formed on the surface of the substrate 102 with the insulating layer 104 interposed therebetween. The substrate 102 having the insulating layer 104 and the insulating layer 104 can be manufactured by, for example, a SIMOX (Separation by IM plantation of Oxygen) method or a bonding method.

  The element isolation 108 electrically isolates adjacent MOSFETs 110. As the element isolation 108, for example, a groove isolation structure in which a groove is formed and an insulating film is embedded in the groove can be employed. Note that the bottom of the element isolation 108 may reach the insulating layer 104 or may be stopped in the middle of the SOI layer 106.

  The MOSFET 110 is formed in the SOI layer 106 surrounded by the element isolation 108. MOSFET 110 may be an n-channel MOS or a p-channel MOS, and a CMOS may be constituted by an n-channel MOS and a p-channel MOS. MOSFET 110 has a gate insulating film, a gate electrode, a source electrode, and a drain electrode.

  The interlayer wiring 112 connects the gate electrode, the source electrode, and the drain electrode of the MOSFET 110 to the other MOSFET 110. Alternatively, the interlayer wiring 112 may be a wiring that takes out each electrode of the MOSFET 110 to the outside. The interlayer wiring 112 may be formed by a damascene method in which a metal such as copper is embedded in a groove formed in the interlayer insulating layer 114 and a metal outside the groove is removed by a CMP (Chemical Mechanical Polishing) method.

  The interlayer insulating layer 114 insulates the interlayer wiring 112. Interlayer insulating layer 114 may be, for example, silicon oxide. The interlayer insulating layer 114 may be an insulating film having a low dielectric constant for the purpose of reducing the capacitance of the interlayer wiring 112. An example of the low dielectric constant insulating film is a halide film.

  The through hole 116 penetrates between the front surface and the back surface of the substrate 102. The through hole 116 can be formed by, for example, anisotropic etching.

  The through via 122 is formed in the through hole 116. The through via 122 electrically couples the front surface and the back surface. The through via 122 may be copper formed by, for example, a plating method. However, when the through via 122 is copper, it is substantially difficult to form the MOSFET 110 after the through via 122 is formed. Therefore, the through via 122 is formed after the MOSFET 110 is formed. When the through via 122 is formed before the MOSFET 110 is formed, polycrystalline silicon can be used as a material. The through via 122 may be an example of a through coupling portion.

  An insulating layer that insulates the through via 122 and the substrate 102 may be formed inside the through hole 116. For example, silicon oxide or silicon nitride can be applied to the insulating layer, and the insulating layer can be formed by a thin film forming method such as a CVD method or a sputtering method.

  Further, a metal layer may be formed on the inner surface of the through hole 116. The metal layer may be a barrier metal that prevents diffusion of copper, which is a material of the through via 122, for example. An example of the barrier metal is titanium nitride. The metal layer may be a seed film when the through via 122 is formed by a plating method, for example. When the through via 122 is formed by copper plating, a copper film can be applied as a seed film. The barrier metal and seed film can be formed by sputtering, for example. The metal layer may be a laminated film of a barrier metal and a seed film.

  The depression 124 exposes the end of the through via 122 on the front surface or the back surface. The recess 124 may be formed by patterning, for example, and may be dishing naturally generated by a CMP method.

  The back bump 126 is formed in the recessed portion 124 in contact with the end portion of the through via 122 and becomes a member that is in electrical contact with another substrate. The back bump 126 may have cream solder. The cream solder may be formed by a printing method. The cream solder may have an amount necessary and sufficient to fill the recess 124 when melted by reflow. The back bump 126 may be an example of a contact member.

  In the semiconductor device 100 of this embodiment, since cream solder is used as the contact member, the semiconductor device 100 can be joined without applying excessive pressure when the semiconductor devices 100 are stacked by performing appropriate reflow. Moreover, since it has the hollow part 124, the cream solder fluidized by the reflow appropriately fills the hollow part 124. Thereby, the reliability of joining can be improved.

  The surface bump 128 is a contact terminal on the surface of the semiconductor device 100. The surface bump 128 can be exemplified by a tin-silver bump, for example.

  2 to 9 show a method for manufacturing the semiconductor device 100 in the order of steps. As shown in FIG. 2, a substrate 102 having an insulating layer 104 and an SOI layer 106 formed in contact with the insulating layer 104 is prepared. Next, as shown in FIG. 3, the element isolation 108 is formed in the SOI layer 106, and the MOSFET 110 is formed. Since a method for forming the MOSFET 110 is well known to those skilled in the art, description thereof is omitted.

  As shown in FIG. 4, an interlayer wiring 112 and an interlayer insulating layer 114 are formed. The interlayer wiring 112 can be formed by a damascene method in which a metal such as copper is buried in a groove formed in the interlayer insulating layer 114 by, for example, a sputtering method and a metal outside the groove is removed by a CMP method. The interlayer insulating layer 114 can be formed by, for example, a CVD method or a sputtering method.

  As shown in FIG. 5, a through hole 116 that penetrates the interlayer insulating layer 114, the interlayer wiring 112, the SOI layer 106, and the insulating layer 104 and reaches the substrate 102 is formed. At this stage, the through hole 116 does not penetrate the substrate 102, but as will be described later, the through hole 116 eventually penetrates the substrate 102. The through hole 116 may penetrate the substrate 102 at this stage.

  As shown in FIG. 6, a through via 122 is formed inside the through hole 116. The through via 122 can be formed by, for example, a plating method. The seed layer and the excess plating film used for the plating method are appropriately patterned. At this stage, the interlayer wiring 112 and the through via 122 are electrically connected. Next, as shown in FIG. 7, the back surface of the substrate 102 is polished by, for example, the CMP method to expose the through via 122.

  Next, as shown in FIG. 8, the end of the through via 122 on the back surface of the substrate 102 is exposed to form a recess 124. Thereafter, as shown in FIG. 9, a back bump 126 is formed in the recess 124 in contact with the end of the through via 122. Furthermore, if the surface bump 128 is formed by, for example, a plating method, the semiconductor device 100 shown in FIG. 1 can be manufactured. The back bump 126 can be formed by cream solder, and in this case, can be formed by a printing method or a coating method.

  FIG. 10 shows a cross-sectional example in the manufacturing process of the laminated semiconductor device 200 of another embodiment. FIG. 11 shows an example of a cross section of the stacked semiconductor device 200. The stacked semiconductor device 200 has a structure in which a plurality of semiconductor devices 100 are stacked.

  As shown in FIGS. 10 and 11, the stacked semiconductor device 200 is configured such that one semiconductor device 100 and the other semiconductor device 100 are connected to each other by combining the back surface bump 126 of one semiconductor device 100 and the back surface bump 126 of another semiconductor device 100. The semiconductor device 100 is stacked.

  The back bump 126 may be cream solder. In this case, the bonding of the one semiconductor device 100 and the other semiconductor device 100 at the back bump 126 is performed by reflow of cream solder. The cream solder may be filled in the space 202 formed by the recess 124 of one semiconductor device 100 and the recess 124 of another semiconductor device 100 without excess or deficiency.

  Since the joining is realized by reflow of the cream solder, the semiconductor devices 100 are reliably joined with a small load. Therefore, underfill or the like is unnecessary, cost competitiveness can be increased, and reliability can be improved. When the cream solder is filled in the space 202 without excess or deficiency, voids are not generated in the space 202, and the reliability of bonding can be improved.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, in the above-described embodiment, the case where the recessed portion 124 and the back surface bump 126 are formed on the back surface side of the substrate 102 has been described. However, the same configuration as the recessed portion 124 and the back bump 126 may be formed on the front surface side of the substrate 102.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

An example of a cross section of the semiconductor device 100 of this embodiment is shown. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. A method for manufacturing the semiconductor device 100 will be described in the order of steps. The cross-sectional example in the manufacturing process of the laminated semiconductor device 200 of other embodiment is shown. An example of a cross section of the laminated semiconductor device 200 is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Substrate 104 Insulating layer 106 SOI layer 108 Element isolation 110 MOSFET
DESCRIPTION OF SYMBOLS 112 Interlayer wiring 114 Interlayer insulation layer 116 Through-hole 122 Through-via 124 Recessed part 126 Back surface bump 128 Front surface bump 200 Multilayer semiconductor device 202 Space

Claims (8)

A substrate having an insulating layer and an SOI layer formed in contact with the insulating layer;
A through-hole penetrating between the front surface and the back surface of the substrate;
A through-coupling portion that is formed in the through-hole and electrically couples between the front surface and the back surface;
A recess that exposes an end of the through-coupling portion on the front surface or the back surface;
A contact member that is in contact with the end portion of the through-coupling portion and is formed in the hollow portion and is a member that comes into electrical contact with another substrate;
A semiconductor device comprising: The contact member has cream solder,
The semiconductor device according to claim 1. The cream solder is formed by a printing method,
The semiconductor device according to claim 2. The cream solder has an amount necessary and sufficient to fill the depression when melted by reflow.
The semiconductor device according to claim 2. A substrate having an insulating layer and an SOI layer formed in contact with the insulating layer;
A through-hole penetrating between the front surface and the back surface of the substrate;
A through-coupling portion that is formed in the through-hole and electrically couples between the front surface and the back surface;
A recess that exposes an end of the through-coupling portion on the front surface or the back surface;
A contact member formed in the recess in contact with the end of the through-coupling part;
A plurality of semiconductor devices having
A stacked semiconductor device formed by stacking the one semiconductor device and the other semiconductor device by coupling the contact member of the one semiconductor device and the contact member of the other semiconductor device. The contact member has cream solder,
The connection at the contact member between the one semiconductor device and the other semiconductor device was performed by reflow of the contact member.
The laminated semiconductor device according to claim 5. The contact member has cream solder,
The cream solder is filled in a space formed by the dent part of the one semiconductor device and the dent part of the other semiconductor device without excess or deficiency,
The laminated semiconductor device according to claim 5. Providing a substrate having an insulating layer and an SOI layer formed in contact with the insulating layer;
Forming a through-hole penetrating between the front surface and the back surface of the substrate;
Forming a through-coupling portion in the through-hole for electrically coupling the front surface and the back surface;
Exposing the end of the through-coupling portion on the front surface or the back surface to form a recess,
Forming a contact member in the indented portion in contact with the end of the through-coupling portion;
Forming the semiconductor device and stacking the one semiconductor device and the other semiconductor device by combining the contact member of the one semiconductor device and the contact member of the other semiconductor device;
A method for manufacturing a laminated semiconductor device comprising:

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