JP2010108048A - Current decision program, current decision device and current decision method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge a scale of a circuit allowing simulation, and to reduce a time required for the simulation, in a design stage of an integrated circuit. <P>SOLUTION: In a current decision program, a net list 12 extracted from layout data 11 of the circuit by an extraction unit 1 is divided by a division unit 2, and a plurality of list files 13, 14, 15 each including a parasitic element such as parasitic resistance are created. Current values of the circuit are measured in parallel by use of the parasitic elements belonging to the respective list files 13, 14, 15 by measurement units 3, 4, 5, and quality of a wiring pattern is decided by a decision unit 7 by use of an average current value 19 obtained by averaging the plurality of obtained measured current values 16, 17, 18 by an averaging unit 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a current determination program, a current determination device, and a current determination method used in an integrated circuit development and design stage.

  2. Description of the Related Art Conventionally, there is known a method for estimating a current density parameter on a signal lead wire of an integrated circuit using a computer-aided design (CAD) tool and reducing computer resources (memory usage, calculation time). For example, the signal lead is modeled as an impedance network including resistors and capacitors, the driving cell is modeled as a triangular current signal, and the parameters (peak value, periodicity) of this triangular current signal are the characteristics of the corresponding driving cell. Determine based on the data. The current density parameter on the signal lead wire is estimated by measuring the signal transmitted on the impedance (see, for example, Patent Document 1).

  There is also known an apparatus that prevents the wiring width for connecting each cell of the integrated circuit from becoming unnecessarily large and prevents disconnection of the wiring due to electromigration that occurs in a metal wiring that is less than the necessary line width. For example, the consumption current calculation unit calculates the consumption current of each cell for each operation time of the integrated circuit, and the necessary line width calculation preprocessing unit calculates the current value flowing for each terminal of each cell and the Al line film used for wiring. The required line width of each terminal is calculated based on the thickness and the allowable maximum current density, and the necessary line width calculation unit calculates the wiring based on the required line width of each terminal, its positional relationship, and the magnitude relationship of the current consumption value of each cell. The required line width is calculated, the line width determining unit determines the line width by correcting the required line width so that the required line width is equal to or greater than the minimum processable line width of the Al line, and the numerical value and image of the line width are calculated. While displaying on the graphic display part, a pattern production | generation part produces | generates the pattern of an integrated circuit using the determined line | wire width (for example, refer patent document 2).

JP-A-2005-32251 JP-A-5-206276

  However, in the conventional technology, since the simulation is performed using the parasitic elements of the entire circuit, there is a problem that if the circuit scale becomes large, the simulation takes a long time, and the simulation cannot be performed. .

  The current determination program, the current determination device, and the current determination method divide a circuit netlist into a plurality of groups, and measure the electrical characteristic values of the circuits for all groups using the parasitic elements belonging to the groups. Then, the measured values are averaged to obtain an average electrical characteristic value. You may perform the process which measures an electrical property value in parallel with respect to two or more groups.

  According to the current determination program, the current determination device, and the current determination method, the electrical characteristic value is measured using the parasitic elements of some of the logic nets in the net list. Compared to the case of measuring the characteristic value, the scale of the circuit that can be simulated can be increased. Moreover, the time required for the simulation can be shortened by processing the measurement processing of the electrical characteristic values in parallel.

  Exemplary embodiments of the current determination program, the current determination device, and the current determination method will be described below in detail with reference to the accompanying drawings.

(Outline)
FIG. 1 is an explanatory diagram of a functional configuration of the current determination device according to the embodiment. As shown in FIG. 1, the current determination device divides a net list extracted from circuit layout data, creates a plurality of list files each including parasitic elements such as parasitic resistances, and the like. The circuit current value is measured, for example, in parallel using the parasitic elements to which the circuit belongs, and the quality of the wiring pattern is determined using the average value of the obtained plurality of measured current values.

(Functional configuration of current determination device)
As shown in FIG. 1, the current determination device includes an extraction unit 1, a division unit 2, measurement units 3, 4, 5, an averaging unit 6, and a determination unit 7. The extraction unit 1 extracts a net list 12 from circuit layout data 11. The extraction unit 1 is not particularly limited, but corresponds to various extractor tools such as Cadence Assura-RCX, Mentor Calibre-xRC, or Synopsys StarRCXT. The dividing unit 2 extracts a plurality of logical nets including parasitic elements based on the net list 12. Furthermore, the dividing unit 2 distributes a plurality of logical nets to a plurality of groups based on the analysis conditions input from the analysis condition input unit 8 and the number of parasitic elements of each logical net, and each group is assigned to the group. List files 13, 14, and 15 indicating the parasitic elements to which they belong are created.

  The measuring unit a3 measures the magnitude of the current flowing through the circuit using the list file a13, and outputs the measured current value a data 16. The same applies to the measurement unit b4 and the measurement unit c5, and the measurement current value b data 17 and the measurement current value c data 18 are output using the list file b14 and the list file c15, respectively. The measured current value a data 16 is data of a current value when a current is measured for a circuit in which only the parasitic elements of the list file a13 are used and the parasitic elements of other list files are deleted. Similarly, the measured current value b data 17 is data of current values when only the parasitic elements of the list file b14 are used, and the measured current value c data 18 is obtained when only the parasitic elements of the list file c15 are used. This is current value data.

  Here, in the description of the present specification and the accompanying drawings, a, b, c, and d of the measurement unit, the list file, and the measured current value data are different from each other. The averaging unit 6 averages the measured current value a, the measured current value b, and the measured current value c, obtains an average value of the current flowing through the circuit, and outputs average current value data 19. The determination unit 7 determines whether or not the average current value obtained from the averaging unit 6 is less than or equal to the current value that can be passed through the wiring, based on the wiring width information obtained from the layout data 11. The result 20 is output.

(Hardware configuration of computer device)
FIG. 2 is an explanatory diagram of a hardware configuration of the computer apparatus according to the embodiment. As shown in FIG. 2, the computer device includes a computer main body 210, an input device 220, and an output device 230. The computer device can be connected to a network 110 such as a LAN, a WAN, or the Internet via a router or a modem (not shown).

  The computer main body 210 includes a CPU, a storage unit, and an interface. The CPU controls the entire computer device. The storage unit is composed of one or more of ROM, RAM, HD, optical disk 211, and flash memory. The storage unit is used as a work area for the CPU.

  In addition, various programs are stored in the storage unit, and loaded according to instructions from the CPU. In the HD and the optical disk 211, data read / write is controlled by a disk drive. Further, the optical disk 211 and the flash memory are detachable from the computer main body 210. The interface controls input from the input device 220, output to the output device 230, and transmission / reception with respect to the network 110.

  The input device 220 includes a keyboard 221, a mouse 222, a scanner 223, and the like. The keyboard 221 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Further, it may be a touch panel type. The mouse 222 performs cursor movement, range selection, window movement, size change, and the like. The scanner 223 optically reads an image. The read image is captured as image data and stored in a storage unit in the computer main body 210. Note that the scanner 223 may have an OCR function.

  Examples of the output device 230 include a display 231, a speaker 232, and a printer 233. The display 231 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. The speaker 232 outputs sounds such as sound effects and reading sounds. The printer 233 prints image data and document data.

  Among the functional units of the current determination device, the extraction unit 1, the division unit 2, the measurement units 3, 4, 5, the averaging unit 6 and the determination unit 7 relate to the functions stored in the storage unit of the current determination device, for example. The function can be realized by causing the CPU to execute the program or by the input / output I / F. The layout data 11, the net list 12, the list files 13, 14, and 15, the measured current value data 16, 17, and 18, the average current value data 19, and the determination result 20 are realized by a storage unit, for example.

(Judgment procedure by current judgment device)
FIG. 3 is an explanatory diagram illustrating an outline of a determination procedure performed by the current determination device according to the embodiment. As shown in FIG. 3, when the current determination process is started, first, the extraction unit 1 extracts the net list 12 from the circuit layout data 11 (step S1). Next, the dividing unit 2 divides the net list 12 into a plurality of groups based on the number of parasitic elements. Specifically, the dividing unit 2 extracts a plurality of logical nets including parasitic elements based on the net list 12. Then, based on the analysis conditions input from the analysis condition input unit 8 and the number of parasitic elements belonging to each logical net, the dividing unit 2 distributes the plurality of logical nets to a plurality of groups, and the parasitic units belonging to each group. List files 13, 14, and 15 indicating elements are created (step S2).

  Next, the current of the circuit is measured by the measurement units 3, 4, and 5 using the parasitic elements of each group. Specifically, the measurement unit a3 measures the magnitude of the current flowing through the circuit using the parasitic element of the list file a13, and the measurement unit b4 measures the magnitude of the current flowing through the circuit using the parasitic element of the list file b14. The measurement unit c5 measures the magnitude of the current flowing through the circuit using the parasitic element of the list file c15 (step S3). Next, the averaging unit 6 uses the measured current value data 16, 17, and 18 obtained from the measuring units 3, 4, and 5 to calculate and obtain an average current value that flows through each wiring of the circuit (step S4). ). Next, the determination unit 7 determines the current value flowing through each wiring of the circuit based on the wiring width information obtained from the layout data 11 and the average current value data 19 obtained from the averaging unit 6 (step). S5). When the average current value is less than or equal to the current value allowed for the wiring width, a determination result 20 that the current density is not violated is obtained, and when the average current value exceeds the allowable current value , A determination result 20 that the current density is violated is obtained, and a series of processing ends.

  FIG. 4 is an explanatory diagram showing a detailed procedure of the dividing process in step S2 of FIG. As shown in FIG. 4, when the dividing process is started, first, the dividing unit 2 reads one element from the net list 12 (step S11), and determines whether or not the element is a parasitic element such as a parasitic resistance. Determination is made (step S12). If it is not a parasitic element (step S12: No), the dividing unit 2 reads the next one element (step S11), and determines whether or not the element is a parasitic element (step S12). If the read element is a parasitic element (step S12: Yes), the dividing unit 2 stores information on the parasitic element in the net table (step S13). The net table is a table in which parasitic element information is collected for each logical net. Next, the dividing unit 2 determines whether or not reading of all elements has been completed (step S14). If the reading has not been completed (step S14: No), steps S11 to S13 are repeated.

  When reading of all the elements is completed (step S14: Yes), the dividing unit 2 sorts the net table, and rearranges the logical nets in the descending order of the number of parasitic elements (step S15). Next, the dividing unit 2 determines whether or not the number of divisions is specified in the analysis condition input from the analysis condition input unit 8 (step S16). If there is a designation of the number of divisions (step S16: Yes), the division unit 2 executes division processing with division number restriction described later (step S17). If there is no designation of the number of divisions (step S16: No), the division unit 2 executes division processing without division number limitation described later (step S18). Then, the series of division processes is terminated, and the process proceeds to the current measurement process in step S3.

  FIG. 5 is an explanatory diagram showing a description example of the parasitic elements extracted by the division procedure shown in FIG. In FIG. 5, R **, N *, and ** are a parasitic element name, a logical net name, and a node name, respectively. After this node name, an electrical characteristic value such as a resistance value (not shown) is described. The description example shown in FIG. 5 is an example when the Assura-RCX is used as an extractor tool, but the same applies when other extractor tools are used.

  FIG. 6 is an explanatory diagram showing an example of a net table storing an example of the parasitic element shown in FIG. In the example of the net table 21 shown in FIG. 6, the logical net N1, the logical net N2, the logical net N3, the logical net N4, the logical net N5, and the logical net N6 are respectively, for example, four, three, six, and two. One and four parasitic elements are included. Hereinafter, the division process with division number restriction and the division process without division number restriction will be described using the example shown in FIG.

  FIG. 7 is an explanatory diagram showing a detailed procedure of the division process with the limited number of divisions in step S17 of FIG. FIG. 8 is an explanatory diagram showing a logical net distribution method in the division process with the limited number of divisions shown in FIG. Here, the number of divisions input from the analysis condition input unit 8 is three. In FIG. 8, the arrows between the net table 21 and the list files 13, 14, and 15 represent storage destinations, and the numbers 1 to 6 attached to the sides of the arrows represent the storage order (FIG. 10). The same applies to the above).

  As shown in FIG. 7, when the division process with the limited number of divisions is started, first, the division unit 2 checks the number of parasitic elements stored in the list files 13, 14, and 15, and the number of storage is the smallest. A list file is selected (step S21). Initially, any of the list files 13, 14, and 15 is empty, so that one list file (for example, list file a13) is selected according to a predetermined rule. Next, the dividing unit 2 selects the logical net N3 having the largest number of parasitic elements, and designates that the six parasitic elements belonging to the logical net N3 are to be measured as the list file a13 selected in step S21. (Step S22). Next, the dividing unit 2 determines whether there is a logical net that has not been stored in the list files 13, 14, 15 (step S23).

  At this point, N1, N2, N4, N5 and N6 logical nets remain. That is, since there is an unstored logical net (step S23: Yes), the process returns to step S21, and the dividing unit 2 selects a list file with the smallest number of stored parasitic elements (step S21). In the second round, since the list file b14 and the list file c15 are empty, one list file (for example, the list file b14) is selected according to a predetermined rule. Next, the division unit 2 selects a logical net N1 having the largest number of parasitic elements from the remaining logical nets, and designates that four parasitic elements belonging to the logical net N1 are to be measured. The list file b14 selected in S21 is stored (step S22). The number of parasitic elements in the logical net N1 is the same as the number of parasitic elements in the logical net N6, but any one logical net (for example, the logical net N1) is selected according to a predetermined rule. The above processing is repeated until there is no unstored logical net (step S23: No).

  In the third round, a designation that four parasitic elements belonging to the logical net N6 having the largest number of parasitic elements among the unstored logical nets are to be measured is stored in the empty list file c15 (step S21, S21). Step S22). At this time, the number of stored list files a13, the number of stored list files b14, and the number of stored list files c15 are 6, 4, and 4, respectively. In the fourth round, one list file (for example, list file b14) is selected from the list file b14 and list file c15 with the smallest number of storages according to a predetermined rule (step S21). The list file b14 stores the designation that three parasitic elements belonging to the logical net N2 having the largest number of parasitic elements among the unstored logical nets are to be measured (step S22).

  In the fifth round, the designation that the two parasitic elements belonging to the logical net N4 having the largest number of parasitic elements among the unstored logical nets are to be measured is stored in the list file c15 having the smallest number of storages ( Step S21, Step S22). In the sixth round, one list file (for example, list file a13) is selected from the list file a13 and list file c15 with the smallest number of storages according to a predetermined rule (step S21), and the list file a13 is selected. Finally, the designation that one parasitic element belonging to the logical net N5 remaining as the unstored logical net is to be measured is stored (step S22). Then, since the processing for all the logical nets is completed and there are no unprocessed logical nets (step S23: No), the series of division processing with a limited number of divisions is completed, and the process proceeds to the current measurement processing in step S3. . In the division process with division number restriction, when the number of stored list files exceeds a predetermined upper limit number of measurement, an alarm may be issued or the number of divisions, that is, the number of list files may be increased. The measurement upper limit number is an upper limit value of the number of parasitic elements that can be measured in one simulation, and is determined by, for example, the resources of the computer device.

  FIG. 9 is an explanatory diagram showing a detailed procedure of the division process with no division number limitation in step S18 of FIG. FIG. 10 is an explanatory diagram showing a logical net distribution method in the division process with no division number restriction shown in FIG. Here, the upper limit number of measurement is five.

  As shown in FIG. 9, when division processing without division number limitation is started, first, the division unit 2 selects a logical net N3 having the largest number of parasitic elements, and six parasitic elements belonging to the logical net N3. The designation that the element is to be measured is selected and stored in a list file that does not exceed the upper limit number of measurements even if the designation is stored (step S31). However, when the number of parasitic elements of the logical net has already exceeded the upper limit of measurement like the logical net N3, the logical net is independently assigned to one list file. Therefore, the list file a13 stores only the designation that the six parasitic elements belonging to the logical net N3 are to be measured.

  Next, the dividing unit 2 determines whether there is a logical net that has not been stored in the list files 13, 14, 15, and 22 (step S32). At this time, all the logical nets other than N3 remain unstored (step S32: Yes), and the division unit 2 performs processing for the remaining logical net. However, since the number of stored list files a13 has already exceeded the upper limit number of measurement (step S33: No), the process proceeds to the next list file (step S35) and returns to step S31.

  In the second round, the division unit 2 selects a logical net N1 having the largest number of parasitic elements from the remaining logical nets, and designates that four parasitic elements belonging to the logical net N1 are to be measured. The list file b14 that does not exceed the upper limit of measurement even if the designation is stored is selected and stored (step S31). Since unstored logical nets still remain at this time (step S32: Yes), the dividing unit 2 determines whether there are logical nets equal to or less than the upper limit number of measurement for the list file b14, that is, the parasitic of the list file b14. The value obtained by adding the specified number of storages (4) for the element to be measured and the number of parasitic elements of the logical net with the smallest number of parasitic elements among the remaining logical nets is the upper limit number of measurements (5). It is determined whether there is a logical net that satisfies the following condition (step S33).

  Here, the number of parasitic elements of the logical net N5 having the smallest number of parasitic elements is one, which satisfies the condition (step S33: Yes). Therefore, the division unit 2 stores in the list file b14 the designation that one parasitic element belonging to the logical net N5 is to be measured (step S34). Then, the process returns to step S32, and the same process is repeated for the list file b14. However, since the number of stored list files b14 has reached the upper limit of measurement in the second round (step S33: No), the third round further shifts to the next list file (step S35) and returns to step S31.

  Similarly, in the fourth round, the designation that four parasitic elements belonging to the logical net N6 are to be measured is stored in the list file c15 (step S31). Next, the dividing unit 2 determines whether there is an unstored logical net (step S32). The logical net N2 and the logical net N4 remain unstored (step S32: Yes). However, the number of parasitic elements in the logical net N2 is 3, and the number of parasitic elements in the logical net N4 is two. Since the list file c15 is already stored in the number of four and there is only one more up to the upper limit of measurement, neither the logical net N2 nor the logical net N4 can be stored in the list file c15. That is, there is no logical net equal to or less than the upper limit number of measurement (step S33: No). Therefore, the process proceeds to the next list file (step S35), and the process returns to step S31.

  Similarly, in the fifth round, designation that three parasitic elements belonging to the logical net N2 are to be measured is stored in the list file d22 (step S31). Next, N4 remains as an unstored logical net (step S32: Yes), and even if the designation that the parasitic element of the logical net N4 is to be measured is stored in the list file d22, the number of lists stored in the list file d22 is as follows. The upper limit number of measurement is not exceeded (step S33: Yes). Therefore, the designation that the parasitic element of the logical net N4 is to be measured is stored in the list file d22 (step S34). Then, since the processing for all the logical nets is completed and there are no unprocessed logical nets (step S32: No), the series of division processing without restriction on the number of divisions is finished, and the process proceeds to the current measurement processing of step S3. .

  The current determination method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  In addition, the current determination device described in the present embodiment is a PLD (Programmable Logic) such as a standard cell or a specific application IC (hereinafter simply referred to as “ASIC”) such as a structured ASIC (Application Specific Integrated Circuit). It can also be realized by Device). Specifically, for example, the current determination device can be manufactured by defining the functions 1 to 7 of the above-described current determination device by HDL description, and logically synthesizing the HDL description and giving it to the ASIC or PLD. .

  According to the embodiments described above, a current determination program, a current determination device, and a current determination method that can increase the scale of a circuit that can be simulated are provided. In addition, a current determination program, a current determination device, and a current determination method that can reduce the time required for simulation are provided.

  According to the embodiment described above, each measuring unit measures the circuit current using the parasitic elements of some of the logical nets in the netlist without using all the parasitic elements of the netlist. Can do. In addition, the circuit current measurement processing can be processed in parallel using a plurality of measurement units. Therefore, the scale of the circuit that can be simulated can be increased as compared with the case where the circuit current is measured using all the parasitic elements. In addition, the time required for the simulation can be shortened.

  It is not necessary to perform circuit current measurement processing in parallel for all list files. For example, the current measurement process using the list file a13, the current measurement process using the list file b14, and the current measurement process using the list file c15 may be sequentially performed by the same measurement unit, or the list file a13 is used. In parallel with the current measurement process and the current measurement process using the list file b14 being sequentially performed by the same measurement unit, the current measurement process using the list file c15 may be performed by another measurement unit.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) The computer measures the electrical characteristic value of the circuit using a dividing unit that divides the netlist of the circuit into a plurality of groups, and a parasitic element belonging to the group for each group divided by the dividing unit. A current determination program that functions as a measurement unit that performs averaging, and an averaging unit that averages the electrical characteristic values measured by the measurement unit.

(Supplementary Note 2) The current determination program according to Supplementary Note 1, wherein the measurement unit performs measurement processing in parallel on two or more groups.

(Supplementary Note 3) Extraction means for extracting the netlist based on layout data of the circuit, determination means for determining a layout pattern of the circuit based on an average characteristic value averaged by the averaging means The current determination program according to appendix 1 or 2, wherein the current determination program is made to function as.

(Additional remark 4) The said division | segmentation means extracts the number of the said parasitic elements for every logical net based on the said net list, and the said extracted parasitic element is uniformly distributed to the group of predetermined division | segmentation number The current determination program according to any one of appendices 1 to 3, wherein the logical net is distributed to the group.

(Additional remark 5) The said division | segmentation means extracts the number of the said parasitic elements for every logical net based on the said net list, and the extracted said parasitic element is uniformly, without exceeding the upper limit number of the parasitic elements per group The current determination program according to any one of appendices 1 to 3, wherein the logical net is distributed to the group so as to be distributed.

(Additional remark 6) The said division | segmentation means allocates the said logical net independently to one group, when the number of the said parasitic elements which belong to the said single said logical net exceeds the said upper limit number. The current determination program described in 1.

(Additional remark 7) Measurement which measures the electrical property value of the said circuit using the division part which divides | segments the netlist of a circuit into a some group, and the parasitic element which belongs to the said group divided | segmented by the said division part And an averaging unit that averages the electrical characteristic values measured by the measuring unit.

(Supplementary note 8) The current determination device according to supplementary note 7, wherein the measurement unit performs measurement processing on two or more groups in parallel.

(Supplementary Note 9) An extraction unit that extracts the netlist based on layout data of the circuit, and a determination unit that determines a layout pattern of the circuit based on an average characteristic value averaged by the averaging unit. The current determination device according to appendix 7 or 8, further comprising:

(Additional remark 10) The said division | segmentation part extracts the number of the said parasitic elements for every logical net based on the said net list, and the said extracted parasitic element is uniformly distributed to the group of predetermined division | segmentation number The current determination device according to any one of appendices 7 to 9, wherein the logical net is distributed to the group.

(Additional remark 11) The said division | segmentation part extracts the number of the said parasitic elements for every logical net based on the said net list, and the extracted said parasitic element is uniformly, without exceeding the upper limit number of the parasitic elements per group The current determination device according to any one of appendices 7 to 9, wherein the logical net is distributed to the group so as to be distributed.

(Additional remark 12) The said division part allocates the said logical net independently to one group, when the number of the said parasitic elements which belong to the said single said logical net exceeds the said upper limit number. The current determination apparatus according to 1.

(Additional remark 13) The division | segmentation step which divides | segments the netlist of a circuit into a some group, and the measurement which measures the electrical characteristic value of the said circuit using the parasitic element which belongs to the said group for every said group divided | segmented by the said division | segmentation step And an averaging step for averaging the electrical characteristic values measured in the measurement step.

(Supplementary note 14) The current determination method according to supplementary note 13, wherein in the measurement step, two or more groups are subjected to measurement processing in parallel.

(Supplementary note 15) Based on the extraction step of extracting the netlist based on the layout data of the circuit before the dividing step, and the average characteristic value averaged by the averaging step after the averaging step The current determining method according to appendix 13 or 14, further comprising a determining step of determining a layout pattern of the circuit.

(Supplementary Note 16) In the dividing step, the number of parasitic elements is extracted for each logical net based on the net list, and the extracted parasitic elements are uniformly distributed to a predetermined number of divided groups. The current determination method according to any one of appendices 13 to 15, wherein the logical net is distributed to the group.

(Supplementary Note 17) In the dividing step, the number of parasitic elements is extracted for each logical net based on the net list, and the extracted parasitic elements are uniformly distributed without exceeding the upper limit number of parasitic elements per group. The current determination method according to any one of appendices 13 to 15, wherein the logical net is distributed to the group so as to be distributed.

(Supplementary note 18) The supplementary note 17, wherein in the dividing step, when the number of the parasitic elements belonging to a single logical net exceeds the upper limit number, the logical net is independently assigned to one group. The current determination method according to 1.

It is explanatory drawing which shows the functional structure of the electric current determination apparatus concerning embodiment. It is explanatory drawing which shows the hardware constitutions of the computer apparatus concerning embodiment. It is explanatory drawing which shows the outline of the determination procedure by the electric current determination apparatus concerning embodiment. It is explanatory drawing which shows the detailed procedure of the division | segmentation process in the determination procedure shown in FIG. It is explanatory drawing which shows the example of a description of the parasitic element extracted by the division | segmentation procedure shown in FIG. It is explanatory drawing which shows an example of the net table which stored the example of the parasitic element shown in FIG. It is explanatory drawing which shows the detailed procedure of the division | segmentation process with a division | segmentation number restriction | limiting shown in FIG. FIG. 8 is an explanatory diagram illustrating a logical net distribution method in the division processing with the limited number of divisions illustrated in FIG. 7. It is explanatory drawing which shows the detailed procedure of the division | segmentation process without a division | segmentation number restriction | limiting shown in FIG. It is explanatory drawing which shows the allocation method of a logical net in the division | segmentation process without division | segmentation number restriction | limiting shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Extraction part 2 Dividing part 3, 4, 5 Measuring part 6 Averaging part 7 Judgment part 11 Layout data 12 Net list

Claims (7)

Computer
A dividing means for dividing the netlist of the circuit into a plurality of groups;
Measuring means for measuring an electrical characteristic value of the circuit using a parasitic element belonging to the group for each of the groups divided by the dividing means;
Averaging means for averaging the electrical characteristic values measured by the measuring means;
A current determination program that functions as   The current determination program according to claim 1, wherein the measurement unit performs measurement processing on two or more groups in parallel. The computer,
Extraction means for extracting the netlist based on layout data of the circuit;
Determining means for determining a layout pattern of the circuit based on an average characteristic value averaged by the averaging means;
The current determination program according to claim 1, wherein the current determination program is functioned as: A dividing unit for dividing the circuit netlist into a plurality of groups;
A measurement unit that measures an electrical characteristic value of the circuit using a parasitic element belonging to the group for each group divided by the division unit;
An averaging unit that averages the electrical characteristic values measured by the measurement unit;
A current determination device comprising:   The current determination apparatus according to claim 4, wherein the measurement unit performs measurement processing on two or more groups in parallel. A division step for dividing the circuit netlist into a plurality of groups;
A measurement step of measuring an electrical characteristic value of the circuit using a parasitic element belonging to the group for each of the groups divided by the division step;
An averaging step of averaging the electrical characteristic values measured by the measuring step;
A current determination method comprising:   The current determination method according to claim 6, wherein in the measurement step, measurement processing is performed in parallel on two or more of the groups.

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