JP2010103362A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of varying a power supply voltage to be supplied to each of function modules in accordance with a program. <P>SOLUTION: A plurality of programmable function modules (memories 0-N) 15-0 to 15-N are mounted in a semiconductor device 1. A DC/DC converter 11 generates and outputs a plurality of power supply voltages (Vdd0-Vdd2) to PPSWs 13-0 to 13-N. The PPSWs 13-0 to 13-N selectively connect any one of the plurality of power supply voltages (Vdd0-Vdd2) generated by the DC/DC converter 11 to the programmable function modules 15-0 to 15-N. Accordingly, the power supply voltage to be supplied to the programmable function modules 15-0 to 15-N can be varied in accordance with a program. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for managing a power supply voltage supplied to each module in a semiconductor device, and more particularly to a semiconductor device capable of programming a power supply voltage supplied to each module in an operating state.

  In recent years, system performance of mobile devices such as mobile phones has been remarkably improved, and miniaturization technology in semiconductor devices to cope with this has been developed as well. Such miniaturization of the semiconductor device makes it difficult to reduce the leakage current in the semiconductor device, and the power supply voltage is not scaled. Therefore, it has become a form that deviates from the conventional Moore's Law trend.

  In order to realize high performance of a mobile system, it is necessary to avoid the above-mentioned problems in miniaturization of semiconductor devices by linking circuit and system design technologies with semiconductor device (process) technologies. One of the representative technologies is power management technology.

  The power management technology can be broadly classified into power gating, DVS / DVFS (Dynamic Voltage Scaling / Dynamic Voltage Frequency Scaling), back gate bias control, and virtual power supply. Hereinafter, these techniques will be briefly described.

  Power gating is to turn off the power when the target module is inactive. Thereby, the leakage current of the inactive target module can be made zero. However, it is necessary to observe the restrictions due to the power-on time and power-down time for power-on / power-off control. In addition, there is a mechanism for disconnecting the power line between the inactive module and other active modules, a mechanism for preventing floating nodes and current leak paths from being generated by signals exchanged between the target modules, etc. Necessary.

  DVS / DVFS is the power consumption during operation by dynamically controlling the power supply voltage and back gate bias of the target module when the target module is in a data holding state or when the operating frequency may be lowered. And the leakage current is reduced. In this technique, similarly to the power gating described above, a mechanism for limiting the transition time of the power supply voltage and preventing a current leak path generated by exchanging signals with other modules is necessary.

  In the back gate bias control, when the target module is inactive, the back gate bias voltage is deepened to suppress the leakage current of the transistor. Further, during the operation of the target module, the back gate bias voltage is made shallow to lower the threshold voltage of the transistor, thereby increasing the operation speed. The optimum value of the power supply voltage can be selected by a trade-off between the operation speed and the power supply voltage. As a result, the power supply voltage during normal operation can be reduced, and the power during operation can be reduced.

  The virtual power supply is virtualized by slightly reducing the power supply / GND level of the target module instead of increasing the back gate bias voltage. Then, by setting the negative voltage gate bias state when the target module is inactive, the threshold voltage of the transistor can be set higher than the original value, and the same effect as the back gate bias control described above can be obtained. Can do.

In order to perform the above-mentioned power gating, DVS / DVFS, and back gate bias control, it is necessary to hierarchize the power supply / GND. Further, in order to perform the back gate bias control, it is necessary to further hierarchize the back gate bias power source. The following non-patent document 1 discloses a technique that employs these techniques. Non-Patent Document 2 below discloses a virtual power supply technique used in a memory or the like.
G. Gammie et al., "A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques", in IEEE Int. Solid-State Circuits Conf. 2008, Dig. Of Tech. Papers, Feb. 2008, pp 258-611. M. Yamaoka et al., "A 300MHz 25uA / Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor", in IEEE Int. Solid-State Circuits Conf. 2004 , Dig. Of Tech. Papers, Feb. 2004, pp494-542.

  As described above, the provision of a high-performance system has been realized conventionally by the miniaturization technology of a semiconductor device. However, as a requirement for a future semiconductor device, it is possible to provide a highly reliable system. In particular, in an ultra-high reliability system, the realization of security, content protection, functional safety, etc. is the key.

  In a conventional semiconductor device, a system is configured by executing software on hardware in combination with a ROM (Read Only Memory) centering on a microcomputer. For parts that lacked performance in software processing, the lack of performance was compensated by installing dedicated hardware. Such development has been carried out mainly on the development side of LSI (Large Scale Integrated circuit) manufacturers, system manufacturers, and the like.

  However, it has become necessary to make changes in the hardware field because the industry standard specifications are changed after the LSI is in the hands of the user who is a customer or the use environment conditions are changed. In order to cope with this, programmable hardware has been used.

  As programmable hardware, there are a reconfigurable processor, a dynamic reconfigurable processor, an embedded programmable array, and the like, and each functional module can be configured by programming them.

  As described above, when each functional module mounted on the LSI is replaced by a programmable module from fixed hardware, it cannot be handled only by the power management technique as described above.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which a power supply voltage supplied to each functional module can be changed by a program.

  According to one embodiment of the present invention, a semiconductor device having a plurality of programmable function modules is provided. The DC / DC converter generates a plurality of power supply voltages and outputs them to a programmable power switch (hereinafter also referred to as a programmable PSW or PPSW). The programmable PSW selectively connects any of the plurality of power supply voltages generated by the DC / DC converter to the programmable function module.

  According to this embodiment, the programmable PSW selectively connects one of the plurality of power supply voltages generated by the DC / DC converter to the programmable function module, so that the power supply voltage supplied to the programmable function module is programmed. It becomes possible to change by. In addition, a combination of a programmable DC / DC converter and a programmable PSW enables power setting with a high degree of freedom.

(Prerequisite technology)
FIG. 1 is a diagram showing an example of a baseband application processor integrated chip for a mobile phone equipped with a power gating function. In FIG. 1, C5 is a block in which a system controller for controlling the entire system is arranged. The CPD is a block in which a common power domain (Common Power Domain) described later is arranged.

  BG1, BW2, and BA2 are blocks in which baseband GSM (Global System for Mobile communications), W-CDMA (Wideband-Code Division Multiple Access), CPU (Central Processing Unit), and the like are arranged. A1A, A1R, A2, and A4U1 are blocks in which various modules of the application part are arranged.

  FIG. 1 shows that C5 and CPD manage the power supply voltage of each block. This baseband application processor integrated chip for mobile phones is separated into a plurality of domains as a power management system, and has a power gating and virtual power supply configuration.

  FIG. 2 is a tree diagram showing a management state of each power domain in the baseband application processor integrated chip for the mobile phone shown in FIG. In this hierarchical configuration, the higher module manages the power of the lower module, and the power of the application part and the baseband part are managed independently.

  In the complete stop state of the semiconductor chip, all modules are turned off. When power is supplied to the semiconductor chip, first, the power of the C5 block is turned on. The C5 block includes a system controller for controlling the entire chip and a PAD controller for controlling the IO unit (PAD unit).

  Next, the power of the C4 block is turned on by the control of the C5 block. The C4 block includes a repeater, a clock generation unit, and a data holding flip-flop. These are also referred to as CPD, and details thereof will be described later.

  Similarly, the power source is independently managed in each of the application part and the baseband part. FIG. 2 shows that power is not supplied to the module at the base of the arrow unless the power of the module at the end of the arrow is on. This is a one-way street.

  In the application part, LCDC (Liquid Crystal Display Controller), VRAM (Video Random Access Memory) and register (Reg) are arranged as the lower layer of C4, and PLL (Phase Locked Loop) circuit of the application part is arranged as the lower layer. The mobile video interface is arranged as a lower layer. Further, a memory controller and serial I / O (Input / Output) are arranged as lower layers, and a system CPU and a real-time CPU are arranged as lower layers.

  In the baseband portion, a memory controller, a RAM, and a DMAC (Direct Memory Access Controller) are arranged as lower layers of C4, a PLL circuit of the baseband portion is arranged as a lower layer, and a baseband CPU, W -CDMA and GSM are deployed. Further, DFT, W-CDMA and GSM are arranged as lower layers, and W-CDMA and GSM are arranged as lower layers.

  The power management tree can be applied not only to power gating but also to DVS / DVFS. That is, the power supply voltage level of the lower module is managed by the higher module.

  The problem here is when a signal generated by the lower module is given to the upper module. In general, in a complementary metal oxide semiconductor (CMOS) circuit, the amplitude of an input signal needs to be the same as a power supply voltage. This is because when a signal having an amplitude smaller than the power supply voltage is input, a through current flows in the CMOS buffer that receives the signal. In order to avoid this, it is necessary to insert a level conversion circuit in the previous stage of the CMOS circuit and make the signal amplitude the same as the power supply voltage and input it to the CMOS buffer. A CPD configuration described later is used as the level conversion circuit.

  FIG. 3 is a diagram illustrating an example of power-off of each module of the baseband application processor integrated chip during system operation. In FIG. 3, the shaded modules are in the power-on state, and the other modules are in the power-off state.

  FIG. 3A shows the power state of each module when the W-CDMA videophone is used. Almost all modules in the baseband part and application part are powered on.

  FIG. 3B shows each module at the time of W-CDMA voice communication. Almost all modules in the baseband part are turned on. In the application portion, the system domain centered on the system CPU is turned on, and the real-time domain centered on the real-time CPU is turned off.

  FIG. 3C shows the power supply state of each module during standby. Almost all modules in the baseband part and application part are turned off.

  FIG. 4 is a diagram illustrating a configuration example of the CPD. As shown in FIGS. 4A to 4C, the CPD has three forms. FIG. 4A shows a global clock buffer which is the first form of CPD. The hatched portion is the global clock buffer. The level conversion circuit (μIO) receives the clock generated by the PLL circuit, generates a global clock having the same amplitude as the highest power supply voltage in the system to which the clock is supplied, and supplies it as a local clock to each module To do. Note that the output of the global clock can be controlled by the CTL signal.

  FIG. 4B shows a repeater which is the second form of CPD. The hatched part is a repeater. The level conversion circuit (μIO) receives the signal (Sig1), amplifies (level converts) the signal, and supplies it to the module in order to drive the long-distance wiring. Note that the output of the signal can be controlled by the CTL signal.

  FIG. 4C shows a backup latch which is a third form of CPD. The hatched portion is a backup latch, which is a backup flip-flop for holding data during standby. The power supply voltage of the CPD is on even during standby, and the backup latch receives and holds data of the lower layer module (original FF) whose power supply voltage is off. After the power supply of the lower layer module is turned on, the backup latch restores the retained data to the module. It is also possible to clear the data held by the CTL signal.

  FIG. 5 is a diagram illustrating an example of a physical arrangement of CPDs in a semiconductor chip. The shaded portion is a block in which CPD is arranged, and three forms of CPD shown in FIGS. 4A to 4C are appropriately arranged as necessary.

  FIG. 6 is a diagram illustrating an example of a hierarchical power supply layout. FIG. 6A shows a wiring example of the power supply line. The uppermost power supply (VDD, VSS) and the power supply (VSSM_CPD) of CPD subsequent thereto are wired on each module as global wiring. A power supply VSSM_PDw is wired as a local wiring on the module PDw. A power supply VSSM_PDe is wired as a local wiring on the module PDe.

  FIG. 6B is a diagram illustrating an example of a switch transistor disposed between the global wiring and the local wiring. A hatched portion indicates a switch transistor that is a power switch (PSW), which is arranged between the global wiring VSS and the local wiring VSSM_PDw or between the global wiring VSS and the local wiring VSSM_PDe, and is controlled by a power management signal. Supply of power supply voltage is controlled. As the switch transistor, a transistor having a small gate leakage current and a thick IO gate oxide film is used.

  Based on the respective technologies described above, the semiconductor device in each embodiment of the present invention will be described in detail below.

(First embodiment)
FIG. 7 is a diagram illustrating a configuration example of a programmable power supply system used in the semiconductor device according to the first embodiment of the present invention. This programmable power supply system includes a global wiring connected to an external power supply, a DC / DC converter 11 connected to the global wiring, a programmable PSW 12 arranged between the DC / DC converter 11 and the semi-global wiring, A programmable PSW 13 disposed between the global wiring and the local wiring and a functional module 14 to which a power supply voltage is supplied are included.

  The DC / DC converter 11 includes a series regulator, a switching regulator, and the like, generates a DC voltage lower than the external power supply voltage (Ext.Vdd), and supplies the DC voltage to the programmable PSW 12. The DC / DC converter 11 includes a constant voltage bias generation circuit, a comparator, and the like. The comparator compares the internal power supply voltage generated by the constant voltage bias generation circuit with a reference voltage that is a set voltage. Then, the constant voltage bias generating circuit maintains the voltage so that it always becomes a constant set voltage according to the comparison result by the comparator.

  FIG. 7 shows a case where there are four types (Vdda, Vddb, Vddc, Vddd) of reference voltages and internal power supply voltages required by the system. Although the case where the DC / DC converter 11 steps down and outputs the external power supply voltage has been described, the external power supply voltage may be boosted by a charge pump circuit or a switching regulator to be used as the internal power supply.

  The programmable PSW 12 is a power switch for controlling the power supply voltage output from the DC / DC converter 11, and is provided with four types of internal power supply voltages (Int.Vdda, Int.Vddb, Int.Vddc, Int.Vddd).

  The programmable PSW 13 is a power switch for controlling the internal power supply voltage supplied via the semi-global wiring, controls the power supply voltage according to the power gating control signal, and supplies power to the functional module 14 via the local power supply wiring. Supply voltage.

  Although the programmable PSW 12 and the programmable PSW 13 are described as the programmable PSW, the programmable PSW 12 may not be an essential configuration but may be a configuration only of the programmable PSW 13. However, in this case, semi-global wiring corresponding to the number of power supply voltages output from the DC / DC converter 11 is required.

  FIG. 8 is a diagram illustrating a configuration example of a semiconductor device to which the programmable power supply system illustrated in FIG. 7 is applied. The semiconductor device 1 includes a DC / DC converter 11, a programmable PSW (hereinafter also referred to as PPSW) 13-0 to 13-N, memories 0 to N (15-0 to 15-N), and logic 0 to 0. M (16-0 to 16-M). In FIG. 8, the power supply voltage supplied to the memories 0 to N (15-0 to 15-N) is controlled by the PPSWs 13-0 to 13-N, but the logic 0 to M (16 Similarly, with respect to −0 to 16-M), the power supply voltage is controlled by PPSW.

  As described above, the DC / DC converter 11 is connected to the external power supply voltage Ext. An internal power supply voltage is generated from Vdd. Note that the programmable DC / DC converter may control the internal voltage to be generated by controlling the reference voltage instead of supplying a plurality of fixed internal power supply voltages.

  Each of the PPSWs 13-0 to 13-N has three types of internal power supply voltages (Vdd0, Vdd1, and Vdd2) from the DC / DC converter 11 and two types of GND (GND-P, GND) (GND: reference voltage). Any one of them is connected to memories 0 to N (15-0 to 15-N). The PPSWs 13-0 to 13-N are composed of a power switch and a control register as shown in the PPSW 13A, and the power ON / OFF is controlled by the set value of the control register. This control register may be configured by a nonvolatile memory such as a flash memory or an MRAM. Note that the programmable PSW 12 shown in FIG. 8 is similarly configured as the PPSW 13A.

  The memories 0 to N (15-0 to 15-N) and the logics 0 to M (16-0 to 16-M) are connected via the data path 17 and are configured by programmable function modules. For example, the memories 0 to N (15-0 to 15-N) are configured by a plurality of modules capable of programming external operation conditions such as word configuration, operation voltage, and operation frequency. The logics 0 to M (16-0 to 16-M) are configured by a plurality of logic modules that can program logic functions such as FPGA. The data path 17 includes a data bus, an address bus, a control signal group, and the like, and the amplitude of the signal is controlled by the above-described CPD to be converted into a signal having an amplitude corresponding to the power supply voltage of each programmable function module. .

  Programming information for setting the function of the programmable function module and programming information for controlling the power supply voltage of the programmable power supply system are set in conjunction with each other, thereby realizing a programmable power gating function and a DVS / DVFS function.

  FIG. 9 is a diagram showing a configuration example of a physical layout of the semiconductor device 1 shown in FIG. Each programmable function module (Block-A to Block-I) is disposed adjacent to a PPSW 13 for supplying local power. The PPSW 13 performs power gating control as described above.

  The CPD 27 is disposed between the programmable function modules (Block-A to Block-I), and controls the amplitude of various signals in the data path 17. Thereby, signal control between arbitrary programmable function modules becomes possible.

  Moreover, the DC / DC converter 11 is arrange | positioned for every several programmable function module, and construction of arbitrary programmable power supply networks is enabled. In FIG. 9, only one DC / DC converter 11 that supplies three types of power supply voltages is shown, but it is assumed to be arranged for each of a plurality of programmable function modules.

  FIG. 10 is a tree diagram showing the management state of each power domain of the semiconductor device 1 shown in FIG. FIGS. 10A to 10C show the hierarchical structure of the power supply of the programmable function modules (A to I) shown in FIG. 9, and the upper module is the lower module as in FIG. The power supply is managed.

  FIG. 10A shows a first power supply hierarchical configuration example, in which module A is arranged in the lower layer of CPD, modules B, D and E are arranged in the lower layer, and module C is arranged in the lower layer. , F, G and I are arranged. In mode 1, only the power source of module A is on. In mode 2, modules A, B, C, E and I are powered on. In mode 3, the modules A, B, C, E, F, H, and I are powered on. As described with reference to FIG. 2, if the power of the module at the end of the arrow (upper layer module) is not on, power is not supplied to the module at the base of the arrow (lower layer module). Follow the rules.

  FIG. 10B shows a second power supply hierarchical configuration example, in which the module E is arranged in the lower layer of the CPD, the modules B, D, F and H are arranged in the lower layer, and in the lower layer. Modules A, G, C and I are arranged. In mode 1, only the power source of module E is on. In mode 2, modules A, B, E, H and I are powered on. In mode 3, the modules C, D, E, F, and G are powered on.

  FIG. 10C shows a third power supply hierarchical configuration example, where module B is arranged in the lower layer of CPD, modules A, E and C are arranged in the lower layer, and module G is arranged in the lower layer. , D, H, F and I are arranged. In mode 1, only the power source of module B is on. In mode 2, the modules B, D, E, F and H are powered on. In mode 3, the modules B, C and I are powered on.

  The programmable power supply network shown in FIGS. 7 to 9 controls a PPSW register to virtually define an arbitrary power supply hierarchy configuration as shown in FIGS. 10 (a) to 10 (c) and control the power supply. It becomes possible to do.

  Here, in the present embodiment, a memory is described as an example of a power supply control target. This memory can be applied, for example, to secure a write / read margin in an SRAM or to compensate for deterioration in write / erase characteristics due to aging deterioration of an insulating film such as a flash memory. Further, the power control target is not limited to the memory, and may be logic.

  As described above, according to the semiconductor device 1 in the present embodiment, the PPSW 13 connects one of the plurality of power supply voltages output from the DC / DC converter 11 to the power supply line of the module. It became possible to realize a programmable power management system.

  Since the programming information for setting the function of the programmable function module and the programming information for controlling the power supply voltage of the programmable power supply system are set in conjunction with each other, the programmable power gating function and DVS / DVFS are set. It became possible to realize the function.

  In addition, by disposing the CPD between the modules, it is possible to perform power shut-off and communication between different power supply voltage modules, thereby realizing a flexible programmable power supply system.

(Second Embodiment)
FIG. 11 is a diagram illustrating the internal configuration of the PPSW. Since the configuration of the entire semiconductor device is the same as that of the semiconductor device 1 shown in FIG. 8, the description thereof is omitted here. The PPSW includes a nonvolatile register 21, a decoder (DEC) 22, P channel MOS transistors 23 to 25, and an N channel MOS transistor 26. The nonvolatile register 21 includes an MRAM (Magnetoresistive Random Access Memory) and a flip-flop (FF), and stores program information for controlling on / off of the PPSW. Details of the nonvolatile register 21 will be described later.

  P-channel MOS transistors 23 to 25 are connected between VDDA to VDDC and the power supply line of the module, respectively, and their gates are connected to an output signal from DEC 22. The N-channel MOS transistor 26 is connected between GND and the power supply line of the module, and its gate is connected to an output signal from the DEC 22.

  The DEC 22 decodes the program information output from the nonvolatile register 21 and outputs the decoding result to the transistors 23 to 26. The DEC 22 turns on one of the power switches 23 to 26 according to the decoding result. For example, when the signal connected to the gate of the P-channel MOS transistor 23 is “0” and the transistor 23 is turned on, the other P-channel MOS transistors 24 and 25 and the N-channel MOS transistor 26 are turned off. VDDA is connected to the line.

  Although a decoder is used to reduce the number of bits of program information stored in the nonvolatile register 21, each bit of program information output from the nonvolatile memory 21 may be directly connected to the transistors 23 to 26. Good.

  FIG. 12 is a diagram illustrating an example of the internal configuration of the nonvolatile register 21. The nonvolatile register 21 includes a control unit 30, TMR (Tunnel Magneto Resistance) elements 40-0 to 40-3 and 41-0 to 41-3, selection transistors 42-0 to 42-3 and 43-0 to 43. -3, sense amplifiers 44-0 to 44-3, latch circuits (Latch) 45-0 to 45-3, multiplexers (MUX) 46-0 to 46-3, flip-flop (FF) circuit 47- 0-47-3, and write drivers 48-0 to 48-3 and 49-0 to 49-3.

  Control unit 30 includes a delay circuit 31, latch circuits 32 to 34, AND circuits 35 to 37 and 50, an OR circuit 38, and an inverter 39. Note that the latch circuits 32 to 34 hold the value input to the DATA terminal when the signal input to the CK terminal is “1”, and to the DATA terminal when the signal input to the CK terminal is “0”. Through the entered value. Here, various signals input to the control unit 30 will be described.

  CSC is a block enable signal indicating that the nonvolatile register 21 has been selected. RECALL is an enable signal indicating that data is read from the TMR element (MRAM element) to the FF circuit.

  STORE is an enable signal indicating that data stored in the FF circuit is written to the MRAM element. SI is a serial data input signal when data is transferred serially from the outside to the FF circuit.

  ISEL <1: 0> is two input select signals for selecting the input of the FF circuit. D <3: 0> is a parallel data input signal when data is transferred from the outside to the FF circuit in parallel. R <3: 0> is a register output signal that outputs the contents of the data register. CLK is a clock signal.

  FIG. 12 shows a configuration in the case of a 4-bit data register as an example of the nonvolatile register 21. For example, a 1-bit data register for storing the least significant bit D <0> includes two MRAM elements (TMR elements) 40-0 and 41-0, select transistors 42-0 and 43-0, and sense The amplifier 44-0, the latch circuit 45-0, the MUX 46-0, the FF circuit 47-0, and write drivers 48-0 and 49-0. The MRAM stores information using complementary data.

  The TMR element is a two-axis magnetic field writing type, and data is written by a combined magnetic field of bit lines (MBL0 to MBL3) and word lines (WWL). For example, the output of the write driver 48-0 and the output of 49-0 are coupled in a loop to form the bit line MBL0, which is in a different direction with respect to the TMR elements 40-0 and 41-0 forming a pair. Current flows, and complementary data is written in the two TMR elements 40-0 and 41-0. At this time, the data to be written is data held by the FF circuit 47-0.

  FIG. 13 is a timing chart for explaining the operation when the input data is serially transferred and written to the nonvolatile register 21. First, the CSC signal is asserted as “0”, and “2′b10” indicating serial data transfer is input to the ISEL <1: 0> signal. At this time, the first serial data “A” is input to the SI signal.

  When “1” is output from the latch circuit 32 at T1, the AND circuit 50 outputs a pulse having the same timing as the CLK signal. At this time, since the MUX 46-0 selects and outputs the SI signal, the FF circuit 47-0 holds the first serial data “A”.

  At T2, the serial data “A” held in the FF circuit 47-0 is transferred to the FF circuit 47-1 via the MUX 46-1, and the FF circuit 47-0 holds the second serial data “B”. .

  At T3, the serial data “A” held in the FF circuit 47-1 is similarly transferred to the FF circuit 47-2 via the MUX 46-2, and the serial data “B” held in the FF circuit 47-0 is transferred. The data is transferred to the FF circuit 47-1 via the MUX 46-1, and the FF circuit 47-0 holds the third serial data “C”.

  At T4, the serial data “A” held in the FF circuit 47-2 is similarly transferred to the FF circuit 46-3 via the MUX 46-3, and the serial data “B” held in the FF circuit 47-1 is transferred. Serial data “C” transferred to the FF circuit 47-2 via the MUX 46-2 and held in the FF circuit 47-0 is transferred to the FF circuit 47-1 via the MUX 46-1, and the FF circuit 47-0. Holds the fourth serial data “D”. At this time, “2′b00” is input to the ISEL <1: 0> signal, the data transfer is completed, and the STORE signal is asserted.

  At T5, when “1” is output from the latch circuit 34, the AND circuit 36 outputs a pulse having the same timing as the delayed CLK signal output from the delay circuit 31. At this time, the inverter 39 outputs “0”, and a current flows through the word line WWL. In addition, the write drivers 48-0 to 48-3 are turned on, and a current in a direction corresponding to the data held in the FF circuits 47-0 to 47-3 flows to the bit lines MBL0 to MBL3. Complementary data is written to each of the TMR elements 40-0 to 40-3 and 41-0 to 41-3 by the magnetic field.

  FIG. 14 is a timing chart for explaining an operation when input data is transferred in parallel and written to the nonvolatile register 21. First, the CSC signal is asserted as “0”.

  When “1” is output from the latch circuit 32 at T1, the AND circuit 50 outputs a pulse having the same timing as the CLK signal. At this time, since the MUXs 46-0 to 46-3 select and output the data held by the FF circuits 47-0 to 47-3, the FF circuits 47-0 to 47-3 hold the same data again.

  At T2, since “2′b01” indicating parallel data transfer is input to the ISEL <1: 0> signal and parallel data “A” is input to the D <3: 0> signal, the FF circuit 47-0 to 47-3 hold parallel data “A” via MUXs 46-0 to 46-3 and output them to R <3: 0>.

  At T3, “2′b00” is input to the ISEL <1: 0> signal, the FF data is set to the holding mode, the STORE signal is asserted, and the data held in the FF is written into the MRAM. When “1” is output from the latch circuit 34, the AND circuit 36 outputs a pulse having the same timing as the delayed CLK signal output from the delay circuit 31. At this time, the inverter 39 outputs “0”, and a current flows through the word line WWL. In addition, the write drivers 48-0 to 48-3 are turned on, and a current in a direction corresponding to the data held in the FF circuits 47-0 to 47-3 flows to the bit lines MBL0 to MBL3. Complementary data is written to each of the TMR elements 40-0 to 40-3 and 41-0 to 41-3 by the magnetic field.

  FIG. 15 is a timing chart for explaining an operation when data held in the MRAM element of the nonvolatile register 21 is read. First, the CSC signal is asserted as “0”, and “1” is input to the RECALL signal.

  When “1” is output from the latch circuit 32 at T1, the AND circuit 50 outputs a pulse having the same timing as the CLK signal. Since “1” is output from the latch circuit 33, the AND circuit 35 outputs a pulse having the same timing as the delayed CLK signal output from the delay circuit 31 to the internal signal RWL. At this time, the selection transistors 42-0 to 42-3 and 41-0 to 41-3 are turned on, and a current flows through the TMR elements 40-0 to 40-3 and 41-0 to 41-3. A voltage value corresponding to the resistance is input to the sense amplifiers 44-0 to 44-3.

  The AND circuit 37 outputs a pulse having a width corresponding to the delay time of the delay circuit 31 to the SAE that is an internal signal at the falling edge of the CLK signal. At this time, the latches 45-0 to 45-3 hold data corresponding to the potential difference amplified by the sense amplifiers 44-0 to 44-3, and store them in the MUXs 46-0 to 46-3 as LD <3: 0>. Output. At this time, “2′b11” indicating data read is input to the ISEL <1: 0> signal.

  At T2, since the AND circuit 50 outputs a pulse having the same timing as the CLK signal, the FF circuits 47-0 to 47-3 output LD <0> to LD <3> output from the MUXs 46-0 to 46-3. Are output to R <0> to R <3>.

  According to the present embodiment, since the nonvolatile register 21 of the PPSW 13 is configured by the MRAM and the FF circuit, the programming information of the MRAM can be read at high speed after the power is turned on, and the power setting of each module is performed at high speed. It became possible. In addition, programming information can be held even when the power supply of the semiconductor device is completely turned off.

  In addition, since the PPSW 13 is composed of small-scale nonvolatile registers suitable for distributed arrangement, the circuit overhead of the semiconductor device can be reduced and the chip area of the semiconductor device can be reduced.

(Third embodiment)
The semiconductor device according to the present embodiment is different from the first embodiment only in that the PPSW nonvolatile register 21 is configured by a context memory. Therefore, the detailed description of the configuration and function overlapping with the semiconductor device 1 in the first embodiment will not be repeated.

  FIG. 16 is a diagram illustrating a configuration example of the PPSW in the third embodiment of the present invention. PPSW 60 includes a context memory 51, DEC 22, P channel MOS transistors 23 to 25, and N channel MOS transistor 26.

  The context memory 51 stores a plurality of programming information corresponding to the power control mode, and outputs programming information corresponding to the power control mode to the DEC 22 by inputting a mode signal input from the outside as an address. Therefore, the power supply voltage can be controlled only by designating the mode from the outside. Hereinafter, this PPSW is also called a multi-context type PPSW.

  For example, in the case of the power supply hierarchy shown in FIG. 10A, the following programming information is stored in the context memory of the PPSW connected to each of the modules A to I. That is, programming information for turning on the power (selecting the power supply voltage) is stored in the area corresponding to mode 1 of the context memory corresponding to module A, and the context memory modes corresponding to the other modules B to I are stored. Programming information for turning off the power is stored in an area corresponding to 1.

  The area corresponding to mode 2 of the context memory corresponding to modules A, B, C, E and I stores programming information for turning on the power (selecting the power supply voltage), and other modules D, Programming information for turning off the power is stored in an area corresponding to mode 2 of the context memory corresponding to F, G, and H.

  Further, programming information for turning on the power (selecting the power supply voltage) is stored in an area corresponding to mode 3 of the context memory corresponding to modules A, B, C, E, F, H, and I. Programming information for turning off the power is stored in an area corresponding to mode 3 of the context memory corresponding to the modules D and G.

  When the power supply is controlled according to a plurality of modes as described above, the control information for the single mode is only retained in the second embodiment, so the control information is rewritten according to the mode change. Is required. On the other hand, in the present embodiment, since information on a plurality of modes is simultaneously stored in the context memory 51 according to the address, the mode can be changed at high speed only by inputting a mode signal input from the outside as an address. Become. Here, the mode signal may be a signal from the inside of the semiconductor device by disposing a CPU for setting the mode change therein. In this way, by storing programming information in the context memory of the PPSW connected to each module, it is possible to perform power management corresponding to the mode only by setting a mode signal from the outside.

  FIG. 17 is a diagram illustrating a configuration example of a programmable power supply system to which the multi-context PPSW illustrated in FIG. 16 is applied. FIG. 17 shows a case where the DC / DC converter 11 supplies a power supply voltage to the four blocks 1 to 4 (61-1 to 61-4), and PPSW1 to 4 (60-1 to 6-4). Are connected to blocks 1 to 4 (61-1 to 61-4).

  Power control information corresponding to each mode is written in each context memory of PPSWs 1 to 4 (60-1 to 60-4). Then, the power supply voltage of each block is controlled by an external mode signal. Even in the same mode, by changing the power supply control information for each context memory, it is possible to supply a power supply voltage corresponding to the operation and operation margin of each block.

  The context memory is a nonvolatile memory such as a flash memory, EEPROM, MRAM, FeRAM, ReRAM, phase change memory, etc., so that programming information can be retained even when the power of the semiconductor device 1 is completely turned off. Data transfer after power-on is not necessary.

  As described above, according to the semiconductor device of the present embodiment, since the nonvolatile register is configured by the context memory, the mode information can be set by setting programming information corresponding to a plurality of power control modes in the context memory. The power supply voltage can be controlled simply by setting the power supply, and the power supply voltage can be switched at high speed.

(Fourth embodiment)
FIG. 18 is a diagram illustrating a configuration example of a semiconductor device according to the fourth embodiment of the present invention. Compared with the semiconductor device in the first embodiment shown in FIG. 8, the semiconductor device 1 in the present embodiment is further provided with a spare memory 15-S and a PPSW 13-S connected thereto, and a multiplexer (MUX). The only difference is that 20-0 to 20-N are added. Therefore, detailed description of overlapping configurations and functions will not be repeated. Although not shown in FIG. 18, it is assumed that MUXs 20-2 to 20-N are also provided corresponding to the memories 2 to N (15-2 to 15-N).

  The MUX 20-0 selectively connects either the signal group from the memory 0 (15-0) or the signal group from the spare memory 15-S to the data path 17. Similarly, the MUX 20-1 selectively connects either the signal group from the memory 1 (15-1) or the signal group from the spare memory 15-S to the data path 17.

  The spare memory 15-S is provided as a spare memory, and the MUXs 20-0 to 20-N are connected so that the memories 0 to N (15-0 to 15-N) are connected to the data path 17 during normal operation. The spare memory 15-S is set and is not used. For example, when an operation failure of the memory 0 (15-0) is detected, the memory 0 (15-0) is disconnected from the data path 17 and the spare memory 15-S is connected to the data path 17. MUX 20-0 is switched. A spare memory 15-S is used instead of the memory 0 (15-0).

  FIG. 19 is a flowchart for explaining a self-repair operation of the semiconductor device 1 shown in FIG. This process may be realized by programming a programmable function module in the semiconductor device 1, or a module for executing such a process may be provided in the semiconductor device 1 in advance.

  First, when the power of the semiconductor device 1 is turned on, the semiconductor device 1 shifts to the self test mode (S1). Then, by setting the DC / DC converter 11 and the PPSWs 13-0 to 13-N, the power supply voltages such as the memories 0 to N (15-0 to 15-N) are set (S2).

  Next, the memories 0 to N (15-0 to 15-N) are tested using a BIST (Built-In Self-Test) circuit or the like (S3). Then, the result of the memory test is determined (S4). If the operations of the memories 0 to N (15-0 to 15-N) are normal (S4, Pass), the semiconductor device 1 ends the self test mode and enters a standby state (Ready).

  If any of the memories 0 to N (15-0 to 15-N) is defective (S4, Fail), a warning (Warning) is output to the outside and a fail bit map as a test result is output. The test result is analyzed with reference to the monitor information (S5). Then, it is determined whether or not an error can be avoided (S6). The reason why the warning is output to the outside is to notify the fact that the memory margin is reduced by changing the power supply voltage or the like, because the operation margin is small.

  If it is determined that the error can be avoided by changing the power supply voltage (S6, (1)), the process returns to step S2, the power supply voltage is changed, and the subsequent processing is performed again. The determination as to whether or not this error can be avoided is made by determining whether or not the power supply voltage can be raised by changing.

  If it is determined that the redundant memory in the same memory can be repaired by referring to the fail bit map when the repair cannot be performed by changing the power supply voltage (S6, (2)), the redundant Row / Column is stored. Is used to relieve the area where the error has occurred (S7), and the process returns to step S2 to perform the subsequent processing.

  Further, when the redundant memory cannot be relieved in the same memory and the spare memory 15-S is not used (S6, (2)), the defective memory is separated from the data path 17 by switching the MUX. Then, the spare memory 15-S is replaced (S8), and the process returns to step S2 to perform the subsequent processing. At this time, the PPSW is also controlled so that the defective memory is disconnected from the power source.

  If none of the power supply voltage change, redundant memory rescue and memory replacement in the same memory can be performed (S6, (3)), an error is output to the outside and the process is terminated.

  As described above, according to the semiconductor device 1 in the present embodiment, when a field malfunction occurs in the memories 0 to N (15-0 to 15-N), the self test results such as BIST and the internal monitor Even if it is detected that the operation margin is insufficient due to a threshold shift due to aging deterioration in the field, etc., it is possible to secure the operation margin by raising the power supply voltage. It became.

  In addition, even when a hardware error occurs due to memory cell destruction or disconnection, it is possible to autonomously avoid a system error by repairing a redundant memory in the same memory and repairing by a spare memory. In addition, it is possible to prevent an increase in leakage current by completely disconnecting the memory in which DC failure is detected from the power source.

  Further, since the power supply voltage of the memory can be changed in the field, a self margin test can be performed in cooperation with the BIST, and an acceleration test in the field in the semiconductor device 1 can be performed. As described above, the system based on the programmable power supply system can improve the fault tolerance performance in the field of the memory in the semiconductor device 1 and realize functional safety.

(Fifth embodiment)
FIG. 20 is a diagram illustrating a configuration example of a semiconductor device according to the fifth embodiment of the present invention. Compared with the semiconductor device in the fourth embodiment shown in FIG. 18, the semiconductor device 1 in this embodiment has a control circuit 18 and a monitor circuit 19 arranged corresponding to PPSWs 13-0 to 13-S. The only difference is that −0 to 19-S is added. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  The monitor circuits 19-0 to 19-S monitor the power supply voltages of the PPSWs 13-0 to 13-S, respectively, and output the detected power supply voltage values to the control circuit 18. This monitor circuit is described, for example, in the literature (M. Nagata, T. Okumoto, K. Taki, "A Built-in Technique for Probing Power Supply and Ground Noise Distribution within Large-Scale Digital Integrated Circuits" IEEE J. Solid-State Circuits. , vol. 40, no. 4, pp. 813-819, Apr., 2005.) and the like.

  The control unit 18 controls the DC / DC converter 11 or the PPSWs 13-0 to 13-S based on the voltage values received from the monitor circuits 19-0 to 19-S. For example, during operation of a certain application, when a power supply voltage drop (IR drop) occurs in the power supply voltage supplied from the PPSWs 13-0 to 13-S due to the deviation of the operation region, and the operation becomes unstable, With reference to the power supply voltage value received from the monitor circuits 19-0 to 19-S, the DC / DC converter 11 or PPSW 13-0 to 13-S is set so that the voltage of the block in which the power supply voltage drop occurs is slightly increased. To control. Thereby, the operation of the semiconductor device 1 can be stabilized.

  With such an operation, after the chip is manufactured, the control unit 18 optimizes the power supply impedance while referring to the power supply voltage values from the monitor circuits 19-0 to 19-S, thereby being able to cope with variations due to processes. it can.

  As described above, according to the semiconductor device 1 in the present embodiment, the control unit 18 refers to the power supply voltage value from the monitor circuits 19-0 to 19-S, and the DC / DC converter 11 or PPSW 13-0. Since 13-S is controlled, the power supply voltage of the block in which the power supply voltage is lowered can be increased, and the semiconductor device 1 can be stably operated.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows an example of the baseband application processor integrated chip | tip for mobile phones carrying a power gating function. FIG. 2 is a tree diagram showing a management state of each power domain in the baseband application processor integrated chip for the mobile phone shown in FIG. 1. It is a figure which shows an example of the power interruption of each module of the baseband application processor integrated chip at the time of system operation. It is a figure which shows the structural example of CPD. It is a figure which shows the example of physical arrangement | positioning of CPD in a semiconductor chip. It is a figure which shows an example of a hierarchical power supply layout. It is a figure which shows the structural example of the programmable power supply system used with the semiconductor device in the 1st Embodiment of this invention. It is a figure which shows the structural example of the semiconductor device with which the programmable power supply system shown in FIG. 7 is applied. It is a figure which shows the structural example of the physical layout of the semiconductor device 1 shown in FIG. FIG. 10 is a tree diagram showing a management state of each power domain of the semiconductor device 1 shown in FIG. 9. It is a figure which shows an example of the internal structure of PPSW. 3 is a diagram illustrating an example of an internal configuration of a nonvolatile register 21. FIG. 5 is a timing chart for explaining an operation when input data is serially transferred and written to a nonvolatile register 21; 4 is a timing chart for explaining an operation when input data is transferred in parallel and written to the nonvolatile register 21; 4 is a timing chart for explaining an operation when data held in an MRAM element of a nonvolatile register 21 is read. It is a figure which shows the structural example of PPSW in the 2nd Embodiment of this invention. It is a figure which shows the structural example of the programmable power supply system to which the multi-context type PPSW shown in FIG. 16 is applied. It is a figure which shows the structural example of the semiconductor device in the 4th Embodiment of this invention. 19 is a flowchart for explaining a self-repair operation of the semiconductor device 1 shown in FIG. It is a figure which shows the structural example of the semiconductor device in the 5th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 11 DC / DC converter, 12, 13-0 to 13-N, 13A, 13-S, 60, 60-1 to 60-4 PPSW, 14 functional module, 15-0 to 15-N, 15 -S memory, 16-0 to 16-M logic, 17 data path, 18 control circuit, 19-0 to 19-S monitor circuit, 20-1 to 20-N MUX, 21 nonvolatile register, 22 DEC, 23 to 25 , 75, 76 P-channel MOS transistor, 26, 73, 74, 77, 78 N-channel MOS transistor, 27 CPD, 30 control unit, 31 delay circuit, 32-34 latch circuit, 35-37, 50 AND circuit, 38 OR Circuit, 39 Inverter, 40-0 to 40-3, 41-0 to 41-3 TMR element, 42-0 to 42-3, 43-0 to 43-3 Select transistor, 44-0 to 44-3 sense amplifier, 45-0 to 45-3 latch circuit, 46-0 to 46-3 MUX, 47-0 to 47-3 FF circuit, 48-0 to 48-3, 49-0 to 49-3 Write driver, 51 Context memory, 61-1 to 61-4 block, 71, 72 Non-volatile memory.

Claims (11)

A semiconductor device having a plurality of modules,
Power supply voltage generating means for generating a plurality of power supply voltages;
And a switching unit that selectively connects any one of the plurality of power supply voltages generated by the power supply voltage generation unit to at least a part of the plurality of modules.   The semiconductor device according to claim 1, wherein some or all of the plurality of modules are programmable function modules. The switch means includes a nonvolatile memory for storing data for switching a power supply voltage;
2. A plurality of transistors for connecting any one of the plurality of power supply voltages generated by the power supply voltage generation unit to at least a part of the plurality of modules according to data stored in the nonvolatile memory. Or the semiconductor device of 2. The switch means further includes a decoder for decoding data stored in the nonvolatile memory,
4. The semiconductor according to claim 3, wherein the plurality of transistors connect one of the plurality of power supply voltages generated by the power supply voltage generation unit to at least a part of the plurality of modules according to a decoding result by the decoder. apparatus. The switch means includes a context memory that stores a plurality of data for switching the power supply voltage;
A plurality of transistors for connecting any one of the plurality of power supply voltages generated by the power supply voltage generation means to at least a part of the plurality of modules according to data output from the context memory in correspondence with a power supply mode; The semiconductor device according to claim 1, comprising: The switch means further includes a decoder for decoding data output from the context memory,
6. The semiconductor according to claim 5, wherein the plurality of transistors connect any one of the plurality of power supply voltages generated by the power supply voltage generation unit to at least a part of the plurality of modules according to a decoding result by the decoder. apparatus. The plurality of modules are arranged in a plurality of blocks,
A plurality of the switch means are arranged corresponding to the plurality of blocks,
7. The semiconductor device according to claim 1, wherein a common power domain including a circuit, a latch, a repeater, and the like that controls an amplitude of a signal between the plurality of blocks is disposed adjacent to the plurality of blocks. A semiconductor device according to claim 1.   The semiconductor device further detects the operation failure of the plurality of modules, changes the power supply voltage of the module with the operation failure, and avoids the operation failure, either of the power supply voltage generation means, the switch means, or The semiconductor device according to claim 1, comprising control means for controlling both. The semiconductor device further includes a spare module;
Replacement means for replacing any of the plurality of modules with the spare module;
The control means avoids a malfunction by changing the power supply voltage by one or both of the power supply voltage generating means and the switch means, or by controlling the replacement means to replace the spare module. The semiconductor device according to claim 8, which can be used. The semiconductor device further includes monitoring means for monitoring a power supply voltage connected by the switch means;
Control means for detecting a module in which a power supply voltage drop is generated with reference to the power supply voltage monitored by the monitoring means and controlling the switch means so that a higher power supply voltage is connected to the module; The semiconductor device according to claim 1.   11. The semiconductor according to claim 10, wherein the control means controls the switch means with reference to the power supply voltage monitored by the monitor means so that an impedance of a power supply line connected by the switch means is optimized. apparatus.

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