JP2010102525A - Method for estimating frequently occurring event - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for estimating the combination of a plurality of events which frequently occur in a short time. <P>SOLUTION: The method for estimating an event which frequently occurs includes: a step of collecting the samples of the information of an instruction address causing the occurrence of such an event as a cache mistake by using a performance monitor; a step of grouping events sampled in each range of specific instruction addresses; a step of extracting the event which occurs with frequency which is equal to or more than a prescribed threshold for each group; and a step of classifying the extracted events as the events which continuously occur in a short time. In addition, this method may include: a step of grouping the events for each range of specific instruction addresses associated with a method or a basic block. Moreover, this method may include: a step of classifying the combinations of objects causing the continuous occurrence of the events by using the step of specifying the instruction addresses causing the occurrence of the events and the object and field of the reference destination to be accessed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for optimizing an event arrangement in a processor, and more particularly, to a method for estimating an event that frequently occurs continuously in time based on discrete event samples using a computer.

  Conventionally, in an object-oriented language such as Java (registered trademark), generally, in order to generate a large number of small objects, a plurality of objects that are accessed simultaneously are arranged so as to enter the same cache line, or memory prefetch It is known to improve performance by using instructions (Non-Patent Documents 1-3). Many recent processors have a performance monitor function that takes a sample at a certain frequency, for example, every 1000 times when an event in the processor such as a memory access or a cache miss occurs. By using this function, it is possible to acquire dynamic information with low overhead.

Conventionally, a device that counts and stores the number of occurrences of characteristic events after the occurrence is known (Patent Document 1). According to this apparatus, the information processing apparatus and the like can efficiently store events that affect program performance.
JP 2008-186080 A Wen-Ke Chen et al., “Profile-guided Proactive Garbage Collection for Locality Optimization”, Programming Language Design and Implementation (PLDI) 2006 Ottawa Canada, June 10-16, 2006 Ali-Reza Adl-Tabatabai et al., “Prefetch Injection Based on Hardware Monitoring and Object Metadata”, PLDI 2004 Washington DC USA, June 9-11, 2004 Florian T. Schneider et al., “Online Optimizations Driven by Hardware Performance Monitoring”, PLDI 2007, San Diego CA USA, June 10-13, 2007

  However, in the performance monitor function according to the prior art, the collected information is not a continuous memory access history but a discrete sample, and cannot be used as it is for detection of simultaneously accessed objects. For example, in order to insert a prefetch instruction and optimize an object arrangement using samples collected by the performance monitor function, it is necessary to determine objects that are continuously accessed within a short time. Therefore, conventionally, a method for static analysis of source code and a code for acquiring a memory access history using a compiler are generated to obtain information dynamically. However, these methods have a problem that overhead is large in terms of processing time and memory capacity. In particular, the method using a compiler has a problem that additional debugging information is required at the time of compilation in order to find the corresponding position of the source code or bytecode from the instruction address where the event occurred. In addition, in a device that counts the number of times after an event occurs, a method for estimating the occurrence of an event such as a cache miss in advance is not shown.

  In the present invention, a combination of a plurality of events that occur frequently and continuously in a short period of time such as a cache miss from a discrete sample of events collected by a processor performance monitor function is not dependent on static analysis. It is an object of the present invention to provide a method that makes it possible to detect by estimation.

  In view of the above problems, the present invention provides the following solutions.

In the method for estimating frequently occurring events according to the present invention, a sample is collected using the performance monitor for information on the instruction address at which the event occurred, and if necessary, additional information about the event details, Then, a combination of events that frequently occur continuously in a short time is specified by the following procedure, and it is estimated that the combination is an event that occurs continuously in a short time.
Procedure 1: Events are grouped into specific instruction address ranges such as methods and basic blocks.
Procedure 2: Statistical processing of events is performed for each group, and events that occur with a frequency equal to or higher than a certain threshold (hereinafter referred to as frequent events) are extracted.
Procedure 3: The frequent events extracted in Procedure 2 are identified as occurring continuously in a short time.

Furthermore, in the method according to the present invention, the following operations can be added to estimate the combination of events in more detail. Thus, it is possible to estimate a combination of objects that cause a cache miss continuously in a short time.
Step 4: To reduce such misjudgment, it is possible to mistakenly find a case in which multiple events occur in the same range from the method of estimating the combination of events or objects alone. In addition, information on the reference relationship between objects is used.
Step 5: In estimating the combinations of events or objects, grouping is performed according to the type of heap in addition to the range of instruction addresses, thereby limiting to only combinations that can actually optimize object placement, etc. . As the type of heap, for example, a distinction between a new generation area (nursery) and an old generation area (tenure) can be used.

  The method according to the present invention can be combined with existing technologies such as programming using an object-oriented language, a program development environment, or related technologies thereof, and such combined technologies are also within the technical scope of the present invention. included. Similarly, a development system including a method or a programming environment including the technique of the present invention is also included in the technical scope of the present invention. In addition, the techniques of the present invention include steps in a method for estimating frequent events, including FPGA (field programmable gate array), ASIC (application specific integrated circuit), and equivalent hardware logic elements, A programmable integrated circuit, or a combination thereof, can be provided as a program form that can be stored, that is, as a program product. Specifically, as a form of a custom LSI (Large Scale Integrated Circuit) having a data input / output, a data bus, a memory bus, a system bus, etc., means for implementing a frequent event according to the present invention, a device, and an embedded device The form of the program product stored in the integrated circuit is also included in the technical scope of the present invention.

  According to the present invention, a combination of a plurality of events that occur frequently and continuously in a short time, such as cache misses, from a discrete sample of events collected by the performance monitor function of the processor can be obtained without using static analysis. Can be detected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. These are merely examples, and the technical scope of the present invention is not limited to these.

FIG. 1 shows an overall flow diagram of a method for estimating frequently occurring events according to one embodiment of the present invention. In one embodiment, the method according to the invention uses the following procedure.
S100: Collect a sample using the performance monitor for information on the instruction address where the event occurred and, if necessary, additional information about the event details.
S110: The events are grouped according to a specific instruction address range such as a method or a basic block.
S120: Event statistical processing is performed for each group, and events (frequent events) occurring at a frequency equal to or higher than a certain threshold are extracted.
S130: The extracted frequent event is specified as an event occurring continuously in a short time.

  That is, the method according to the present invention uses steps (S110) to (S130) to identify combinations of events that frequently occur continuously in a short time, and the identified event combinations continue in a short time. Can be estimated.

FIG. 2 shows a flowchart of a procedure for estimating a combination of objects that cause a cache miss continuously in a short time according to an embodiment of the present invention. In one embodiment, the method according to the invention uses the following procedure.
S200: Collect a sample of the instruction address where the cache miss occurred and the reference object and field to be accessed at that time using the performance monitor.
S210: Group cache miss events by specific instruction address range (for example, method).
S220: Event statistical processing is performed for each group, and a field causing a cache miss exceeding a certain threshold (hereinafter referred to as a frequent field) and an object class (hereinafter referred to as a frequent class) are extracted.
S230: When there are a plurality of frequently appearing classes, the combination of these objects is specified to cause consecutive cache misses. Similarly, when there is a class including a plurality of frequently appearing fields, these fields are specified to cause consecutive cache misses.

  That is, in the method according to the present invention, the method for estimating the combination of objects shown in FIG. 2 can be used in addition to the method for estimating frequently occurring events shown in FIG. Thereby, the method according to the present invention can perform an operation for estimating a combination of events in more detail.

  According to the procedure shown in FIG. 2, it is possible to specify a combination of objects that cause successive cache misses and a field that causes successive cache misses. According to this information, in the method according to the present invention, allocation or garbage collection (abbreviated as GC) is performed so that a set of objects identified as consecutively causing a cache miss enters the same cache line in the memory. It is possible to automatically generate, using statistical processing, information indicating that it is desirable to arrange an object of a class including a plurality of frequently appearing fields so as not to cross the boundary of the cache line. Therefore, by using the method according to the present invention, it is possible to estimate frequently occurring events based on discrete event samples and optimize the arrangement of objects in the memory using the estimated information. Program performance can be improved.

  In the method according to the present invention, as shown in the above-mentioned step (S210), before the statistical processing of the event samples, each instruction address range (for example, method) is divided, and each is statistically processed independently. There is a feature. As a result, it can be determined that an event that occurs in a short instruction address range occurs at a timing close in time. In other words, in the method according to the present invention, information that a specific event occurs in a spatially limited range of instruction addresses is used, and based on the information, the specific event continues in a short time. It is estimated that the event has occurred. This is because, from a discrete sample, it is logically impossible to obtain temporal information that a specific event occurrence is continuous in a short time.

  Such estimation in the method according to the present invention is based on the assumption that the execution of a certain instruction address range (method) is continuous in time within the execution time of the entire program. However, this assumption may not hold in situations where a method is called in multiple contexts (simple setter / getter, etc.). However, since such simple methods are mostly expanded inline, it can be solved by performing sampling after optimization of inline expansion is performed.

  In order to perform classification for each instruction address range in the above-described step (S110), there may be a need to map the correspondence between the instruction address and the range (for example, method). However, this is much smaller than the information from the instruction address required for the existing technology to the source code or byte code.

  In order to reduce the amount of processing of the above-described processing procedure, when performing the processing after step (S120), by targeting only samples whose number in the range exceeds a certain threshold, in other ranges The processing for the sample can be omitted.

  Although the above description uses a cache miss as an example, the method according to the present invention is applicable to other events.

FIG. 3 shows a flow chart of a procedure for using the reference relationship information between objects according to an embodiment of the present invention. Taking the cache miss event as an example, the method according to the present invention uses the following procedure.
S310: The cache miss events are grouped for each specific instruction address range (for example, method or basic block).
S320: Statistical processing of events is performed for each group, and classes (hereinafter referred to as frequent classes) that cause cache misses more than a certain threshold value within the range are extracted.
S330: Among objects having a cache miss, an object that is an instance of a frequent class is examined, and if an object of the frequent class exists, a combination of a reference source class and a reference destination class is found. Record the number of occurrences for each.
S340: Among the combinations of the reference source class and the reference destination class generated here, an object whose appearance count exceeds a certain threshold is identified as an object that is continuously accessed in a short time.

  The procedure shown in FIG. 3 is to reduce erroneous determinations in the method shown in FIGS. 1 and 2 described above, such as when a plurality of events are accidentally found in the same range. Can be used. In this procedure, in addition to performing the statistical processing of the sample for each range by dividing the instruction address range in step (S310), information that the objects are connected in a reference relationship is used. By doing so, it is possible to improve the accuracy of estimation.

  In the method according to the present invention, when grouping is performed in step (S310) and when the reference relationship between objects is examined in step (S330), grouping is performed based on the heap type in addition to the instruction address range. By performing the above, it is possible to limit the analysis of the reference relationship to only combinations that can actually optimize the object arrangement. For example, as a heap, a distinction between a new generation area (nursery) and an old generation area (tenure) can be used. Therefore, for example, an object in the nursery area and an object in the tenure area are not easily moved so as to ride on the same cache line in the existing GC processing, so a sample based on the type of heap By classifying and processing, it is possible to prevent such a combination from being detected.

  Similarly, in the method according to the present invention, when grouping by reference destination class in step (S320), an offset in the object of the reference destination address or an instruction address causing a cache miss is further used. You may classify it finely.

Example 1
The example which estimates the combination of the several object which causes a cache miss continuously using the method which concerns on this invention is shown. For example, a case where the cache miss sampling result in the performance monitor is as shown in the following table will be described.

  When this example is processed, for method1, first, a cache miss is caused by accessing four types of classes. However, if the threshold used in the above step (S120) is 10%, class A, class B, and class D are frequent classes. It becomes. Here, the objects referred to in the objects of these classes that actually cause the cache miss are examined. For example, if many objects of class B and class C are referenced from the sampled objects of class A, since class B is also a frequent class, the combination of class A and class B is specified as an object to be accessed simultaneously. The same processing is performed for method2 and method3, but there are no candidates because a plurality of frequent classes are not included.

  For these processes, before creating the table as above, only the method that caused the cache miss is first examined, and if the cache miss for each method does not reach the threshold, the reference The processing for checking the object class and the statistical processing for the number of mistakes for each class may be omitted. In particular, in order to find an object header from a reference destination address and resolve it to a class, a processing amount that cannot be ignored is necessary. Therefore, omitting this has an effect of reducing measurement overhead. In the above example, for example, a cache miss of 45% occurs in method 1, 5% in method 2, and 20% in method 3. Here, when the threshold value is 15%, method 2 is excluded from the processing target, and for the cache miss that occurs in method 2 and others, the reference destination object need not be investigated.

  In the above example, let us consider a case where processing is not performed separately for each range (here, method). For example, classA may refer to an object of classB or an object of classC. Then, since class A, class B, and class C cause many cache misses on average, if they are handled as an average without dividing each method, the effect is not expected because cache misses do not occur continuously. Can be a candidate for optimization.

(Example 2)
A case where a plurality of fields that cause consecutive cache misses is estimated using the method according to the present invention will be described. For example, assume that the cache miss sampling result in the performance monitor is as shown in the following table.

  As in the case of a plurality of objects, processing is performed separately for each method. For example, in class A, there are many cache misses at two offsets of 8 bytes and 32 bytes. In such a case, since the frequently accessed class A object crosses the cache line boundary, there is a possibility that access to one object causes a plurality of cache misses. Therefore, by arranging the objects of class A so as not to cross the cache line boundary, cache misses can be reduced. However, such a sample can be obtained even when different objects of the same class cause a cache miss in method1, but this case has no effect.

[Hardware configuration for estimating frequent events]
FIG. 4 is a diagram showing a hardware configuration of a frequent event estimation device according to an embodiment of the present invention. In FIG. 4, the frequent event estimation device is an information processing device 1000, and its hardware configuration is illustrated. In the following, an overall configuration of an information processing apparatus typified by a computer will be described, but it goes without saying that the minimum required configuration can be selected according to the environment.

  The information processing apparatus 1000 includes a CPU (Central Processing Unit) 1010, a bus line 1005, a communication I / F 1040, a main memory 1050, a BIOS (Basic Input Output System) 1060, a parallel port 1080, a USB port 1090, a graphic controller 1020, and a VRAM 1024. , An audio processor 1030, an I / O controller 1070, and input means such as a keyboard and mouse adapter 1100. Storage means such as a flexible disk (FD) drive 1072, a hard disk 1074, an optical disk drive 1076, and a semiconductor memory 1078 can be connected to the I / O controller 1070.

  A microphone 1036, an amplifier circuit 1032, and a speaker 1034 are connected to the audio processor 1030. A display device 1022 is connected to the graphic controller 1020.

  The BIOS 1060 stores a boot program executed by the CPU 1010 when the information processing apparatus 1000 is activated, a program depending on the hardware of the information processing apparatus 1000, and the like. An FD (flexible disk) drive 1072 reads a program or data from the flexible disk 1071 and provides it to the main memory 1050 or the hard disk 1074 via the I / O controller 1070. FIG. 4 shows an example in which the hard disk 1074 is included in the information processing apparatus 1000, but an external device connection interface (not shown) is connected to the bus line 1005 or the I / O controller 1070. A hard disk may be connected or added to the outside of 1000.

  As the optical disk drive 1076, for example, a DVD-ROM drive, a CD-ROM drive, a DVD-RAM drive, or a CD-RAM drive can be used. In this case, it is necessary to use the optical disk 1077 corresponding to each drive. The optical disk drive 1076 can also read a program or data from the optical disk 1077 and provide it to the main memory 1050 or the hard disk 1074 via the I / O controller 1070.

  The computer program provided to the information processing apparatus 1000 is stored in a recording medium such as the flexible disk 1071, the optical disk 1077, or a memory card and provided by the user. This computer program is read from the recording medium via the I / O controller 1070 or downloaded via the communication I / F 1040 to be installed and executed in the information processing apparatus 1000. The operation that the computer program causes the information processing apparatus to perform is the same as the operation in the apparatus that has already been described, and is therefore omitted.

  The aforementioned computer program may be stored in an external storage medium. As the storage medium, in addition to the flexible disk 1071, the optical disk 1077, or the memory card, a magneto-optical recording medium such as an MD or a tape medium can be used. Further, a storage device such as a hard disk or an optical disk library provided in a server system connected to a dedicated communication line or the Internet may be used as a recording medium, and a computer program may be provided to the information processing apparatus 1000 via the communication line. Good.

  In the above example, the information processing apparatus 1000 has been mainly described. However, the information described above is obtained by installing a program having the function described in the information processing apparatus in a computer and causing the computer to operate as the information processing apparatus. Functions similar to those of the processing device can be realized.

  This apparatus can be realized as hardware, software, or a combination of hardware and software. A typical example of implementation using a combination of hardware and software is implementation on a computer system having a predetermined program. In such a case, the predetermined program is loaded into the computer system and executed, whereby the program causes the computer system to execute the processing according to the present invention. This program is composed of a group of instructions that can be expressed in any language, code, or notation. Such instructions can be either or both of the following: (1) conversion to another language, code, or notation; (2) replication to other media; Can be executed after the Of course, the present invention includes not only such a program itself but also a program product including a medium on which the program is recorded. The program for executing the functions of the present invention can be stored in any computer-readable medium such as a flexible disk, MO, CD-ROM, DVD, hard disk device, ROM, MRAM, and RAM. Such a program can be downloaded from another computer system connected via a communication line or copied from another medium for storage on a computer-readable medium. Further, such a program can be compressed or divided into a plurality of parts and stored in a single or a plurality of recording media.

  Although the present invention has been described based on the embodiment, the present invention is not limited to the above-described embodiment. The effects described in the embodiments of the present invention are only the most preferable effects resulting from the present invention, and the effects of the present invention are limited to those described in the embodiments or examples of the present invention. Is not to be done.

1 is an overall flow diagram of a method for estimating frequently occurring events according to an embodiment of the present invention. FIG. It is a flowchart of the procedure which estimates the combination of the object which causes a cache miss continuously in a short time based on one Embodiment of this invention. It is a flowchart of the procedure which uses the information of the reference relationship between objects based on one Embodiment of this invention. It is a figure which shows the hardware constitutions of the frequent event estimation apparatus based on one Embodiment of this invention.

Explanation of symbols

  1000 Information processing equipment

Claims (10)

A method for identifying events that occur continuously in time based on discrete event samples in time,
Grouping the events into specific instruction address ranges;
Extracting an event that occurs at a frequency equal to or greater than a predetermined threshold for each of the grouped groups;
Classifying the extracted events as events that occur continuously in time.   The method of claim 1, wherein the discrete event sample is an event sample using a performance monitor.   The method of claim 1, wherein the grouping step further groups the events by a range of specific instruction addresses associated with a method or basic block. Further, the step of specifying the instruction address where the event has occurred, the referenced object and field to be accessed, and
Grouping the events into specific instruction address ranges;
Extracting a field in which the event occurs and a class of the object at a frequency equal to or higher than a predetermined threshold for each of the grouped groups;
If there are a plurality of classes of the extracted object, the combination of the objects is classified as a combination that continuously generates the event, and
The method of claim 1.   The method according to claim 4, wherein the step of classifying the event as a combination that generates an event further uses a grouping based on a heap type to classify only combinations that can optimize object placement.   5. The method of claim 4, comprising placing the objects classified as combinations that generate the events in succession to enter the same cache line in memory.   The method according to claim 4, further comprising restricting an object of a class including a plurality of the fields in which the event occurs at a frequency equal to or higher than the predetermined threshold from being placed in different cache lines.   The computer program for performing the step of any method of Claim 1 to 7 using a computer. A system for identifying events that occur continuously in time based on discrete event samples in time,
Grouping means for grouping the events into specific instruction address ranges;
An extracting means for extracting an event that occurs at a frequency equal to or higher than a predetermined threshold for each of the grouped groups;
And a classifying unit that classifies the extracted events as events that occur continuously in time. A method for identifying events that occur continuously in time based on discrete event samples in time using a performance monitor,
Grouping the events by a range of specific instruction addresses associated with a method or basic block;
Extracting an event that occurs at a frequency equal to or greater than a predetermined threshold for each of the grouped groups;
Classifying the extracted events as events that occur continuously in time;
Identifying the instruction address where the event occurred, the referenced object and field to be accessed;
Extracting a field and an object class in which the event occurs with a frequency equal to or higher than a predetermined threshold for each of the grouped groups;
If there are a plurality of classes of the extracted object, the combination of the objects is classified as a combination that continuously generates the event, and
Method.

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