JP2010101874A - Chip burn-in device capable of expanding control signal quantity - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip burn-in device expanding a control signal quantity. <P>SOLUTION: A controller enables the four first clock pins of an input interface in due order in the first time, outputs data in the input interface to corresponding input pins of the four first registers in each batch and preserves temporarily, and inputs from the input pin into the second register synchronously and preserves temporarily, and the controller enables the second clock pin of the input interface further in the next time, and transfers primarily all data signals preserved in the second register to an output interface. Thus, a function for expanding the input interface is attained, and even a memory burn-in device structure with an existing hardware facility enables chip burn-in, and thereby cost is saved on, and a convenient advantages is acquired at high speed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a kind of logic chip burn-in firmware structure, and more particularly to a chip burn-in apparatus, and more particularly to a chip burn-in apparatus capable of expanding the number of control signals.

  In general, a known memory chip often has a smaller number of pins than that of a known logic chip. Therefore, when a memory chip is burned in, a known standard memory chip burn-in device primarily outputs a programmable control signal. There is no need to increase the number of chip pins.

  FIG. 1 is a display diagram of a known interface card and burn-in board. The interface card 9 on the standard memory chip burn-in device shown has a plurality of output pins 91, and the plurality of output pins 91 are further burn-in boards. 90, the data in the interface card 9 is burned into the memory chip 92 of the burn-in board 90.

  On the other hand, a general logic chip differs from the above-mentioned memory chip in that the logic chip is provided with more than a hundred pins, so that a standard logic chip burn-in device has more than a hundred programmable control signal pins. It is necessary to perform chip burn-in work.

  As a result, when a burn-in device for a memory chip is originally modified and applied to a burn-in device for a logic chip, the original memory chip burn-in device has several tens of output pins. In addition to modifications to hundreds of output pins, other internal hardware modifications must also be made, leading to longer pre-burn-in preparatory work, which increases time, manpower, and hardware costs.

  The present invention provides a chip burn-in device capable of expanding a kind of control signal quantity, which includes a first bus, a second bus, at least two first registers, a second register, an output interface, an input interface, and a controller. To do.

  Each first register has N input pins, a clock pin, and N output pins, of which N refers to a positive integer greater than or equal to 1, and each of the N input pins and the clock pin is the first one. The N output pins are electrically connected to the second bus, and the N output pins are electrically connected to the second bus.

  The second register has M input pins, clock pins, and M output pins, of which M refers to a positive integer greater than N, and each of the M input pins is electrically connected to the second bus. And electrically connected to one output pin of each of the at least two first registers, the clock pin of the second register is also electrically connected to the second bus, and the M output pins are Each is electrically connected to the second bus.

  The output interface has M data output pins respectively corresponding to and electrically connected to the M output pins of the second register.

  The input interface is electrically connected to the first bus, the input interface having N input pins, at least two first clock pins, and one second clock pin, of which the at least two The number of first clock pins is the same as the number of the at least two first registers, and the at least two first clock pins are electrically connected to the clock pins of the at least two first registers, respectively. The second clock pin is electrically connected corresponding to the clock pin of the second register.

  The controller first enables the at least two first clock pins of the input interface and then enables the second clock pin of the input interface at the next time.

  In addition, the controller may be a controller having an equivalent effect such as an FPGA chip module or a PC. The controller enables the at least two first clock pins of the input interface, in order or in any order, batches the data signals of the N input pins of the input interface through the first bus, and enables them in order. The data is stored for a while through the N input pins of the first register corresponding to the first clock pin, and the data is stored for a while through the input pins in the second Gilesta in synchronization.

  Of these, the positive integer M is an integer multiple of the positive integer N, but may be a non-integer multiple, as long as M is a positive integer greater than N, and at least two first registers are latched and Can be done. The second register may be a latch.

  The present invention achieves the function of expanding the input interface, achieves the purpose of logic chip burn-in using the memory burn-in device structure without modifying the existing hardware equipment, saves cost, and provides fast and convenient advantages. Have.

FIG. 2 is a display diagram of the first embodiment of the present invention. As shown in the figure, this embodiment is a chip burn-in device capable of expanding a kind of control signal quantity, which includes a first bus 10, a second bus 20, four first registers 21, 22, 23, 24, a first. 2 register 31, output interface 40, input interface 1, and controller 5.
Each of the first registers 21, 22, 23, 24 has N input pins d1, d2, d3,..., Dn, a clock pin CLK, and N output pins q1, q2, q3,. qn. In this embodiment, the first registers 21, 22, 23, and 24 are latches.

  N is a positive integer of 1 or more (N ≧ 1), and N input pins d1, d2, d3,..., Dn, and clock pin CLK are electrically connected to the first bus 10, respectively. N output pins q1, q2, q3,..., Qn are electrically connected to the second bus 20, respectively.

  In the present embodiment, the first register 21 has 25 input pins d1, d2, d3,..., D25, 25 output pins q1, q2, q3,. It has CLK1. As shown in FIG. 2, the other first registers 22, 23, and 24 are also inferred from this.

  The second register 31 has M input pins D1, D2, D3,..., Dm, one clock pin CLK5, and M output pins Q1, Q2, Q3,. In the present embodiment, the second register 31 is a latch.

  M is a positive integer greater than N (ie, M> N ≧ 1), or M is an integer multiple of N or a non-integer multiple, where M is greater than N It may be a large positive integer.

  As shown in FIG. 2, the M input pins D1, D2, D3,..., Dm are electrically connected to the second bus 20 respectively, and the corresponding first registers 21, 22, 23, 24 are respectively connected. Are electrically connected to one output pin q1, q2, q3,..., Qn. In the present embodiment, the second register 31 has 100 input pins D1, D2, D3,..., D100 and 100 output pins Q1, Q2, Q3,.

  The output interface 40 is installed on the burn-in board 4 and has M data output pins DR1, DR2, DR3,. In this embodiment, the output interface 40 has 100 data output pins DR1, DR2, DR3,..., DR100, which are 100 output pins Q1, Q2, Q3,. -Corresponding to Q100, it is electrically connected.

  The input interface 1 is electrically connected to the first bus 10, and the input interface 1 includes N input pins p1, p2, p3,..., Pn, four first clock pins CLK1, CLK2, CLK3, It has CLK4 and one second clock pin CLK5. In this embodiment, the input interface 1 has 25 input pins p1, p2, p3,..., P25.

  Among them, the number of the four first clock pins CLK1, CLK2, CLK3, and CLK4 is the same as the number of the four first registers 21, 22, 23, and 24, and the four first clock pins CLK1, CLK2, CLK3, CLK4 is electrically connected to the clock pins CLK1, CLK2, CLK3, and CLK4 of the four first registers 21, 22, 23, and 24, respectively, and the second clock pin CLK5 is connected to the clock pin CLK5 of the second register 31. Corresponding and electrically connected.

  The controller 5 has one second clock pin, of which the number of the at least two first clock pins is the same as the number of the at least two first registers, and the at least two first clock pins. Each pin is electrically connected corresponding to the clock pin of the at least two first registers, and the second clock pin is electrically connected corresponding to the clock pin of the second register 31.

  The controller 5 may be a controller having an equivalent effect such as an FPGA chip module or a PC. The controller 5 selectively enables the four first clock pins CLK1, CLK2, CLK3, and CLK4 of the input interface 1 before the first time T1, respectively.

  The controller 5 enables the first clock pins CLK1, CLK2, CLK3, and CLK4 of the input interface 1 in order or in any order, and the 25 input pins p1, p2, p3,. 25 input pins of the first registers 21, 22, 23, 24 corresponding to the first clock pins CLK1, CLK2, CLK3, CLK4 which are sequentially transmitted through the first bus 10 and are sequentially enabled. It is temporarily stored in the first registers 21, 22, 23, 24 through d 1, d 2, d 3,..., d 25.

  The controller 5 enables the second clock pin CLK5 of the input interface 1 at the next time T2, and outputs a data signal to the 100 output pins Q1, Q2, Q3,. , And DR100 are outputted to the 100 data output pins DR1, DR2, DR3,.

  In summary, in this embodiment, the burn-in data I1, I2, I3, I4 (not shown) in the input interface 1 through the controller 5 is changed to the input pins p1, p2, p3,. To the first bus 10.

  When the first clock pin CLK1 is enabled, the input pins p1, p2, p3,..., P25 of the input interface 1 output the burn-in data I1 synchronously and store it in the first register 21 for a while. When the pin CLK2 is enabled, the input pins p1, p2, p3,..., P25 of the input interface 1 output the burn-in data I2 synchronously and store it in the first register 22 for a while, and the first clock pin CLK3 is When enabled, the input pins p1, p2, p3,..., P25 of the input interface 1 output the burn-in data I3 synchronously and store it temporarily in the first register 23, and the first clock pin CLK4 is enabled. When the input pins p1, p2, p3,..., P25 of the input interface 1 receive the burn-in data I4 synchronously. And force, briefly stored in the first register 24, and the burn-in data I1, I2, I3, I4 in synchronization are stored briefly in the second register 31. Further, when the second clock pin CLK5 is enabled, the burn-in data I1, I2, I3, and I4 in the second register 31 are provided to the output interface 40 and used for chip burn-in.

  As a result, the input pins p1, p2, p3,..., P25 of the input interface 1 are expanded through the first registers 21, 22, 23, 24 and the second register 31, and the output pins Q1, Q2, Q3,..., Q100. The present invention expands the pins without modifying the hardware equipment under the finite pin structure of the memory burn-in device, and has a large number of pins under the memory burn-in device structure. Achieve the purpose of allowing the logic chip to burn-in, save cost, fast and convenient.

  FIG. 3 is a display diagram of the second embodiment of the present invention. In this embodiment, the structure is almost the same as that of the above-described embodiment except that the input interface 51 in the controller 50 has only two first clock pins CLK1, CLK2, and only two first registers. 61 and 62 are provided. In this embodiment, each of the first registers 61 and 62 has 25 input pins d1, d2, d3,..., D25 and 25 output pins q1, q2, q3,. ing. Thus, the second register 32 has only 50 input pins D1, D2, D3,..., D50 and only 50 output pins Q1, Q2, Q3,. The number of the first registers 61 and 62 is elastically increased / decreased depending on the number of pins of the output interface 41 required by the burn-in board 42. Output pins q1, q2, q3,..., Q25 can be expanded.

It is a display figure of a known interface card and a burn-in board. It is a display figure of 1st Example of this invention. It is a display figure of 2nd Example of this invention.

Explanation of symbols

1, 51 Input interface 10 First bus 20 Second bus 21, 22, 23, 24 First register 31, 32 Second register 4, 42 Burn-in board 40, 41 Output interface 5, 50 Controller 61, 62 First register 9 Interface card 90 Burn-in board 91 Output pin 92 Memory chips p1, p2, p3,..., Pn input pins d1, d2, d3,..., Dn input pins D1, D2, D3,. q1, q2, q3,..., qn Output pins Q1, Q2, Q3,..., Qm Output pins CLK1, CLK2, CLK3, CLK4 First clock pin T1, T2 Time DR1, DR2, DR3,. DRm Data output pin CLK5 Second clock pin I1, I2, I3, I4 Burn-in data

Claims (5)

In chip burn-in equipment that can expand the number of control signals,
The first bus,
The second bus,
At least two first registers, each first register having N input pins, one clock pin, and N output pins, where N is a positive integer greater than or equal to 1, The N input pins and the clock pin are each electrically connected to the first bus, and the N output pins are each electrically connected to the second bus, the at least two first registers. When,
A second register having M input pins, one clock pin, and M output pins, where M refers to a positive integer greater than N, and the M input pins are A second register electrically connected to the second bus and electrically connected to one of the output pins of each of the at least two first registers;
An output interface having M data output pins respectively corresponding to and electrically connected to the M output pins of the second register;
An input interface electrically connected to the first bus, the input interface having N input pins, at least two first clock pins, and one second clock pin, of which at least The number of the two first clock pins is the same as the number of the at least two first registers, and the at least two first clock pins are electrically connected to the clock pins of the at least two first registers, respectively. The input interface connected and electrically connected corresponding to the clock pin of the second register;
A controller that first enables the at least two first clock pins of the input interface and then enables the second clock pin of the input interface at a further time; and
A chip burn-in device capable of expanding the number of control signals.   2. The chip burn-in device capable of expanding the number of control signals according to claim 1, wherein the controller includes an FPGA chip module.   2. The chip burn-in device capable of expanding the number of control signals according to claim 1, wherein the controller sequentially enables the at least two first clock pins of the input interface, and data signals of N input pins of the input interface are: Batch transmitted through the first bus and stored temporarily through N input pins of the first register corresponding to the first clock pin enabled in sequence, and stored temporarily through the input pins to the second Gilesta in synchronization. A chip burn-in device capable of expanding the number of control signals.   2. The chip burn-in device capable of expanding the number of control signals according to claim 1, wherein the controller enables the second clock pin of the input interface at the next time, and sets the M input pins of the second register. A chip burn-in device capable of expanding the number of control signals, wherein a data signal is output to the M data output pins of the output interface.   2. The chip burn-in device capable of expanding the control signal quantity according to claim 1, wherein the positive integer M is an integer multiple of the positive integer N. .

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