JP2010091773A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device with which satisfactory image display can be attained by reducing image persistence without impairing the quality of a displaying image. <P>SOLUTION: The plasma display device 100 using a plasma display panel 150 as a display device is provided with a non-linear scaler circuit 120 which displays an input image in a region over the entire part of the screen and partially changes a magnification rate or a reduction rate. The application of the magnification rate or reduction rate is successively changed for each time and video region by the non-linear scaler circuit 120, and thereby the display screen is moved without occurrence of chipping on the surface of the input screen, and the image persistence of the plasma display panel 150 is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display apparatus using a plasma display panel (hereinafter also referred to as PDP) as a display device.

  PDPs are broadly divided into AC and DC types in terms of driving. There are two types of discharge types: surface discharge type and counter discharge type. However, because of high definition, large screen, and easy manufacturing, Then, the surface discharge type of a three-electrode structure is the mainstream.

  In this surface discharge type PDP structure, at least a pair of substrates transparent at least on the front side are arranged so as to form a discharge space between the substrates, and partition walls for partitioning the discharge space are arranged on the substrate. In addition, a plurality of discharge cells are configured by arranging an electrode group on the substrate so that discharge is generated in a discharge space partitioned by the partition walls, and providing phosphors that emit red, green, and blue light emitted by discharge. Thus, the phosphor is excited by vacuum ultraviolet light having a short wavelength generated by discharge, and red, green, and blue visible light is emitted from the red, green, and blue discharge cells, respectively, to perform color display.

Such a PDP is capable of high-speed display compared to a liquid crystal panel, has a wide viewing angle, is easy to increase in size, and is self-luminous, so that the display quality is high. Recently, it has attracted particular attention among panel displays, and is used in various applications as a display device in a place where many people gather and a display device for enjoying a large screen image at home (see Patent Document 1). ).
JP 2003-131580 A

  By the way, in the plasma display apparatus using the PDP as a display device, when the same image is displayed for a certain time or more, so-called “burn-in” may occur.

  The present invention has been made in view of such a current situation, and an object of the present invention is to provide a plasma display device capable of realizing good image display by reducing image sticking without impairing the quality of an image to be displayed.

  In order to achieve the above object, the plasma display device of the present invention is a plasma display device using a plasma display panel as a display device, and displays an input image in the entire area of the screen and is partially enlarged or A non-linear scaler circuit that changes the reduction rate is provided, and the non-linear scaler circuit changes the application of the enlargement / reduction rate temporally and for each video area without causing a lack of display on the input screen. The display screen is moved to reduce the burn-in of the plasma display panel.

  According to the present invention, it is possible to reduce the burn-in without impairing the quality of an image to be displayed, and thus it is possible to provide a plasma display device capable of realizing a good image display.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a plasma display device according to an embodiment of the present invention. The plasma display apparatus 100 includes a nonlinear scaler circuit 120 that nonlinearly enlarges or reduces an input image, a microcomputer 110 that controls the nonlinear scaler circuit 120, a clock generator 130 that supplies a clock to the nonlinear scaler circuit 120, an image to the PDP 150, and the PDP 150. Is provided with a discharge circuit 140.

  Further, the non-linear scaler circuit 120 mixes the video data output from the switches 121 and 124, the line memories 122 and 123, and the line memories 122 and 123 for selecting a line memory for storing the video data, and generates a video. A data mixer 125 is provided.

  In the above configuration, control for nonlinearly expanding an input video signal will be described below. The digital video signal input to the non-linear scaler circuit 120 is selectively written into one of the two line memories 122 and 123 via the switch 121 by the write clock WCK. Both the line memories 122 and 123 are controlled by receiving the write clock WCK and the read clock RCK independently and the read enable signal RE generated from the clock generator 130.

  Then, a switch 124 controlled opposite to the switch 121 is switched for each horizontal line, and data written in the line memories 122 and 123 are alternately read by the read clock RCK. The pixel data read from the line memories 122 and 123 is input to the data mixer 125, which generates pixel data by mixing two pieces of pixel data at a mixing ratio according to a predetermined coefficient, and is nonlinear. Video data is output from the scaler circuit 120.

  FIG. 2 schematically shows the writing and reading operations of one of the two line memories 122 and 123, with the horizontal axis representing time and the vertical axis representing the memory address. The period indicates writing, and the latter one horizontal period indicates reading. The other line memory performs a read operation when one line memory is writing, and performs a write operation when reading.

  FIG. 3 is a diagram schematically showing a video display state with respect to the read state of the line memory in FIG. 2 (straight line A, curve B, and curve C in FIG. 2).

  Here, with respect to the write clock WCK, if the read clock RCK is also read linearly as shown by the straight line A in FIG. 2, it is the same as the input as shown in FIG. The image video is output. Here, it is possible to enlarge the video by increasing the readout speed, and conversely, it is possible to reduce the video by reducing the readout speed. Here, non-linear enlargement / reduction can be performed by changing the enable signal of the read clock with time.

  For example, when the reading method is as shown by the curve B in FIG. 2, the reading speed on the start side of the video is fast, the video is reduced, and the reading speed on the end side of the video is slow. As shown in FIG. 3B, the image is enlarged and the center is shifted to the left.

  Further, when the reading method as shown by the curve C in FIG. 2 is performed, since the reading speed on the start side of the video is slow, the video is enlarged and the reading speed on the end side of the video is high. The image is reduced, and the center is shifted to the right as shown in FIG. In this way, by providing the read enable signal RE in a non-linear manner, a non-linear video can be taken out.

  FIG. 4 is a diagram for explaining the operation of the data mixer 125 in FIG. A1, B1, C1, and D1 are pixel data input at the timing of the clock WCK input to the line memory. A2, B2, C2, D2, and E2 are pixel data described at the timing of RCK output from the line memory. Here, a method for generating output pixel data from a plurality of input pixel data will be described so as not to cause a sense of incongruity when video conversion with different input / output timings is performed as much as possible. For example, since A2 has the same timing as the data of A1, A2 = A1, but B2 is between A1 and B1, so the influence level on the A1 side and the influence degree on the B1 side are timingd. And B2 = A1 * β / (α + β) + B1 * α / (α + β). Similarly, C2 = B1 * θ / (γ + θ) + C1 * γ / (γ + θ) may be given.

  Further, similarly to having a line memory, having a frame memory makes it possible to take out a non-linear image in the vertical direction by operating the vertical image reading in a non-linear manner.

  By using the non-linear scaler block as described above, the non-linear video output as shown in FIGS. 3B and 3C is performed on the original image as shown in FIG. 3A. Things will be possible. As a result, by changing the application of the enlargement ratio and reduction ratio for each video area in time, it is possible to move the position of the video at regular intervals without losing the entire video, It is possible to realize a system that can reduce burn-in.

  This non-linear scaler circuit diverts a circuit used in aspect processing called “just”, which displays a 4: 3 image at 16: 9 with an enlargement ratio from the center to the periphery. If it can be done, it can be realized without adding a new circuit.

  Here, for comparison, a plasma display device 500 as shown in FIG. 5 will be described with reference to the drawings.

  FIG. 5 is a block diagram showing a schematic configuration of a plasma display device for comparison. The plasma display apparatus 500 displays an image on a scaler circuit 520 that enlarges or reduces an input image, a microcomputer 510 that controls the scaler circuit 520, a clock generator 530 that supplies a clock to the scaler circuit 520, a PDP 550, and a PDP 550. A discharge circuit 540.

  Also, the scaler circuit 520 includes switches 521 and 524 for selecting a line memory for storing video data, line memories 522 and 523, a circuit 525 for performing position control when reading the video output from the line memories 522 and 523, a line A data mixer 526 is provided that mixes video data output from the memories 522 and 523 to generate a video.

  In the above configuration, first, the scaler circuit 520 converts the video into display pixels. Here, assuming that a VGA (640 × 480 pixels) video is enlarged on an XGA (1024 × 768 pixels) display, the scaler 520 sets the horizontal magnification to 1024/640 times and 768/480 times vertical. By setting the magnification in the direction, it can be displayed in the size of the display.

  At this time, the switches 521 and 524 are controlled so that if the line memories 522 and 523 write to one of the lines, the other line memory is read so that the video is sequentially output to the data mixer 526. To do. The line memories 522 and 523 are set so that the write clock is 25.18 MHz of VGA and the read clock for output is 65.00 MHz of XGA. The read controller 525 and the data mixer 526 mix and output the sequentially input video data.

  In the above configuration, image sticking is reduced by moving the image position. The operation will be described below.

  The operation will be described with reference to FIG. FIG. 6A is a diagram showing timing for reading video from the line memory. Normally, by reading out data from the first pixel data position where the video is stored as shown in this figure, the boundary of the display and the boundary of the input video match to generate the video as shown in FIG. To do.

  Here, when the readout timing is delayed by several pixels as shown in FIG. 6C, the image is moved to the left with respect to the left boundary of the display as shown in FIG. 6D. Further, when the readout timing is advanced by several pixels as shown in FIG. 6E, the video image looks as if it has moved to the right as shown in FIG.

  Similarly to having a line memory, by having a frame memory, the video display position can be moved up and down with respect to the vertical position by changing the vertical video readout position.

  The movement operation as described above is performed by one pixel every several seconds to several minutes, and the light emission time of the pixel data displayed at one place is dispersed by providing a movement range of several pixels both horizontally and vertically. Is done. For example, by moving one pixel at a time within a range of ± 5 dots in both vertical and horizontal directions, as shown in FIG. 6 (g), the center pixel moves within the range of the surrounding 40 pixels. , The light emission time is dispersed and burn-in is reduced.

  However, in the method for reducing the burn-in in the comparative plasma display device as described above, since the entire screen is moved, peripheral images are put out of the screen. For example, as shown in FIG. 6D, the left side is missing. In an information display device such as a personal computer signal, the quality of the displayed image is degraded, such as when the information is insufficient, or when the area outside the black image is seen on the side opposite to the lacking side, the image is uncomfortable. The problem will occur.

  However, as described above, the plasma display device according to the embodiment of the present invention includes a non-linear scaler circuit that displays the input image in the entire area of the screen and partially changes the enlargement ratio or the reduction ratio. With this nonlinear scaler circuit, it is possible to reduce the burn-in of the PDP without causing defects in the display of the input screen by changing the application of the enlargement / reduction ratio temporally and for each video area. Become.

  As described above, the present invention is useful for providing a large-screen, high-definition plasma display device.

The block diagram which shows schematic structure of the plasma display apparatus by one embodiment of this invention. Diagram showing line memory write / read operations, with the horizontal axis representing time and the vertical axis representing memory address The figure which shows typically the state of the image display with respect to the reading state of the line memory in FIG. The figure for demonstrating operation | movement of the data mixer in FIG. Block diagram showing schematic configuration of plasma display device for comparison The figure for demonstrating the operation | movement of the burning reduction in the plasma display apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Plasma display apparatus 110 Microcomputer 120 Nonlinear scaler circuit 121, 124 Switch 122, 123 Line memory 125 Data mixer 130 Clock generator 140 Discharge circuit 150 Plasma display panel (PDP)

Claims (1)

A plasma display apparatus using a plasma display panel as a display device, comprising: a non-linear scaler circuit that displays an input image in an entire screen area and partially changes an enlargement ratio or a reduction ratio; By changing the application of the enlargement / reduction ratio over time and for each video area, the display screen can be moved without causing any chipping in the display of the input screen to reduce the burn-in of the plasma display panel. A plasma display device.

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