JP2010088186A - Motor control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a system in the prior art wherein it might malfunction because a ground line fluctuates and noise arises and there is low reliability on data serially communicated in the meantime, by a large current flowing at drive of a motor, when controlling the motor, based on a set value set from outside, using serial communication. <P>SOLUTION: A motor control circuit achieves motor control with reduced malfunction of a motor, by validating only reliable data, while filtering unreliable data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a motor control circuit, and more particularly to a motor control circuit that performs external control using serial communication.

  For example, Japanese Patent Application Laid-Open No. H10-228561 discloses a transfer technique when a large amount of data is transferred between a servo motor and a computer. In Patent Document 1, there is a measurement device that samples servo motor status data, and there is a storage device that stores measurement results measured by the measurement device. The contents stored in the storage device are stored using a microcomputer and a serial conversion device. Output to the CPU.

  Patent Document 2 discloses a servo motor device that includes a serial interface circuit for serial transmission to a controller in the servo motor device. In Patent Document 2, motor ID information is divided, and the divided motor ID information is superimposed on magnetic pole information from a ball sensor and serially transmitted to a controller.

  In both cases, there is a disclosure of a technique for communicating with a servo motor. However, motor control is a technique in which a microcomputer communicates unrelated data directly by serial communication.

In conventional motor control, drivers are required according to the number of motors, and in order to control a plurality of motors, the same number of drivers are required. In recent years, ICs incorporating a plurality of driver functions have been sold. In a configuration in which a plurality of drivers are incorporated, for example, Patent Document 3 proposes a multi-channel load driving device that drives a plurality of motors.
Japanese Patent Laid-Open No. 9-9678 JP-A-4-229088 JP2007-306637

  However, when the driver IC is controlled from an external microcomputer using a signal line, the driver IC may collide with a large current changing operation of the motor. At that time, a large current flows through the motor at the moment of driving, and noise may get on the ground line of the driver IC.

  If a new set value is set to the signal line from the microcomputer, the new set value may be erroneously set under the influence of the noise. There has been a problem that the motor is damaged due to a malfunction caused by the erroneous setting.

  The present invention relates to a current supplied to the motor in a motor control circuit that controls driving of the motor based on a set value set through the serial communication using serial communication that communicates with two terminals of a clock terminal and a data terminal. An invalid period detection circuit that receives a control signal of a transistor that controls the period and outputs an invalid period signal indicating an invalid period, and a gate circuit that gates a clock applied from the clock terminal during the period when the invalid period signal indicates an invalid period And a motor control circuit comprising:

  Alternatively, in the motor control circuit that controls the driving of the motor based on the set value set through the serial communication using the serial communication that communicates with the two terminals of the clock terminal and the data terminal, the current supplied to the motor is An invalid period detection circuit that receives a control signal of a transistor to be controlled and outputs an invalid period signal indicating an invalid period; a gate circuit that gates a clock applied from the clock terminal during a period when the invalid period signal indicates an invalid period; A motor control circuit is provided.

  When controlling the motor from the outside of the present invention, it is possible to prevent malfunction due to an error in the set value.

  FIG. 1 is a block diagram showing a motor control circuit 1 of a motor control circuit according to the present invention. The motor control circuit 1 is connected to the microcomputer 2 and is controlled by the microcomputer 2. The microcomputer 2 has a serial port, and can use this serial port to control other ICs. Although a parallel port may be used, the parallel port requires a large number of external terminals for communication, and is not practical.

The serial port is generally composed of two terminals, a clock terminal and a data terminal synchronized with the clock terminal. Among them, the I ² C bus is particularly common and is used in many ICs. And versatility. This time, as an example, we will introduce a case using an I ² C bus. With the I ² C bus, a plurality of slave ICs can be connected, and the master IC can freely control the slave IC by designating the address of the slave IC determined individually and communicating with the slave IC. I can do it.

The detailed specification of the I ² C bus is a general matter, and details are disclosed on the website of Philips, etc., and are omitted here. ^Two signal lines used in the I ² C bus are a serial clock (SCK) and serial data (SDA), and SCK is applied from a terminal 104 and SDA is applied from a terminal 105, respectively. In order to start communication, it is necessary for the master IC to specify the address of the slave IC selected by communication. The master IC corresponds to the microcomputer 2, and the slave IC corresponds to the motor control circuit 1.

The motor control circuit 1 includes two driver circuits, a first driver circuit 7 and a second driver circuit 8 that drive the first motor 3 and the second motor 4. However, in order to control two driver circuits individually with one I ² C bus, it is not necessary to prepare two unique addresses for each motor driver circuit, and one unique address may be prepared. .

Here, in order to set a unique address, an address terminal is provided in this embodiment. The terminal 106, the terminal 107, and the terminal 108 correspond to this, and the lower 3 bits of the 7-bit unique address value assigned to the slave IC set by a general I ² C bus depend on the state of the terminal. It can be set from the outside. This is configured such that a maximum of 8 ICs can be connected to the same I ² C bus by changing the lower 3 bits. When only one is connected or when an external terminal cannot be provided, an internal ROM may be used to collate with ROM data.

As shown in FIG. 2, after a start condition for communication via the I ² C bus is sent from the microcomputer 2, a unique address value (7 bits) assigned to the slave IC is output in synchronization with the clock. Is done. The I ² C bus controller circuit 12 in the interface circuit 11 sends the data (address) sent after the start condition to the reception data buffer circuit 13. The reception data buffer circuit 13 sends the held data (address) to the address match detection circuit 14.

  The address match detection circuit 14 holds an address value therein in advance. If the sent data (address value) can be confirmed to be the address values indicating the first motor 3 and the second motor 4, the data from the microcomputer 2 is allowed to be transmitted sequentially, and this motor Communication with the control circuit is enabled.

  The address coincidence detection circuit 14 has two address values, that is, the address value of the first motor 3 and the address value of the second motor 4, and is set individually for each of the first motor 3 and the second motor 4. However, even if there is only one address, the first half of the 24 bits of the memory indicated by the one address is the setting of the first motor 3, and the latter half of the 24 bits is the setting of the second motor 4. If you divide it, you don't need two addresses.

Thus, it is not necessary to set a unique address for each motor driver circuit, and a single address as an IC can be set. As a result, even when a plurality of driver circuits are provided, it is sufficient to prepare one address of the I ² C bus, and even if the number of addresses is limited as IC identification, it can be used effectively.

Conventionally, when two motor drivers are mounted, since the ICs are separate, naturally, it is necessary to set each individually, and two addresses are required. However, even if the number of built-in motor drivers increases, This can be dealt with by simply increasing the capacity of the register, and communication with a plurality of motors is possible using only the address terminal of one I ² C bus. For example, even if there are 8 ICs with 4 motored drivers, there is no need for 32 addresses, and there may be 8 which is the same as the number of ICs.

  In this embodiment, when the communication of the set values for the two motor drivers is completed, the microcomputer 2 sends a stop condition for the completion of data transfer to the motor control circuit 1 to set the first motor 3 and the second motor 4. Ends. During the data transfer, the reception buffer circuit 13 writes the received data into the reception data storage register 15 in units of 8 bits.

  As the reception data buffer circuit 13 and the reception data storage register 15, a register (storage device) composed of flip-flops is used. Although it may be configured by a memory such as SRAM or DRAM, address management is required, and on the contrary, the chip area of the IC is increased and the system design is also complicated. If the registers are stored in a fixed order, address management is not required and necessary information can be stored efficiently.

  In general, if the motor operating environment is significantly changed during operation, the motor itself may be damaged, so the latest set value written in the received data storage register 15 is immediately updated. It is not reflected in the operating environment of 1 motor 3.

Reflects the most recent setting value of the motor, through the I 2 ^C bus, after the data transfer is completed by a stop condition, and the I 2 ^C bus clock terminal (SCK), separately provided motor driving pulses ( CLK1) terminal 100 is used to detect a change in the drive pulse, and the latest setting is reflected in the motor operating environment according to the timing of the change. The motor driving pulse (CLK1) applied from the terminal 100 is removed by the first shaping noise removal circuit 20 to remove noise such as whiskers, and is applied to both the first rise detection circuit 24 and the first delay circuit 28. The

  The first rise detection circuit 24 detects a change in the drive pulse (CLK1) from the stop state. The configuration of the first rising edge detection circuit 24 has a comparator and a counter inside, and if there is no change for a certain period, it is determined as a stopped state. Is notified to the first motor mode setting holding circuit 16. The first motor mode setting holding circuit 16 transfers the data held in the reception data storage register circuit 15 as it is in accordance with the signal from the first rising detection circuit 24.

  The first delay circuit 28 delays the drive pulse (CLK1). Since the first delay circuit 28 does not require a delay as large as one cycle, it is composed of a basic delay circuit in which several stages of buffers are combined. If sufficient time is required, a shift register may be used to delay. While being delayed by the first delay circuit 28, the set value of the first motor mode setting holding circuit 16 is reflected in the motor operating environment provided in the first driver circuit 7 that actually controls the motor. It will be.

FIG. 3 shows a detailed timing diagram in which the latest set value is reflected by the rising change of the motor drive pulse (CLK1) after the stop condition through the I ² C bus. First, the latest motor setting value is held in the reception data storage register circuit 15. Next, the rising change of the motor driving pulse (CLK1) and the motor driving pulse (CLK2) is detected, and the latest setting value held in the reception data storage register circuit 15 at the timing is changed to the first motor mode setting holding circuit. 16 and the second motor mode setting holding circuit 17.

  At this time, even if the latest data is stored in the reception data storage register circuit 15 after the stop condition, the operation reflecting the latest setting value is not performed immediately. In communication using a serial port, since the data is transmitted serially, the latest setting values are not completed in a short time. Since it takes time, there is a problem that it cannot always be updated at a fixed timing.

  Therefore, the drive pulse (CLK1) is used to determine the timing for reflecting the latest set value. The drive pulse (CLK1) is set to L level (stopped state) for a certain period, and then the latest motor set value is reflected at the timing of starting the operation (restart timing).

  By this process, the timing at which the latest set value is reflected on the first motor 3 can be clarified. However, since the drive pulse (CLK1) is directly related to the rotation of the motor, the content of the first motor mode setting holding circuit 16 is switched and it is difficult to control the rotation immediately. Therefore, a slight time difference is required. In order to create this slight time difference, the first delay circuit 28 is required.

  The point of this operation is that the latest setting value is stored in the reception data register circuit 15 using a relatively time-consuming serial port, and the driving pulse stop period for a certain period is used to obtain the latest setting value. It is configured to determine the update timing.

  With the above procedure, the microcomputer 2 can freely operate the timing for updating to the latest set value of the first motor 3. The motor is not always in the rotating state from the stopped state. It is common to change the setting value while the motor is rotating. If the setting value of the counter is changed during operation, there is a possibility that a malfunction will be moved over, resulting in inconvenience that continuous motor operation cannot be performed. Therefore, it is the safest timing for the motor to set the drive pulse to a stop state for a certain period and update the set value at the next operation start timing.

The capacity of the reception data storage register circuit 15 needs to have a storage capacity corresponding to the number of bits necessary to control the motor. If there are about 48 bits, the capacity of the first motor 3 and the second motor 4 can be controlled. The required number of bits. Assuming that the reception data buffer circuit 13 is 8 bits, the data is full when it is transmitted to the reception data storage register circuit 15 six times. That is, after transmitting data 6 times through the I ² C bus, it is necessary to send a stop condition to complete the data.

  Further, it is convenient that the reception data storage register circuit 15 has the same number of bits as the sum of the first motor mode setting holding circuit 16 and the second motor mode setting holding circuit 17. If the number of bits is the same, there is no need for an address decoder or the like, and the data can be simply transferred to the same bit position as it is, so that a simple configuration is possible.

  FIG. 4 shows an internal block diagram of the first driver circuit 7. The first driver circuit 7 includes a clock rise / fall detection circuit 71 for controlling the motor, an excitation mode setting circuit 72 for setting each excitation mode of the motor, and a reference for generating a reference voltage and determining a motor current. In accordance with the detection result from the voltage generation circuit 73 and the rising / falling detection circuit 71 and the setting signal from the excitation mode setting circuit 72, the phase advance counter 74 that operates, the transistor 50 that actually controls the first motor 3, A pseudo sine wave generation circuit 76 that receives signals from the phase excitation signal generation circuit 75, the reference voltage generation circuit 73, and the phase advance counter 74 that performs switching control of 51, 52, and 53, and generates a pseudo sine wave. A PWM control circuit 77 that receives a sine wave from the wave generation circuit 76 and generates a PWM waveform corresponding to the sine wave is provided.

In the first motor mode setting holding circuit 16, in order, the first 4 bits (from the first bit to the fourth bit) are used for setting the rising / falling detection circuit 71, and the next 4 bits (from the fifth bit to the fifth bit). 8 bits) are used for setting the excitation mode setting circuit 72, the next 4 bits (9th to 12th bits) are used for setting the advance counter 74, and the next 4 bits (13th bit). (Up to the 16th bit) are used for the setting of the phase excitation signal generation circuit 75, and the next 4 bits (from the 17th bit to the 20th bit) are used for the setting of the reference voltage generation circuit 73. The order of each bit may be matched to the operating environment of the first driver circuit.
The phase excitation signal generation circuit 75 uses the count value from the phase advance counter 74 to generate a signal necessary for the excitation mode. With these series of settings, the motor control circuit 1 outputs two-phase drive terminals φ1 (A), φ2 (AB), φ3 (B), and φ4 (BB) to the first motor 3.

  As a specific output example, FIG. 5 shows a timing chart of the two-phase excitation mode, and FIG. 6 shows a timing chart of the 1-2 phase excitation mode. Various motor excitation modes can be freely set according to the phase advance counter value from the phase excitation signal generation circuit 75.

In the above-described embodiment, a case where a two-phase stepping motor is used has been described. However, even in a three-phase motor and a five-phase motor, the basic circuit configuration is not significantly changed as the number of control transistors increases.
<< Detailed explanation >>
The motor control circuit 1 may collide at the moment of receiving a set value from the microcomputer 2 using the signal line of the I ² C bus, just during the large current change operation of the first motor 3 and the second motor 4. At that time, a large current flows through the motor at the moment of driving, and noise may be applied to the GND line of the motor control circuit 1, which may affect the operation of the entire IC.

Then, the signal line of the I ² C bus may be affected, and a new set value from the microcomputer 2 may be erroneously set due to the influence of the noise. Incorrect setting may cause the motor to malfunction and damage the motor or IC.

FIG. 8 shows the above operation. A GND noise may occur for 100 ns at the timing when the transistor drive signals (φ1 to φ4) that turn on and off the transistors 50 to 57 that control the driving of the first motor 3 and the second motor 4 change. It also affects the inside of the IC, and as shown in the output signal waveform, it also affects the signal waveform due to GND noise. Naturally, the set signal from the microcomputer 2 through the signal line of the I ² C bus becomes low in reliability during this GND noise period.

  Therefore, an invalid period signal is generated for a short period from the timing when the transistor drive signals (φ1 to φ4) rise so that the set signal from the microcomputer 2 is not taken during the period in which the GND noise occurs. This invalid period signal is created by the invalid period detection circuit 93. The invalid period detection circuit 93 detects the rising of the signal from the phase excitation signal generation circuit in the first driver circuit 7 and the second driver circuit 8, and creates a signal that becomes active for a certain period in which GND noise occurs. The constant period may be created using a counter or a delay circuit.

FIG. 9 illustrates a motor constant current control transistor drive signal (gate drive waveform) generated based on CLK1 used for motor control, an I ² C bus SCK (serial clock), an invalid period signal, a system The clock and the output from the gate circuit 94 are shown. Even if the system clock is stopped and sampling is stopped by the invalid period signal, only the noise can be removed from the output from the gate circuit 94 as shown in FIG. Although there is a condition that the sampling clock is fast to some extent and the invalid period signal is not so long, the influence of the GND noise can be ignored, and from the microcomputer 2 through the signal line of the I ² C bus. The signal set with can significantly improve the reliability.

FIG. 10 shows details of the inside of the gate circuit 94. Here, an example of a four-stage rising detection circuit is shown. The gate circuit 94 is provided on the clock terminal (SCK) side of the I ² C bus that particularly affects the gate circuit 94.

  First, an output from the clock generator 92 receives a signal from the crystal oscillator 90, and through a clock oscillation circuit 91 that generates a rectangular wave, a frequency dividing circuit (programmably changing the frequency dividing ratio of the signal from the clock oscillation circuit 91). The output from the clock generator 92). The clock output from the clock generator 92 is widely used inside the IC as a system clock used for timing of latches, flip-flops and the like inside the motor control circuit 1.

There are three input signals to the gate circuit 94. The bus clock signal (SCK) of the I ² C bus, the system clock from the clock generator 92, and the invalid period signal from the invalid period detection circuit. SCK is applied to data terminals of flip-flops connected in four stages in series, and a gate clock obtained by gating the system clock with an invalid period signal is used as the clock terminal of the flip-flop.

  With the above configuration, even if the GND noise is placed on the SCK, a configuration that is not affected by the GND noise can be achieved by using a four-stage flip-flop and a gate clock that avoids the GND noise period. Even if the system clock is not output for a certain period due to the GND noise, there is no influence of the system.

The reason is that the system clock is generally scheduled to be about 10 MHz or more. The crystal oscillator 90 uses an oscillator of about 20 MHz or more, and divides it by two to obtain a system clock. The I ² C bus clock signal (SCK) has a high-speed specification, but generally, about 1 MHz is often used, and GND is generated even if SCK is not sampled for about one cycle during a period of GND noise. Even if the SCK is changed at the timing after the noise disappears, the system clock is high speed, so that no problem occurs in the next processing.

  Further, in FIG. 10, the rise detection circuit is constituted by four stages of flip-flops connected in series, but it is effective in one or two stages. However, since the cause of the noise in question here is due to instantaneous level fluctuations between the GND line of the external circuit that sends out SCK and the GND line of the input circuit block of this IC, the first stage of the input circuit that hits the signal entrance If it is not inserted, it has no effect. Otherwise, once it is taken into the IC, it is necessary to take a special measure of double-triple so as not to cause a malfunction in the subsequent processing circuit.

  Although the best mode for carrying out the invention has been described above, the above embodiment is intended to facilitate understanding of the present invention and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

For example, although the motor driver circuit shown in FIG. 1 is a case with two built-in cases, it can be similarly used even when three or four motor drivers are built-in. FIG. 7 shows a case where four motor driver circuits are incorporated. Even when four motor driver circuits are built in, one unique address value may be prepared in advance in the address match detection circuit.
As described above, even if the number of motor driver circuits is increased, it is only necessary to increase the capacity of the register, and it is not necessary to newly provide an external terminal, so that the motor can be efficiently controlled.

It is a block diagram which shows the structure of the motor control circuit which concerns on this embodiment. It is a timing diagram which shows the outline | summary of the serial communication process which concerns on this embodiment. It is a timing diagram in the setting value update of the motor which concerns on this embodiment. 2 is a block diagram showing a configuration of a first driver circuit 7 according to the present embodiment. FIG. It is a timing diagram which shows the case of the two-phase excitation mode which concerns on this embodiment. It is a timing diagram which shows the case of the 1-2 phase excitation mode which concerns on this embodiment. It is a block diagram which shows the structure of the motor control circuit which concerns on this embodiment. It is a timing diagram which shows the GND noise which concerns on this embodiment. It is a timing diagram which shows the relationship between the invalid period signal which concerns on this embodiment, and another signal. It is a block diagram which shows the detail of the gate circuit which concerns on this embodiment.

Explanation of symbols

1 motor control circuit 2 microcomputer 3 first motor 4 second motor 5 third motor 6 fourth motor 7 first driver circuit 8 the second driver circuit 11 interface circuit 12 ^{I 2} C bus controller circuit 13 receives a buffer circuit 14 address match detection Circuit 15 Received data storage register circuit 16 First motor mode setting holding circuit 17 Second motor mode setting holding circuit 20 First shaping noise removing circuit 21 Second shaping noise removing circuit 24 First rising detection circuit 25 Second rising detection circuit 28 First delay circuit 29 Second delay circuit

Claims (3)

In the motor control circuit for controlling the driving of the motor based on the set value set through the serial communication, using the serial communication communicating with the two terminals of the clock terminal and the data terminal,
An invalid period detection circuit that receives a control signal of a transistor that controls a current supplied to the motor and outputs an invalid period signal indicating an invalid period;
A motor control circuit comprising: a gate circuit that gates a clock applied from the clock terminal during a period when the invalid period signal indicates an invalid period. The motor control circuit according to claim 1,
It has a clock oscillation circuit,
The gate circuit includes a logic circuit and a flip-flop, and the logic circuit creates a gate clock obtained by gating the signal from the clock oscillation circuit with the invalid period signal, and the gate clock is converted into the flip-flop. The motor control circuit according to claim 1, wherein the motor control circuit is applied to the motor. The gate circuit includes a plurality of flip-flops connected in series,
3. The motor control circuit according to claim 2, wherein the clock is applied to a first data terminal of the plurality of flip-flops, and the gate clock is applied to clock terminals of the plurality of flip-flops.

Images