JP2010087645A - Ring oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ring oscillator allowing the oscillation frequency thereof to be changed by forming a state equivalent to the state of changing the number of stages of inverter circuits to be used for oscillation without changing the number of stages of the inverter circuits to be used for the oscillation. <P>SOLUTION: After putting the inverter circuit 3<SB>9</SB>into an inactive state upon initialization, when PMOS transistors 11<SB>1</SB>, 11<SB>3</SB>-11<SB>7</SB>and 11<SB>9</SB>and NMOS transistors 12<SB>2</SB>, 12<SB>4</SB>-12<SB>6</SB>and 12<SB>8</SB>are turned off, the ring oscillator inside a voltage controlled oscillation part 1 is operated as the one in which the number of the stages of the inverter circuits is 9. After putting the inverter circuits 3<SB>1</SB>, 3<SB>4</SB>and 3<SB>7</SB>into an inactive state upon initialization, when the PMOS transistors 11<SB>1</SB>, 11<SB>3</SB>-11<SB>7</SB>and 11<SB>9</SB>and the NMOS transistors 12<SB>2</SB>, 12<SB>4</SB>-12<SB>6</SB>and 12<SB>8</SB>are turned off, the ring oscillator inside the voltage controlled oscillation part 1 is operated as the one equivalent to the one in which the number of the stages of the inverter circuits is 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a ring oscillator formed by ring-connecting inverter circuits.

As a ring oscillator with a ring connection of inverter circuits, a ring circuit that can change the oscillation frequency by inserting a selector circuit in the oscillation signal path and changing the number of stages of the inverter circuit used for oscillation by this selector circuit Has been proposed (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 9-238053 Japanese Patent Laid-Open No. 5-343956 WO2005-039051

  However, when a selector circuit is inserted into the oscillation signal path, a plurality of oscillation signals having different paths are given to the selector circuit, and there is a problem that jitter characteristics deteriorate due to crosstalk.

  The present invention makes it possible to change the oscillation frequency by changing the number of stages of the inverter circuit used for oscillation without changing the number of stages of the inverter circuit used for oscillation. An object of the present invention is to provide a ring oscillator capable of obtaining characteristics.

  The ring oscillator disclosed herein includes a ring oscillation unit formed by ring-connecting an odd number of inverter circuits, and an inverter indicated by a control signal at a connection point of the odd number of inverter circuits when the ring oscillation unit is initialized. And an initializing unit for setting an initial potential for inactivating the circuit.

  According to the disclosed ring oscillator, the number of inverter circuits to be inactivated can be changed at the time of initialization of the ring oscillation unit by changing the instruction content of the control signal. That is, it is possible to create a state equivalent to a state in which the number of inverter circuits used for oscillation is changed without changing the number of inverter circuits used for oscillation, thereby changing the oscillation frequency. As a result, it is not necessary to insert a selector circuit for changing the oscillation frequency in the oscillation signal path, so that good jitter characteristics can be obtained.

  Hereinafter, the first embodiment and the second embodiment of the present invention will be described with reference to FIGS. 1 to 15 by taking the case where the present invention is applied to a voltage controlled oscillator as an example. It is not limited to 1st Embodiment and 2nd Embodiment, A various form can be taken, without deviating from the summary of this invention.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The first embodiment of the present invention includes a voltage controlled oscillator 1 and an initialization unit 2 that initializes the voltage controlled oscillator 1. In the first embodiment of the present invention, the ring oscillator in the voltage controlled oscillator 1 is configured by nine inverter circuits, and the voltage controlled oscillator 1 is operated with nine inverter circuits, or It is possible to select whether the inverter circuit is operated as an equivalent circuit having three stages.

In the voltage controlled oscillator 1, 3 _{1 to} 3 ₉ are inverter circuits, and 4 is an NMOS transistor. The inverter circuits 3 _{1 to} 3 ₉ are ring-connected to form a ring oscillator, and connect the high-potential side power supply node to the VDD power supply wiring 5 that supplies the positive power supply voltage VDD to connect the low-potential side power supply node. Is connected to the drain of the NMOS transistor 4. NMOS transistor 4, which forms a power supply voltage control circuit for controlling the power supply voltage on the low potential side of the inverter circuit 3 ₁ to 3 _9, grounding the source, is configured to control voltage VCNT is applied to the gate Yes.

Figure 2 is a circuit diagram showing a configuration of the inverter circuit 3 _1. The inverter circuit 3 ₁ is a CMOS type inverter, a PMOS transistor 6, and an NMOS transistor 7. Reference numeral 8 denotes a high potential side power supply node, and reference numeral 9 denotes a low potential side power supply node. The inverter circuits 3 _{2 to} 3 ₉ have the same configuration.

In FIG. 1, reference numeral 10 denotes an inverter circuit for outputting an oscillation signal. The inverter circuit 10, and outputs connected to the input terminal to the output terminal of the inverter circuit 3 _9, a signal obtained by inverting the output signal of the inverter circuit 3 ₉ as an oscillation signal OUT. The inverter circuit 10 is a CMOS type inverter circuit, which connects a high potential side power supply node to the VDD power supply wiring 5 and grounds a low potential side power supply node.

11 _{1 to} 11 ₉ are PMOS transistors. The PMOS transistor 11 _i (where i = 1, 2,..., 8; the same applies hereinafter) has a source connected to the VDD power supply line 5 and a drain connected to the output terminal of the inverter circuit 3 _i and the inverter circuit. it is connected to the 3 i which is a connection point between the input terminal of the _{+ 1} node N _i. PMOS transistor 11 ₉ connects the source connected to the VDD power supply line 5, the drain to node N ₉ is a connection point between the output terminal and the input terminal of the inverter circuit 3 ₁ of the inverter circuit 3 _9.

A control signal A is supplied to the gate of the PMOS transistor 11 ₁ . PMOS transistor 11 ₂ is connected to the gate to the source. A control signal A is applied to the gate of the PMOS transistor 11 ₃ . Control signal C is applied to a gate of the PMOS transistor 11 _4. Control signal E is applied to a gate of the PMOS transistor 11 _5. Control signal C is applied to a gate of the PMOS transistor 11 _6. Control signal A is applied to a gate of the PMOS transistor 11 _7. PMOS transistor 11 ₈ connects the gate to the source. Control signal A is applied to a gate of the PMOS transistor 11 _9.

Reference numerals 12 _{1 to} 12 ₉ denote NMOS transistors. NMOS transistor 12 _i has a drain connected to the node N _i, are grounded source. The NMOS transistor 12 ₉ has a drain connected to the node N ₉ and a source grounded.

NMOS transistor 12 ₁ is connected to the gate to the source. The gate of the NMOS transistor 12 ₂ is supplied with the control signal B. NMOS transistor 12 ₃ is connected to the gate to the source. Control signal D is applied to a gate of the NMOS transistor 12 _4. Control signal F is applied to the gate of NMOS transistor 12 _5. Control signal D is applied to a gate of the NMOS transistor 12 _6. NMOS transistor 12 ₇ connects the gate to the source. The gate of the NMOS transistor 12 ₈ is given a control signal B. The NMOS transistor 12 ₉ has a gate connected to the source.

  FIG. 3 is a circuit diagram showing a configuration of the initialization unit 2. The initialization unit 2 includes an inverter 13 and 2-input 1-output type selectors 14 to 17. The inverter 13 inverts the reset signal RESET and outputs a control signal A. The reset signal RESET is also used as the control signal B, and is set to the H level when the voltage controlled oscillator 1 is initialized, and set to the L level when the voltage controlled oscillator 1 performs the oscillation operation.

The selection operations of the selectors 14 to 17 are controlled by a selection control signal SEL. Selection control signal SEL, either the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ stages of the inverter circuit to operate as a nine-stage, or stages of the inverter circuit to operate as one equivalent of 3-stage This is a signal for selection. Selection control signal SEL, when operating the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ as the number of stages of inverter circuits of nine stages is the L level, as the number of stages of the inverter circuit is a three-stage and those of the equivalent Is set to H level.

  The selector 14 selects the control signal A when the selection control signal SEL = H level, and outputs the control signal A as the control signal C. When the selection control signal SEL = L level, the selector 14 selects the power supply voltage VDD. The power supply voltage VDD is output as the control signal C. The selector 15 selects the ground voltage 0V and outputs the ground voltage 0V as the control signal D when the selection control signal SEL = H level, and selects the reset signal RESET when the selection control signal SEL = L level. The reset signal RESET is output as the control signal D.

  The selector 16 selects the power supply voltage VDD when the selection control signal SEL = H level, and outputs the power supply voltage VDD as the control signal E. When the selection control signal SEL = L level, the selector 16 selects the control signal A. The control signal A is output as the control signal E. The selector 17 selects the reset signal RESET when the selection control signal SEL = H level, and outputs the reset signal RESET as the control signal F. When the selection control signal SEL = L level, the selector 17 selects the ground voltage 0V. The ground voltage 0 V is output as the control signal F. Table 1 shows the function of the initialization unit 2.

  That is, if the reset signal RESET = H level and the selection control signal SEL = L level, the control signal A = L level, the control signal B = H level, the control signal C = H level, the control signal D = H level, the control signal E = L level and control signal F = L level. When the reset signal RESET = L level and the selection control signal SEL = L level, the control signal A = H level, the control signal B = L level, the control signal C = H level, the control signal D = L level, the control signal E = H level and control signal F = L level.

  On the other hand, when the reset signal RESET = H level and the selection control signal SEL = H level, the control signal A = L level, the control signal B = H level, the control signal C = L level, the control signal D = L level, The control signal E = H level and the control signal F = H level. When the reset signal RESET = L level and the selection control signal SEL = H level, the control signal A = H level, the control signal B = L level, the control signal C = H level, the control signal D = L level, the control signal E = H level and control signal F = L level.

FIG. 4 is a circuit diagram showing a state at the time of initialization of the first operation example of the first embodiment of the present invention, and FIG. 5 is a timing chart showing a first operation example of the first embodiment of the present invention. The first operation example of the first embodiment of the present invention is a case where the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ stages of the inverter circuit is operated as the nine stages. In this case, at initialization, the reset signal RESET = H level and the selection control signal SEL = L level. In this way, as shown in Table 1, control signal A = L level, control signal B = H level, control signal C = H level, control signal D = H level, control signal E = L level, control signal F = L level.

As a result, as shown in FIG. 4, the state of the PMOS transistor 11 ₁ = ON, the state of the PMOS transistor 11 ₂ = OFF, the state of the PMOS transistor 11 ₃ = ON, the state of the PMOS transistor 11 ₄ = OFF, the PMOS transistor 11 ₅ State = ON, state of PMOS transistor 11 ₆ = OFF, state of PMOS transistor 11 ₇ = ON, state of PMOS transistor 11 ₈ = OFF, state of PMOS transistor 11 ₉ = ON.

Also, the state of the NMOS transistor 12 ₁ = OFF, the state of the NMOS transistor 12 ₂ = ON, the state of the NMOS transistor 12 ₃ = OFF, the state of the NMOS transistor 12 ₄ = ON, the state of the NMOS transistor 12 ₅ = OFF, the NMOS transistor 12 ₆ state = ON, NMOS transistor 12 ₇ state = OFF, NMOS transistor 12 ₈ state = OFF, NMOS transistor 12 ₉ state = OFF.

Therefore, as shown in FIG. 4, the levels of the nodes N _{1 to} N ₉ are the level of the node N ₁ = H level, the level of the node N ₂ = L level, the level of the node N ₃ = H level, and the level of the node N ₄ Level = L level, node N ₅ level = H level, node N ₆ level = L level, node N ₇ level = H level, node N ₈ level = L level, node N ₉ level = H level Become. In this case, only the inverter circuit 3 _1, input and output nodes are at both the same level (H-level) becomes inactive.

Next, the reset signal RESET = L level. In this way, as shown in Table 1, control signal A = H level, control signal B = L level, control signal C = H level, control signal D = L level, control signal E = H level, control signal F = L level. As a result, the PMOS transistors 11 _{1 to} 11 ₉ and the NMOS transistors 12 _{1 to} 12 ₉ are turned off, and the ring oscillator including the inverter circuits 3 _{1 to} 3 ₉ starts an oscillation operation.

In this case, since only the inverter circuit 3 ₁ is in an inactive state, first, the output of the inverter circuit 3 ₁ changes to the L level as shown in FIG. The output of the inverter circuit 3 ₂ changes to H level. The output of the inverter circuit 3 ₃ changes to the L level. The output of the inverter circuit 3 ₄ changes to H level. The output of the inverter circuit ₃₅ changes to the L level. The output of the inverter circuit 3 ₆ changes to the H level. Then, the output of the inverter circuit 3 ₇ changes to the L level. Next, the output of the inverter circuit 3 ₈ changes to H level. The output of the inverter circuit 3 ₉ changes to the L level.

Next, the output of the inverter circuit 3 ₁ changes to H level. The output of the inverter circuit 3 ₂ changes to the L level. The output of the inverter circuit 3 ₃ changes to H level. The output of the inverter circuit 3 ₄ changes to L level. The output of the inverter circuit ₃₅ changes to H level. The output of the inverter circuit 3 ₆ changes to the L level. Then, the output of the inverter circuit 3 ₇ changes to H level. Next, the output of the inverter circuit 3 ₈ changes to the L level. The output of the inverter circuit 3 ₉ changes to H level. Hereinafter, the output of the inverter circuit 3 ₁ to 3 ₉ is changed in the same manner, the oscillating operation of the inverter circuit 3 ₁ to 3 ₉ are performed.

Here, when one of the delay time of the inverter circuit 3 ₁ to 3 ₉ is T, the period of the oscillation signal OUT becomes 18T. In other words, the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ stages of the inverter circuit can be operated as a 9-stage. In this state, when the control voltage VCNT changes, the frequency of the oscillation signal OUT changes. When the control voltage VCNT becomes relatively high, ON resistance of the NMOS transistor 4 becomes relatively small, since the power supply voltage of the low potential side of the inverter circuit 3 ₁ to 3 ₉ is relatively low, the oscillation frequency relative To be high. When the control voltage VCNT is relatively low, ON resistance of the NMOS transistor 4 becomes relatively large, the power supply voltage of the low potential side of the inverter circuit 3 ₁ to 3 ₉ is relatively high, the oscillation frequency relative It becomes low.

FIG. 6 is a circuit diagram showing a state at the time of initialization of the second operation example of the first embodiment of the present invention, and FIG. 7 is a timing chart showing a second operation example of the first embodiment of the present invention. The second operation example of the first embodiment of the present invention is a case where the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ stages of the inverter circuit to operate as one equivalent of three stages. In this case, at initialization, the reset signal RESET = H level and the selection control signal SEL = H level. In this way, as shown in Table 1, control signal A = L level, control signal B = H level, control signal C = L level, control signal D = L level, control signal E = H level, control signal F = H level.

As a result, as shown in FIG. 6, the state of the PMOS transistor 11 ₁ = ON, the state of the PMOS transistor 11 ₂ = OFF, the state of the PMOS transistor 11 ₃ = ON, the state of the PMOS transistor 11 ₄ = ON, and the PMOS transistor 11 ₅ State = OFF, PMOS transistor 11 ₆ state = ON, PMOS transistor 11 ₇ state = ON, PMOS transistor 11 ₈ state = OFF, PMOS transistor 11 ₉ state = ON.

Further, the state of the NMOS transistor 12 ₁ = OFF, the state of the NMOS transistor 12 ₂ = ON, the state of the NMOS transistor 12 ₃ = OFF, the state of the NMOS transistor 12 ₄ = OFF, the state of the NMOS transistor 12 ₅ = ON, the NMOS transistor 12 ₆ state = OFF, NMOS transistor 12 ₇ state = OFF, NMOS transistor 12 ₈ state = ON, NMOS transistor 12 ₉ state = OFF.

Therefore, as shown in FIG. 6, the levels of the nodes N _{1 to} N ₉ are as follows: the level of the node N ₁ = H level, the level of the node N ₂ = L level, the level of the node N ₃ = H level, and the level of the node N ₄ Level = H level, Node N ₅ level = L level, Node N ₆ level = H level, Node N ₇ level = H level, Node N ₈ level = L level, Node N ₉ level = H level Become. In this case, the inverter circuits 3 ₁ , 3 ₄ , and 3 ₇ are inactivated at the same level (H level) at the input node and the output node.

Next, the reset signal RESET = L level. In this way, as shown in Table 1, control signal A = H level, control signal B = L level, control signal C = H level, control signal D = L level, control signal E = H level, control signal F = L level. As a result, the PMOS transistors 11 _{1 to} 11 ₉ and the NMOS transistors 12 _{1 to} 12 ₉ are turned off, and the ring oscillator including the inverter circuits 3 _{1 to} 3 ₉ starts an oscillation operation.

In this case, since the inverter circuits 3 ₁ , 3 ₄ and 3 ₇ are in an inactive state, as shown in FIG. 7, first, the outputs of the inverter circuits 3 ₁ , 3 ₄ and 3 ₇ change to the L level. . Next, the outputs of the inverter circuits 3 ₂ , 3 ₅ and 3 ₈ change to the H level. Next, the outputs of the inverter circuits 3 ₃ , 3 ₆ and 3 ₉ change to the L level. Next, the outputs of the inverter circuits 3 ₁ , 3 ₄ and 3 ₇ change to the H level. Next, the outputs of the inverter circuits 3 ₂ , 3 ₅ and 3 ₈ change to the L level. Next, the outputs of the inverter circuits 3 ₃ , 3 ₆ and 3 ₉ change to the H level. Hereinafter, the output of the inverter circuit 3 ₁ to 3 ₉ is changed in the same manner, the oscillating operation of the inverter circuit 3 ₁ to 3 ₉ are performed.

Here, when one of the delay time of the inverter circuit 3 ₁ to 3 ₉ is T, the period of the oscillation signal OUT becomes 6T. In other words, the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ stages of the inverter circuit can be operated as one equivalent of three stages. In this state, when the control voltage VCNT changes, the frequency of the oscillation signal OUT changes. When the control voltage VCNT becomes relatively high, ON resistance of the NMOS transistor 4 becomes relatively small, since the power supply voltage of the low potential side of the inverter circuit 3 ₁ to 3 ₉ is relatively low, the oscillation frequency relative To be high. When the control voltage VCNT is relatively low, ON resistance of the NMOS transistor 4 becomes relatively large, the power supply voltage of the low potential side of the inverter circuit 3 ₁ to 3 ₉ is relatively high, the oscillation frequency relative It becomes low.

As described above, according to the first embodiment of the present invention, the ring oscillator composed of inverters 3 ₁ to 3 _9, an initialization unit 2, a PMOS transistor 11 ₁ to 11 _9, NMOS transistors 12 ₁ 12 ₉ . As a result, at the time of initialization, and the reset signal RESET = H level, the selection control signal SEL = L level, then, by a reset signal RESET = L level, the inverter ring oscillator consisting of the inverter circuit 3 ₁ to 3 ₉ is operated as the number of stages of the circuit of nine stages, one of the delay time of the inverter circuit 3 ₁ to 3 ₉ When is T, it is possible to obtain an oscillation signal OUT in cycles is 18T. In this case, the frequency of the oscillation signal OUT can be changed by the control voltage VCNT.

Further, at the time of initialization, the reset signal RESET = H level, the selection control signal SEL = H level, then, by a reset signal RESET = L level, the ring oscillator composed of inverter circuits 3 ₁ to 3 ₉ inverter circuit the number of stages can be operated as the equivalent of 3 stages, one of the delay time of the inverter circuit 3 ₁ to 3 ₉ When is T, it is possible to obtain an oscillation signal OUT in cycles is 6T. In this case, the frequency of the oscillation signal OUT can be changed by the control voltage VCNT.

That is, according to the first embodiment of the present invention, by setting the selection control signal SEL to the L level or the H level, one or three of the ring oscillators composed of the inverter circuits 3 _{1 to} 3 ₉ are initialized. inverters can be inactivated, the ring oscillator composed of inverter circuits 3 ₁ to 3 _9, those stages of the inverter circuit is nine stages, or to perform the oscillating operation as the equivalent of 3-stage be able to. As a result, it is not necessary to insert a selector circuit for changing the oscillation frequency in the oscillation signal path, so that good jitter characteristics can be obtained.

In the first embodiment of the present invention, the provided NMOS transistors 4, a control voltage to change the power supply voltage of the low potential side of the inverter circuit 3 ₁ to 3 ₉ by VCNT, thereby so as to vary the oscillation frequency It is, but instead may be configured to vary the power supply voltage of the high potential side of the inverter circuit 3 ₁ to 3 _9.

In the first embodiment of the present invention, the present invention has been described as applied to a voltage controlled oscillator, without providing the NMOS transistor 4, the ground power supply node of the low potential side of the inverter circuit 3 ₁ to 3 ₉ You may make it do. In this case, it cannot be used as a voltage controlled oscillator having two oscillation frequency ranges, but can be used as a ring oscillator having two possible oscillation frequencies.

(Second Embodiment)
FIG. 8 is a circuit diagram showing a second embodiment of the present invention. The second embodiment of the present invention includes a voltage controlled oscillator 21 and an initialization unit 22 that initializes the voltage controlled oscillator 21. In the second embodiment of the present invention, the ring oscillator in the voltage controlled oscillator 21 is constituted by 15 inverter circuits, and the voltage controlled oscillator 21 is operated with 15 inverter circuits, or It is possible to select whether the inverter circuit is operated as equivalent to five stages or whether the inverter circuit is operated as equivalent to three stages.

In the voltage controlled oscillator 21, reference numerals 23 ₁ to 23 ₁₅ denote inverter circuits, and 24 denotes an NMOS transistor. The inverter circuit 23 ₁ to 23 ₁₅ is of the inverter circuit 3 ₁ to 3 ₉ the same structure shown in FIG. 1, is a ring connected constitute a ring oscillator, a power supply node of the high potential side VDD power supply wiring 25, and the power supply node on the low potential side is connected to the drain of the NMOS transistor 24. The NMOS transistor 24 forms a power supply voltage control circuit for controlling the power supply potential on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ , and is configured so that the source is grounded and the control voltage VCNT is applied to the gate. Yes.

Reference numeral 30 denotes an inverter circuit for outputting an oscillation signal. The inverter circuit 30, and outputs connected to the input terminal to the output terminal of the inverter circuit 23 _15, a signal obtained by inverting the output signal of the inverter circuit 23 ₁₅ as an oscillation signal OUT. The inverter circuit 30 is a CMOS type inverter circuit, which connects a power node on the high potential side to the VDD power wiring 25 and grounds the power node on the low potential side.

Reference numerals 31 _{1 to} 31 ₁₅ denote PMOS transistors. The PMOS transistor 31 _j (j = 1, 2,..., 14 and so on) has a source connected to the VDD power supply wiring 25 and a drain connected to the output terminal of the inverter circuit 23 _j and the inverter circuit. 23 _{j + 1} is connected to a node N _j which is a connection point with the input terminal. The PMOS transistor 31 ₁₅ has a source connected to the VDD power supply wiring 25 and a drain connected to a node N ₁₅ which is a connection point between the output terminal of the inverter circuit 23 _{15 and} the input terminal of the inverter circuit 23 ₁ .

A control signal A is supplied to the gate of the PMOS transistor 31 ₁ . PMOS transistor 31 ₂ is connected to the gate to the source. A control signal A is supplied to the gate of the PMOS transistor 31 ₃ . Control signal C is applied to a gate of the PMOS transistor 31 _4. Control signal E is applied to a gate of the PMOS transistor 31 _5. Control signal G is applied to a gate of the PMOS transistor 31 _6. Control signal I is applied to a gate of the PMOS transistor 31 _7.

Control signal K is applied to a gate of the PMOS transistor 31 _8. Control signal I is applied to a gate of the PMOS transistor 31 _9. Control signal G is applied to a gate of the PMOS transistor 31 _10. Control signal E is applied to a gate of the PMOS transistor 31 _11. Control signal C is applied to a gate of the PMOS transistor 31 _12. Control signal A is applied to a gate of the PMOS transistor 31 _13. PMOS transistor 31 ₁₄ connects the gate to the source. Control signal A is applied to a gate of the PMOS transistor 31 _15.

Reference numerals 32 _{1 to} 32 ₁₅ denote NMOS transistors. The NMOS transistor 32 _j has a drain connected to the node N _j and a source grounded. The NMOS transistor 32 ₁₅ has a drain connected to the node N ₁₅ and a source grounded.

The NMOS transistor 32 ₁ has a gate connected to the source. A control signal B is applied to the gate of the NMOS transistor 32 ₂ . The NMOS transistor 32 ₃ has a gate connected to the source. Control signal D is applied to a gate of the NMOS transistor 32 _4. Control signal F is applied to the gate of NMOS transistor 32 _5. A control signal H is supplied to the gate of the NMOS transistor 32 ₆ . Control signal J is applied to the gate of NMOS transistor 32 _7.

Control signal L is applied to the gate of NMOS transistor 32 _8. Control signal J is applied to the gate of NMOS transistor 32 _9. A control signal H is supplied to the gate of the NMOS transistor 32 ₁₀ . A control signal F is supplied to the gate of the NMOS transistor 32 ₁₁ . A control signal D is supplied to the gate of the NMOS transistor 32 ₁₂ . The NMOS transistor 32 ₁₃ has a gate connected to the source. A control signal B is supplied to the gate of the NMOS transistor 32 ₁₄ . The NMOS transistor 32 ₁₅ has a gate connected to the source.

  FIG. 9 is a circuit diagram showing a configuration of the initialization unit 22. The initialization circuit 22 includes an inverter circuit 33 and 4-input 1-output type selectors 34 to 43. The inverter 33 inverts the reset signal RESET and outputs a control signal A. The reset signal RESET is also used as the control signal B, and is at the H level when the voltage controlled oscillator 21 is initialized, and at the L level when the voltage controlled oscillator 21 performs the oscillation operation.

The selectors 34 to 43 have their selection operations controlled by a selection control signal SEL [1: 0]. The selection control signal SEL [1: 0] is equivalent to a ring oscillator composed of inverter circuits 23 ₁ to 23 ₁₅ operated with 15 inverter circuits or equivalent to 5 inverter circuits. Or a signal for selecting whether the inverter circuit is operated as an equivalent circuit having three stages.

The selection control signal SEL [1: 0] is set to [L level, L level] when the ring oscillator composed of the inverter circuits 23 ₁ to 23 ₁₅ is operated with the inverter circuit having 15 stages. [L level, H level] is used when operating with the number of stages equivalent to five, and [H level, L level] when operating with the number of stages of inverter circuits equivalent to three. It is said.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 34 selects the power supply voltage VDD, outputs the power supply voltage VDD as the control signal C, and selects the selection control signal SEL [1: When 0] = [L level, H level], the power supply voltage VDD is selected, the power supply voltage VDD is output as the control signal C, and the selection control signal SEL [1: 0] = [H level, L level] When the control signal A is selected, the control signal A is output as the control signal C.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 35 selects the reset signal RESET, outputs the reset signal RESET as the control signal D, and selects the selection control signal SEL [1: When 0] = [L level, H level], the reset signal RESET is selected, the reset signal RESET is output as the control signal D, and the selection control signal SEL [1: 0] = [H level, L level] When the ground voltage is 0V, the ground voltage 0V is output as the control signal D.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 36 selects the control signal A, outputs the control signal A as the control signal E, and selects the selection control signal SEL [1: When 0] = [L level, H level], the control signal A is selected, the control signal A is output as the control signal E, and the selection control signal SEL [1: 0] = [H level, L level]. When the power supply voltage VDD is selected, the power supply voltage VDD is output as the control signal E.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 37 selects the ground voltage 0V, outputs the ground voltage 0V as the control signal F, and selects the selection control signal SEL [1: When 0] = [L level, H level], the ground voltage 0V is selected, the ground voltage 0V is output as the control signal F, and the selection control signal SEL [1: 0] = [H level, L level] When the reset signal RESET is selected, the reset signal RESET is output as the control signal F.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 38 selects the power supply voltage VDD, outputs the power supply voltage VDD as the control signal G, and selects the selection control signal SEL [1: When 0] = [L level, H level], the control signal A is selected, the control signal A is output as the control signal G, and the selection control signal SEL [1: 0] = [H level, L level]. When the control signal A is selected, the control signal A is output as the control signal G.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 39 selects the reset signal RESET, outputs the reset signal RESET as the control signal H, and selects the selection control signal SEL [1: When 0] = [L level, H level], the ground voltage 0V is selected, the ground voltage 0V is output as the control signal H, and the selection control signal SEL [1: 0] = [H level, L level] When the ground voltage is 0V, the ground voltage 0V is output as the control signal H.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 40 selects the control signal A, outputs the control signal A as the control signal I, and selects the selection control signal SEL [1: When 0] = [L level, H level], the power supply voltage VDD is selected, the power supply voltage VDD is output as the control signal I, and the selection control signal SEL [1: 0] = [H level, L level] When the control signal A is selected, the control signal A is output as the control signal I.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 41 selects the ground voltage 0V, outputs the ground voltage 0V as the control signal J, and selects the selection control signal SEL [1: When 0] = [L level, H level], the reset signal RESET is selected, the reset signal RESET is output as the control signal J, and the selection control signal SEL [1: 0] = [H level, L level] When the ground voltage is 0V, the ground voltage 0V is output as the control signal J.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 42 selects the power supply voltage VDD, outputs the power supply voltage VDD as the control signal K, and selects the selection control signal SEL [1: When 0] = [L level, H level], the control signal A is selected, the control signal A is output as the control signal K, and the selection control signal SEL [1: 0] = [H level, L level]. When the power supply voltage VDD is selected, the power supply voltage VDD is output as the control signal K.

  When the selection control signal SEL [1: 0] = [L level, L level], the selector 43 selects the reset signal RESET, outputs the reset signal RESET as the control signal L, and selects the selection control signal SEL [1: When 0] = [L level, H level], the ground voltage 0V is selected, the ground voltage 0V is output as the control signal L, and the selection control signal SEL [1: 0] = [H level, L level] When the reset signal RESET is selected, the reset signal RESET is output as the control signal L. Table 2 shows the function of the initialization unit 22.

  That is, if the reset signal RESET = H level and the selection control signal SEL [1: 0] = [L level, L level], the control signal A = L level, the control signal B = H level, the control signal C = H level, Control signal D = H level, control signal E = L level, control signal F = L level, control signal G = H level, control signal H = H level, control signal I = L level, control signal J = L level, control The signal K = H level and the control signal L = H level.

  If the reset signal RESET = L level and the selection control signal SEL [1: 0] = [L level, L level], the control signal A = H level, the control signal B = L level, the control signal C = H level, Control signal D = L level, control signal E = H level, control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control The signal K = H level and the control signal L = L level.

  When the reset signal RESET = H level and the selection control signal SEL [1: 0] = [L level, H level], the control signal A = L level, the control signal B = H level, the control signal C = H level, Control signal D = H level, control signal E = L level, control signal F = L level, control signal G = L level, control signal H = L level, control signal I = H level, control signal J = H level, control The signal K = L level and the control signal L = L level.

  When the reset signal RESET = L level and the selection control signal SEL [1: 0] = [L level, H level], the control signal A = H level, the control signal B = L level, the control signal C = H level, Control signal D = L level, control signal E = H level, control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control The signal K = H level and the control signal L = L level.

  When the reset signal RESET = H level and the selection control signal SEL [1: 0] = [H level, L level], the control signal A = L level, the control signal B = H level, the control signal C = L level, Control signal D = L level, control signal E = H level, control signal F = H level, control signal G = L level, control signal H = L level, control signal I = L level, control signal J = L level, control The signal K = H level and the control signal L = H level.

  When the reset signal RESET = L level and the selection control signal SEL [1: 0] = [H level, L level], the control signal A = H level, the control signal B = L level, the control signal C = H level, Control signal D = L level, control signal E = H level, control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control The signal K = H level and the control signal L = L level.

FIG. 10 is a circuit diagram showing a state at the time of initialization of the first operation example of the second embodiment of the present invention, and FIG. 11 is a timing chart showing the first operation example of the second embodiment of the present invention. The first operation example of the second embodiment of the present invention is a case where a ring oscillator composed of inverter circuits 23 ₁ to 23 ₁₅ is operated with 15 inverter circuits. In this case, at initialization, the reset signal RESET = H level and the selection control signal SEL [1: 0] = [L level, L level]. In this way, as shown in Table 2, the control signal A = L level, the control signal B = H level, the control signal C = H level, the control signal D = H level, the control signal E = L level, the control signal F = L level, control signal G = H level, control signal H = H level, control signal I = L level, control signal J = L level, control signal K = H level, control signal L = H level.

As a result, as shown in FIG. 10, PMOS transistors 31 ₁ state = ON, PMOS transistor 31 ₂ states = OFF, PMOS transistor 31 ₃ state = ON, PMOS transistor 31 ₄ states = OFF, PMOS transistor 31 ₅ state = ON, state = OFF of the PMOS transistors 31 _6, PMOS transistor 31 ₇ state = ON, state = OFF of the PMOS transistors 31 _8, PMOS transistor 31 ₉ state = ON, the PMOS transistor 31 ₁₀ state = OFF of PMOS transistors 31 ₁₁ state = ON, state = OFF of the PMOS transistors 31 _12, PMOS transistors 31 ₁₃ state = ON, the PMOS transistor 31 ₁₄ state = OFF, the state = ON of the PMOS transistor 31 _15.

Further, the state of the NMOS transistor 32 ₁ = OFF, the state of the NMOS transistor 32 ₂ = ON, the state of the NMOS transistor 32 ₃ = OFF, the state of the NMOS transistor 32 ₄ = ON, the state of the NMOS transistor 32 ₅ = OFF, the NMOS transistor 32 ₆ state = ON, NMOS transistor 32 ₇ state = OFF, NMOS transistor 32 ₈ state = ON, NMOS transistor 32 ₉ state = OFF, NMOS transistor 32 ₁₀ state = ON, NMOS transistor 32 ₁₁ state = OFF The state of the NMOS transistor 32 ₁₂ is ON, the state of the NMOS transistor 32 ₁₃ is OFF, the state of the NMOS transistor 32 ₁₄ is ON, and the state of the NMOS transistor 32 ₁₅ is OFF.

Therefore, as shown in FIG. 10, the levels of the nodes N _{1 to} N ₁₅ are the level of the node N ₁ = H level, the level of the node N ₂ = L level, the level of the node N ₃ = H level, and the level of the node N ₄ Level = L level, node N ₅ level = H level, node N ₆ level = L level, node N ₇ level = H level, node N ₈ level = L level, node N ₉ level = H level, Node N ₁₀ level = L level, Node N ₁₁ level = H level, Node N ₁₂ level = L level, Node N ₁₃ level = H level, Node N ₁₄ level = L level, Node N ₁₅ level = H level. In this case, only the inverter circuit 23 ₁ is inactivated at both the input node and the output node at the same level (H level).

Next, the reset signal RESET = L level. In this way, as shown in Table 2, the control signal A = H level, the control signal B = L level, the control signal C = H level, the control signal D = L level, the control signal E = H level, the control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control signal K = H level, control signal L = L level. As a result, the PMOS transistors 31 _{1 to} 31 ₁₅ and the NMOS transistors 32 _{1 to} 32 ₁₅ are turned off, and the ring oscillator including the inverter circuits 23 ₁ to 23 ₁₅ starts an oscillation operation.

In this case, since only the inverter circuit 23 ₁ is inactive, first, the output of the inverter circuit 23 ₁ changes to the L level as shown in FIG. Next, the output of the inverter circuit 23 ₂ changes to the H level. Next, the output of the inverter circuit 23 ₃ changes to the L level. Next, the output of the inverter circuit 23 ₄ changes to H level. Next, the output of the inverter circuit 23 ₅ changes to the L level. Next, the output of the inverter circuit 23 ₆ changes to the H level.

Then, the output of the inverter circuit 23 ₇ is changed to the L level. The output of the inverter circuit 23 ₈ is changed to the H level. Next, the output of the inverter circuit 23 ₉ changes to the L level. Next, the output of the inverter circuit 23 ₁₀ changes to the H level. Next, the output of the inverter circuit 23 ₁₁ changes to the L level. Next, the output of the inverter circuit 23 ₁₂ changes to the H level. Next, the output of the inverter circuit 23 ₁₃ changes to the L level. Next, the output of the inverter circuit 23 ₁₄ changes to H level. Next, the output of the inverter circuit 23 ₁₅ changes to the L level.

Next, the output of the inverter circuit 23 ₁ changes to H level. Next, the output of the inverter circuit 23 ₂ changes to the L level. Next, the output of the inverter circuit 23 ₃ changes to the H level. Next, the output of the inverter circuit 23 ₄ changes to the L level. Next, the output of the inverter circuit 23 ₅ changes to the H level. Next, the output of the inverter circuit 23 ₆ changes to the L level. Then, the output of the inverter circuit 23 ₇ is changed to the H level. The output of the inverter circuit 23 ₈ is changed to L level.

Next, the output of the inverter circuit 23 ₉ changes to the H level. Next, the output of the inverter circuit 23 ₁₀ changes to the L level. Next, the output of the inverter circuit 23 ₁₁ changes to the H level. Next, the output of the inverter circuit 23 ₁₂ changes to the L level. Next, the output of the inverter circuit 23 ₁₃ changes to the H level. The output of the inverter circuit 23 ₁₄ is changed to the L level. Next, the output of the inverter circuit 23 ₁₅ changes to the H level. Hereinafter, the output of the inverter circuit 23 ₁ to 23 ₁₅ is changed in a similar manner, the oscillating operation of the inverter circuit 23 ₁ to 23 ₁₅ is performed.

Here, if one delay time of the inverter circuits 23 ₁ to 23 ₁₅ is T, the cycle of the oscillation signal OUT is 30T. That is, the ring oscillator composed of the inverter circuits 23 ₁ to 23 ₁₅ can be operated with 15 inverter circuits. In this state, when the control voltage VCNT changes, the frequency of the oscillation signal OUT changes. When the control voltage VCNT becomes relatively high, the ON resistance of the NMOS transistor 24 becomes relatively small, and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes relatively low. To be high. When the control voltage VCNT becomes relatively low, the ON resistance of the NMOS transistor 24 becomes relatively large, and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes relatively high. It becomes low.

FIG. 12 is a circuit diagram showing a state at the time of initialization of the second operation example of the second embodiment of the present invention, and FIG. 13 is a timing chart showing a second operation example of the second embodiment of the present invention. The second operation example of the second embodiment of the present invention is a case where a ring oscillator composed of inverter circuits 23 ₁ to 23 ₁₅ is operated as an equivalent circuit having five inverter circuits. In this case, at initialization, the reset signal RESET = H level and the selection control signal SEL [1: 0] = [L level, H level]. In this way, as shown in Table 2, the control signal A = L level, the control signal B = H level, the control signal C = H level, the control signal D = H level, the control signal E = L level, the control signal F = L level, control signal G = L level, control signal H = L level, control signal I = H level, control signal J = H level, control signal K = L level, control signal L = L level.

As a result, as shown in FIG. 12, PMOS transistors 31 ₁ state = ON, PMOS transistor 31 ₂ states = OFF, PMOS transistor 31 ₃ state = ON, PMOS transistor 31 ₄ states = OFF, PMOS transistor 31 ₅ state = ON, the PMOS transistor 31 ₆ state = ON, the PMOS transistor 31 ₇ state = OFF, state = ON of the PMOS transistor 31 _8, PMOS transistor 31 ₉ state = OFF, the PMOS transistors 31 ₁₀ state = ON, PMOS transistors 31 ₁₁ state = ON, state = OFF of the PMOS transistors 31 _12, PMOS transistors 31 ₁₃ state = ON, the PMOS transistor 31 ₁₄ state = OFF, the state = ON of the PMOS transistor 31 _15.

Further, the state of the NMOS transistor 32 ₁ = OFF, the state of the NMOS transistor 32 ₂ = ON, the state of the NMOS transistor 32 ₃ = OFF, the state of the NMOS transistor 32 ₄ = ON, the state of the NMOS transistor 32 ₅ = OFF, the NMOS transistor 32 ₆ state = OFF, NMOS transistor 32 ₇ state = ON, NMOS transistor 32 ₈ state = OFF, NMOS transistor 32 ₉ state = ON, NMOS transistor 32 ₁₀ state = OFF, NMOS transistor 32 ₁₁ state = OFF The state of the NMOS transistor 32 ₁₂ is ON, the state of the NMOS transistor 32 ₁₃ is OFF, the state of the NMOS transistor 32 ₁₄ is ON, and the state of the NMOS transistor 32 ₁₅ is OFF.

Therefore, as shown in FIG. 12, the levels of the nodes N _{1 to} N ₁₅ are the level of the node N ₁ = H level, the level of the node N ₂ = L level, the level of the node N ₃ = H level, and the level of the node N ₄ Level = L level, node N ₅ level = H level, node N ₆ level = H level, node N ₇ level = L level, node N ₈ level = H level, node N ₉ level = L level, Node N ₁₀ level = H level, Node N ₁₁ level = H level, Node N ₁₂ level = L level, Node N ₁₃ level = H level, Node N ₁₄ level = L level, Node N ₁₅ level = H level. In this case, the inverter circuits 23 ₁ , 23 ₆ , and 23 ₁₁ are inactivated at both the input node and the output node at the same level (H level).

Next, the reset signal RESET = L level. In this way, as shown in Table 2, the control signal A = H level, the control signal B = L level, the control signal C = H level, the control signal D = L level, the control signal E = H level, the control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control signal K = H level, control signal L = L level. As a result, the PMOS transistors 31 _{1 to} 31 ₁₅ and the NMOS transistors 32 _{1 to} 32 ₁₅ are turned off, and the ring oscillator including the inverter circuits 23 ₁ to 23 ₁₅ starts an oscillation operation.

In this case, since the inverter circuits 23 ₁ , 23 ₆ and 23 ₁₁ are in an inactive state, as shown in FIG. 13, first, the outputs of the inverter circuits 23 ₁ , 23 ₆ and 23 ₁₁ are set to the L level. Change. Next, the outputs of the inverter circuits 23 ₂ , 23 ₇ and 23 ₁₂ change to the H level. Next, the outputs of the inverter circuits 23 ₃ , 23 ₈ and 23 ₁₃ change to the L level. Next, the outputs of the inverter circuits 23 ₄ , 23 ₉ and 23 ₁₄ change to the H level. Next, the outputs of the inverter circuits 23 ₅ , 23 ₁₀ , 23 ₁₅ change to the L level.

Next, the outputs of the inverter circuits 23 ₁ , 23 ₆ and 23 ₁₁ change to the H level. Next, the outputs of the inverter circuits 23 ₂ , 23 ₇ and 23 ₁₂ change to the L level. Next, the outputs of the inverter circuits 23 ₃ , 23 ₈ and 23 ₁₃ change to the H level. Next, the outputs of the inverter circuits 23 ₄ , 23 ₉ , and 23 ₁₄ change to the L level. Next, the outputs of the inverter circuits 23 ₅ , 23 ₁₀ , 23 ₁₅ change to the H level. Hereinafter, the output of the inverter circuit 23 ₁ to 23 ₁₅ is changed in a similar manner, the oscillating operation of the inverter circuit 23 ₁ to 23 ₁₅ is performed.

Here, assuming that one delay time of the inverter circuits 23 ₁ to 23 ₁₅ is T, the cycle of the oscillation signal OUT is 10T. That is, the ring oscillator composed of the inverter circuits 23 ₁ to 23 ₁₅ can be operated as an equivalent circuit having five inverter circuits. In this state, when the control voltage VCNT changes, the frequency of the oscillation signal OUT changes. When the control voltage VCNT becomes relatively high, the ON resistance of the NMOS transistor 24 becomes relatively small, and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes relatively low. To be high. When the control voltage VCNT becomes relatively low, the ON resistance of the NMOS transistor 24 becomes relatively large, and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes relatively high. It becomes low.

FIG. 14 is a circuit diagram showing a state at the time of initialization of the third operation example of the second embodiment of the present invention, and FIG. 15 is a timing chart showing the third operation example of the second embodiment of the present invention. A third operation example of the second embodiment of the present invention is a case in which a ring oscillator composed of inverter circuits 23 ₁ to 23 ₁₅ is operated as an equivalent circuit having three inverter circuits. In this case, at initialization, the reset signal RESET = H level and the selection control signal SEL [1: 0] = [H level, L level]. In this case, as shown in Table 2, the control signal A = L level, the control signal B = H level, the control signal C = L level, the control signal D = L level, the control signal E = H level, the control signal F = H level, control signal G = L level, control signal H = L level, control signal I = L level, control signal J = L level, control signal K = H level, control signal L = H level.

As a result, as shown in FIG. 14, PMOS transistors 31 ₁ state = ON, PMOS transistor 31 ₂ states = OFF, PMOS transistor 31 ₃ state = ON, PMOS transistor 31 ₄ states = ON, PMOS transistor 31 ₅ state = OFF, PMOS transistors 31 ₆ state = ON, the PMOS transistor 31 ₇ state = ON, state = OFF of the PMOS transistors 31 _8, PMOS transistor 31 ₉ state = ON, the PMOS transistor 31 ₁₀ state = ON, PMOS transistors 31 ₁₁ state = OFF, the PMOS transistors 31 ₁₂ state = ON, the PMOS transistor 31 ₁₃ state = ON, state = OFF of the PMOS transistors 31 _14, a state = ON of the PMOS transistor 31 _15.

Further, the state of the NMOS transistor 32 ₁ = OFF, the state of the NMOS transistor 32 ₂ = ON, the state of the NMOS transistor 32 ₃ = OFF, the state of the NMOS transistor 32 ₄ = OFF, the state of the NMOS transistor 32 ₅ = ON, the NMOS transistor 32 ₆ state = OFF, NMOS transistor 32 ₇ state = OFF, NMOS transistor 32 ₈ state = ON, NMOS transistor 32 ₉ state = OFF, NMOS transistor 32 ₁₀ state = OFF, NMOS transistor 32 ₁₁ state = ON The state of the NMOS transistor 32 ₁₂ is OFF, the state of the NMOS transistor 32 ₁₃ is OFF, the state of the NMOS transistor 32 ₁₄ is ON, and the state of the NMOS transistor 32 ₁₅ is OFF.

Therefore, as shown in FIG. 14, the levels of the nodes N _{1 to} N ₁₅ are the level of the node N ₁ = H level, the level of the node N ₂ = L level, the level of the node N ₃ = H level, and the level of the node N ₄ Level = H level, Node N ₅ level = L level, Node N ₆ level = H level, Node N ₇ level = H level, Node N ₈ level = L level, Node N ₉ level = H level, Node N ₁₀ level = H level, Node N ₁₁ level = L level, Node N ₁₂ level = H level, Node N ₁₃ level = H level, Node N ₁₄ level = L level, Node N ₁₅ level = H level. In this case, the inverter circuits 23 ₁ , 23 ₄ , 23 ₇ , 23 ₁₀ , and 23 ₁₃ are inactivated at the same level (H level) at the input node and the output node.

Next, the reset signal RESET = L level. In this way, as shown in Table 2, the control signal A = H level, the control signal B = L level, the control signal C = H level, the control signal D = L level, the control signal E = H level, the control signal F = L level, control signal G = H level, control signal H = L level, control signal I = H level, control signal J = L level, control signal K = H level, control signal L = L level. As a result, the PMOS transistors 31 _{1 to} 31 ₁₅ and the NMOS transistors 32 _{1 to} 32 ₁₅ are turned off, and the ring oscillator including the inverter circuits 23 ₁ to 23 ₁₅ starts an oscillation operation.

In this case, since the inverter circuits 23 ₁ , 23 ₄ , 23 ₇ , 23 ₁₀ , and 23 ₁₃ are in an inactive state, first, as shown in FIG. 15, the inverter circuits 23 ₁ , 23 ₄ , 23 ₇ , 23 ₁₀ and 23 ₁₃ change to the L level. Next, the outputs of the inverter circuits 23 ₂ , 23 ₅ , 23 ₈ , 23 ₁₁ and 23 ₁₄ change to the H level. Next, the outputs of the inverter circuits 23 ₃ , 23 ₆ , 23 ₉ , 23 ₁₂ and 23 ₁₅ change to the L level. Next, the outputs of the inverter circuits 23 ₁ , 23 ₄ , 23 ₇ , 23 ₁₀ , 23 ₁₃ change to the H level. Next, the outputs of the inverter circuits 23 ₂ , 23 ₅ , 23 ₈ , 23 ₁₁ and 23 ₁₄ change to the L level. Next, the outputs of the inverter circuits 23 ₃ , 23 ₆ , 23 ₉ , 23 ₁₂ and 23 ₁₅ change to the H level. Hereinafter, the output of the inverter circuit 23 ₁ to 23 ₁₅ is changed in a similar manner, the oscillating operation of the inverter circuit 23 ₁ to 23 ₁₅ is performed.

Here, assuming that one delay time of the inverter circuits 23 ₁ to 23 ₁₅ is T, the period of the oscillation signal OUT is 6T. That is, the ring oscillator composed of the inverter circuits 23 ₁ to 23 ₁₅ can be operated as an equivalent circuit having three inverter circuits. In this state, when the control voltage VCNT changes, the frequency of the oscillation signal OUT changes. When the control voltage VCNT becomes relatively high, the ON resistance of the NMOS transistor 24 becomes relatively small and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes low, so that the oscillation frequency becomes relatively high. . When the control voltage VCNT becomes relatively low, the ON resistance of the NMOS transistor 24 becomes relatively large and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ becomes high, so that the oscillation frequency becomes relatively low. .

As described above, according to the second embodiment of the present invention, the initialization unit 22, the PMOS transistors 31 _{1 to} 31 _15, and the NMOS transistors 32 ₁ to 32 ₁₅ are compared with the ring oscillator composed of the inverters 23 ₁ to 23 _15. 32 ₁₅ are provided. As a result, at the time of initialization, the reset signal RESET = H level, the selection control signal SEL [1: 0] = [L level, L level], and then the reset signal RESET = L level. _The ring oscillator composed of ₁ to 23 ₁₅ can be operated with ₁₅ inverter circuits, and if one delay time of the inverter circuits 23 ₁ to 23 ₁₅ is T, the oscillation signal has a period of 30T. OUT can be obtained. In this case, the frequency of the oscillation signal OUT can be changed by the control voltage VCNT.

At the time of initialization, the reset signal RESET = H level, the selection control signal SEL [1: 0] = [L level, H level], and then the reset signal RESET = L level, whereby the inverter circuit 23 _{1 is set.} number of inverter circuits to the ring oscillator consisting of to 23 ₁₅ can be operated as one equivalent of 5 stages, when one of the delay time of the inverter circuit 23 ₁ to 23 ₁₅ is T, the period 10T and The oscillation signal OUT to be obtained can be obtained. In this case, the frequency of the oscillation signal OUT can be changed by the control voltage VCNT.

At the time of initialization, the reset signal RESET = H level, the selection control signal SEL [1: 0] = [H level, L level], and then the reset signal RESET = L level, whereby the inverter circuit 23 _{1 is set.} The ring oscillator composed of ˜23 ₁₅ can be operated as an equivalent of three inverter circuits, and if one delay time of the inverter circuits 23 ₁ ˜23 ₁₅ is T, the period is 6T. The oscillation signal OUT to be obtained can be obtained. In this case, the frequency of the oscillation signal OUT can be changed by the control voltage VCNT.

That is, according to the second embodiment of the present invention, the selection control signal SEL [1: 0] is set to [L level, L level] or [L level, H level] or [H level, L level]. When the ring oscillator composed of the inverter circuits 23 ₁ to 23 ₁₅ is initialized, the number of inverter circuits to be inactivated can be one, three, or five, and the inverter circuits 23 ₁ to 23 _{15 are} composed. Oscillating operation is performed with a ring oscillator having 15 inverter circuits, equivalent to 5 inverter circuits, or equivalent to 3 inverter circuits Can be made. As a result, a selector circuit for changing the oscillation frequency is not required in the oscillation signal path, so that good jitter characteristics can be obtained.

In the second embodiment of the present invention, the NMOS transistor 24 is provided, and the power supply voltage on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ is changed by the control voltage VCNT, thereby changing the oscillation frequency. However, instead, the power supply voltage on the high potential side of the inverter circuits 23 ₁ to 23 ₁₅ may be changed.

In the second embodiment of the present invention, the case where the present invention is applied to a voltage controlled oscillator has been described. However, the NMOS transistor 24 is not provided, and the power supply node on the low potential side of the inverter circuits 23 ₁ to 23 ₁₅ is grounded. You may make it do. In such a case, it cannot be used as a voltage controlled oscillator having three oscillation frequency ranges, but can be used as a ring oscillator having three possible oscillation frequencies.

  In the first embodiment of the present invention, a case is described in which a ring oscillator is configured by ring-connecting nine inverter circuits, and in the second embodiment of the present invention, 15 inverter circuits are ring-connected. Although the case where a ring oscillator is configured has been described, the present invention is preferably applied to a case where an odd number of inverter circuits obtained by an odd product of 3 or more are ring-connected. The number of inverter circuits that can be inactivated at the time of initialization is the odd number of 3 or more which is a divisor of the number obtained by 1 or the odd product of 3 or more.

1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows the structure of the inverter circuit with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the initialization part with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows the state at the time of initialization of the 1st operation example of 1st Embodiment of this invention. It is a timing chart which shows the 1st operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the state at the time of initialization of the 2nd operation example of 1st Embodiment of this invention. It is a timing chart which shows the 2nd operation example of 1st Embodiment of this invention. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the initialization part with which 2nd Embodiment of this invention is provided. It is a circuit diagram which shows the state at the time of initialization of the 1st operation example of 2nd Embodiment of this invention. It is a timing chart which shows the 1st operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the state at the time of initialization of the 2nd operation example of 2nd Embodiment of this invention. It is a timing chart which shows the 2nd operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the state at the time of initialization of the 3rd operation example of 2nd Embodiment of this invention. It is a timing chart which shows the 3rd operation example of 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Voltage control oscillation part 2 ... Initialization part 3 _{1-3 9} ... Inverter circuit 4 ... NMOS transistor 5 ... VDD power supply wiring 6 ... PMOS transistor 7 ... NMOS transistor 8 ... High potential side power supply node 9 ... Low potential side Power supply node 10 ... Inverter circuit 11 _{1 to} 11 ₉ ... PMOS transistor 12 _{1 to} 12 ₉ ... NMOS transistor 13 ... Inverter 14 to 17 ... Selector 21 ... Voltage-controlled oscillation unit 22 ... Initialization unit 23 ₁ to 23 ₁₅ ... Inverter circuit 24 ... NMOS transistor 25 ... VDD power supply wiring 30 ... Inverter circuit 31 _{1 to} 31 ₁₅ ... PMOS transistor 32 _{1 to} 32 ₁₅ ... NMOS transistor 33 ... Inverter 34 to 43 ... selector

Claims (3)

A ring oscillation unit formed by connecting an odd number of inverter circuits in a ring;
An initialization unit that sets an initial potential that inactivates the inverter circuit indicated by the control signal at the connection point of the odd number of inverter circuits at the time of initialization of the ring oscillation unit;
A ring oscillator comprising: 2. The ring oscillator according to claim 1, further comprising a power supply voltage control circuit that is controlled by a control voltage to control a power supply voltage on a high potential side or a power supply voltage on a low potential side of the odd number of inverter circuits. . The odd number is a number obtained by an odd product of 3 or more,
3. The number of inverter circuits in the inactive state is the odd number of 3 or more which is a divisor of the number obtained by 1 or the odd product of 3 or more. 4. Ring oscillator.

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