JP2010079432A - Abstraction device and verification device of circuit description, abstraction program and verification program of the circuit description, and abstraction method and verification method of the circuit description - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an abstraction device and a verification device of circuit description, an abstraction program and a verification program of the circuit description, and an abstraction method and a verification method of the circuit description, allowing facilitation of verification of the circuit description converted into a formal specification, wherein description contents of a program can be verified by a formal technique. <P>SOLUTION: A control device 11 sets a discrimination condition when discriminating whether a path is set as a verification target to a plurality of paths prescribed by a plurality of states included in a logic model shown by specification data 24 of the circuit description and state transition between the respective states based on input operation from an input device 12. By inspecting the state transition in each path to the plurality of paths based on the discrimination condition, a non-verifying path excluded from the verification target by the verification program 22 and a verifying path set as the verification target are discriminated, and the plurality of paths are stored while the non-verifying path and the verifying path can be identified based on a discrimination result thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit description abstraction device and verification device in which the description content of a computer program is converted into a formal specification that can be verified by a formal method, circuit description abstraction program and verification program, and circuit description abstraction The present invention relates to a method and a verification method.

Conventionally, a verification apparatus using a formal method is widely known as a technique for verifying whether a designed computer program behaves as designed by a designer (for example, Patent Document 1). ). In this verification apparatus, for example, the description contents of a program described using a program language such as C, C ++, FORTRAN, etc. are first converted into a circuit description using a formal specification description language using existing modeling conversion software (such as Simulink, Scale, etc.). I try to convert it. Then, by verifying all states and all transitions in the logic model indicated by the circuit description mathematically using verification software, the correctness of the design of the program content converted into the circuit description of the formal specification is confirmed. It is possible to prove.
Japanese Patent No. 3660097

  By the way, in recent years, with the demand for more sophisticated and complex computer processing, computer programs tend to have a larger scale of description content, and the description content of the program has become a formal specification that can be verified by a formal method. The number of all states and all transitions in the model derived from the transformed circuit description is also increasing exponentially. Therefore, the conventional verification apparatus reduces the processing load required for verification of the circuit description by deleting a part of the circuit description to reduce the scale of the circuit to be verified.

  However, in the conventional verification apparatus, the verifier arbitrarily selects an area to be deleted from the circuit description, and manually creates a verification model in which the arbitrarily selected area is deleted from the circuit description. Since the verification model is configured to verify based on a formal method, the verification work requires a great deal of labor and time. In addition, when a new verification operation is performed again, the deleted area is restored and a new verification model is created, which is troublesome.

  The present invention has been made in view of such circumstances, and an object of the present invention is to make it easy to verify a circuit description obtained by converting a program description content into a formal specification that can be verified by a formal method. An object of the present invention is to provide a circuit description abstraction device and verification device, a circuit description abstraction program and verification program, and a circuit description abstraction method and verification method.

  To achieve the above object, a circuit description abstracting device according to claim 1 is a memory capable of storing circuit description specification data obtained by converting a description content of a program into a formal specification that can be verified by a formal method. Circuit description abstraction device comprising: means and control means for controlling a processing procedure of abstraction of the logical model represented by the circuit description specification data, wherein the control means is included in the logic model Discriminating condition setting means for setting discriminating conditions for discriminating whether or not the path is to be verified with respect to a plurality of paths defined by a plurality of states and state transitions between the states; Path determination for determining a non-verification path excluded from the verification target and a verification path to be verified by inspecting the state transition for each path based on the setting mode of the determination condition And when the circuit description is verified based on the determination result of the determination means, the non-verification path among the plurality of paths is avoided and the verification path is verified. Further, the present invention includes a path storage unit that stores the plurality of paths in a state where the non-verification path and the verification path can be identified.

  According to the above configuration, when the circuit description is verified using the verification device, a path stored in a state that can be identified as a verification path by the path storage unit is set as a verification target, but as a non-verification path. Since it is possible to execute a verification work excluded from verification targets for paths stored in an identifiable state, the verification work is quick and easy. In addition, the path to be excluded from the verification target is stored in the original circuit description together with the verification path to be verified in a state that can be identified as a non-verification path without deleting it from the circuit description. Even when the setting of the determination condition is changed in order to newly perform the verification work, the work for restoring the path once deleted is not necessary, and the re-verification can be performed quickly and easily. Therefore, it is possible to simplify the verification of the circuit description obtained by converting the program description contents into a formal specification that can be verified by a formal method.

  The circuit description abstraction device according to claim 2 is the circuit description abstraction device according to claim 1, wherein the determination condition is a state transition via the state among a plurality of states constituting the path. The path determination means, when inspecting a path including the state in which the prohibition flag is set as the determination condition in the state transition inspection stage for each path, The gist is to distinguish the path from the non-verification path.

  According to the above configuration, the path discriminating unit is used for non-verification in which the path including the state is excluded from the verification target at the time when the prohibition flag passes through the state set as the discrimination condition in the state transition check stage for each path. Since it can be determined as a path, circuit description can be easily abstracted.

  The circuit description abstraction device according to claim 3 is the circuit description abstraction device according to claim 1 or 2, wherein the determination condition is a starting point of a plurality of states constituting the path. A path flag indicating that the state should be passed in the middle of the state transition from the state to the end point state, and the path determination unit is configured to check the state transition for each path. The gist is that, when a path that reaches the end point through the state in which the passage flag is set as the determination condition is inspected, the path is determined as the verification path.

  According to the above configuration, even when there are a plurality of paths from the starting point state to the ending point state, it is possible to narrow down and save the paths that are verification paths. It can be carried out.

  The circuit description abstraction device according to claim 4 is the circuit description abstraction device according to any one of claims 1 to 3, wherein the path determination unit checks the state transition for each path. Further comprising time determination means for determining whether or not an elapsed time from the start of the time exceeds a preset threshold time, wherein the path determination means is configured such that the elapsed time exceeds the threshold time. The gist of the present invention is to end the state transition inspection for each path when it is determined that it has been met.

  According to the above configuration, it is possible to properly end the inspection in which the state that is the further transition destination is newly extracted and continues indefinitely even if the state that becomes the end point is reached in the state transition inspection stage. However, circuit description can be easily abstracted.

  The circuit description abstraction device according to claim 5 is the circuit description abstraction device according to any one of claims 1 to 4, wherein the path discriminating unit checks at that time. The gist is to sequentially extract the states of further transition destinations from the existing state at each inspection stage of each state, and to inspect further state transitions from the extracted states of the transition destination in parallel.

According to the above configuration, since the state transitions in a plurality of paths can be comprehensively inspected in parallel, the circuit description can be easily abstracted in this respect as well.
The circuit description verification apparatus according to claim 6, comprising: storage means capable of storing specification data of a circuit description obtained by converting a description content of a program into a formal specification that can be verified by a formal method; And a circuit description verification device comprising: control means for controlling a processing procedure for verifying the logic model to be performed, wherein the control means includes a plurality of states included in the logic model and state transitions between the states. Based on a determination condition setting means for setting a determination condition for determining whether or not the path is to be verified for a plurality of defined paths, and for the plurality of paths, based on a setting mode of the determination condition By checking whether or not the state transition is approved for each path, a path discrimination unit that discriminates a non-verification path that is excluded from the verification target and a verification path that is the verification target, and a determination result of the discrimination unit When the circuit description is verified, among the plurality of paths, the non-verification path is prevented from being verified, and the verification path is verified. A path storage unit that stores the path for verification and the verification path in an identifiable state, and a verification unit that performs a verification operation using the path stored as a verification path identifiable by the path storage unit The main point is that

According to the above configuration, the processing load required for verification of the model can be reduced by reducing the scale of the model indicated by the circuit description.
The circuit description verification device according to claim 7 is the circuit description verification device according to claim 6, wherein the determination condition prohibits a state transition via the state among a plurality of states constituting the path. The path discriminating unit is configured to check the path including the state in which the prohibition flag is set as the discrimination condition in the state transition check stage for each path. Is determined as the non-verification path. According to the said structure, the effect similar to the invention of Claim 2 is acquired.

  The circuit description verification device according to claim 8 is the circuit description verification device according to claim 6 or 7, wherein the determination condition is a starting point at a state transition among a plurality of states constituting the path. Including a passage flag indicating that the state should be passed in the middle from the state to be the end point to the end point, and the path determination unit is configured to check the state transition in the state transition check stage for each path. The gist is to determine the path as the verification path when the path reaching the end point through the state where the passage flag is set as the determination condition is inspected. According to the said structure, the effect similar to the invention of Claim 3 is acquired.

  The circuit description verification device according to claim 9 is the circuit description verification device according to any one of claims 6 to 8, wherein the path determination unit starts checking the state transition for each path. A time determination unit that determines whether or not an elapsed time since the time has exceeded a preset threshold time, wherein the path determination unit determines that the elapsed time has exceeded the threshold time At this point, the gist is to end the state transition inspection for each path. According to the said structure, the effect similar to the invention of Claim 4 is acquired.

  The circuit description verification device according to claim 10 is the circuit description verification device according to any one of claims 6 to 9, wherein the path discrimination unit is inspecting at that time. It is a summary to sequentially extract the states of further transition destinations from each of the inspection stages of each state, and inspect further state transitions from the extracted states of the transition destination in parallel. According to the said structure, the effect similar to the invention of Claim 5 is acquired.

  The circuit description abstracting program according to claim 11 comprises: storage means capable of storing specification data of a circuit description obtained by converting the description content of the program into a formal specification that can be verified by a formal method; and the specification data. A circuit description abstracting program used for operating a circuit description abstracting device comprising a control means for controlling a processing procedure of abstraction of a represented logical model, wherein the control means comprises the logic Discrimination condition setting means for setting a discriminating condition for discriminating whether or not the path is a verification target for a plurality of states defined by state transitions between the states and the states included in the model For the plurality of paths, non-verification paths and verification targets that are excluded from the verification target by checking whether or not the state transition is approved for each path based on the setting mode of the determination condition. Based on the determination result of the determination means and the determination result of the determination means, the non-verification path among the plurality of paths is avoided from being verified when the circuit description is verified At the same time, the verification path functions as path storage means for storing the plurality of paths in a state where the non-verification path and the verification path can be identified so that the verification is performed. According to the said structure, the effect similar to the invention of Claim 1 is acquired.

  The circuit description abstract program according to claim 12 is the circuit description abstract program according to claim 11, wherein the determination condition is a state transition via the state among a plurality of states constituting the path. When the path discriminating unit inspects the path including the state in which the prohibition flag is set as the discrimination condition in the state transition inspection stage for each path, The gist is to cause the path discrimination means to discriminate the path from the non-verification path. According to the said structure, the effect similar to the invention of Claim 2 is acquired.

  The circuit description abstract program according to claim 13 is the circuit description abstract program according to claim 11 or 12, wherein the determination condition is a state transition of a plurality of states constituting the path. It is configured to include a passage flag indicating that it is a state that should be passed in the middle from the state that becomes the start point to the state that becomes the end point, and the path discriminating unit performs the state transition in the state transition check stage for each path. The gist is to let the path discriminating unit discriminate the path from the verification path when the path that has reached the end point state through the state in which the passage flag is set as a discrimination condition is inspected. To do. According to the said structure, the effect similar to the invention of Claim 3 is acquired.

  The circuit description abstracting program according to claim 14 is the circuit description abstracting program according to any one of claims 11 to 13, wherein the control means is provided for each path by the path discrimination means. And further functioning as time determination means for determining whether or not the elapsed time since the start of the state transition inspection has exceeded a preset threshold time, and the path determination means determines that the elapsed time is The gist of the invention is that when it is determined that the threshold time has been exceeded, the path discriminating unit ends the state transition inspection for each path. According to the said structure, the effect similar to the invention of Claim 4 is acquired.

  The circuit description abstract program according to claim 15 is the circuit description abstract program according to any one of claims 11 to 14, wherein the path discrimination means is inspected at that time. The gist is to sequentially extract the states of further transition destinations from the existing state for each state inspection stage and to inspect further state transitions from the extracted states of the transition destination in parallel. According to the said structure, the effect similar to the invention of Claim 5 is acquired.

  The circuit description verification program according to claim 16, wherein the description data of the circuit description is converted into a formal specification that can be verified by a formal method, storage means capable of storing circuit description specification data, and the specification data A circuit description verification program for use in operating a circuit description verification apparatus comprising a control means for controlling a processing procedure of verification of a logical model, the control means being included in the logical model Discriminating condition setting means for setting discriminating conditions for discriminating whether or not the path is subject to verification with respect to a plurality of paths defined by a plurality of states and state transitions between the states, Non-verification paths that are excluded from verification targets and verifications that are verification targets by checking whether or not the state transition is approved for each path based on the setting mode of the determination condition. A path discriminating unit for discriminating between paths, and when the circuit description is verified based on the discrimination result of the discriminating unit, the non-verification path among the plurality of paths is avoided from being verified and the verification path Can be identified as a verification path by the path storage means for storing the plurality of paths in a state where the non-verification path and the verification path can be identified so that the verification can be performed. The gist is to make it function as a verification means for executing a verification operation using a path stored in the file as a verification target. According to the said structure, the effect similar to the invention of Claim 6 is acquired.

  The circuit description verification program according to claim 17 is the circuit description verification program according to claim 16, wherein the determination condition prohibits a state transition via the state among a plurality of states constituting the path. When the path discriminating unit inspects a path including the state in which the prohibition flag is set as the discrimination condition in the state transition check stage for each path, The gist is to make the path discriminating means discriminate from the non-verification path. According to the said structure, the effect similar to the invention of Claim 7 is acquired.

  The circuit description verification program according to claim 18 is the circuit description verification program according to claim 16 or claim 17, wherein the determination condition is a state transition start point of a plurality of states constituting the path. Including a passage flag indicating that the state should be passed in the middle from the state to the end point, and the path determination unit determines the determination condition in the state transition inspection stage for each path. When the path reaching the end point state through the state in which the passage flag is set is inspected, the gist is to cause the path determination unit to determine the path as the verification path. According to the said structure, the effect similar to the invention of Claim 8 is acquired.

  The circuit description verification program according to claim 19 is the circuit description verification program according to any one of claims 16 to 18, wherein the control unit is configured to change the state of each path by the path determination unit. It further functions as time determination means for determining whether or not the elapsed time from the start of the transition check exceeds a preset threshold time, and the time determination means determines that the elapsed time has exceeded the threshold time. At this point, the gist of the present invention is to end the state transition inspection for each path in the path discrimination means. According to the said structure, the effect similar to the invention of Claim 9 is acquired.

  The circuit description verification program according to claim 20 is the circuit description verification program according to any one of claims 16 to 19, wherein the path discrimination means is inspecting at that time. The gist is to sequentially extract the states of further transition destinations from each of the inspection stages of each state, and to inspect further state transitions from the extracted states of the transition destination in parallel. According to the said structure, the effect similar to the invention of Claim 10 is acquired.

  The circuit description abstracting method according to claim 21 is a circuit description abstracting method in which the description content of a program is converted into a formal specification that can be verified by a formal method, and the logical model indicated by the circuit description A determination condition setting stage for setting a determination condition for determining whether or not the path is to be verified for a plurality of states defined by state transitions between the states and the states included in The non-verification path that is excluded from the verification target and the verification path that is the verification target are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the determination condition for the plurality of paths. And when the circuit description is verified, the non-verification path of the plurality of paths is avoided from being verified and the verification path is As testimony is performed, and the gist that a path storage step of storing the said verification path and the non-verification pass using distinguishable states of the plurality of paths. According to the said structure, the effect similar to the invention of Claim 1 is acquired.

  23. The circuit description abstraction method according to claim 22, wherein the determination condition is a state transition via the state among a plurality of states constituting the path. In the path determination stage, when a path including the state in which the prohibition flag is set as the determination condition in the state transition inspection stage for each path is inspected, The gist is to distinguish the path from the non-verification path. According to the said structure, the effect similar to the invention of Claim 2 is acquired.

  The circuit description abstraction method according to claim 23 is the circuit description abstraction method according to claim 21 or 22, wherein the determination condition is a start point of a plurality of states constituting the path. It is configured to include a passage flag indicating that the state should be passed in the middle of the state transition from the state to the end point state, and in the path determination stage, in the state transition inspection stage for each path The gist is that, when a path that reaches the end point through the state in which the passage flag is set as the determination condition is inspected, the path is determined as the verification path. According to the said structure, the effect similar to the invention of Claim 3 is acquired.

  The circuit description abstraction method according to claim 24 is the circuit description abstraction method according to any one of claims 21 to 23, wherein state transition for each path is performed in the path determination step. It further comprises a time determination step for determining whether or not an elapsed time from the start of inspection exceeds a preset threshold time, and in the path determination step, the elapsed time is the threshold time in the time determination step. The gist is to end the inspection of the state transition for each path when it is determined that the threshold value is exceeded. According to the said structure, the effect similar to the invention of Claim 4 is acquired.

  25. The circuit description abstraction method according to claim 25 is the circuit description abstraction method according to any one of claims 21 to 24, wherein at the time of the path determination step, an inspection is performed at that time. The gist is to sequentially extract the states of further transition destinations from the existing state at each inspection stage of each state, and to inspect further state transitions from the extracted states of the transition destination in parallel. According to the said structure, the effect similar to the invention of Claim 5 is acquired.

  The circuit description verification method according to claim 26 is a circuit description verification method in which the description content of a program is converted into a formal specification that can be verified by a formal method, and is included in a logic model indicated by the circuit description. A determination condition setting step for setting a determination condition for determining whether or not the path is to be verified for a plurality of paths defined by a plurality of states and state transitions between the states; and A path for determining a non-verification path excluded from a verification target and a verification path as a verification target by checking whether or not the state transition is approved for each path based on the setting mode of the determination condition for a plurality of paths. When the circuit description is verified based on the determination stage and the determination result in the path determination stage, the non-verification path among the plurality of paths is avoided and the verification path is verified. And a path storage stage for storing the plurality of paths in a state in which the non-verification path and the verification path can be identified, and the path storage stage is stored so as to be identifiable as a verification path. The gist of the present invention is to provide a verification stage for executing a verification operation with a path as a verification target. According to the said structure, the effect similar to the invention of Claim 6 is acquired.

  27. The circuit description verification method according to claim 27, wherein the determination condition prohibits a state transition via the state from among a plurality of states constituting the path. In the path determination stage, when a path including the state in which the prohibition flag is set as the determination condition is inspected in the state transition inspection stage for each path, the path is determined. Is determined as the non-verification path. According to the said structure, the effect similar to the invention of Claim 7 is acquired.

  The circuit description verification method according to claim 28 is the circuit description verification method according to claim 26 or claim 27, wherein the determination condition is determined from a state as a starting point of a plurality of states constituting the path. It is configured to include a passage flag indicating that the state should be passed in the middle of the state transition until reaching the end point state, and in the path determination stage, the determination is performed in the state transition check stage for each path. The gist is to determine the path as the verification path when a path that has reached the end point through the state in which the passage flag is set as a condition is inspected. According to the said structure, the effect similar to the invention of Claim 8 is acquired.

  A circuit description verification method according to a twenty-ninth aspect is the circuit description verification method according to any one of the twenty-sixth to twenty-eighth aspects, wherein the state transition check for each path is performed in the path determination stage. A time determination step of determining whether or not an elapsed time since the start has exceeded a preset threshold time, and in the path determination step, the elapsed time exceeds the threshold time in the time determination step; The gist of the present invention is to end the state transition inspection for each path when it is determined that it has been. According to the said structure, the effect similar to the invention of Claim 9 is acquired.

  A circuit description verification method according to a thirty-third aspect is the circuit description verification method according to any one of the twenty-sixth to twenty-ninth aspects, wherein the state is inspected at that time in the path determination stage. It is a summary to sequentially extract the states of further transition destinations from each of the inspection stages of each state, and inspect further state transitions from the extracted states of the transition destination in parallel. According to the said structure, the effect similar to the invention of Claim 10 is acquired.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
As shown in FIG. 1, the computer system 10 in this embodiment includes a control device 11, an input device 12, an output device 13, a reading device 14, and a disk device 15. The computer system 10 can perform various types of information processing as an abstraction device and a verification device for circuit description by connecting these devices 11 to 15 so as to be able to transmit information to each other via the bus 16. It is configured as follows. A recording medium 17 such as a CD (Compact Disc) can be inserted into and removed from the reading device 14. In the present embodiment, the recording device 17 that records the program data to be verified described using the program language and the description contents of the program data described using the program language are read from the reading device 14. Is selectively inserted into or removed from the recording medium 17 on which modeling conversion software (such as Simulink and Scade) used for converting the data into a circuit description in a formal specification description language is recorded.

  The control device 11 functions as a control means for controlling the operating state of the computer system 10, and a specific configuration thereof will be described later. The input device 12 includes a keyboard, a mouse, and the like, and is used when manually inputting various information. The output device 13 includes a CRT display that can output and display the contents of various information input via the input device 12. The reading device 14 reads various data such as program data recorded on the recording medium 17 when the recording medium 17 such as a CD is inserted. The disk device 15 functions as a storage unit that can store various data read by the reading device 14.

  As shown in FIG. 1, the control device 11 includes an interface (not shown) that mediates exchange of information with an external device, a CPU 18 as a central processing unit, a ROM 19 that stores predetermined information in a readable manner, and various types It is configured as a digital computer including a RAM 20 that stores the information in a writable / readable manner. In order for the control device 11 to function as a digital computer, the CPU 18 is necessary for abstraction of the circuit description and verification of the abstracted circuit description when various types of information are input through the interface. In addition to performing various logical operations, various information used in the logical operations are read and written. The ROM 19 also has an abstraction program 21 and a verification program 22 that are used by the CPU 18 to control the operating state of the entire computer system 10 during the abstraction process of the circuit description and the verification process of the abstracted circuit description. It is remembered. The RAM 20 appropriately stores various information contents that are used and rewritten in the logical operation by the CPU 18 during operation of the computer system 10.

  When the recording medium 17 on which modeling conversion software (for example, Simulink) is recorded is inserted into the reading device 14, the CPU 18 causes the reading device 14 to read the data content of the modeling conversion software recorded on the recording medium 17, The read data contents are stored in the disk device 15 as the modeling tool 23. When the recording medium 17 on which the program data to be verified described using the program language is recorded is inserted into the reading device 14, the CPU 18 temporarily stores the program data recorded on the recording medium 17 in the RAM 20. Let Next, by starting the modeling tool 23 stored in the disk device 15, the program data once stored in the RAM 20 is converted into the specification data 24 of the circuit description in the formal specification description language, and the converted circuit description Are stored in the disk device 15.

  Further, when the abstraction program 21 stored in the ROM 19 is started, the CPU 18 uses a plurality of states included in the logical model represented by the specification data 24 of the circuit description stored in the disk device 15 and state transitions between the states. A plurality of defined paths are displayed on the display of the output device 13 in the state transition diagram display mode shown in FIG. Then, the CPU 18 determines, from the input device 12, a determination condition for determining whether or not each path on the state transition diagram displayed on the display of the output device 13 is to be verified in the verification process by the verification program 22. Allow input. In this respect, it can be said that the CPU 18 includes a determination condition setting unit 25 as a determination condition setting means for setting a determination condition input from the user via the input device 12 to be applicable in the abstraction process.

  Further, the CPU 18 inspects each path in the logical model to determine whether or not the determination condition set by the determination condition setting unit 25 is satisfied, and each path is a verification target based on the inspection result. It is determined whether or not. In this regard, the CPU 18 determines that a path that satisfies the determination condition is a verification target in the verification process, and determines that a path that does not satisfy the determination condition is not a verification target in the verification process. It can be said that a path discrimination unit 26 as a means is provided.

  Further, the CPU 18 determines, for each path in the logical model, a path determined by the path determination unit 26 as a verification target during the verification process or a path determined as not a verification target during the verification process. Is stored in an identifiable state. Then, the specification data 24 of the circuit description represented by the logical model in which each path is stored in such an identifiable state is overwritten and stored on the specification data 24 already stored in the disk device 15. In this regard, it can be said that the CPU 18 includes a path storage unit 27 as path storage means.

  Further, the CPU 18 has a timer function, determines whether or not an elapsed time after the path determination unit 26 starts checking each path has exceeded a preset threshold time, and determines the path. It is determined whether or not to end the inspection. In this regard, it can be said that the CPU 18 includes a time determination unit 28 as time determination means.

  Further, when the verification program 22 stored in the ROM 19 is activated, the CPU 18 analyzes each identifier assigned to each path stored in the path storage unit 27 and is given an identifier indicating that it is a verification target. The path is read from the RAM 20, and verification work is executed for each read path. In this respect, it can be said that the CPU 18 includes a verification unit 29 as verification means.

  FIG. 2 schematically shows the state transition of the shift stage of the transmission gear of the automatic transmission to which the computer system 10 of the present embodiment is applied. Specifically, the state indicated by “6th” indicates that the transmission gear is set to the sixth gear. Further, the state indicated by “6 → 2” indicates a transition state in the middle of the shift of the transmission gear from the sixth gear to the second gear. The user can set various marks based on an input operation from the input device 12 as a discrimination condition for discriminating and abstracting a path serving as a locus of the state transition of the transmission gear.

  That is, an S (Start) mark 30 indicating the state that is the starting point of the path, an E (End) mark 31 that indicates the state that is the ending point of the path, and state transition via the state among the plurality of states constituting the path is prohibited. X mark 32 as a prohibition flag to be performed, and P1 as a passage flag indicating that the state should be passed in the middle from the state that is the start point of the state transition to the state that is the end point among a plurality of states constituting the path The mark 33 can be set.

  Incidentally, in the present embodiment, the S mark 30 is “6th”, the E mark 31 is “3rd”, the X mark 32 as the prohibition flag is “1th”, “4th”, “5th”, and the P1 mark 33 as the passage flag is “ 2th "is set for each. The setting stage of the S mark 30, E mark 31, X mark 32, and P1 mark 33, which are determination conditions using the input device 12, corresponds to the determination condition setting stage.

  Next, a control processing routine executed by the CPU 18 according to the present embodiment when the abstract program 21 is activated will be described with reference to FIGS. The control processing routine includes a main routine shown in FIG. 3 and a subroutine shown in FIG.

  First, when the main routine shown in FIG. 3 is started, the CPU 18 starts measuring time, reads the specification data 24 of the circuit description from the disk device 15, and in the state transition diagram included in the logical model represented by the specification data 24. The state that is the starting point of the path is determined (step S11). In the case of this embodiment, since the S mark 30 is set in the “6th” state in the state transition diagram shown in FIG. 2, the CPU 18 determines that the “6th” state is the start state of the state transition to be inspected. decide.

  Subsequently, the CPU 18 extracts all transitionable states from the state that is the starting point determined in step S11 (step S12). Specifically, the transition destination states that can transition from “6th” set as the start point are “6 → 1”, “6 → 2”, “6 → 3”, “6 → 4”, and “6 → 5”. Extract transition state.

  Subsequently, as a path discrimination stage, the CPU 18 performs an inspection to determine whether or not a preset discrimination condition is satisfied for every state extracted in step S12 (step S13). That is, in this step S13, the CPU 18 checks in parallel whether or not the subroutine shown in FIG. 4 satisfies the preset discrimination condition for at least one state extracted in step S12 in the main routine of FIG. Execute.

Here, the subroutine relating to the path determination process in step S13 will be described with reference to FIG.
First, when this subroutine is started, the CPU 18 determines each state to be inspected extracted in step S12 (“6 → 1”, “6 → 2”, “6 → 3”, “6 → 4”, “6 → 5”). It is determined whether or not the x mark 32 as a prohibition flag is not set (step S21). If the determination result in step S21 is negative (with a x mark), the CPU 18 determines that a path including a state (for example, a transition state “6 → 5”) to be inspected at that time is set in advance. After determining that the condition is not satisfied and temporarily storing and saving the path in the RAM 20 with an identifier for identifying the path as a non-verification path excluded from the verification target of the circuit description by the verification program 22, The inspection relating to the path is ended by setting the END condition flag. On the other hand, if the determination result in step S21 is affirmative (no mark), the CPU 18 determines that the path including the state to be inspected at that time satisfies a predetermined determination condition, and performs the process. Control goes to step S22.

  Next, the CPU 18 determines whether or not the E mark 31 is set in the state that is the inspection target at that time (step S22). If the determination result in step S22 is affirmative (no E mark), the CPU 18 determines that the path including the state to be inspected at that time does not satisfy the determination condition, and performs the following processing. Control goes to step S23.

  Subsequently, as a time determination stage, the CPU 18 performs a determination process in which the time required for the inspection is set in advance between the path including the state to be inspected at that time from the start state of the state transition to the current state. It is determined whether or not the threshold time has been exceeded (step S23). If the determination result in step S23 is affirmative (time over), the CPU 18 has already sufficiently inspected the path including the state to be inspected at that time, and no further inspection is necessary. And the process for the inspection (that is, the subroutine shown in FIG. 4) is forcibly terminated at an intermediate stage. Even in this case, the CPU 18 is provided with an identifier for identifying a path for which the inspection is forcibly terminated in the middle of the process as a non-verification path that is excluded from the verification target of the circuit description by the verification program 22. After temporarily storing and saving in the RAM 20, the inspection relating to the path is ended by setting the END condition flag.

  On the other hand, when the determination result in step S23 is negative (less than the threshold time), the CPU 18 determines that the path inspection including the state to be inspected at that time is insufficient and further inspection is necessary. Then, the process returns to step S12 of the main routine shown in FIG. 3 to extract all the states that can be transited from the current state again, and again whether or not a predetermined discrimination condition is satisfied for each extracted state. Perform inspection. As a result, the CPU 18 repeats the subroutine processing shown in FIG. If the determination result in step S22 is negative (with an E mark) in the repetition processing of such a subroutine, the CPU 18 determines that the path including the state to be inspected at that time satisfies the determination condition. Then, the process proceeds to step S24.

  For example, suppose that the state to be inspected at the time of the processing in step S22 is the “3th” state in which the E mark 31 is set in FIG. 2, and the path to be inspected is the initial state “6th”. If the path passes from the state to the final state “3th” via the transition state “6 → 2”, the state “2th”, and the state “2 → 3”, the processing content in step S24 Is as follows.

  That is, the CPU 18 includes a state in which the P1 mark 33 as the passage flag is set from the state where the path is the start point (“6th”) to the state where the path is the end point (“3th”). Is determined (step S24). If the determination result in step S24 is negative (no P1 mark), the CPU 18 determines that the path does not satisfy the predetermined determination condition, and the process proceeds to step S23 described above.

  On the other hand, if the determination result in step S24 is affirmative (P1 mark present), as a path storage stage, the CPU 18 sets the P1 mark 33 as a passage flag from the state where the path is the starting point (this state) In this case, it is determined that the state has reached the end point via the “2th” state) and the preset determination condition is satisfied. Then, after temporarily storing and saving in the RAM 20 with an identifier for identifying the path including the state to be inspected at that time as a verification path to be verified by the verification program 22, The inspection is ended by setting the END condition flag (step S25).

  As described above, when step S13 of the main routine in FIG. 3 (that is, the subroutine shown in FIG. 4) is completed by setting the END condition flag, the CPU 18 completes the inspection regarding the determination condition in step S13 in all passes. Whether or not (step S14). If the determination result in step S14 is a negative determination (that is, a determination result that there is still a path for which the END condition flag is not set), the CPU 18 returns the process to step S13 and again performs step S12. The process of step S13 is performed for the remaining states in which the inspection relating to the determination condition has not been performed among the states extracted in (1).

  On the other hand, if the determination result in step S14 is affirmative, the CPU 18 stores the contents of the data temporarily stored in the disk device 15 in the RAM 20 in a state where each path can be identified as a non-verification path and a verification path. After overwriting and saving the stored specification data 24 of the circuit description, the main routine of this control process based on the activation of the abstract program 21 is terminated.

  Thereafter, when verifying the program contents to be verified based on the specification data 24 of the circuit description stored in the disk device 15, the CPU 18 activates the verification program 22 stored in the ROM 19 as a verification stage. Then, the specification data 24 of the circuit description stored in the disk device 15 is read. Then, the CPU 18 reads out a path to which an identifier indicating a verification path is assigned from among a plurality of paths included in the logical model represented by the specification data 24, and relates to an automatic transmission that uses the path as a verification target. Perform various debugging verifications.

  As described above, when verifying the state of the speed stage of the transmission gear and the transition between the states, the number of paths is exponentially executed by recursively extracting all the states that can be transitioned from each state. However, according to the computer system 10 of this embodiment, after the transitionable state is extracted from each state, the determination condition is satisfied. Missing paths are excluded from the model as non-verification paths. Therefore, compared to the case where the model is constructed with all the paths obtained by randomly extracting the states that can be transitioned from each state as the constituent elements, the number of paths to be verified is reduced. The scale can be reduced. Therefore, even if the scale of the specification data 24 of the circuit description increases, it is possible to execute verification of the model while suppressing an increase in the processing load on the CPU 18.

  Further, as a method of reducing the scale of the model represented by the specification data 24 of the circuit description, a plurality of paths included in the model are deleted by the verification program 22 without deleting a part of the specification data 24 of the circuit description. All of the verification paths to be verified and the non-verification paths excluded from the verification targets are left in an identifiable state. That is, even if the x mark 32 is set as a prohibition flag for the states in the model or transitions between the states, those states are not deleted from the model. Therefore, setting the determination condition does not affect various other simulation settings related to the transmission gear of the automatic transmission.

According to the present embodiment, the following effects can be obtained.
(1) According to the circuit description verification method using the verification program 22 in the above embodiment, when the computer system 10 verifies the logical model represented by the specification data 24 of the circuit description, the verification path in the logical model Paths that are stored in a state that can be identified as, can be verified, while paths that are stored in a state that can be identified as a non-verification path can be excluded from verification. Therefore, the verification operation is quick and easy. In addition, the path to be excluded from the verification target is not deleted from the circuit description specification data 24, and is included in the original circuit description specification data 24 together with the verification path to be verified in a state that can be identified as a non-verification path. Therefore, when changing the setting of the judgment condition to redo a new verification work, there is no need to restore a path that has been deleted once, and re-verification can be performed quickly and easily. it can. Therefore, it is possible to simplify the verification of the specification data 24 of the circuit description obtained by converting the description content of the program into a formal specification that can be verified by a formal method.

  (2) According to the circuit description abstraction method using the abstraction program 21 in the above-described embodiment, the state where the x mark 32 as the prohibition flag is set as the determination condition in the state transition check stage for each path is passed. At this time, since the path including the state can be determined as a non-verification path that is excluded from the verification target, the logical model represented by the specification data 24 of the circuit description can be easily abstracted.

  (3) According to the circuit description abstraction method using the abstraction program 21 in the above embodiment, in the state transition check stage for each path, the state transition from the start state to the end point state is performed. At the time when the P1 mark 33 as the passage flag passes through the state set as the determination condition in the middle, the path including the state can be determined as the verification path to be verified, and therefore is represented by the specification data 24 of the circuit description. The logical model can be easily abstracted.

  (4) According to the circuit description abstraction method using the abstraction program 21 in the above embodiment, the elapsed time from the start of the state transition check for each path is set to the threshold time of the discrimination process set in advance. The inspection is forcibly terminated when it is determined that the value has been exceeded. For this reason, even if a state that becomes the end point is reached in the state transition inspection stage, a state in which a further transition destination is newly extracted and continued indefinitely can be properly terminated, and the specification data 24 of the circuit description can be terminated. The model represented by can be easily abstracted.

  (5) According to the circuit description abstraction method using the abstraction program 21 in the above embodiment, further transition destination states from the state currently inspected at that time are sequentially extracted for each state inspection stage. In addition, further state transitions from the extracted transition destination states are inspected in parallel. Therefore, since the state transitions in a plurality of paths can be comprehensively inspected in parallel, the model represented by the specification data 24 of the circuit description can be easily abstracted.

The above embodiment may be changed to another embodiment as described below.
In the above embodiment, the abstraction program 21 sequentially starts the state before the transition of the state being inspected at that time after starting the inspection starting from the state that is the end point in each path. It is also possible to extract the state before the further transition from the extracted state before the transition and to inspect in parallel toward the state as the starting point.

  In the above embodiment, the abstraction program 21 extracts a state that can be transitioned from the state that is the starting point, and then selects one of the extracted states, and all transitions that can be transitioned from the selected state. You may make it perform alternately operation which test | inspects a state.

  In the above-described embodiment, the abstraction program 21 may count the number of states in which the inspection related to the discrimination condition is executed, and end the inspection when it is determined that the value exceeds a preset threshold value.

In the above embodiment, the abstraction program 21 may display and set a prohibition flag as a determination condition with a mark other than the x mark 32.
In the above embodiment, the passage flag as the determination condition may be displayed and set with a mark other than the P1 mark 33.

  In the above embodiment, the abstraction program 21 may have a program configuration included in the verification program 22.

The block diagram which shows the computer system of this embodiment. The state transition diagram which shows typically the state transition of the gear stage of a transmission gear. The flowchart which shows the main routine of an abstract program. The flowchart which shows the subroutine of an abstract program.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Computer system as abstraction apparatus and verification apparatus, 11 ... Control apparatus as control means, 15 ... Disk apparatus as storage means, 18 ... Discrimination condition setting means, Path discrimination means, Path storage means, Time determination means, And CPU as verification means, 21 ... abstraction program, 22 ... verification program, 24 ... specification data of circuit description, 30 ... S mark constituting discrimination condition, 31 ... E mark constituting discrimination condition, 32 ... discrimination condition X mark as a prohibition flag constituting 33, P1 mark as a passage flag constituting discrimination conditions.

Claims (30)

Controls the storage means capable of storing the specification data of the circuit description obtained by converting the description contents of the program into a formal specification that can be verified by a formal method, and the processing procedure of abstraction of the logical model represented by the specification data A circuit description abstraction device comprising a control means,
The control means includes
Discrimination condition for setting a discrimination condition when discriminating whether or not the path is a verification target for a plurality of paths defined by state transitions between the states and the states included in the logical model Setting means;
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. Path discrimination means;
Based on the determination result of the determination means, when the circuit description is verified, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. An abstraction device for circuit description, comprising: path storage means for storing a plurality of paths in a state where the non-verification path and the verification path can be identified. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
The path determination unit determines that the path is the non-verification path when the path including the state in which the prohibition flag is set as the determination condition is inspected in the state transition inspection stage for each path. The circuit description abstracting device according to claim 1, wherein: The determination condition includes a passage flag indicating that the state should pass in the middle from the state that is the start point in the state transition to the state that is the end point among the plurality of states that constitute the path. And
The path discriminating unit, when inspecting a path that reaches the end point state through the state where the passage flag is set as the discrimination condition in the state transition inspection stage for each path, The circuit description abstracting device according to claim 1, wherein the circuit description abstracting device is determined as the verification path. A time determination unit for determining whether or not an elapsed time from the start of the state transition inspection for each path by the path determination unit exceeds a preset threshold time;
The path determination unit ends the state transition inspection for each path when the time determination unit determines that the elapsed time exceeds the threshold time. The circuit description abstraction device according to any one of the above. The path discriminating means sequentially extracts further transition destination states from the state being inspected at that time for each state inspection stage, and further extracts further state transitions from the extracted transition destination states. 5. The circuit description abstracting device according to claim 1, wherein the circuit description abstracting device performs checking in parallel. Storage means capable of storing the specification data of the circuit description obtained by converting the description contents of the program into a formal specification that can be verified by a formal method, and control for controlling the processing procedure of verification of the logical model represented by the specification data A circuit description verification device comprising means,
The control means includes
Discrimination condition for setting a discrimination condition when discriminating whether or not the path is a verification target for a plurality of paths defined by state transitions between the states and the states included in the logical model Setting means;
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. Path discrimination means;
Based on the determination result of the determination means, when the circuit description is verified, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. A path storage unit that stores a plurality of paths in a state where the non-verification path and the verification path can be identified; and a verification that uses a path stored as a verification path by the path storage unit as a verification target A circuit description verification device comprising: verification means for executing work. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
The path determination unit determines that the path is the non-verification path when the path including the state in which the prohibition flag is set as the determination condition is inspected in the state transition inspection stage for each path. The circuit description verification apparatus according to claim 6, wherein the apparatus is a circuit description verification apparatus. The determination condition includes a passage flag indicating that the state should pass in the middle from the state that is the start point in the state transition to the state that is the end point among the plurality of states that constitute the path. And
The path discriminating unit, when inspecting a path that reaches the end point state through the state where the passage flag is set as the discrimination condition in the state transition inspection stage for each path, 8. The circuit description verification apparatus according to claim 6, wherein the verification path is determined as the verification path. A time determination unit for determining whether or not an elapsed time from the start of the state transition inspection for each path by the path determination unit exceeds a preset threshold time;
9. The path determination unit ends the state transition inspection for each path when the time determination unit determines that the elapsed time exceeds the threshold time. The circuit description verification apparatus according to any one of the above. The path discriminating means sequentially extracts further transition destination states from the state being inspected at that time for each state inspection stage, and further extracts further state transitions from the extracted transition destination states. 10. The circuit description verification apparatus according to claim 6, wherein the verification is performed in parallel. Controls the storage means capable of storing the specification data of the circuit description obtained by converting the description contents of the program into a formal specification that can be verified by a formal method, and the processing procedure of abstraction of the logical model represented by the specification data A circuit description abstraction program used for operating a circuit description abstraction device comprising a control means,
The control means;
Discrimination condition for setting a discrimination condition when discriminating whether or not the path is a verification target for a plurality of paths defined by state transitions between the states and the states included in the logical model Setting means,
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. Path discrimination means, and
Based on the determination result of the determination means, when the circuit description is verified, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. An abstraction program for circuit description, characterized by causing a plurality of paths to function as path storage means for storing the non-verification path and the verification path in an identifiable state. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
When the path discriminating unit inspects a path including the state in which the prohibition flag is set as the discriminating condition in the state transition inspection stage for each path, the path discriminating path is passed to the non-verification path. The circuit description abstracting program according to claim 11, wherein the abstracting program is a circuit description. The determination condition includes a passage flag indicating that the state should pass in the middle from the state that is the start point of the state transition to the state that is the end point among the plurality of states that constitute the path. And
When the path discriminating unit inspects a path that reaches the end point state through the state where the passage flag is set as the discrimination condition in the state transition inspection stage for each path, the path is 13. The circuit description abstracting program according to claim 11, wherein the path discriminating unit discriminates the path from the verification path. The control means;
Further functioning as time determination means for determining whether or not the elapsed time from the start of the state transition inspection for each path by the path determination means exceeds a preset threshold time,
The time determination unit causes the path determination unit to end the state transition check for each path when the elapsed time is determined to have exceeded the threshold time. An abstraction program for circuit description according to any one of the above. The path discriminating means sequentially extracts further transition destination states from the state being inspected at that time for each inspection stage of each state, and further extracts further state transitions from the extracted transition destination states in parallel. The circuit description abstract program according to claim 11, wherein the circuit description abstract program according to claim 11 is checked. Storage means capable of storing the specification data of the circuit description obtained by converting the description contents of the program into a formal specification that can be verified by a formal method, and control for controlling the processing procedure of verification of the logical model represented by the specification data A circuit description verification program used for operating a circuit description verification apparatus comprising means,
The control means;
Discrimination condition for setting a discrimination condition when discriminating whether or not the path is a verification target for a plurality of paths defined by state transitions between the states and the states included in the logical model Setting means,
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. Path discrimination means,
Based on the determination result of the determination means, when the circuit description is verified, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. Path storage means for storing a plurality of paths in a state in which the non-verification path and the verification path can be identified; and
A circuit description verification program which functions as verification means for executing a verification operation on a path stored as a verification target identifiable by the path storage means. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
When the path discriminating unit inspects a path including the state in which the prohibition flag is set as the discriminating condition in the state transition inspection stage for each path, the path discriminating path is passed to the non-verification path. The circuit description verification program according to claim 16, wherein the verification program is a circuit description verification program. The determination condition includes a passage flag indicating that the state should pass in the middle from the state that is the start point of the state transition to the state that is the end point among the plurality of states that constitute the path. And
When the path discriminating unit inspects a path that reaches the end point state through the state where the passage flag is set as the discrimination condition in the state transition inspection stage for each path, the path is 18. The circuit description verification program according to claim 16, wherein the path determination unit is configured to determine the verification path. The control means;
Further functioning as time determination means for determining whether or not the elapsed time from the start of the state transition inspection for each path by the path determination means exceeds a preset threshold time,
19. The method according to claim 16, wherein when the time determination unit determines that the elapsed time has exceeded the threshold time, the path determination unit ends the state transition inspection for each path. The circuit description verification program according to any one of the preceding claims. The path discriminating means sequentially extracts further transition destination states from the state being inspected at that time for each inspection stage of each state, and further extracts further state transitions from the extracted transition destination states in parallel. 20. The circuit description verification program according to claim 16, wherein the verification program is a circuit description verification program. A circuit description abstraction method that converts the description of a program into a formal specification that can be verified by a formal method,
Discrimination conditions for discriminating whether or not the path is to be verified with respect to a plurality of states included in the logic model indicated by the circuit description and a plurality of paths defined by state transitions between the states. A discrimination condition setting stage to be set,
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. A path discrimination stage;
When the circuit description is verified based on the determination result in the path determination step, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. A circuit description abstracting method comprising: a path storage step for storing the plurality of paths in a state where the non-verification path and the verification path can be identified. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
In the path determination step, when a path including the state in which the prohibition flag is set as the determination condition is inspected in the state transition inspection step for each path, the path is determined to be the non-verification path. 22. The circuit description abstraction method according to claim 21, wherein the circuit description is abstracted. The determination condition includes a passage flag indicating that a state should be passed in the middle of a state transition from a start state to an end point state among a plurality of states constituting the path. In the path discrimination stage, when the path that has reached the end point state through the state in which the passage flag is set as the discrimination condition in the state transition check stage for each path is inspected, 23. The circuit description abstraction method according to claim 21, wherein a path is determined as the verification path. A time determination step of determining whether or not an elapsed time from the start of the state transition inspection for each path in the path determination step exceeds a preset threshold time;
24. In the path determination step, the state transition inspection for each path is terminated when it is determined in the time determination step that the elapsed time has exceeded the threshold time. The circuit description abstraction method according to any one of the above. In the path determination stage, further transition destination states from the state currently inspected at that time are sequentially extracted for each state inspection stage, and further state transitions from the extracted transition destination states are extracted. 25. The circuit description abstraction method according to claim 21, wherein the circuit description is examined in parallel. A method for verifying a circuit description in which the program description is converted into a formal specification that can be verified by a formal method,
Discrimination conditions for discriminating whether or not the path is to be verified with respect to a plurality of states included in the logic model indicated by the circuit description and a plurality of paths defined by state transitions between the states. A discrimination condition setting stage to be set,
The non-verification path excluded from the verification target and the verification path to be verified are discriminated by inspecting whether or not the state transition is approved for each path based on the setting mode of the discrimination condition for the plurality of paths. A path discrimination stage;
When the circuit description is verified based on the determination result in the path determination step, the non-verification path among the plurality of paths is avoided from being verified, and the verification path is verified. A path storage step for storing the plurality of paths in a state where the non-verification path and the verification path can be identified;
A verification method for circuit description, comprising: a verification step for performing a verification operation on a verification target stored in a path that is identifiable as a verification path in the path storage step. The determination condition includes a prohibition flag for prohibiting a state transition via the state among a plurality of states constituting the path,
In the path determination step, when a path including the state in which the prohibition flag is set as the determination condition is inspected in the state transition inspection step for each path, the path is determined to be the non-verification path. 27. The circuit description verification method according to claim 26, wherein: The determination condition includes a passage flag indicating that a state should be passed in the middle of a state transition from a start state to an end point state among a plurality of states constituting the path. In the path discrimination stage, when the path that has reached the end point state through the state in which the passage flag is set as the discrimination condition in the state transition check stage for each path is inspected, 28. The circuit description verification method according to claim 26, wherein a path is discriminated from the verification path. A time determination step of determining whether or not an elapsed time from the start of the state transition inspection for each path in the path determination step exceeds a preset threshold time;
29. The state transition check for each path is terminated when the path determination stage determines that the elapsed time has exceeded the threshold time in the time determination stage. The circuit description verification method according to any one of the above. In the path determination stage, further transition destination states from the state currently inspected at that time are sequentially extracted for each state inspection stage, and further state transitions from the extracted transition destination states are extracted. 30. The circuit description verification method according to claim 26, wherein the verification is performed in parallel.

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