JP2010074043A - Semiconductor manufacturing method and semiconductor manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method and a semiconductor manufacturing device that can improve the uniformity of pattern sizes in a wafer surface to suppress variations in characteristics of a semiconductor device. <P>SOLUTION: When a wafer is exposed to a mask pattern through a plurality of exposure shots, a correction exposure amount in each exposure shot is found based upon a previously measured pattern size distribution in each exposure shot after etching, exposure is carried out with respective correction exposure amounts in the respective exposure shots, and the exposed wafer is etched to form the pattern on the wafer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing method and a semiconductor manufacturing apparatus used, for example, in a semiconductor wafer exposure process.

  In recent years, with higher integration and higher performance of semiconductor devices, further improvement in dimensional accuracy is required for semiconductor microfabrication technology. The main points in such microfabrication technology are lithography technology in which a circuit pattern on a photomask is exposed and transferred to a photosensitive film coated on a substrate, and a pattern is formed through development, and circuit pattern of the transferred photosensitive film. This is a dry etching technique for processing a film to be etched based on the above.

  In the lithography process, since the substrate to be transferred is warped, it may not be able to completely adhere to the bake plate during the baking process, and temperature variation may occur in the wafer surface. In addition, due to the influence of reaction by-products in the dry etching process, the etching amount may be nonuniform within the wafer surface, particularly at the substrate center and at the substrate edge. Due to these factors, variations occur in the dimensions of the pattern formed in the wafer surface. Such a dimensional variation often becomes a dimensional variation distribution close to a concentric circle. In order to improve the dimensional accuracy, improvements for suppressing variations on the coating / developing apparatus and the dry etching apparatus side have been studied, but this is not sufficient.

Therefore, in the lithography process, a method of offsetting variations in pattern dimensions to some extent by changing the exposure amount for each exposure shot is used (for example, see Patent Document 1). In addition, a method of correcting in advance so that the illuminance distribution in the exposure shot is uniform is used (see, for example, Patent Document 2). However, there is a problem that it is difficult to obtain dimensional accuracy that can cope with higher integration of semiconductor devices.
JP-A-10-256114 ([Claim 1], [0010], etc.) JP 2000-21764 A ([Claim 1] etc.)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor manufacturing method and a semiconductor manufacturing apparatus capable of improving uniformity of pattern dimensions in a wafer surface and suppressing variation in characteristics of semiconductor devices.

  According to an aspect of the present invention, when a mask pattern is exposed on a wafer by a plurality of exposure shots, the pattern size distribution in each exposure shot after etching is measured in advance. A semiconductor manufacturing method is provided, wherein a pattern is formed on the wafer by obtaining a corrected exposure amount, exposing each exposure shot at the corrected exposure amount, and etching the exposed wafer. Is done.

  Further, according to one aspect of the present invention, a light source for transferring a mask pattern onto a wafer by a plurality of exposure shots, an exposure amount filter for adjusting an exposure amount in the exposure shots, A storage medium for storing a corrected exposure amount in each exposure shot based on a pattern size distribution in each of the exposure shots after etching corresponding to a position measured in advance, and for each exposure shot based on the corrected exposure amount The semiconductor manufacturing apparatus is provided with an exposure amount control mechanism for controlling the exposure amount filter.

  According to one embodiment of the present invention, it is possible to improve the uniformity of pattern dimensions within a wafer surface and suppress variations in characteristics of semiconductor devices.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 shows the configuration of an exposure apparatus which is a semiconductor manufacturing apparatus of this embodiment. As shown in the figure, a light source 11 for irradiating light for transferring a mask pattern and a slit 12 for shaping light from the light source are provided on the wafer w. The slit 12 is provided with an exposure amount filter 13 for adjusting the intensity distribution of irradiation light at an optical system position where the filter itself does not resolve on the wafer w. Further, a mask stage 15 on which a mask 14 on which a mask pattern is formed is placed, a projection lens 16, and a wafer stage 17 on which a wafer w is placed and driven in the XY directions are installed.

  Then, the mask stage 15 and the wafer stage 17 are connected to the control unit 20 which is an exposure amount control mechanism together with the exposure amount filter 13 via the position sensors 18 and 19 for acquiring the irradiation position information from these relative positions. Has been. Laser interferometers may be used for these position sensors. Further, the control unit 20 is connected to the storage medium 23 in which the pattern size distribution in the exposure shot is measured by the measurement mechanism 21 and the exposure correction amount calculated by the calculation mechanism 22 based on this is input and stored.

  Using such an exposure apparatus, an exposure process is performed as follows.

  As shown in the flowchart in FIG. 2, first, as a pre-stage of the exposure process, a sample wafer having a mask pattern transferred by changing the exposure amount in advance is formed, and the pattern dimension after etching is measured. Data on the exposure dose dependency of the dimensions is acquired (S1).

Next, using another sample wafer, the measurement mechanism 21 such as CD-SEM (Critical Dimension-Scanning Electron Microscope) measures the pattern size after etching at a plurality of positions in each exposure shot on the wafer w. Data on the pattern size distribution in the exposure shot is acquired (S2). In this case, for example, as shown in FIG. 3, and _{a 1, a} 2 ··· _{a n} in each chip 32 in the exposure shot 31, it is preferable to perform the measurement in lattice points. The same applies not only when a plurality of chips are exposed in one shot as described above, but also when one chip is exposed in one shot.

An example of the result of measuring the pattern size in the exposure shot in this way is shown in FIG. In the figure, the difference ΔCD between the measured dimension after etching at the measurement points a ₁ and a _{2 to} a ₃₀ and the target dimension is a region 41 where +3 nm ≦ <+4 nm, a region 42 where +2 nm ≦ ΔCD <+3 nm is a region 42, The region of +1 nm ≦ ΔCD <+2 nm is the region 43, the region of approximately −1 nm ≦ ΔCD <+1 nm is the region 44, the region of −2 nm ≦ ΔCD <−1 nm is the region 45, and the region of −3 nm ≦ ΔCD <−2 nm is the target. The region 46 is a region 47 where −4 nm ≦ ΔCD <−3 nm.

  Here, ΔCD> 0 means that the actually measured dimension of the remaining wiring line is thicker than the target dimension, and ΔCD <0 means that the actually measured dimension of the remaining wiring line is thinner than the target dimension. The etching conversion difference is (resist remaining dimension after lithography process) − (remaining wiring line dimension after etching).

  In this case, the thick areas 41, 42, and 43 are corrected to increase the exposure amount to reduce the dimensions, and the thin areas 45, 46, and 47 are corrected to decrease the exposure amount to increase the dimensions. There is a need. Therefore, the calculation mechanism 22 calculates the exposure amount required to correct the difference ΔCD between the actually measured dimension after etching and the target dimension based on the exposure amount dependency data of the pattern dimension. Then, based on the calculated exposure amount, corrected exposure amount distribution data in each exposure shot is calculated (S3). The acquired corrected exposure amount distribution data in each exposure shot is stored in the storage medium 23.

  Then, based on the corrected exposure amount distribution data in each exposure shot stored in the storage medium 23, exposure is performed while adjusting the exposure amount in each exposure shot, and a resist photosensitive film is applied onto the film to be processed. The transferred wafer w is transferred (S4).

  At this time, irradiation light from the light source 11 is shaped in the slit 12, and the mask 14 is scanned by moving the mask stage 15 and the wafer stage 17 by the control unit 20. At the same time, the exposure amount filter 13 is controlled by the control unit 20 on the basis of the information on the irradiation position in the exposure shot detected by the position sensors 18 and 19 and the exposure correction amount from the storage medium 23, and the direction perpendicular to the scanning direction. The intensity distribution of the irradiation light in the (slit longitudinal direction) is adjusted.

  For example, as shown in FIG. 5, the exposure amount filter 13 is composed of a plurality of filters 13 a having a gradient in transmittance. Each filter is moved in the direction perpendicular to the longitudinal direction of the slit 12 by the control unit 20. Thus, the slit 12 is controlled to have a desired transmittance.

  Further, the irradiation light is exposed through the projection lens 16 while scanning the wafer w, thereby transferring the mask pattern onto the wafer w.

  When exposure for one shot is completed, the wafer stage 17 is moved by the control unit 20 to move the exposure position on the wafer w to the next position, and exposure for one shot is performed in the same manner. Further, it is determined whether or not the entire surface exposure has been completed (S5). If it has not been completed, the exposure position on the wafer w is again moved to the next position, and the exposure is repeated.

  After the exposure of the entire surface of the wafer w is completed, development and baking are performed, and the film to be processed is etched, thereby forming a circuit pattern on the wafer w (S6).

  In this way, by correcting the exposure amount in the exposure shot according to the exposure position, it is possible to suppress variations in pattern dimensions with higher accuracy and improve uniformity.

  In the present embodiment, the exposure amount filter 13 including a plurality of filters 13a having a transmittance gradient is used. However, the exposure amount filter 13 is not particularly limited as long as the transmittance of the irradiation light from the light source can be controlled by the position. It is not something. For example, as shown in FIG. 6, the transmittance may be changed by densely arranging poles 63 a that block a plurality of optical paths and changing the number of poles at the position of the slit 62. In addition, as shown in FIG. 7, the transmittance may be changed by arranging a plurality of poles 73 a having an oval cross section and changing the area to be shielded by appropriately rotating depending on the position of the slit 72.

  In the present embodiment, the pattern dimensions after etching at a plurality of positions in each exposure shot on the wafer w are measured, but it is preferable to measure all the exposure shots on the wafer w.

  However, as shown in FIG. 8 as an example of the relationship between the etching conversion difference indicating the variation in the pattern size and the distance from the wafer center, for example, in a 12-inch wafer, in the range of 0 to 120 mm where the variation of the etching conversion difference is moderate, It is considered that the variation in pattern size in the shot is small. In such a case, as shown in the conceptual diagram of the measurement area in FIG. 9, the exposure shot 91 in the area (including the area including more than half) of the 120 mm line from the center of the wafer w displayed by the broken line, The pattern dimension may be measured for the exposure shot 92 (hatched area) in an area outside the line 120 mm from the center of the wafer w (including an area including more than half) without measuring the pattern dimension. Good.

  In this way, by limiting the measurement region based on the distance dependency from the wafer center of the variation in the etching conversion difference, the measurement time can be shortened and the throughput can be improved.

  Further, in the present embodiment, the region where the difference ΔCD between the actually measured dimension after etching, which is a variation in the pattern dimension, and the target dimension ΔCD is −1 nm ≦ ΔCD <+1 nm is not corrected almost as the target. Is appropriately set according to product specifications. If the exposure shot is within the set range in all regions, it can be determined that no correction is required for the exposure shot.

  Further, in the present embodiment, the case where the irradiation light is formed in a uniaxial direction by the slit and scanned is given as an example. However, the present invention is not limited to this, and may be applied to, for example, surface irradiation. Is possible. In this case, the exposure amount filter only needs to be capable of controlling the transmittance two-dimensionally.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

1 is a diagram showing a configuration of an exposure apparatus in one embodiment of the present invention. FIG. 5 is a diagram illustrating a flowchart in one embodiment of the present invention. The figure which shows an example of the measurement position of the pattern dimension in 1 aspect of this invention. The figure which shows an example of the result of having measured the pattern dimension in the exposure shot in 1 aspect of this invention. The conceptual diagram which shows the exposure amount filter in 1 aspect of this invention. The conceptual diagram which shows the exposure amount filter in 1 aspect of this invention. The conceptual diagram which shows the exposure amount filter in 1 aspect of this invention. FIG. 6 is a diagram illustrating an example of a relationship between an etching conversion difference and a distance from the wafer center in one embodiment of the present invention. The conceptual diagram of the measurement area | region in 1 aspect of this invention.

Explanation of symbols

w ... wafer 11 ... light source 12, 62, 72 ... slit 13, 63, 73 ... exposure amount filter 13a ... filter 14 ... mask 15 ... mask stage 16 ... projection lens 17 ... wafer stage 18, 19 ... position sensor 20 ... control unit 21 ... Measurement mechanism 22 ... Calculation mechanism 23 ... Storage medium 31, 91, 92 ... Exposure shot 32 ... Chip 41, 42, 43, 44, 45, 46, 47 ... Area 63a, 73a ... Pole

Claims (5)

When exposing a mask pattern on a wafer with multiple exposure shots,
Based on a pre-measured pattern size distribution in each exposure shot after etching, a corrected exposure amount in each exposure shot is obtained,
In each of the exposure shots, exposure is performed at the corrected exposure amount.
A pattern is formed on the wafer by etching the exposed wafer to form a semiconductor manufacturing method. Based on the pattern size distribution, a dimensional correction amount is obtained,
2. The semiconductor manufacturing method according to claim 1, wherein the corrected exposure amount is obtained from the dimensional correction amount based on a relationship between the pattern size after etching and the exposure amount obtained in advance. Set an allowable value of variation in pattern dimensions in the pattern dimension distribution,
3. The semiconductor manufacturing method according to claim 1, wherein the exposure shots in which the variation of the pattern dimension is within the allowable value are uniformly exposed at an average value of the corrected exposure amount. 4.   4. The semiconductor manufacturing method according to claim 1, wherein the correction exposure amount is obtained for the exposure shot in an area of a predetermined distance or more from the center of the wafer. 5. A light source for transferring the mask pattern onto the wafer by a plurality of exposure shots;
An exposure amount filter for adjusting an exposure amount in the exposure shot;
A storage medium for storing a corrected exposure amount in each of the exposure shots based on a pattern size distribution in each of the exposure shots after the etching measured in advance corresponding to a position in the wafer;
A semiconductor manufacturing apparatus, comprising: an exposure amount control mechanism that controls the exposure amount filter for each exposure shot based on the corrected exposure amount.

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