JP2010073596A - Lighting inspection method and checking display for plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate an individual potential control to a plurality of address electrodes, and to shorten time required for lighting inspection. <P>SOLUTION: In order to determine right and wrong of a lighting condition in a display panel, a checking display for a plasma display panel repeatedly displays a frame constituted from both or either of a first sub-frame requiring to light up the whole cells in a display panel, and a second sub-frame not requiring to light up the whole cells. In order to display the first sub-frame, the checking display sequentially performs an addressing-preparation operation to form a wall charge for a write-in addressing at each cell between a scan-maintaining electrode and an address electrode in each cell, a whole-surface addressing operation to apply a scanning pulse sequentially in line at a condition where a plurality of address electrodes are kept in a non-selective potential at a batch, and a sustaining operation to apply a sustaining pulse all together to the cells. In order to display the second sub-frame, the checking display sequentially performs a reset operation to reduce the remaining wall charge between the scan-maintaining electrode and the address electrode at each cell in the display panel, the whole-surface addressing operation, and the sustaining operation. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lighting inspection method and an inspection display device for an AC plasma display panel capable of color display.

  The plasma display panel has a gas-filled space sandwiched between a front substrate and a rear substrate and partitioned by partition walls, and selectively emits three colors of UV-excited phosphors of red, green, and blue by gas discharge. Perform color display. The display discharge for causing the phosphor to emit light is a so-called surface discharge type discharge (hereinafter referred to as a surface discharge). The surface discharge occurs between the electrodes of the first and second display electrodes extending in parallel along the horizontal direction of the screen, which is a matrix display area. The display electrodes are generally arranged on the front substrate, and display lines corresponding to the rows of the matrix display are defined in the screen. Address electrodes are arranged on the screen so as to intersect the display lines, and cells serving as display elements correspond to the intersections between the display lines and the address electrodes.

  A typical screen color arrangement is a so-called stripe arrangement in which red, green and blue are arranged in the horizontal direction. In the stripe arrangement screen, the color of cells belonging to the vertical cell column corresponding to each column of the matrix display is the same, and the color development is different between adjacent vertical cell columns. Each vertical cell column corresponds to one address electrode. That is, each address electrode corresponds to any one of the three colors red, green, and blue.

  In a factory that manufactures a plasma display panel, a lighting inspection is performed on the completed plasma display panel. In the conventional inspection, the entire white display for lighting all the cells is performed, and after that or before that, the single color display for lighting all the cells of one color is sequentially performed for the three colors. An inspection person observes these displays to determine whether the plasma display panel is good or bad. During the entire white display, the presence or absence of dark cells (dark spots) and conspicuously bright cells (bright spots) are mainly examined. Then, during monochrome display, the presence or absence of disconnection of the address electrode corresponding to the display color is checked.

Japanese Patent Application Laid-Open No. 2004-133867 proposes automating inspection using a CCD camera for lighting inspection using white display. Further, in this document, when aging a plasma display panel, one of four long external electrodes (electrode bars) is arranged on each of four terminal groups arranged along the four sides of the rectangular plasma display panel. It is described that a voltage is applied to the electrodes of the plasma display panel through the four electrode bars and the terminal group in a state where they are in contact with each other.
JP 2006-100122 A

  In order to perform monochromatic display, a large number of address electrodes whose total number is three times the horizontal resolution of the screen must be individually controlled for each color of the corresponding cell. Unlike the white display, a large number of address electrodes cannot be connected together and connected to the drive circuit at once. For this reason, in the lighting inspection, the address electrode and the drive circuit are connected using a wiring board having a terminal group corresponding to the terminal group of the address electrode. The drive circuit used has a driver that allows individual potential control for the address electrodes. In general, since the terminal arrangement interval is as small as 200 μm or less, it is difficult to position the wiring board with respect to the plasma display panel. In the future, as the screen becomes higher in definition, positioning becomes more difficult and the time required for positioning work becomes longer.

  Further, in order to check the presence / absence of disconnection of the address electrode, it takes a corresponding time to display a single color three times for each of the three colors.

  Furthermore, when inspecting multiple types of plasma display panels with different drivers, the drive circuit must be replaced according to the model.

  The present invention has been made in view of such circumstances, and an object thereof is to eliminate the need for individual potential control for a plurality of address electrodes.

  A method for achieving the above object includes a first substrate and a second substrate sandwiching a gas-filled space, a plurality of sustain electrodes and a plurality of scans arranged in parallel on the first substrate and defining display lines for matrix display in the screen. A sustain electrode, a first insulator layer that covers the sustain electrode and the scan sustain electrode, a plurality of address electrodes that are arranged on the second substrate and intersect the sustain electrode and the scan sustain electrode, and cover the address electrode A plasma display panel lighting inspection method comprising: a second insulator layer, wherein each of the plurality of address electrodes corresponds to one of three cells having different colors forming the screen. In order to determine whether the lighting state of the screen is good or not, the first sub-frame which is a binary image having all the cells in the screen as cells to be lit and all the cells in the screen are lit. In order to repeatedly display a frame composed of both or one of the second sub-frames that are binary images that are not to be cells, and to display the first sub-frame at that time, scanning in each cell in the screen An addressing preparation operation for forming a wall charge for write addressing between the sustain electrode and the address electrode, and a line sequential to the cells in the screen in a state where the plurality of address electrodes are collectively kept at a non-selection potential. In order to perform the entire addressing operation for applying the scan pulse and the sustain operation for simultaneously applying the sustain pulse to the cells in the screen, and to display the second subframe, the scanning in each cell in the screen is performed. Reset operation for reducing wall charges remaining between the sustain electrode and the address electrode, and the entire addressing operation , And performs said sustain operation in order. Means for determining whether or not the lighting state is good is arbitrary. The operator can make a determination based on the result of visual observation, and the determination can be automated using an image recognition technique.

  In the lighting inspection by this method, the white display in which the lighting control for all the cells in the screen is continuously performed, the black display in which the non-lighting display is continuously performed, the lighting control is intermittently performed, and It is possible to make a pass / fail judgment on the gray display in which the non-lighting control is performed between the lighting control and the next lighting control. The display color in the gray display is darker white (gray) than the white display, that is, a neutral gray color. However, the brightness of the screen depends on the number of lightings per unit time. Here, the lighting control means drive control that turns on a cell when it is normal. Non-lighting control means drive control that does not light a cell even if it is normal. If all the cells are normal, all the cells are lit whenever the lighting control is performed.

  If the brightness and display color are uniform over the entire screen, the lighting state is good and the plasma display panel can be made good. On the other hand, if there is a remarkable dark spot or bright spot, the lighting state is poor. The lighting state is also poor when there are horizontal or vertical dark lines that appear due to electrode breakage.

  The disconnection of the address electrode appears as a display color disorder. If there is no disconnection of the address electrode, the display color of the set of three adjacent columns is achromatic as described above. However, if the address electrode corresponding to, for example, the red column in the set is disconnected, the red cell is not lit, so the display color of the set is a complementary color (cyan) of red. This display color is a chromatic color. When two columns in the set are not lit, the display color of the set is the color of the remaining one column. This is also a chromatic color. Disturbances in the display color in which a chromatic line appears on the achromatic background are conspicuous visually and are easy to find. By discriminating what color the chromatic color is, it is possible to know which color of the address electrode corresponding to the disconnection is broken.

  According to the present invention, since it is possible to confirm the presence or absence of disconnection of the address electrodes without sequentially performing three types of single color display with different colors, the single color display that requires individual potential control for a plurality of address electrodes is omitted. be able to.

  Also, since a plurality of address electrodes may be electrically shared and connected to the drive circuit, the connection work is facilitated, and it is not necessary to switch the potential of the address electrodes, so that a driver for the address electrodes is not required. Become.

  In a factory that manufactures a plasma display panel, an operator performs a visual lighting inspection using the inspection display device 1 shown in FIG. The inspection display device 1 displays a frame to be described later in response to a predetermined switch operation or a signal input from an external device. The operator observes the screen displaying the frame and determines whether there is a defect such as a cell defect or electrode disconnection.

  The AC type plasma display panel 2 to be inspected has a screen 50 capable of color display. In the screen 50, the first display electrodes X that are alternately arranged sustain electrodes and the second display electrodes Y that are scan sustain electrodes extend in the horizontal direction, and the address electrodes A extend in the vertical direction. The display electrode X and the display electrode Y define a display line in the screen 50, and constitute an electrode pair for generating a display discharge in a surface discharge type in each display line. A cell is defined at each intersection between the display electrode pair and the address electrode A. Each address electrode A corresponds to one type of the three types of cells having different colors. When the specification of the screen 50 is, for example, the full high-vision specification, the number of display lines is 1080, which is the same as the vertical resolution, and the total number of address electrodes A is 5760, which is three times the horizontal resolution.

  The inspection display device 1 supplies an X driver 61 that applies a voltage pulse to the display electrode X, a Y driver 62 that applies a voltage pulse to the display electrode Y, a controller 65 that controls pulse application by the driver, and power for discharge. Power supply circuit 66 and contact members 67, 68, 69 for electrical connection with the plasma display panel 2. The inspection display device 1 does not have a driver for applying a pulse to the address electrode A. The Y driver 62 includes a reset circuit 620 that applies a pulse for an addressing preparation operation or a reset operation, a scanning circuit 621 that applies a scan pulse, and a sustain circuit 622 that applies a sustain pulse. The controller 65 includes a control unit 651 for displaying a first subframe, which will be described later, and a control unit 652 for displaying a second subframe. The control units 651 and 652 control the X driver 61 and the Y driver 62 so as to apply a predetermined driving voltage to the plasma display panel 2 with reference to a memory that stores waveform data in advance.

  The X driver 61 drives the plurality of display electrodes X all at once via the contact member 67. The contact member 67 is a conductor made of a metal fiber and has a length corresponding to the terminal row of the display electrodes X arranged along one edge in the horizontal direction of the plasma display panel 2. By overlapping the contact member 67 on the terminal row, a large number of display electrodes X are electrically shared.

  The Y driver 62 individually drives the plurality of display electrodes Y via the contact member 68. The contact member 68 is a wiring board having a conductor pattern corresponding to each display electrode Y, and is overlapped with a terminal row of the display electrodes Y arranged along the other edge in the horizontal direction of the plasma display panel 2. . Each display electrode Y is individually connected to a Y driver 62.

  A large number of address electrodes A are collectively maintained at a non-selection potential via a contact member 69 made of a metal fiber. In this example, the non-selection potential is the ground potential, strictly speaking, the potential of the ground terminal of the power supply circuit 66. The contact member 69 has a length corresponding to the terminal row of the address electrode A arranged along one edge in the vertical direction of the plasma display panel 2. By overlapping the contact member 69 on the terminal row, all the address electrodes A are electrically shared and connected to the ground terminal.

  In preparation for lighting inspection, contact members 67, 68, and 69 are stacked at predetermined positions on the periphery of the plasma display panel 2 carried into the inspection display device 1, and are fixed to the plasma display panel 2 with clips (not shown), for example. . At this time, the contact member 67 and the contact member 69 may be in contact with the terminal group to be shared, and high-precision positioning is not necessary. In particular, since the arrangement pitch of the terminals of the address electrodes A is smaller than the arrangement pitch of the terminals of the display electrodes X and Y, the fact that the terminal groups of the address electrodes A may be electrically bundled together with the display device 1 for inspection. This contributes to speeding up the connection with the plasma display panel 2.

  In the lighting inspection, the inspection display device 1 to which the plasma display panel 2 is connected repeatedly displays the frame F shown in FIG. 2 at a frame rate of 1/60, for example. The frame F includes a first subframe SF1 that is a binary image in which all the cells in the screen are to be lit and a second subframe SF2 that is a binary image in which all the cells are not to be lit. Composed. The number of first subframes SF1 and the number of second subframes SF2 are equal, and the number of subframes of frame F is an even number.

  For example, the frame F is composed of a total of 10 subframes including 5 first subframes SF1 and 5 second subframes SF2. A frame period Tf of about 16.7 ms is equally divided into ten, and a time of about 1.67 ms is allocated to each first subframe SF1 and each second subframe SF2. The first subframe SF1 and the second subframe SF2 are alternately displayed one by one. Thereby, if there is no defect in the screen 50, the screen 50 appears as a uniform achromatic surface having a brightness between white and black in the overall visual observation.

The time allocated to the first subframe SF1 is divided into an addressing preparation period TR1, an address period TA, and a sustain period TS, and the time allocated to the second subframe SF2 is divided into a reset period TR2, an address period TA, and a sustain period TS. Is done. The lengths of the three divided periods are equal between the first subframe SF1 and the second subframe SF2, and the drive waveforms of the address period TA and the sustain period TS are common as shown in FIG. is there. The drive waveforms are different between the addressing preparation period TR1 of the first subframe SF1 and the reset period TR2 of the second subframe SF2.
[Driving sequence of first subframe SF1]
In the addressing preparation period TR1, an addressing preparation operation for forming wall charges for write addressing between the display electrode Y (scanning sustain electrode) and the address electrode A in each cell in the screen 50 is performed. The addressing preparation operation illustrated in FIG. 3 uses a so-called blunt wave reset technique to control the wall charge so that a predetermined amount of wall charge remains at the end of the operation. In the blunt wave reset, a weak discharge is continuously generated in each cell by applying a blunt wave pulse typified by a ramp waveform pulse, thereby adjusting the amount of wall charges in the dielectric. Specifically, as shown in FIG. 3, a positive ramp wave pulse Pr1 and a negative ramp wave pulse Pr2 are sequentially applied to the display electrode Y. At this time, an offset bias is applied to the display electrode X in order to accelerate the rise in the voltage between the display electrodes. The potential of the address electrode A is a ground potential.

  By applying the ramp wave pulse Pr1, wall charges are formed between the display electrode Y and the display electrode X and between the display electrode Y and the address electrode A. Since the ramp wave pulse Pr1 is positive, the polarity of the wall charges on the display electrode Y side is negative, and the polarity of the wall charges on the display electrode X side and the address electrode A side is positive. A wall voltage corresponding to the wall charge amount is generated between the electrodes.

  Application of the second ramp wave pulse Pr2 reduces the wall charge previously formed. The decrease in wall charge continues from the start of the minute discharge until the end of the application of the ramp wave pulse Pr2. The application of the ramp wave pulse Pr2 is not intended for erasing the wall charges, and ends when the amount of wall charges necessary for generating discharge remains in response to the application of the scan pulse Py in the address period TA. . When the ramp wave pulse Pr2 is applied, the display electrode X has a potential difference between the display electrode Y and the display electrode Y at the end of the application of the ramp wave pulse Pr2, and the display electrode at the end of the application of the ramp wave pulse Pr3 in the second subframe SF2. It is biased so as to be about the same as the potential difference with Y.

  In the address period TA, a negative scan pulse Py is sequentially applied to the display electrodes Y as many as the number of display lines one by one from the first to the last nth in the array. Selected. The potential of the address electrode A is the ground potential throughout the address period TA. However, since the voltage due to the application of the scan pulse Py is superimposed on the wall voltage due to the wall charges remaining at the start of the address period TA, the scan pulse Py is applied. Each time, an address discharge is generated between the display electrode Y and the address electrode A in the cell of the selected display line. This address discharge triggers a discharge between the display electrode Y and the appropriately biased display electrode X, and a wall charge necessary for sustain is formed on the dielectric covering the display electrode pair. In other words, in the address period TA of the first subframe SF1, a full addressing operation in a writing format is performed in which wall charges are controlled so that all cells are lit in the next sustain period TS.

In the sustain period TS, the sustain pulse Ps is alternately applied to the display electrode Y and the display electrode X. The amplitude of the sustain pulse Ps is a sustain voltage (Vs) slightly lower than the surface discharge start voltage. In the sustain period TS of the first subframe SF1, if a cell in the screen 50 is normal, a discharge between display electrodes occurs every time the sustain pulse Py is applied, and the cell is turned on. A lighted cell exhibits a display color determined by the phosphor it has.
[Driving Sequence of Second Subframe SF2]
In the reset period TR2, a reset operation for reducing wall charges remaining between the display electrode Y (scanning sustain electrode) and the address electrode A in each cell in the screen 50 is performed. Of course, the potential of the address electrode A is the ground potential even in the reset operation. The reset operation illustrated in FIG. 3 uses a blunt wave reset technique and is similar to the above-described addressing preparation operation. The difference from the addressing preparation operation on the drive waveform is that the ramp wave pulse Pr3 is applied in the reset period TR2 instead of the ramp wave pulse Pr2 of the addressing preparation operation. The absolute value of the reached voltage V22 of the ramp wave pulse Pr3 in the reset operation is larger than the absolute value of the reached voltage V12 of the ramp wave pulse Pr2 in the addressing preparation operation.

  The wall charges formed by the application of the ramp wave pulse Pr1 are reduced by the application of the ramp wave pulse Pr3. The decrease in wall charge continues from the start of the minute discharge until the end of the application of the ramp wave pulse Pr3. The application of the ramp wave pulse Pr3 is intended to substantially erase the wall charge, and the wall charge is reduced to such an extent that no discharge corresponding to the application of the scan pulse Py in the address period TA occurs.

  In the address period TA, as in the case of the first sub-frame SF1, negative scan pulses are sequentially applied from the first to the last nth of the array one by one for the same number of display electrodes Y as the number of display lines. Py is applied. However, since the address electrode A remains grounded, no pulse is applied to the address electrode A, and the wall voltage superimposed on the voltage due to the application of the scan pulse Py is zero or close to it. The cell voltage during the period does not exceed the discharge start voltage. Since the address discharge does not occur, wall charges necessary for the sustain are not formed on the dielectric covering the display electrode pair, and the wall charge amount is almost the same as that at the end of the reset operation. That is, in the address period TA of the second subframe SF2, the full addressing operation is performed to maintain the wall charge initialization state so that all the cells are not turned on in the next sustain period TS.

  In the sustain period TS, as in the case of the first subframe SF1, the sustain pulse Ps is alternately applied to the display electrode Y and the display electrode X. If the cell in the screen 50 is normal, it is not lit, and if it is not normal, it is not normally lit. However, excessive lighting may occur for some reason.

Next, the difference between the addressing preparation operation and the reset operation will be described in more detail with reference to FIG. 4A and 4B, the transition of the applied voltage Vd _YA , the wall voltage Vw _YA and the cell voltage Vc _YA between the YA electrodes which are between the display electrode Y and the address electrode A is depicted. The cell voltage Vc _YA is the sum of the applied voltage Vd _YA and the wall voltage Vw _YA . The polarity of each voltage in the figure is based on the address electrode A, and the case where the potential on the display electrode Y side is higher than the potential on the address electrode A side is positive, and the case where it is opposite is negative.

In FIG. 4A, since the sustain period immediately before the addressing preparation period TR1 is a non-lighting period, the wall voltage Vw _YA at the start of the addressing preparation period TR1 is substantially zero as indicated by a chain line in the drawing. Therefore, although not shown, the cell voltage Vc _YA at the start of the addressing preparation period TR1 is substantially equal to the applied voltage Vd _YA . By applying the ramp wave pulse Pr1 (see FIG. 3), the minute discharge starts when the cell voltage Vc _YA substantially equal to the applied voltage Vd _YA exceeds the discharge start voltage + Vf _YA between the YA electrodes. Thereafter, wall charges are formed so as to cancel the increase in the applied voltage Vd _YA , and the cell voltage Vc _YA is substantially maintained at the discharge start voltage Vf _YA . When a ramp wave pulse Pr2 having an opposite polarity is applied subsequent to the ramp wave pulse Pr1, the wall charge is gradually reduced by a minute discharge, but the ultimate voltage of the ramp wave pulse Pr2 is selected to be lower as described above. A predetermined amount of wall charge remains.

In the address period TA following the addressing preparation period TR1, the negative scan pulse Py is applied in a state where the negative wall voltage Vw _YA is generated between the YA electrodes. As a result, the cell voltage Vc _YA exceeds the discharge start voltage −Vf _YA and address discharge occurs. Since wall charges are used to generate the address discharge, it is not necessary to make the amplitude of the scan pulse Py larger than the discharge start voltage −Vf _YA .

On the other hand, in FIG. 4B, at the start of the reset period TR2, the wall charge in the vicinity of the address electrode A is almost zero, but the immediately preceding sustain period is the lighting period and the wall charge in the vicinity of the display electrode Y. Therefore, a positive wall voltage Vw _YA is generated between the YA electrodes. In the reset period TR2, first, the polarity of the wall voltage Vw _YA is reversed by applying a ramp wave pulse Pr1 (see FIG. 3), and negative wall charges are formed in the vicinity of the display electrode Y in the same manner as the addressing preparation operation. Next, the wall charge is sufficiently reduced by applying a ramp wave pulse Pr3 (see FIG. 3).

In the address period TA following the reset period TR2, the scan pulse Py is applied in a state where the wall voltage Vw _YA between the YA electrodes is substantially zero. Since the cell voltage Vc _YA does not exceed the discharge start voltage −Vf _YA , no address discharge occurs.

  As described above, the drive sequence including the line sequential addressing operation applied to the first subfield SF1 and the second subframe SF2 is similar to the drive sequence when the plasma display panel 2 is used for displaying an arbitrary image. In addition, it is useful in confirming the lighting state during actual use, and has an advantage that a drive device for actual use can be used for lighting inspection. In the display of the frame F, all the cells are driven so as to be lit up or not lit up at the same time. Therefore, it is theoretically possible to apply the scan pulse Py to all the display lines all at once instead of selecting the sequential display lines. Is possible. However, if it is done, it will be very different from the driving mode in actual use.

  The time required for the addressing operation depends on the scan pulse width and the number of display lines. For example, when the scan pulse width is 1 μs and the number of display lines is 1080, the addressing time per subframe is 1.08 ms. When the frame F has a 10-subframe organization, the allocation time for one subframe is about 1.67 ms, so that, for example, 0.27 ms and 0.32 ms can be sequentially assigned to the reset operation and the sustain operation. If a pulse width in which a pair of sustain pulses for applying an alternating polarity voltage between display electrodes is regarded as one pulse is 10 μs, 64 sustain discharges can be generated in a sustain period TS of 0.32 ms.

  An operator in charge of lighting inspection of the plasma display panel 2 observes the screen 50 in a state where the inspection display device 1 repeatedly displays the frame F over a period of, for example, several minutes, and detects cell defects and electrodes. Check for defects such as wire breakage. If the brightness and display color are uniform throughout the screen 50, the lighting state is good, and if there is a noticeable dark spot or bright point, the lighting state is bad. Most of the dark spots are caused by defective patterning of the display electrodes. The main cause of the bright spot is a lack of partition walls that partition the gas discharge space. Standards for determining whether the plasma display panel 2 is good or bad are set in advance, and the operator determines the quality of the plasma display panel 2 based on the observation results.

  The disconnection of the address electrode appears as a display color disorder and is easy to find. If there is no disconnection of the address electrode, the red, green and blue cells are lit, so that the display color is a halftone achromatic color as described above. However, for example, if the address electrode A corresponding to a blue cell is disconnected, the display color near the disconnected address electrode A is a blue complementary color (mixed color of red and green). When the address electrode A corresponding to the green cell is disconnected, the display color near the disconnected address electrode A is a complementary color of green (mixed color of red and blue). If adjacent address electrodes A are both disconnected, the display color near the disconnected address electrode A is one of the three colors. In any case, the display color is locally chromatic on the screen 50. When three address electrodes A including one address electrode A and the adjacent electrodes are disconnected, a portion corresponding to these address electrodes A in the screen 50 appears as a dark line.

  FIG. 5 shows an example of the cell structure of the plasma display panel 2. The plasma display panel 2 includes a front plate 10, a back plate 20, and a discharge gas (not shown). In the figure, the front plate 10 and the back plate 20 are shown separated to facilitate understanding of the internal structure.

  The front plate 10 includes a glass substrate 11, a first display electrode (sustain electrode) X, a second display electrode (scan sustain electrode) Y, a dielectric layer 17, and a protective film 18 that prevents sputtering on the dielectric layer 17. Prepare. Each of the display electrodes X and Y is composed of a transparent conductor and a metal band as a power supply bus. The first insulator composed of the dielectric layer 17 and the protective film 18 extends over the entire screen and covers the display electrodes X and Y.

  The back plate 20 includes a glass substrate 21, an address electrode A, a dielectric layer 22 as a second insulator, a grid-like partition wall 23, a red (R) phosphor 26, a green (G) phosphor 27, and A blue (B) phosphor 28 is provided. The partition wall 23 includes a plurality of vertical walls 24 parallel to the address electrodes A and a plurality of horizontal walls 25 parallel to the display electrodes X and display electrodes Y.

  The color arrangement of the screen determined by the arrangement of the phosphors is a stripe arrangement in which three colors are repeatedly arranged in the order of R, B, and G in the horizontal direction. In the vertical cell column corresponding to each column of the matrix display, the color development of the cells is the same, and the color development is different between the adjacent vertical cell columns. Each address electrode A corresponds to any one of three colors of red, green and blue.

  Note that the arrangement of the display electrodes X and Y may be either of two widely known forms. One is to arrange display electrodes one by one on the display line as shown in the figure so that the electrode gap between adjacent display lines is wider than the electrode gap (surface discharge gap) in each display line. In the other one, display electrodes are arranged at equal intervals, and all display electrode gaps are used as surface discharge gaps. The partition pattern is not limited to the illustrated lattice pattern, and may be a stripe pattern.

  According to the above embodiment, since the halftone is displayed by alternately displaying the first sub-frame SF1 that is the full lighting image and the second sub-frame SF2 that is the full non-lighting image, the driving frequency is lowered. In comparison with the case where only the full lighting image is displayed, the phenomenon that the cell that should not be lighted is lighted by induction from the lighted cell (excessive lighting) is less likely to occur, and it is easy to find the disconnection of the electrode.

  In addition, since the ramp wave pulse Pr2 and the ramp wave pulse Pr3 have the same ramp wave slope, and the arrival voltage V12 and the arrival voltage V22 are made different depending on the length of the slope portion, the circuit has a relatively simple configuration. Addressing preparation operation and reset operation can be realized. The reset circuit 620 of the Y driver 62 includes a block that outputs a positive ramp wave pulse Pr1 and a block that outputs negative ramp wave pulses Pr2 and Pr3. Each block includes, for example, a capacitor and a constant current source that charges the capacitor. Have The controller 65 controls the ultimate voltage by turning on and off the constant current source.

  In the above-described embodiment, the combination of the first subframe SF1 and the second subframe SF2 in the frame F is arbitrary. The subframe organization of the frame F for the inspection by gray display may be any as long as the number of subframes is two or more and includes the first subframe SF1 and the second subframe SF2. The number of first subframes SF1 and the number of second subframes SF2 are preferably the same, but they may be different. It is not always necessary to alternately display the first subframe SF1 and the second subframe SF2 one by one, and the second subframe SF2 may be displayed after two or more first subframes SF1 are displayed in succession or vice versa. A display order in which the first subframe SF1 is displayed after the two or more second subframes SF2 are continuously displayed can be employed. Further, it is not necessary to allocate the same length of time to the first subframe SF1 and the second subframe SF2. The length of the sustain period TS may be different between the first subframe SF1 and the second subframe SF2.

  Also, white display is possible by organizing all the subframes of the frame F only by the first subframe SF1, and black display is possible by organizing all the subframes by only the second subframe SF2. . By appropriately switching the combination of the first subframe SF1 and the second subframe SF2, not only gray display but also display inspection in white display and black display can be performed.

  Although an example in which the worker determines whether the lighting state is good or bad is given, the inspection can be automated using an image recognition technique. The setting of the plasma display panel 2 to the inspection position and the electrical connection between the inspection display device 1 and the plasma display panel 2 performed using the contact members 67 to 69 may be automated, or may be performed by an operator. .

  The illustrated driving waveform is an example, and the amplitude, polarity, and timing can be changed variously. For example, in the sustain period TS, the sustain voltage may be applied between the display electrodes by simultaneously applying pulses having different polarities to the display electrode X and the display electrode Y. In order to increase the discharge probability of the sustain discharge, the initial pulse amplitude and pulse width of the sustain period may be increased. It is possible to adopt a double scan method in which the address electrode A is divided into two and two display lines are selected simultaneously. When selecting the ultimate voltages V12 and V22 of the ramp wave pulses Pr2 and Pr3, the slope of the ramp wave may be varied. The non-selection potential is not limited to the ground potential, and may be a positive or negative potential close to zero volts.

It is a figure which shows the outline of a structure of the display apparatus for a test | inspection which concerns on embodiment of this invention. It is a figure which shows the structure of the flame | frame which a display apparatus for a test | inspection displays. It is a figure which shows an example of a drive waveform. It is a figure which shows the change of the wall voltage in an addressing preparation operation and reset operation. It is a figure which shows an example of the cell structure of a plasma display panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inspection display apparatus 2 Plasma display panel 17 Dielectric layer (1st insulator layer)
18 Protective film (first insulator layer)
22 Dielectric layer (second insulator layer)
X First display electrode (sustain electrode)
Y second display electrode (scanning sustain electrode)
A address electrode 50 screen SF1 first subframe SF2 second subframe F frame TR1 addressing preparation period TR2 reset period TA address period TS sustain period Py scan pulse Ps sustain pulse 69 contact member (conductor)
61 X driver 62 Y driver 65 Controller 651, 652 Control unit

Claims (7)

A first substrate and a second substrate sandwiching a gas filled space, a plurality of sustain electrodes and a plurality of scan sustain electrodes arranged in parallel on the first substrate and defining display lines for matrix display in the screen, the sustain electrodes and the scan A first insulator layer covering the sustain electrodes; a plurality of address electrodes arranged on the second substrate and intersecting the sustain electrodes and the scan sustain electrodes; and a second insulator layer covering the address electrodes. The plasma display panel lighting inspection method corresponds to each of the plurality of address electrodes corresponding to one of the three differently colored cells constituting the screen.
In order to determine whether the lighting state of the screen is good or bad, the first subframe which is a binary image in which all the cells in the screen are to be lit, and all the cells in the screen are not to be lit In order to repeatedly display a frame composed of both or one of the second sub-frames which are binary images, and to display the first sub-frame at that time, the scan sustaining electrode and the address electrode in each cell in the screen Addressing preparation operation for forming wall charges for write addressing, and scan pulses are sequentially applied to the cells in the screen in a state in which the plurality of address electrodes are collectively kept at a non-selection potential. A full addressing operation and a sustain operation in which a sustain pulse is applied simultaneously to the cells in the screen are sequentially performed, and the second subframe is displayed. In order to achieve this, a reset operation for reducing wall charges remaining between a scan sustain electrode and an address electrode in each cell in the screen, the entire addressing operation, and the sustain operation are sequentially performed. A lighting inspection method for plasma display panels. The lighting inspection method for the plasma display panel according to claim 1, wherein the address electrode is kept at the non-selection potential throughout a period for displaying the frame. The lighting check method for a plasma display panel according to claim 2, wherein the non-selection potential is a potential of a ground terminal of a power source, and the frame is displayed in a state where the address electrode is connected to the ground terminal. The lighting inspection method for the plasma display panel according to claim 2, wherein the plurality of address electrodes are electrically shared by connecting their end portions with a conductor. The lighting inspection method for the plasma display panel according to claim 2, wherein the first subframe and the second subframe are alternately displayed. The lighting inspection method for the plasma display panel according to claim 2, wherein the combination of the first subframe and the second subframe in the frame is arbitrarily switched. A first substrate and a second substrate sandwiching a gas filled space, a plurality of sustain electrodes and a plurality of scan sustain electrodes arranged in parallel on the first substrate and defining display lines for matrix display in the screen, the sustain electrodes and the scan A first insulator layer covering the sustain electrodes; a plurality of address electrodes arranged on the second substrate and intersecting the sustain electrodes and the scan sustain electrodes; and a second insulator layer covering the address electrodes. The display device for inspection used for the lighting inspection of the plasma display panel corresponding to one of the three types of cells of different color forming the screen for each of the plurality of address electrodes,
An X driver for applying a drive pulse to the sustain electrodes;
A Y driver for applying a drive pulse to the scan sustaining electrode;
Either or one of the first subframe, which is a binary image in which all cells in the screen are to be lit, and the second subframe, which is a binary image in which all cells in the screen are not to be lit A controller for controlling the X driver and the Y driver so as to repeatedly display a frame composed of:
The controller is
An addressing preparation operation for forming a wall charge for write addressing between a scan sustain electrode and an address electrode in each cell in the screen, and the plurality of address electrodes in a state where the plurality of address electrodes are collectively maintained at a non-selection potential. The first subframe that causes the X driver and the Y driver to perform a full addressing operation in which scan pulses are sequentially applied to cells in a screen in a line and a sustain operation in which sustain pulses are simultaneously applied to cells in the screen. A control unit for displaying
Causing the X driver and the Y driver to perform a reset operation for reducing a wall charge remaining between a scan sustain electrode and an address in each cell in the screen, the entire addressing operation, and the sustain operation. A test display device comprising a control unit for displaying two subframes.

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