JP2010073257A - Semiconductor memory and method of manufacturing semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate signal lines and internal circuits which are not used for test. <P>SOLUTION: A semiconductor memory includes a larger number of internal data buses than external data buses. The internal data buses include first and second internal data buses. A data input and output circuit includes a plurality of first selection circuits and second and third selection circuits to input data to a memory cell array or output data read from the memory cell array. Each first selection circuit selectively supplies the data from the memory cell array to the first or second internal data bus. The second selection circuit switches the first or second internal data bus to connect with an external data bus. The third selection circuit selectively supplies a first or second clock signal on the basis of a test mode signal. This allows supply of the data to the external data buses selectively using the first or second internal data bus. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a semiconductor memory having a test function.

As a semiconductor memory such as a DRAM, for example, a DDR (Double Data rate) type SDRAM having a high data transfer rate has been developed. This type of semiconductor memory has more internal data buses than the number of external data buses, and transmits data signals in parallel to the internal data bus, thereby lowering the operating frequency of the internal circuit compared to the external operating frequency. ing. In general, in order to test a semiconductor memory such as a DDR-SDRAM, an expensive test apparatus having high performance is required (for example, see Patent Document 1). On the other hand, in order to test a semiconductor memory using an inexpensive test apparatus having low performance, it has been proposed to lower the data transfer rate of the semiconductor memory during the test operation mode (see, for example, Patent Document 2).
JP 2006-78447 A JP 2004-362762 A

  However, when the data transfer rate is lowered during the test operation mode, there may be signal lines and internal circuits that are not used in the semiconductor memory. If there are signal lines and internal circuits that are not used, that part cannot be tested. As a result, an inexpensive test device cannot be used, and the semiconductor memory must be tested using an expensive test device.

  An object of the present invention is to eliminate signal lines and internal circuits that are not used in the test. In particular, when a test is performed at a low data transfer rate, internal circuits and signal lines that are not used are eliminated.

  The semiconductor memory has a plurality of internal data buses that are larger than the number of external data buses. The internal data bus includes a first internal data bus and a second internal data bus. The data input / output circuit inputs data to the memory cell array or outputs data read from the memory cell array. The data input / output circuit includes a plurality of first selection circuits, a second selection circuit, and a third selection circuit. Each first selection circuit selectively supplies data from the memory cell array to the first internal data bus or the second internal data bus. The second selection circuit switches between the first internal data bus and the second internal data bus and connects to the external data bus. The third selection circuit selectively supplies the first clock signal or the second clock signal based on the test mode signal.

  By selectively using the first internal data bus or the second internal data bus and supplying data to the external data bus, signal lines and internal circuits that are not used in the test can be eliminated. Since data can be read from the memory cell array using only one of the first internal data bus and the second internal data bus, the semiconductor memory can be operated at a low data transfer rate. As a result, signal lines and internal circuits that are not used can be eliminated when the test is performed at a low data transfer rate. As a result, the semiconductor memory can be tested using an inexpensive test apparatus, and the cost of the semiconductor memory can be reduced.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, a plurality of signal lines indicated by bold lines are shown. A part of the block to which the thick line is connected has a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “Z” at the end indicates positive logic. A signal preceded by “/” indicates negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows a semiconductor memory MEM in one embodiment. For example, the semiconductor memory MEM is a DDR (Double Data Rate) type SDRAM. The semiconductor memory MEM also operates as an SDR (Single Data Rate) type SDRAM. The semiconductor memory MEM may be designed as a semiconductor memory device enclosed in a package, or may be designed as a memory macro (IP) mounted on a system LSI or the like.

  The semiconductor memory MEM includes a command input buffer 10, a command decoder 12, a core control circuit 14, a mode setting circuit 16, an address input buffer 18, an address latch circuit 20, a clock generation circuit 22, a clock switching circuit 24, a data input buffer 26, data An output buffer 28, a data multiplexer 30, a bus switching circuit 32, and a memory core 34 are included. The data input buffer 26, the data output buffer 28, the data multiplexer 30 and the bus switching circuit 32 arranged between the data terminal DQ and the memory core 34 are circuits for inputting or outputting data.

  The command input buffer 10 receives the command signal CMD and outputs the received command signal CMD as an internal command signal ICMD. For example, the command signal CMD is a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE.

  The command decoder 12 decodes the command signal ICMD and outputs an active command signal ACTV, a precharge command signal PRE, a read command signal RD, a write command signal WR, a refresh command signal REF, or a mode setting command signal MSET. The active command ACTV is supplied when setting the memory cell array ARY to the active state. The precharge command PRE is supplied when precharging the bit lines BL and / BL (FIG. 2) of the memory cell array ARY. The read command signal RD is supplied when reading data held in the memory cell array ARY. The write command signal WR is supplied when data is written to the memory cell array ARY. The refresh command signal REF is supplied when the memory cell MC (FIG. 2) is refreshed. The mode setting command MSET is supplied when setting the mode setting circuit 16 to a predetermined state. The code BL is also used as the name of the burst length.

  The core control circuit 14 outputs a control signal CNT (timing signal) for controlling the operation of the memory core 34 in response to the command signals ACTV, PRE, RD, WR, and REF. The control signal CNT activates the precharge control signal BRSZ for precharging the bit lines BL and / BL, the bit control signal BTZ for controlling the connection switch BT (FIG. 2), and the word line WL (FIG. 2). A word control signal WLZ for activation, a sense amplifier control signal LEZ for activating the sense amplifier SA, a column control signal CLZ for turning on the column switch CSW (FIG. 2), and a read for activating the read amplifier RA. An amplifier control signal RAEZ and a write amplifier control signal WAEZ for activating the write amplifier WA are included.

  The mode setting circuit 16 has a plurality of registers that are set according to the value of the address signal IAD (AD) received together with the mode setting command MSET. Mode setting circuit 16 may be set according to the value of data signal DQ received together with mode setting command MSET. Mode setting circuit 16 activates test mode signal TMZ to a high level when the value of address signal IAD (AD) received together with mode setting command MSET indicates the test operation mode. As the test mode signal TMZ is activated, the semiconductor memory MEM is set to the test operation mode.

  In the mode setting circuit 16, a data transfer mode, a burst length BL, and a read latency RCL are also set. When the data transfer mode is set to the DDR mode, the low-level operation mode signal SDRZ is output. When the data transfer mode is set to the SDR mode, the high-level operation mode signal SDRZ is output. The high-level mode signal SDRZ (SDR mode) also functions as a test mode signal for testing the semiconductor memory MEM using the internal data bus DBB, as shown in FIGS.

  The burst length BL is the number of times of output of a data signal output from the data terminal DQ in response to one read command RD and the number of input of a data signal received at the data terminal DQ in response to one write command WR. is there. The read latency RCL is the number of clocks until the first read data is output from the data terminal DQ after receiving the read command RD. The mode setting circuit 16 has a register function generally called a mode register or a configuration register.

  Address input buffer 18 outputs address signal AD received at the address terminal as internal address signal IAD. The address latch circuit 20 latches an address signal IAD (row address signal) supplied in synchronization with the row address strobe signal / RAS in a row address latch, and outputs the latched signal as a row address signal RAD. The row address signal RAD is used for selecting the word line WL. The address latch circuit 20 latches the upper bit of the address signal IAD (column address signal) supplied in synchronization with the column address strobe signal / CAS in the column address latch, and outputs the latched signal as the upper column address signal CADU. To do.

  The address latch circuit 20 has an internal address generation circuit ADGEN. The internal address generation circuit ADGEN latches the lower bit of the address signal IAD (column address signal) supplied in synchronization with the column address strobe signal / CAS in the column address latch and outputs it as the lower column address signal CADL. Further, the internal address generation circuit ADGEN increases the upper 2 bits (for example, CADL2-1) of the column address signal CADL by 1 in synchronization with the clock signal CLK. Column address signals CADU and CDAL are used to select bit line pair BL and / BL. For example, the column address signal CADL is 3 bits, and the column address signal CADU is 6 bits.

  The clock generation circuit 22 generates internal clock signals CLK1 and CLK2 in synchronization with the clock signal CLK. For example, the clock signal CLK2 is a signal obtained by inverting the phase of the clock signal CLK1. That is, the clock signals CLK1 and CLK2 have opposite phases. The clock generation circuit 22 outputs only the clock CLK1 and stops generating the clock signal CLK2 while receiving the high-level mode signal SDRZ during the normal operation mode (during SDR mode).

  Clock switching circuit 24 generates internal clock signals CLKa and CLKb in synchronization with clock signals CLK1 and CLK2 when test mode signal TMZ is at a low level (in the normal operation mode). The clock switching circuit 24 has a function of setting the generation order of the clock signals CLKa and CLKb according to the value of the least significant bit of the column address signal CADL during the DDR mode (SDRZ = low level). For example, when the least significant bit of the column address signal CADL is logic 0, the clock switching circuit 24 generates the clock signal CLKa in response to the read command RD or the write command WR. Thereafter, the clock switching circuit 24 generates clock signals CLKb, CLKa, CLKb,. When the least significant bit of the column address signal CADL is logic 1, the clock switching circuit 24 generates the clock signal CLKb in response to the read command RD or the write command WR. Thereafter, the clock switching circuit 24 generates clock signals CLKa, CLKb, CLKa,.

  The clock switching circuit 24 generates only the internal clock signal CLKa and does not generate the internal clock signal CLKb during the SDR mode. When the test mode signal TMZ is at a high level (during the test operation mode), the clock switching circuit 24 outputs the clock signal CLK1 as the internal clock signal CLKb. During the test operation mode, the internal clock signal CLKa is not output.

  When receiving the write command WR, the data input buffer 26 receives the data signal DQ (DQ0-31, write data) supplied to the data terminal in synchronization with the clock signal CLK, and sends the received signal to the external data bus EXTB. Output to (EXTB0-31). The data input buffer 26 sequentially receives the number of data signals DQ corresponding to the burst length BL. In the DDR mode, the data signal DQ is supplied in synchronization with the rising edge and falling edge of the clock signal CLK. In the SDR mode, the data signal DQ is supplied in synchronization with only the rising edge of the clock signal CLK.

  When receiving the read command RD, the data output buffer 28 outputs read data supplied from the data multiplexer 30 to the external data bus EXTB to the data terminal DQ in synchronization with the clock signal CLK. The data output buffer 28 sequentially outputs the number of data signals DQ corresponding to the burst length BL. In the DDR mode, the data signal DQ is output in synchronization with the rising edge and falling edge of the clock signal CLK. In the SDR mode, the data signal DQ is output in synchronization with only the rising edge of the clock signal CLK.

  Data multiplexer 30 connects internal data bus DBA (DBA0-31) to external data bus EXTB in synchronization with clock signal CLKa. Data multiplexer 30 connects internal data bus DBB (DBB0-31) to external data bus EXTB in synchronization with clock signal CLKb. Thus, in the semiconductor memory MEM of this embodiment, the ratio of the number of internal data buses DBA and DBB (= 64) to the number of external data buses EXTB (= 32) is designed to be 2: 1. By making the number of internal data buses DBA and DBB larger than the number of external data buses EXTB, data signals can be read from the memory core 34 in parallel. In addition, data signals can be written to the memory core 34 in parallel. Thereby, the operation of the memory core 34 can be made slower than the operations of the data output buffer 28 and the data input buffer 26, and the timing design of the memory core 34 can be facilitated. The data multiplexer 30 operates as a parallel / serial conversion circuit during a read operation, and operates as a serial / parallel conversion circuit during a write operation.

  In the normal operation mode (TMZ = low level), the bus switching circuit 32 converts the internal data bus EDB (EDB0-31) to the internal data bus DBA (DBA0-31) when the mode signal SDRZ is low level (DDR mode). The internal data bus ODB (ODB0-31) is connected to the internal data bus DBB (DBB0-31). Further, in the normal operation mode, the bus switching circuit 32 connects the internal data buses EDB and ODB to the internal data bus DBA when the mode signal SDRZ is at a high level (SDR mode). That is, in the SDR mode, write data and read data are transmitted only to the internal data bus DBA.

  Each bit of the external data bus EXTB and the internal data buses DBA, DBB, EDB, and ODB may have a single signal line or a complementary signal line. In the following description, it will be described as a single signal line.

  Further, the bus switching circuit 32 connects the internal data buses EDB and ODB to the internal data bus DBB in the test operation mode (TMZ = high level). That is, in the test operation mode, write data and read data are transmitted only to the internal data bus DBB. The test operation mode operates in the SDR mode, and data is input / output in synchronization with only the rising edge of the clock signal CLK. Thus, the internal data bus DBB that is not used in the SDR mode during the normal operation mode and a circuit connected to the internal data bus DBB can be used during the test operation mode. In other words, the data signal transmission path including the internal data bus DBB can be tested using the test operation mode. As a result, the test coverage can be improved and the reliability of the semiconductor memory MEM can be improved. Test coverage is the ratio of the signal path being tested to the total signal path.

  The memory core 34 includes a plurality of memory cell arrays ARY, a word decoder WDEC corresponding to each memory cell array ARY, a sense amplifier area SAA arranged between the memory cell arrays ARY, a column decoder CDEC, a read amplifier RA, and a write amplifier WA. is doing. Each memory cell array ARY has memory blocks EV and OD. The memory block EV is selected when the least significant bit of the column address signal CADL is logic 0. The memory block OD is selected when the least significant bit of the column address signal CADL is logic 1. The memory blocks EV and OD have a plurality of dynamic memory cells arranged in a matrix.

  The word decoder WDEC decodes the row address signal RAD in order to select one of the word lines WL. The column decoder CDEC decodes the column address signal CADU and turns on a predetermined number of column switches CSW in order to select a bit line pair BL, / BL that is an integral multiple of the number of bits (= 32) of the data terminal DQ. Column select signal CL0 (FIG. 2). For example, “integer multiple” is “8” equal to the maximum value of the burst length BL. The “predetermined number” is “256” obtained by multiplying the maximum value of the burst length BL by the number of data terminals DQ (= 32).

  The read amplifier RA amplifies a read data signal output via the column switch CSW during a read operation, and outputs it to the internal data buses EDB and ODB. The read amplifier RA determines the output order of the read data according to the value of the lower column address signal CADL. The write amplifier WA amplifies a write data signal supplied via the internal data buses EDB and ODB and outputs the amplified data to the bit line pair BL and / BL during a write operation. The write amplifier WA determines the input order of the write data according to the value of the lower column address signal CADL.

  When this embodiment is applied to a clock synchronous pseudo SRAM, for example, the command signal CMD is a chip enable signal / CE, a write enable signal / WE, and an output enable signal / OE. At this time, the command decoder 12 decodes only the read command RD, the write command WR, or the mode setting command MSET. The core control circuit 14 includes a refresh request generation circuit that periodically generates an internal refresh command (internal refresh request signal) and an external access command (read command signal RDZ or write command signal) to periodically execute a refresh operation. WRZ) has an arbiter that determines the priority order of the access operation and the refresh operation when the internal refresh command conflicts.

  FIG. 2 shows an example of the memory core 34 shown in FIG. For example, FIG. 2 shows a part of the sense amplifier area SAA corresponding to one column address (area corresponding to two data terminals DQ).

  The memory cell array ARY includes a plurality of word lines WL connected to columns of memory cells MC arranged in the vertical direction in the figure, and a plurality of bit line pairs BL, / connected to columns of memory cells MC arranged in the horizontal direction in the figure. BL. Memory cell MC includes a capacitor for holding data as electric charge and a transfer transistor for connecting one end of the capacitor to bit line BL (or / BL). The other end of the capacitor is connected to a reference voltage line. The reference voltage supplied to the reference voltage line is, for example, the same as the precharge voltage VPR.

  The sense amplifier area SAA includes a precharge circuit PRE and a connection switch BT corresponding to each memory cell array ARY, and a sense amplifier SA and a column switch CSW shared by a pair of adjacent memory cell arrays ARY. For example, the sense amplifier area SAA is laid out with two sense amplifiers SA as one unit. Each precharge circuit PRE has three nMOS transistors. The precharge circuit PRE connects the bit line pair BL, / BL to the precharge voltage line VPR according to the precharge control signal BRS0 (or BRS1). Precharge control signals BRS0-1 are generated in synchronization with precharge control signal BRSZ.

  Each connection switch BT has two nMOS transistors. The connection switch BT is turned on in response to the switch control signal line BT0 (or BT1), and connects the bit line pair BL, / BL to the bit line SBL (/ SBL) of the sense amplifier SA. The switch control signal lines BT0-1 are generated in synchronization with the bit control signal BTZ.

  Each sense amplifier SA has two nMOS transistors connected to the sense amplifier activation signal line NSA and two pMOS transistors connected to the sense amplifier activation signal line PSA. The sense amplifier activation signal lines PSA and NSA are generated in synchronization with the sense amplifier control signal LEZ.

  Each column switch CSW is turned on in response to a column selection signal CL (here, CL0), and connects the bit line pair BL, / BL to the data lines DT, / DT (DT0-1, DT0-1). For example, 256 column switches CSW (32DQ × 8 bits) are turned on in response to a common column selection signal CL (here, CL0). In other words, one column selection signal line CL0 is commonly connected to eight column switches CSW for each data terminal DQ. Four of the eight column switches CSW are connected to the memory block EV, and the remaining four are connected to the memory block OD. For example, in the read operation, 128 bits (4 bits for each data terminal) from the memory block EV and 128 bits (4 bits for each data terminal) from the memory block OD are transferred to the read amplifier RA. In the write operation, 128 bits (4 bits per data terminal) are transferred from the write amplifier WA to the memory block EV, and 128 bits (4 bits per data terminal) are transferred from the write amplifier WA to the memory block OD.

  The column selection signal CL0 is generated in synchronization with the column control signal CLZ. The column selection signal CL0 is selected according to the upper column address signal CADU excluding the lower 3-bit column address signal CADL in the column address signal CAD. For example, the column address signal CADU is 6 bits and selects any one of the 64 column selection signals CL0-63.

  The data lines DT and / DT are connected to the write amplifier WA and the read amplifier RA shown in FIG. Read data signals read to the eight data lines DT and / DT through the column switch CSW and amplified by the read amplifier RA are output to the internal data bus EDB or ODB. Similarly, the write data signal transferred from the bus switching circuit 32 to the internal data bus EDB or ODB is amplified by the write amplifier WA and output to one of the eight data lines DT and / DT. Since the operation (timing) of the sense amplifier area SAA is the same as that of a general SDRAM, detailed description thereof is omitted.

  FIG. 3 shows an example of the clock switching circuit 24 shown in FIG. The clock switching circuit 24 has four switch circuits SW1-4 that are turned on or off according to the test mode signal TMZ. For example, the switch circuits SW1-4 have a CMOS transfer gate. The CMOS transfer gate labeled N is turned on during the normal operation mode (TMZ = low level). The CMOS transfer gate labeled T is turned on during the test operation mode (TMZ = high level). Thus, during the normal operation mode, the clock signal lines CLKa and CLKb are connected to the clock signal lines CLK1 and CLK2, respectively. During the test operation mode, the clock signal lines CLKa and CLKb are connected to the ground line VSS and the clock signal line CLK1, respectively.

  Note that the switch circuit SW4 is arranged to align the load of the clock signal line CLKa with the load of the clock signal line CLKb. That is, each clock signal line CLKa, CLKb is connected to two CMOS transfer gates. However, when the load on the CMOS transfer gate is relatively small, the switch circuit SW4 may not be arranged.

  FIG. 4 shows an example of the operation of the clock generation circuit 22 and the clock switching circuit 24 shown in FIG. In the normal operation mode and the DDR mode (TMZ = low level, SDRZ = low level), the clock signal CLKa has the same phase as the clock signal CLK1. The clock signal CLKb has the same phase as the clock signal CLK2. The phases of the clock signals CLKa and CLKb are opposite to each other.

  In the normal operation mode and SDR mode (TMZ = low level, SDRZ = high level), only the clock signal CLKa is generated in synchronization with the clock signal CLK1, and the generation of the clock signal CLKb is prohibited. In the test operation mode TMD (TMZ = high level, SDRZ = high level), only the clock signal CLKb is generated in synchronization with the clock signal CLK1, and generation of the clock signal CLKa is prohibited. The phase of the clock signal CLKb is the same as the phase of the clock signal CLK1.

  FIG. 5 shows an example of the bus switching circuit 32 and the data multiplexer 30 shown in FIG. FIG. 5 shows only a circuit corresponding to the data terminal DQ0. The bus switching circuit 32 and the data multiplexer 30 corresponding to the data terminals DQ1-31 are also the same as in FIG.

  The bus switching circuit 32 includes four switch circuits SW5-8 that are turned on or off in response to the test mode signal TMZ, similarly to the clock switching circuit 24 shown in FIG. During the normal operation mode (TMZ = low level), the internal data buses DBA0 and DBB0 are connected to the internal data buses EDB0 and ODB0, respectively. During the test operation mode (TMZ = high level), internal data buses DBA0 and DBB0 are connected to ground line VSS and internal data bus EDB0, respectively.

  Switch circuit SW8 is arranged to align the load on internal data bus DBA0 with the load on internal data bus DBB0. That is, each internal data bus DBA0, DBB0 is connected to two CMOS transfer gates. However, when the load on the CMOS transfer gate is relatively small, the switch circuit SW8 may not be arranged.

  During the SDR mode, the internal data buses EDB0 and ODB0 are connected to each other via the switch circuit SW9. For example, the switch circuit SW9 has a CMOS transfer gate. Thereby, for example, during the normal operation mode and the SDR mode, read data on the internal data bus ODB0 is transmitted not only to the internal data bus DBB0 but also to the internal data bus DBA0. Write data on the internal data bus DBA0 is transmitted not only to the internal data bus EDB0 but also to the internal data bus ODB0.

  The data multiplexer 30 includes two switch circuits SW10-11 that are turned on while the clock signals CLKa and CLKb are at a high level, and a latch circuit LT1 that latches a data signal on the external data bus EDB0. For example, the switch circuit SW10-11 has a CMOS transfer gate.

  FIG. 6 shows a system SYS on which the semiconductor memory MEM shown in FIG. 1 is mounted. A system SYS (user system) in FIG. 6 illustrates at least a part of a mobile device such as a mobile phone or a mobile game. Alternatively, the system SYS in FIG. 6 shows at least a part of a computer apparatus such as a video recorder or a personal computer.

  In the embodiment described later, the same system SYS as that in FIG. 6 is configured. The system SYS has a system-in-package SiP in which a plurality of chips are mounted on a package substrate such as a lead frame. Alternatively, the system SYS has a multi-chip package MCP in which a plurality of chips are stacked on a package substrate. Alternatively, the system SYS has a system-on-chip SoC in which a plurality of macros are integrated on a silicon substrate. Furthermore, the system SYS may be configured in the form of a chip-on-chip CoC, a package-on-package PoP, or a printed circuit board.

  For example, the SiP includes the semiconductor memory MEM shown in FIG. 1, the memory controller MCNT that accesses the semiconductor memory MEM, the flash memory FLASH, the memory controller FCNT that accesses the flash memory FLASH, and the CPU (main controller) that controls the entire system. Have. The CPU and the memory controllers MCNT and FCNT are connected to each other by a system bus SBUS. The SiP is connected to an upper system via an external bus SCNT. The clock signal CLK is generated inside the SiP and is supplied to the CPU, the memory controller MCNT, the semiconductor memory MEM, and the like. Note that the clock signal CLK may be supplied from the outside of the SiP.

  The CPU outputs a command signal (access request) and an address signal to perform a read operation of the semiconductor memory MEM, receives a read data signal from the semiconductor memory MEM, and the CPU performs a write operation of the semiconductor memory MEM. Therefore, a command signal, an address signal, and a write data signal are output. Further, the CPU outputs a command signal, an address signal, and a write data signal to FLASH or receives a read data signal from FLASH in order to perform a FLASH access operation (read operation, program operation or erase operation).

  The memory controller MCNT outputs a command signal CMD, an address signal AD, and a write data signal DQ to the semiconductor memory MEM based on a command signal, an address signal, and a write data signal from the CPU, and a read data signal DQ from the semiconductor memory MEM. Is output to the CPU. The memory controller FCNT operates in the same manner as the memory controller MCNT except that it outputs an address signal from the CPU to the data line DT. Note that the command signal CMD and the address signal AD for performing the read operation and the write operation of the semiconductor memory MEM may be directly output from the CPU to the semiconductor memory MEM without providing the memory controller MCNT in the system SYS. Further, the system SYS may have only a CPU and a semiconductor memory MEM.

  FIG. 7 shows a test system TSYS for testing the semiconductor memory MEM shown in FIG. In the embodiment described later, the same test system TSYS as in FIG. 7 is used.

  First, a plurality of semiconductor memories MEM are formed on a semiconductor wafer WAF by a semiconductor manufacturing process. The semiconductor memory MEM is tested by a test apparatus before being cut out from the wafer WAF. For example, the test apparatus is an LSI tester TEST. The LSI tester TEST supplies not only the control signals CMD, AD, DQ, and CLK but also the power supply voltage VDD and the ground voltage VSS.

  The semiconductor memory MEM is connected to the LSI tester TEST via a probe PRB of a probe card attached to the prober, for example. In the figure, one semiconductor memory MEM is connected to the LSI tester TEST, but a plurality of semiconductor memories MEM (for example, four, eight, or sixteen) may be connected to the LSI tester TEST at a time. The number of semiconductor memories MEM connected to the LSI tester TEST at a time depends on the number of terminals of the LSI tester TEST (the number of drivers and comparators) and the number of terminals of the memory MEM.

  The LSI tester TEST supplies a command signal CMD, an address signal AD, and a write data signal DQ to the memory MEM, and receives a read data signal DQ from the memory MEM. Note that the LSI tester TEST may be used to test the packaged memory MEM.

  FIG. 8 shows an example of the read operation in the normal operation mode of the semiconductor memory MEM shown in FIG. The semiconductor memory MEM is set to the DDR mode (SDRZ = low level L). The semiconductor memory MEM is set to have a burst length BL = 8 and a read latency RCL = 2.

  First, the active command ACTV and the row address signal RAD are supplied to the semiconductor memory MEM in synchronization with the first clock signal CLK (FIG. 8A). The semiconductor memory MEM activates the word line WL shown in FIG. 2 in response to the active command ACTV. The data held in the memory cell MC is read to the bit line BL (or / BL) by the activation of the word line WL and latched by the sense amplifier SA.

  Next, the read command RD and the column address signal CAD are supplied to the semiconductor memory MEM in synchronization with the third clock signal CLK (FIG. 8B). The column switch CSW is turned on in response to the upper column address signal CADU, and connects the bit line pair BL, / BL to the read amplifier RA. The read data is amplified by the read amplifier RA.

  In this example, the read amplifier RA latches 8-bit read data at a time for each data terminal DQ in response to the read command RD. Specifically, the read amplifier RA (E) corresponding to the memory block EV latches 4-bit read data ED0-3 for each data terminal DQ (FIG. 8 (c)). The read amplifier RA (O) corresponding to the memory block OV latches the 4-bit read data OD0-3 for each data terminal DQ (FIG. 8 (d)).

  In this example, the lower column address signal CADL2-1 supplied together with the read command RD is “00”. The internal address generation circuit ADGEN increases the column address signal CADL2-1 by 1 in synchronization with the rising edges of the fifth to seventh clock signals CLK. The read amplifier RA reads the read data corresponding to the lower column address signal CADL (CADL2-1) excluding the least significant bit in synchronization with the falling edges of the fourth to seventh clock signals CLK, and the internal data bus EDB, Output to ODB. Therefore, the read amplifier RA outputs the read data ED0 / OD0 to the internal data buses EDB and ODB in synchronization with the falling edge of the fourth clock signal CLK. Similarly, the read amplifier RA outputs the read data ED1 / OD1, ED2 / OD2, ED3 / OD3 to the internal data buses EDB, ODB in synchronization with the falling edges of the fifth to seventh clock signals CLK (see FIG. 8 (e)).

  The bus switching circuit 32 transmits read data on the internal data buses EDB and ODB to the internal data buses DBA and DBB, respectively (FIG. 8 (f)). In this example, the least significant bit CADL0 of the lower column address signal supplied together with the read command RD is “0”. Therefore, the clock signal CLKa is generated in synchronization with the rising edge of the clock signal CLK, and the clock signal CLKb is generated in synchronization with the falling edge of the clock signal CLK. The data multiplexer 30 transmits read data on the internal data bus DBA to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKa (FIG. 8 (g)). The data multiplexer 30 transmits the read data on the internal data bus DBB to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKb (FIG. 8 (h)). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge and falling edge of the clock signal CLK.

  FIG. 9 shows an example of the write operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. The semiconductor memory MEM is set to the DDR mode and the burst length BL = 8.

  In this example, a write command WR is supplied to the semiconductor memory MEM instead of the read command RD of FIG. The first write data ED0 is supplied to the external data bus EXTB via the data terminal DQ in synchronization with the rising edge of the clock signal CLK (fourth clock) next to the clock signal CLK to which the write command WR is supplied. (FIG. 9A). Thereafter, the write data OD0, ED1, OD1, ED2, OD2, ED3, and OD3 are sequentially supplied to the external data bus EXTB via the data terminal DQ in synchronization with the falling and rising edges of the clock signal CLK ( FIG. 9B).

  In this example, the least significant bit CADL0 of the lower column address signal supplied together with the write command WR is “0”. Therefore, the clock signal CLKa is generated in synchronization with the rising edge of the clock signal CLK, and the clock signal CLKb is generated in synchronization with the falling edge of the clock signal CLK1. The data multiplexer 30 transmits the write data ED0, ED1, ED2, and ED3 on the external data bus EXTB to the internal data bus DBA in synchronization with the rising edge of the clock signal CLKa (FIG. 9 (c)). Similarly, the data multiplexer 30 transmits the write data OD0, OD1, OD2, OD3 on the external data bus EXTB to the internal data bus DBB in synchronization with the rising edge of the clock signal CLKb (FIG. 9 (d)).

  The bus switching circuit 32 transmits the write data on the internal data buses DBA and DBB to the internal data buses EDB and ODB, respectively (FIG. 9 (e)). In this example, the lower column address signal CADL2-1 supplied together with the write command WR is “00”. The internal address generation circuit ADGEN increases the column address signal CADL2-1 by 1 in synchronization with the falling edges of the fourth to sixth clock signals CLK. The write amplifier WA (E) corresponding to the memory block EV sequentially latches data corresponding to the column address signal CADL2-1 among the write data transmitted to the internal data bus EDB (FIG. 9 (f)). The write amplifier WA (O) corresponding to the memory block OD sequentially latches data corresponding to the column address signal CADL2-1 among the write data transmitted to the internal data bus ODB (FIG. 9 (g)). The write data latched by the write amplifier WA is written to the memory cell MC via the column switch CSW and the bit line BL (/ BL).

  FIG. 10 shows another example of the read operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. The semiconductor memory MEM is set to the SDR mode, the burst length BL = 4, and the read latency RCL = 2. The operation up to the fourth clock cycle and the operation until the read amplifier RA latches 8-bit read data for each data terminal DQ are the same as those in FIG. 8 except that the clock signal CLK2 is not output.

  The read amplifier RA outputs read data corresponding to the column address signal CADL to the internal data bus EDB or ODB in synchronization with the falling edges of the fourth to seventh clock signals CLK. In this example, the least significant bit CADL0 of the lower column address signal supplied together with the read command RD is “0”. For this reason, the read amplifier RA outputs the first read data ED0 to the internal data bus EDB in synchronization with the falling edge of the fourth clock signal CLK (FIG. 10A). Thereafter, the read amplifier RA outputs the second read data OD0 to the internal data bus ODB in synchronization with the falling edge of the fifth clock signal CLK (FIG. 10B). Similarly, the read amplifier RA outputs the read data ED1 and OD1 to the internal data buses EDB and ODB in synchronization with the falling edges of the sixth and seventh clock signals CLK (FIG. 10 (c)).

  The bus switching circuit 32 transmits read data on the internal data buses EDB and ODB to the internal data buses DBA and DBB, respectively (FIG. 10 (d)). During the SDR mode, the switch SW7 that connects the internal data buses ODB and DBB to each other may be turned off to prohibit the read data from being transmitted to the internal data bus DBB.

  The data multiplexer 30 sequentially transmits the read data ED0, OD0, ED1, OD1 on the internal data bus DBA to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKa (FIG. 10 (e)). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge of the clock signal CLK.

  FIG. 11 shows another example of the write operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 9 are omitted. The semiconductor memory MEM is set to the SDR mode and the burst length BL = 4. The operation up to the rising edge of the third clock signal CLK is the same as that in FIG. 9 except that the clock signal CLK2 is not output.

  In the SDR mode, the write data ED0, OD0, ED1, and OD1 are sequentially supplied to the external data bus EXTB via the data terminal DQ in synchronization with the rising edges of the third to sixth clock signals CLK (FIG. 11). (A)). The data multiplexer 30 sequentially transmits the write data ED0, OD0, ED1, OD1 on the external data bus EXTB to the internal data bus DBA in synchronization with the rising edge of the clock signal CLKa (FIG. 11 (b)). For example, the semiconductor memory MEM includes a resistance element and a switch circuit that pulls down the internal data bus DBB in order to set the internal data bus DBB to a low level L during the SDR mode.

  The bus switching circuit 32 transmits write data on the internal data bus DBA to the internal data buses EDB and ODB, respectively (FIG. 11 (c)). In this example, the least significant bit CADL0 of the lower column address signal supplied together with the write command WR is “0”. Therefore, the write amplifier WA (E) corresponding to the memory block EV sequentially latches the write data transmitted to the internal data bus EDB in synchronization with the third and fifth clock signals CLK (FIG. 10 ( d)). The write amplifier WA (O) corresponding to the memory block OD sequentially latches the write data transmitted to the internal data bus ODB in synchronization with the fourth and sixth clock signals CLK (FIG. 10 (e)). . The write data latched by the write amplifier WA is written to the memory cell MC via the column switch CSW and the bit line BL (/ BL). The read operation and the write operation in the normal operation mode and the SDR mode shown in FIGS. 10 and 11 are also used when testing the semiconductor memory MEM as shown in FIG.

  When the lower column address signal CADL0 is “1”, the first write data is latched by the write amplifier WA (O) corresponding to the memory block OD. The next write data is latched by the write amplifier WA (E) corresponding to the memory block EV.

  FIG. 12 shows an example of the read operation in the test operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 10 are omitted. The semiconductor memory MEM is set to the SDR mode, the burst length BL = 4, and the read latency RCL = 2. The operation up to the fourth clock cycle and the operation until read data is transmitted from the read amplifier RA to the internal data buses EDB and ODB are the same as those in FIG. In this example, the least significant bit CADL0 of the lower column address signal supplied together with the read command RD is “0”. Therefore, the read amplifier RA outputs the first read data ED0 to the internal data bus EDB.

  In the test operation mode, the clock signal CLKb is generated in synchronization with the rising edge of the clock signal CLK (FIG. 12A). The clock signal CLKa is not generated. The bus switching circuit 32 transmits read data on the internal data buses EDB and ODB only to the internal data bus DBB (FIG. 12B). The data multiplexer 30 transmits the read data on the internal data bus DBB to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKb (FIG. 12C). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge of the clock signal CLK.

  In the test operation mode and the SDR mode, read data is transmitted to the data terminal DQ via a path including the internal data bus DBB. Thereby, it is possible to test the quality of the operation of the path including the internal data bus DBB and the circuit connected to the internal data bus DBB. In the write operation in the test operation mode and the SDR mode, the internal data bus DBB is used and the internal data bus DBA is not used, as in the read operation.

  FIG. 13 shows an example of a test flow of the semiconductor memory MEM shown in FIG. The test flow of FIG. 13 is performed using the test system TSYS shown in FIG. 7 in the manufacturing process of the semiconductor memory MEM. Specifically, the test of the semiconductor memory MEM is performed by the LSI tester TEST executing the test program and accessing the semiconductor memory MEM. Then, the semiconductor memory MEM is manufactured by performing the test flow.

  First, in process 100, the state of the semiconductor memory MEM is set to the normal operation mode (TMZ = low level) and the SDR mode (SDRZ = high level). Next, in process 102, a write operation is executed as shown in FIG. 11, and test data is written to the memory core 34. That is, the test data is stored in the memory cell MC. Next, in process 104, a read operation is executed as shown in FIG. 10, and test data is read from the memory cell MC. In the process 106, the read data is compared with the expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBA and the circuit connected to the internal data bus DBA is determined.

  Next, in process 108, the state of the semiconductor memory MEM is set to the test operation mode (TMZ = high level) and the SDR mode (SDRZ = high level). Next, in process 110, a read operation is performed as shown in FIG. 12, and test data is read from the memory cell MC. In the process 112, the read data is compared with the expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBB and the circuit connected to the internal data bus DBB is determined.

  The read operation of the process 104 serves not only for the operation test of the memory core 34 but also for the evaluation of the path including the internal data bus DBA and the circuit connected to the internal data bus DBA. The read operation of the process 110 serves not only for the operation test of the memory core 34 but also for the evaluation of the path including the internal data bus DBB and the circuit connected to the internal data bus DBB. By sequentially evaluating the data paths DBA and DBB of the semiconductor memory MEM using the SDR mode, the semiconductor memory MEM can be tested using the LSI tester TEST corresponding to the SDR mode. In other words, the semiconductor memory MEM can be tested without using an expensive LSI tester TEST corresponding to the DDR mode.

  As described above, in this embodiment, by selectively using the internal data buses DBA and DBB and supplying data to the external data bus EXTB, internal circuits and signal lines that are not used in the test can be eliminated. Since data is read from the memory cell array ARY using only one of the internal data buses DBA and DBB using the SDR mode, the semiconductor memory MEM can be tested at a low data transfer rate. As a result, the semiconductor memory MEM can be tested using an inexpensive LSI tester TEST, prober, or probe card, and the manufacturing cost of the semiconductor memory MEM can be reduced.

  In the semiconductor memory MEM having the DDR mode and the SDR mode, data is input / output using the internal data bus DBB not used in the SDR mode during the test operation mode. Thus, by testing the semiconductor memory MEM using the SDR mode and the test operation mode, it is possible to eliminate internal circuits and signal lines that are not used in the test.

  FIG. 14 shows a semiconductor memory MEM of another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. This semiconductor memory MEM is designed such that the ratio of the number of internal data buses DBA, DBB, DBC, DBD and the number of external data buses EXTB is 4: 1. As a result, the memory core 34A can be operated more slowly than in FIG. When the memory core 34A operates at a speed equivalent to that of the memory core 34 in FIG. 1, the input / output rate of the data signal DQ can be improved to twice that in FIG.

  The semiconductor memory MEM includes a mode setting circuit 16A, a clock generation circuit 22A, a clock instead of the mode setting circuit 16, the clock generation circuit 22, the clock switching circuit 24, the data multiplexer 30, the bus switching circuit 32, and the memory core 34 shown in FIG. It has a switching circuit 24A, a data multiplexer 30A, a bus switching circuit 32A, and a memory core 34A. Other configurations are the same as those in FIG.

  The mode setting circuit 16A has a function of outputting the normal mode signal NRMZ and the test mode signals TM2Z, TM3Z, TM4Z to the mode setting circuit 16 shown in FIG. Mode setting circuit 16A does not output test mode signal TMZ.

  The clock generation circuit 22A has a function of outputting internal clock signals CLK3 and CLK4 to the clock generation circuit 22 shown in FIG. The clock generation circuit 22A generates internal clock signals CLK1-4 in synchronization with the clock signal CLK. For example, the high level periods of the clock signals CLK1-4 do not overlap each other. The clock generation circuit 22A outputs only the clock CLK1 during the SDR mode (SDRZ = high level) and stops generating the clock CLK2-4.

  Clock switching circuit 24A outputs clock signals CLK1-4 as internal clock signals CLKa-d when normal mode signal NRMZ is at a high level (during the normal operation mode). The clock switching circuit 24A receives the least significant 2 bits of the column address signal CADU in order to set the generation order of the clock signals CLKa-d. For example, when the least significant 2 bits of the column address signal CADU are logic 0, the clock switching circuit 24A generates the clock signal CLKa in response to the read command RD or the write command WR, and then the clock signals CLKb, CLKc, CLKd. Generate ... When the least significant bit of the column address signal CADU is logic 1, the clock switching circuit 24A generates the clock signal CLKb in response to the read command RD or the write command WR, and then the clock signals CLKc, CLKd, CLKa,. Is generated.

  The clock switching circuit 24A generates only the clock CLKa and does not generate the clock signal CLKb-d during the SDR mode. When any of the test mode signals TM2Z, 3Z, 4Z is at a high level (during the test operation mode), the clock switching circuit 24A converts the clock signal CLK1 to the internal clock signal CLKb-d according to the logic level of the test mode signal TMZ. Output as one of the following.

  Data multiplexer 30A connects internal data bus DBA (DBA0-31) to external data bus EXTB in synchronization with clock signal CLKa. Data multiplexer 30 connects internal data buses DBB (DBB0-31), DBC (DBC0-31), and DBD (DBD0-31) to external data bus EXTB in synchronization with clock signals CLKb, CLKc, and CLKd, respectively. .

  In the normal operation mode (NRMZ = high level), the bus switching circuit 32A uses the internal data buses DB0, DB1, DB2, DB3 as internal data buses DBA, DBB, DBC when the mode signal SDRZ is low level (DDR mode). , Connect to the DBD. The internal data buses DB0, DB1, DB2, and DB3 each have 32 bits (DB00-031, DB10-131, DB20-231, and DB30-331). The internal data buses DBA, DBB, DBC, DBD also have 32 bits (DBA0-31, DBB0-31, DBC0-31, DBD-31), respectively. The data multiplexer 30A and the bus switching circuit 32A operate as a parallel / serial conversion circuit during a read operation, and operate as a serial / parallel conversion circuit during a write operation.

  Further, the bus switching circuit 32A connects the internal data buses DB0, DB1, DB2, DB3 to the internal data bus DBA when the mode signal SDRZ is at the high level (SDR mode) in the normal operation mode (NRMZ = high level). To do. That is, in the SDR mode, write data and read data are transmitted only to the internal data bus DBA. Each bit of the external data bus EXTB and the internal data buses DBA, DBB, ODB, EDB may have a single signal line or a complementary signal line. In the following description, it will be described as a single signal line.

  Furthermore, the bus switching circuit 32A connects the internal data bus DB0 to any of the internal data buses DBB, DBC, DBD in the test operation mode (any of TM2Z-4Z is at a high level). That is, in the test operation mode, write data and read data are transmitted to any of internal data buses DBB, DBC, DBD. In the test operation mode, data is input / output in synchronization with only the rising edge of the clock signal CLK, as in the SDR mode. As a result, the internal data buses DBB, DBC, DBD that are not used in the SDR mode and the circuits connected to the internal data buses DBB, DBC, DBD can be used during the test operation mode. In other words, the transmission path of data signals including the internal data buses DBB, DBC, DBD can be tested using the test operation mode. As a result, the test coverage indicating the ratio of signal paths to be tested can be improved, and the reliability of the semiconductor memory MEM can be improved.

  Each memory cell array ARY of the memory core 34A has four memory blocks BLK0-3. Each memory block BLK0-3 has a plurality of dynamic memory cells arranged in a matrix. The memory block BLK0 is selected when the lowest 2 bits of the column address signal CADL are “00”. Similarly, the memory blocks BLK1-3 are selected when the least significant two bits of the column address signal CADL are “01”, “10”, and “11”, respectively.

  Read amplifier RA and write amplifier WA corresponding to memory block BLK0 are connected to internal data bus DB00-031. The read amplifier RA and the write amplifier WA corresponding to the memory block BLK1 are connected to the internal data bus DB10-131. The read amplifier RA and the write amplifier WA corresponding to the memory block BLK2 are connected to the internal data bus DB20-231. The read amplifier RA and the write amplifier WA corresponding to the memory block BLK3 are connected to the internal data bus DB30-031.

  FIG. 15 shows an example of the clock switching circuit 24A shown in FIG. The clock switching circuit 24A has seven switch circuits SW21-27. For example, the switch circuit SW21-27 has a CMOS transfer gate.

  The switch circuits SW21, SW23, SW25, and SW27 labeled N are turned on when the normal mode signal NRMZ is at a high level. Thereby, during the normal operation mode, the clock signal lines CLKa, CLKb, CLKc, and CLKd are connected to the clock signal lines CLK1, CLK2, CLK3, and CLK4, respectively.

  The switch circuit SW22 is turned on when the test mode signal TM2Z is at a high level. As a result, the clock signal line CLKb is connected to the clock signal line CLK1. The switch circuit SW24 is turned on when the test mode signal TM3Z is at a high level. As a result, the clock signal line CLKc is connected to the clock signal line CLK1. The switch circuit SW26 is turned on when the test mode signal TM4Z is at a high level. As a result, the clock signal line CLKd is connected to the clock signal line CLK1. That is, any one of the switch circuits SW22, SW24, and SW26 with a symbol T is selectively turned on during the test operation mode.

  The clock switching circuit 24A includes a resistance element and a switch circuit for pulling down clock signal lines CLKa, CLKb, CLKc, and CLKd that are not used during the test operation mode. Note that a dummy transfer gate may be connected to the clock signal line CLKa in order to match the load of the clock signal line CLKa with the load of the clock signal line CLKb-d.

  FIG. 16 shows an example of the operation of the clock generation circuit 22A and the clock switching circuit 24A shown in FIG. In the normal operation mode and the DDR mode (NRMZ = high level, TM2Z-4Z = low level, SDRZ = low level), the clock signals CLK1-4 are sequentially generated in synchronization with the rising edge and falling edge of the clock signal CLK. The Clock signals CLKa-CLKd have the same phase as clock signals CLK1-4. The generation order of the clock signals CLK1-4 differs depending on the logic of the column address signal CADL.

  In the normal operation mode and the SDR mode (NRMZ = high level, TM2Z-4Z = low level, SDRZ = high level), only the clock signal CLKa is generated and generation of the clock signal CLKb-d is prohibited. In the test operation mode TMD (NRMZ = low level, one of TM2Z-4Z is high level, SDRZ = high level), one of the clock signals CLKb-d having the same phase as the clock signal CLK1 is generated.

  FIG. 17 shows an example of the bus switching circuit 32A shown in FIG. In FIG. 17, only the circuit corresponding to the data terminal DQ0 is shown. The bus switching circuit 32A corresponding to the data terminal DQ1-31 is also the same as FIG.

  The bus switching circuit 32A has seven switch circuits SW31-37, similarly to the clock switching circuit 24A shown in FIG. During the normal operation mode (NRMZ = high level), the internal data buses DBA0, DBB0, DBC0, DBD0 are connected to the internal data buses DB00, DB10, DB20, DB30, respectively. During the test operation mode (one of TM2Z-4Z is at high level), one of internal data buses DBA0, DBB0, DBC0, DBD0 is connected to internal data bus DB00 according to the logic level of test mode signal TM2Z-4Z Is done. In order to match the load of the internal data bus DBA0 with the load of the internal data buses DBB0, DBC0, DBD0, a dummy transfer gate may be connected to the internal data bus DBA0.

  During the SDR mode, the internal data buses DB00, DB10, DB20, and DB30 are connected to each other via the switch circuits SW38, 39, and 40. For example, the switch circuits SW38, 39, 40 have CMOS transfer gates. Thereby, for example, during the normal operation mode and the SDR mode, the read data on the internal data buses DB10, DB20, DB30 is also transmitted to the internal data bus DBA0. Write data on the internal data bus DBA0 is also transmitted to the internal data buses DB10, DB20, and DB30.

  FIG. 18 shows an example of the data multiplexer 30A shown in FIG. In FIG. 18, only the circuit corresponding to the data terminal DQ0 is shown. The data multiplexer 30A corresponding to the data terminal DQ1-31 is also the same as FIG.

  The data multiplexer 30A includes four switch circuits SW51-54 and a latch circuit LT1 that latches a data signal on the external data bus EDB0. For example, the switch circuits SW51-54 have a CMOS transfer gate. The switch circuit SW51 is turned on while the clock signal CLKa is at a high level. The switch circuit SW52 is turned on while the clock signal CLKb is at a high level. The switch circuit SW53 is turned on while the clock signal CLKc is at a high level. The switch circuit SW54 is turned on while the clock signal CLKd is at a high level.

  FIG. 19 shows an example of the read operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. In the normal operation mode, the normal mode signal NRMZ is set to a high level, and the test mode signals TM2Z-4Z are set to a low level. The semiconductor memory MEM is set to the DDR mode, the burst length BL = 8, and the read latency RCL = 2. The operation until the read command RD is supplied is the same as that in FIG. 8 except that the clock signals CLK1-4 are sequentially generated. Symbols CLKa-d attached to the clock signals CLK1-4 indicate that any one of the clock signals CLK1-d is generated in synchronization with each clock signal CLK1-4.

  For example, the read amplifier RA (0) corresponding to the read memory block BLK0 latches 2-bit read data D00-01 for each data terminal DQ (FIG. 19 (a)). Similarly, the read amplifiers RA (1)-(3) corresponding to the read memory blocks BLK1-3 latch the 2-bit read data D10-11, D20-21, D30-31 for each data terminal (FIG. 19). (B)). Read amplifiers RA (0)-(3) output read data D00, D10, D20, D30 to internal data buses DB0, DB1, DB2, DB3 in synchronization with the falling edge of the fourth clock signal CLK, respectively. (FIG. 19C).

  The read data that the read amplifier RA (0)-(3) first outputs to the internal data buses DB0, DB1, DB2, DB3 depends on the value of the lower third bit (CADL2) of the column address signal CADL. In this example, the value of the column address signal CADL2 supplied together with the read command RD is logic 0. Therefore, the read data D00, D10, D20, and D30 are output first in synchronization with the fifth clock signal CLK. When the value of the column address signal CADL2 is logic 1, read data D01, D11, D21, and D31 are output first. The bus switching circuit 32A transmits read data on the internal data buses DB0, DB1, DB2, and DB3 to the internal data buses DBA, DBB, DBC, and DBD, respectively (FIG. 19 (d)).

  In this example, the column address signal CADL1-0 supplied together with the read command RD is “00”. Therefore, the clock signals CLKa and CLKb are generated in synchronization with the rising edge and falling edge of the fifth clock signal CLK. Clock signals CLKc and CLKd are generated in synchronization with the rising and falling edges of the sixth clock signal CLK. Similarly, the clock signals CLKa-d are sequentially generated in the seventh and eighth clock cycles.

  The data multiplexer 30A sequentially transmits read data on the internal data buses DBA, DBB, DBC, DBD to the external data bus EXTB in synchronization with the rising edges of the clock signals CLKa-d (FIG. 19 (e)). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge and falling edge of the clock signal CLK.

  FIG. 20 shows an example of the write operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 9 and 19 are omitted. The semiconductor memory MEM is set to the DDR mode and the burst length BL = 8. The column address signal CADL2-0 supplied together with the write command WR is “000”.

  In this example, a write command WR is supplied to the semiconductor memory MEM instead of the read command RD of FIG. The first write data D00 is supplied to the external data bus EXTB via the data terminal DQ in synchronization with the rising edge of the clock signal CLK (fourth clock) next to the clock signal CLK to which the write command WR is supplied. (FIG. 20A). Thereafter, the write data D10, D20, D30, D01, D11, D21, and D31 are sequentially supplied to the external data bus EXTB via the data terminal DQ in synchronization with the falling and rising edges of the clock signal CLK ( FIG. 20 (b)).

  Data multiplexer 30A transmits write data D00 on external data bus EXTB to internal data bus DBA in synchronization with the rising edge of clock signal CLKa (FIG. 20 (c)). Similarly, data multiplexer 30A transmits write data D10, D20, D30 on external data bus EXTB to internal data buses DBB, DBC, DBD in synchronization with the rising edge of clock signal CLKb-d, respectively (FIG. 20). (D)).

  The bus switching circuit 32A transmits write data on the internal data buses DBA, DBB, DBC, DBD to the internal data buses DB0, DB1, DB2, DB3, respectively (FIG. 20 (e)). The write amplifier WA (0) corresponding to the memory block BLK0 latches the write data transmitted to the internal data bus DB0 (FIG. 10 (f)). The write amplifiers WA (0)-(3) corresponding to the memory blocks BLK1-3 sequentially latch the write data transmitted to the internal data buses DB1, DB2, DB3 (FIG. 20 (g)). The write data latched by the write amplifier WA is written to the memory cell MC via the column switch CSW and the bit line BL (/ BL).

  FIG. 21 shows another example of the read operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 10 and 19 are omitted. The semiconductor memory MEM is set to the SDR mode, the burst length BL = 4, and the read latency RCL = 2. The operation up to the fourth clock cycle and the operation until the read amplifier RA latches 8-bit read data for each data terminal DQ are the same as those in FIG. 19 except that the clock signal CLK2-4 is not output. . The column address signal CADL2-0 supplied together with the read command RD is “000”.

  Read amplifier RA outputs read data corresponding to column address signal CADL to internal data buses DB0, DB1, DB2, and DB3, respectively. In the SDR mode, the read amplifier RA outputs the read data D00 to the internal data bus DB0 in synchronization with the falling edge of the fourth clock signal CLK (FIG. 21 (a)). Similarly, the read amplifier RA outputs read data D10, D20, D30 to the internal data buses DB1, DB2, DB3 in synchronization with the falling edges of the fifth, sixth and seventh clock signals CLK, respectively ( FIG. 21 (b)).

  The bus switching circuit 32A transmits read data on the internal data bus DB0 to the internal data buses DBA, DBB, DBC, DBD (FIG. 21 (c)). The bus switching circuit 32A transmits read data on the internal data bus DB1 to the internal data buses DBA, DBB, DBC, DBD (FIG. 21 (d)). Read data on the internal data buses DB2 and DB3 is also transmitted to all the internal data buses DBA, DBB, DBC, and DBD (FIG. 21 (e)). In the normal operation mode and the SDR mode, only read data on the internal data bus DBA is connected to the external data bus EXTB. Therefore, the read data may be prohibited from being transmitted to the internal data buses DBB, DBC, DBD by turning off the switch circuits SW33, SW35, SW37 of FIG.

  The data multiplexer 30A transmits read data on the internal data bus DBA to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKa (FIG. 21 (f)). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge of the clock signal CLK.

  FIG. 22 shows another example of the write operation in the normal operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 11 and 20 are omitted. The semiconductor memory MEM is set to the SDR mode and the burst length BL = 4. The operation up to the rising edge of the third clock signal CLK is the same as that in FIG. 20 except that the clock signals CLK2-4 are not output. The column address signal CADL2-0 supplied together with the write command WR is “000”.

  In the SDR mode, the write data D00, D10, D20, and D30 are sequentially supplied to the external data bus EXTB via the data terminal DQ in synchronization with the rising edge of the clock signal CLK (FIG. 22 (a)). Data multiplexer 30A sequentially transmits write data D00, D10, D20, D30 on external data bus EXTB to internal data bus DBA in synchronization with the rising edge of clock signal CLKa (FIG. 22B). In order to set the internal data buses DBB, DBC, DBD to the low level L during the SDR mode, for example, the semiconductor memory MEM has a resistance element and a switch circuit for pulling down the internal data buses DBB, DBC, DBD. .

  The bus switching circuit 32A transmits write data on the internal data bus DBA to the internal data buses DB0, DB1, DB2, and DB3 (FIG. 22C). The write amplifier WA (0) corresponding to the memory block BLK0 latches the write data transmitted to the internal data bus DB0 in synchronization with the third clock signal CLK (FIG. 22 (d)). The write amplifier WA (1) corresponding to the memory block BLK1 latches the write data transmitted to the internal data bus DB1 in synchronization with the fourth clock signal CLK (FIG. 22 (e)). Similarly, the write amplifiers WA (2)-(3) corresponding to the memory blocks BLK2, BLK3 synchronize the write data transmitted to the internal data buses DB2, DB3 in synchronization with the third and fourth clock signals CLK. Latch (FIG. 22 (f)). The write data latched by the write amplifier WA is written to the memory cell MC via the column switch CSW and the bit line BL (/ BL).

  Note that the read operation and the write operation in the normal operation mode and the SDR mode shown in FIGS. 21 and 22 are also used when testing the semiconductor memory MEM as shown in FIG.

  FIG. 23 shows an example of the read operation in the test operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 12 and 21 are omitted. The semiconductor memory MEM is set to the SDR mode, the burst length BL = 4, and the read latency RCL = 2. The normal mode signal NRMZ is set to a low level. Test mode signal TM2Z is set to a high level, and test mode signals TM3Z and TM4Z are set to a low level. The column address signal CADL2-0 supplied together with the read command RD is “000”.

  The clock switching circuit 24A shown in FIG. 15 receives the high-level test mode signal TM2Z and outputs the clock signal CLK1 as the clock signal CLKb. The clock signals CLKa, CLKc, and CLKd are held at a low level by pull-down resistors. The operation up to the fourth clock cycle and the operation until read data is transmitted from the read amplifier RA to the internal data buses DB0 to DB3 are the same as those in FIG.

  The bus switching circuit 32A transmits read data on the internal data buses DB0 to DB3 only to the internal data bus DBB (FIG. 23 (a, b)). The data multiplexer 30A transmits read data on the internal data bus DBB to the external data bus EXTB in synchronization with the rising edge of the clock signal CLKb (FIG. 23 (c)). The read data transmitted to the external data bus EXTB is sequentially output from the data terminal DQ in synchronization with the rising edge of the clock signal CLK.

  In the test operation mode, when the test mode signal TM2Z is set to a high level, the read data is transmitted to the data terminal DQ through a path including the internal data bus DBB. Thereby, it is possible to test the quality of the operation of the path including the internal data bus DBB and the circuit connected to the internal data bus DBB. In the test operation mode, when the test mode signal TM3Z (or TM4Z) is set to a high level, the read data is transmitted to the data terminal DQ via a path including the internal data bus DBC (or DBD). . Thereby, it is possible to test the quality of the operation of the path including the internal data bus DBC (or DBD) and the circuit connected to the internal data bus DBC (or DBD). In the write operation in the test operation mode and the SDR mode, any of the internal data buses DBB, DBC, and DBD is used and the internal data bus DBA is not used, as in the read operation.

  FIG. 24 shows an example of a test flow of the semiconductor memory MEM shown in FIG. Detailed description of the same processing as in FIG. 13 is omitted. The test flow of FIG. 24 is performed using the test system TSYS shown in FIG. 7 in the manufacturing process of the semiconductor memory MEM. Specifically, the LSI tester TEST executes the test program and accesses the semiconductor memory MEM. Then, the semiconductor memory MEM is manufactured by performing the test flow.

  First, in the process 200, the state of the semiconductor memory MEM is set to the normal operation mode (NRMZ = high level, TM2Z-4Z = low level) and the SDR mode (SDRZ = high level). Next, in process 202, a write operation is executed as shown in FIG. 22, and test data is written into the memory cell MC. Next, in process 204, a read operation is performed as shown in FIG. 21, and test data is read from the memory cell MC. In process 206, the read data is compared with an expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBA is determined.

  Next, in the process 208, the state of the semiconductor memory MEM is set to the test operation mode (NRMZ = low level, TM2Z = high level, TM3Z-4Z = low level) and the SDR mode (SDRZ = high level). Next, in process 210, a read operation is performed as shown in FIG. 23, and test data is read from the memory cell MC. In process 212, the read data is compared with the expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBB is determined.

  Next, in process 214, the state of the semiconductor memory MEM is set to the test operation mode (NRMZ = low level, TM3Z = high level, TM2Z, 4Z = low level) and the SDR mode (SDRZ = high level). Next, in process 216, a read operation is executed as in FIG. 23, and test data is read from the memory cell MC. In process 218, the read data is compared with an expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBC is determined.

  Next, in the process 220, the state of the semiconductor memory MEM is set to the test operation mode (NRMZ = low level, TM4Z = high level, TM2Z-3Z = low level) and the SDR mode (SDRZ = high level). Next, in process 222, a read operation is executed in the same manner as in FIG. 23, and test data is read from the memory cell MC. In process 224, the read data is compared with an expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBD is determined.

  The read operation of the process 204 serves not only for the operation test of the memory core 34 but also for the evaluation of the path including the internal data bus DBA and the circuit connected to the internal data bus DBA. The read operation of the process 210 serves not only for the operation test of the memory core 34 but also for the evaluation of the path including the internal data bus DBB and the circuit connected to the internal data bus DBB. Similarly, the read operation of the processes 216 and 222 serves not only for the operation test of the memory core 34 but also for the evaluation of the paths including the internal data buses DBC and DBD and the circuits connected to the internal data buses DBC and DBD.

  By sequentially evaluating the data paths DBA, DBB, DBC, DBD of the semiconductor memory MEM using the SDR mode, the semiconductor memory MEM can be tested using the LSI tester TEST corresponding to the SDR mode. In other words, the semiconductor memory MEM can be tested without using an expensive LSI tester TEST corresponding to the DDR mode.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, even in a semiconductor memory MEM in which the ratio of the number of internal data buses DBA, DBB, DBC, DBD and the number of external data buses EXTB is 4 or more, it is possible to eliminate internal circuits and signal lines that are not used in the test. The manufacturing cost of MEM can be reduced.

  FIG. 25 shows a semiconductor memory MEM of another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor memory MEM operates in the DDR mode during the normal operation mode, and operates in the SDR mode during the test operation mode. As a result, the semiconductor memory MEM can be tested using the LSI tester TEST corresponding to the SDR mode.

  The semiconductor memory MEM includes a mode setting circuit 16B, a clock generation circuit 22B, a clock switching circuit 24B, and a bus switching circuit 32B instead of the mode setting circuit 16, the clock generation circuit 22, the clock switching circuit 24, and the bus switching circuit 32 shown in FIG. have. Other configurations are the same as those in FIG.

  The mode setting circuit 16B has a function of outputting the test mode signal TM1Z-2Z except for the function of outputting the mode signal SDRZ from the mode setting circuit 16 of FIG. One of the test mode signals TM1Z-2Z is set to a high level during the test operation mode. While test mode signal TM1Z is at a high level, a test is performed using internal data bus DBA (DBA0-31). While test mode signal TM2Z is at a high level, a test is performed using internal data bus DBB (DBB0-31). The semiconductor memory MEM operates in the DDR mode when both the test mode signals TM1Z-2Z are at a low level. The semiconductor memory MEM operates in the SDR mode when any one of the test mode signals TM1Z-2Z is at a high level.

  The clock generation circuit 22B outputs the internal clock signal CLK1 synchronized with the clock signal CLK and the internal clock signal CLK2 obtained by inverting the phase of the clock signal CLK without receiving the mode signal SDRZ of FIG. When both test mode signals TM1Z-2Z are at a low level (normal operation mode), clock switching circuit 24B outputs internal clock signal CLK1 as internal clock signal CLKa and outputs internal clock signal CLK2 as internal clock signal CLKb. When the test mode signal TM1Z is high and the test mode signal TM2Z is low (test operation mode), the clock switching circuit 24B outputs the internal clock signal CLK1 as the internal clock signal CLKa and generates the internal clock signal CLKb. Stop. When the test mode signal TM2Z is high and the test mode signal TM1Z is low (test operation mode), the clock switching circuit 24B outputs the internal clock signal CLK2 as the internal clock signal CLKb and generates the internal clock signal CLKa. Stop.

  The bus switching circuit 32B connects the internal data bus ODB (ODB0-31) to the internal data bus DBB (DBB0-31) when the test mode signal TM1Z is at a low level. The bus switching circuit 32B connects the internal data bus ODB (ODB0-31) to the internal data bus DBA (DBA0-31) when the test mode signal TM1Z is at a high level. The bus switching circuit 32B connects the internal data bus EDB (EDB0-31) to the internal data bus DBA (DBA0-31) when the test mode signal TM2Z is at a low level. The bus switching circuit 32B connects the internal data bus EDB (EDB0-31) to the internal data bus DBB (DBB0-31) when the test mode signal TM2Z is at a high level.

  FIG. 26 shows an example of the clock switching circuit 24B shown in FIG. The clock switching circuit 24B has three switch circuits SW61-63 that are turned on or off in response to the test mode signal TM1Z-2Z. For example, the switch circuits SW61-63 have a CMOS transfer gate. The switch circuit SW61 is turned on when the test mode signal TM2Z is at a low level and turned off when the test mode signal TM2Z is at a high level. The switch circuit SW62 is turned on when both of the test mode signals TM1Z-2Z are at a low level, and turned off when any of the test mode signals TM1Z-2Z is at a high level. The switch circuit SW63 is turned on when the test mode signal TM2Z is at a high level and turned off when the test mode signal TM2Z is at a low level. When switch circuit SW63 is on, a clock signal obtained by inverting clock signal CLK2 is transmitted as clock signal CLKb.

  During the normal operation mode (TM1Z-2Z = low level), the switches SW61-62 are turned on, and the clock signals CLK1, CLK2 are output as the clock signals CLKa, CLKb, respectively. During the test operation mode (TM1Z = high level, TM2Z = low level), only the switch SW61 is turned on and the clock signal CLK1 is output as the clock signal CLKa. Generation of the clock signal CLKb is prohibited. The clock signal line CLKb is connected to, for example, a pull-down circuit and maintained at a low level when the test mode signal TM1Z-2Z is at a high level and a low level, respectively. Further, during the test operation mode (TM1Z = low level, TM2Z = high level), only the switch circuit SW63 is turned on, and an inverted signal of the clock signal CLK2 is output as the clock signal CLKb. Generation of the clock signal CLKa is prohibited. The clock signal line CLKa is connected to, for example, a pull-down circuit and maintained at a low level when the test mode signal TM1Z-2Z is at a low level and a high level, respectively.

  FIG. 27 shows an example of the bus switching circuit 32B and the data multiplexer 30 shown in FIG. FIG. 27 shows only a circuit corresponding to the data terminal DQ0. The bus switching circuit 32B and the data multiplexer 30 corresponding to the data terminals DQ1-31 are also the same as in FIG. The data multiplexer 30 is the same as in FIG.

  The bus switching circuit 32B has four switch circuits SW71-74. For example, the switch circuits SW71-74 have a CMOS transfer gate. The CMOS transfer gate labeled N is turned on during the normal operation mode (TM1Z-2Z = low level). Any of the CMOS transfer gates labeled T is turned on during the test operation mode (TM1Z = high level or TM2Z = high level).

  FIG. 28 shows an example of the read operation in the test operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 10 are omitted. Note that the operation in the normal operation mode (DDR mode) is the same as in FIGS.

  The semiconductor memory MEM has a burst length BL = 4 and a read latency RCL = 2. Test mode signal TM1Z is set to a high level, and test mode signal TM2Z is set to a low level. When the test mode signal TM1Z is at a high level, the semiconductor memory MEM operates in the SDR mode. The column address signal CADL2-0 supplied together with the read command RD is “000”.

  In this embodiment, the switch circuits SW71 and 74 shown in FIG. 27 are turned on, and the switch circuits SW72 and 73 are turned off. Thus, the read data ED0, OD0, ED1, and OD1 read from the read amplifier RA to the internal data buses EDB and ODB are transferred only to the internal data bus DBA. That is, the test of the semiconductor memory MEM is performed using only the internal data bus DBA in the SDR mode. Other operations are the same as those in FIG.

  FIG. 29 shows another example of the read operation in the test operation mode of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 12 are omitted. The semiconductor memory MEM has a burst length BL = 4 and a read latency RCL = 2. Test mode signal TM1Z is set to a low level, and test mode signal TM2Z is set to a high level. When the test mode signal TM2Z is at a high level, the semiconductor memory MEM operates in the SDR mode. The column address signal CADL2-0 supplied together with the read command RD is “000”.

  In this embodiment, the switch circuits SW72 and 73 shown in FIG. 27 are turned on, and the switch circuits SW71 and 74 are turned off. As a result, the read data ED0, OD0, ED1, and OD1 read from the read amplifier RA to the internal data buses EDB and ODB are transferred only to the internal data bus DBB. That is, the test of the semiconductor memory MEM is performed using only the internal data bus DBB in the SDR mode. The operation of FIG. 29 is the same as that of FIG.

  FIG. 30 shows an example of a test flow of the semiconductor memory MEM shown in FIG. The semiconductor memory MEM is manufactured by performing the test flow. Detailed description of the same processing as in FIG. 13 is omitted. 30 is performed using the test system TSYS shown in FIG. 7 in the manufacturing process of the semiconductor memory MEM.

  First, in the process 300, the state of the semiconductor memory MEM is set to the first test operation mode (TM1Z = high level, TM2Z = low level). Next, in processes 302 and 304, a write operation and a read operation are executed. The processes 302 and 304 are the same as the processes 102 and 104 shown in FIG. However, the write data is written into the memory cell MC using only the internal data bus DBA. Next, in process 306, the read data is compared with an expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBA is determined.

  Next, in process 308, the state of the semiconductor memory MEM is set to the second test operation mode (TM1Z = low level, TM2Z = high level). Next, in process 310, a read operation is performed. The process 310 is the same as the process 110 shown in FIG. Next, in process 312, the read data is compared with an expected value, and the quality of the semiconductor memory MEM including the quality of the internal data bus DBB is determined.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in the semiconductor memory MEM having only the DDR mode as the normal operation mode, the test can be performed in the SDR mode by using the internal data buses DBA and DBB alternately. Therefore, when the test is performed at a low data transfer rate, internal circuits and signal lines that are not used can be eliminated. As a result, the test cost can be reduced and the manufacturing cost of the semiconductor memory MEM can be reduced.

  The embodiment described above has been described with respect to an example applied to a DDR-SDRAM. However, for example, the above-described embodiment may be applied to other semiconductor memories such as a DDR-SRAM and a DDR pseudo SRAM. At this time, the semiconductor memory has a function of operating in the SDR mode at least during the test operation mode.

  In the above-described embodiment, the example in which the test operation mode is set using the test mode signal TMZ or TM1Z-4Z output from the mode setting circuit 16, 16A, or 16B has been described. However, for example, the semiconductor memory MEM may be set to the test operation mode by supplying the test mode signal TMZ or TM1Z-4Z from the LSI tester TEST or the like via the external terminal. Alternatively, the test mode signal TMZ or TM1Z-4Z may be generated using a program circuit such as a fuse circuit. For example, in FIG. 1, a high-level test mode signal TMZ is output from the program circuit before the program circuit is programmed. After the program circuit is programmed (after the fuse is cut), a low-level test mode signal TMZ is output from the program circuit. Processes 108 to 112 shown in FIG. 13 are performed before programming of the program circuit. After the program circuit is programmed, processes 100 to 106 shown in FIG. 13 are performed.

The following additional notes are disclosed with respect to the embodiment shown in FIGS.
(Appendix 1)
A memory cell array;
A plurality of internal data buses greater than the number of external data buses, the internal data bus including a first internal data bus and a second internal data bus;
A data input / output circuit that inputs data to the memory cell array or outputs data read from the memory cell array;
The data input / output circuit is
A plurality of first selection circuits for selectively supplying data from the memory cell array to the first internal data bus or the second internal data bus;
A second selection circuit for switching the first internal data bus or the second internal data bus to connect to the external data bus;
A semiconductor memory comprising: a third selection circuit that selectively supplies a first clock signal or a second clock signal based on a test mode signal.
(Appendix 2)
The first clock signal operates the first internal data bus;
The second clock signal operates the second internal data bus;
The semiconductor memory according to appendix 1, wherein the second clock signal is an inverted signal of the first clock signal.
(Appendix 3)
The second selection circuit includes:
A first transfer gate for connecting the first internal data bus to the external data bus;
The semiconductor memory according to appendix 1 or appendix 2, wherein the semiconductor memory has a second transfer gate for connecting the second internal data bus to the external data bus.
(Appendix 4)
The first selection circuit includes:
The semiconductor memory according to appendix 1, appendix 2 or appendix 3, wherein data from the memory cell array is supplied to the first internal data bus or the second internal data bus based on the test mode signal.
(Appendix 5)
The semiconductor memory according to appendix 1, appendix 2, appendix 3 or appendix 4, further comprising a test mode setting circuit for supplying the test mode signal to the third selection circuit.
(Appendix 6)
The semiconductor memory according to appendix 1, appendix 2, appendix 3, appendix 4 or appendix 5, wherein the semiconductor memory is a DDR memory.
(Appendix 7)
In a semiconductor memory comprising a data input / output circuit for outputting data from a plurality of internal data buses to the external data bus greater than the number of external data buses, and inputting data from the external data bus to the plurality of internal data buses,
During normal operation, a first path for outputting the first data from the first internal data bus to the external data bus based on the first clock signal and a second internal data bus based on the second clock signal A second path for outputting to the external data bus from
In a test operation, the first data is output to the external data bus using the second path.
(Appendix 8)
The semiconductor memory according to appendix 7, wherein the second clock signal is an inverted signal of the first clock signal.
(Appendix 9)
The first data is stored in a first area of the memory cell array;
The second data is stored in a second region of the memory cell array;
9. The semiconductor memory according to appendix 7 or appendix 8, wherein the first data and the second data are output to the external data bus via the second internal data bus during the test operation.
(Appendix 10)
The semiconductor memory according to appendix 7, appendix 8, or appendix 9, wherein the semiconductor memory is a DDR memory.
(Appendix 11)
Storing first data in a first area of the memory cell array and storing second data in a second area of the memory cell array;
The first data and the second data are supplied to a first internal data bus based on a test signal, and the first data and the second data are based on a first clock signal corresponding to the first internal data bus. 2 data to the external data bus,
The first data and the second data are supplied to a second internal data bus based on a test signal, and the first data and the second data are based on a second clock signal corresponding to the second internal data bus. 2 data to the external data bus,
A semiconductor memory having the memory cell array is generated by performing a test in which the first data and the second data are output from the first internal data bus and the second data bus to the external data bus. A method for manufacturing a semiconductor memory.
(Appendix 12)
The method of manufacturing a semiconductor memory according to appendix 11, wherein the second clock signal is an inverted signal of the first clock signal.
(Appendix 13)
The number of the internal data buses is larger than the number of the external data buses. The method of manufacturing a semiconductor memory according to appendix 11 or appendix 12.

  From the above detailed description, features and advantages of the embodiment will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

1 illustrates a semiconductor memory in one embodiment. An example of the memory core shown in FIG. 1 is shown. An example of the clock switching circuit shown in FIG. 1 is shown. 2 shows an example of the operation of the clock generation circuit and the clock switching circuit shown in FIG. An example of the bus switching circuit and the data multiplexer shown in FIG. 1 is shown. 2 shows a system in which the semiconductor memory shown in FIG. 1 is mounted. 2 shows a test system for testing the semiconductor memory shown in FIG. 2 shows an example of a read operation in the normal operation mode of the semiconductor memory shown in FIG. 2 shows an example of a write operation in the normal operation mode of the semiconductor memory shown in FIG. 6 shows another example of the read operation in the normal operation mode of the semiconductor memory shown in FIG. 6 shows another example of the write operation in the normal operation mode of the semiconductor memory shown in FIG. 2 shows an example of a read operation in the test operation mode of the semiconductor memory shown in FIG. 2 shows an example of a test flow of the semiconductor memory shown in FIG. 3 illustrates another embodiment of a semiconductor memory. An example of the clock switching circuit shown in FIG. 14 is shown. 15 illustrates an example of operations of the clock generation circuit and the clock switching circuit illustrated in FIG. 14. An example of the bus switching circuit shown in FIG. 14 is shown. An example of the data multiplexer shown in FIG. 14 is shown. 15 shows an example of a read operation in the normal operation mode of the semiconductor memory shown in FIG. 15 shows an example of a write operation in the normal operation mode of the semiconductor memory shown in FIG. 15 shows another example of the read operation in the normal operation mode of the semiconductor memory shown in FIG. 15 shows another example of the write operation in the normal operation mode of the semiconductor memory shown in FIG. 15 shows an example of a read operation in the test operation mode of the semiconductor memory shown in FIG. 15 shows an example of a test flow of the semiconductor memory shown in FIG. 3 illustrates another embodiment of a semiconductor memory. An example of the clock switching circuit shown in FIG. 25 is shown. An example of the bus switching circuit and the data multiplexer shown in FIG. 25 is shown. 26 shows an example of a read operation in the test operation mode of the semiconductor memory shown in FIG. 26 shows another example of the read operation in the test operation mode of the semiconductor memory shown in FIG. 26 shows an example of a test flow of the semiconductor memory shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Command input buffer; 12 ... Command decoder; 14 ... Core control circuit; 16, 16A, 16B ... Mode setting circuit; 18 ... Address input buffer; 20 ... Address latch circuit; , 24A, 24B, clock switching circuit; 26, data input buffer; 28, data output buffer; 30, 30A, data multiplexer, 32, 32A, 32B, bus switching circuit; 34, 34A, memory core; CDEC, column decoder; CLK1, CLK2, CLK3, CLK4, internal clock signal; CLKa, CLKb, CLKc, CLKd, internal clock signal; DB0, DB1, DB2, DB3, internal data bus; DBA, DBB, DBC, DBD, internal Data bus: EDB Part data bus; EXTB ‥ external data bus; ODB ‥ internal data bus; RA ‥ read amplifier; SAA ‥ sense amplifier region; WA ‥ write amplifier; WDEC ‥ word decoder

Claims (5)

A memory cell array;
A plurality of internal data buses greater than the number of external data buses, the internal data bus including a first internal data bus and a second internal data bus;
A data input / output circuit that inputs data to the memory cell array or outputs data read from the memory cell array;
The data input / output circuit is
A plurality of first selection circuits for selectively supplying data from the memory cell array to the first internal data bus or the second internal data bus;
A second selection circuit for switching the first internal data bus or the second internal data bus to connect to the external data bus;
A semiconductor memory comprising: a third selection circuit that selectively supplies a first clock signal or a second clock signal based on a test mode signal. The first clock signal operates the first internal data bus;
The second clock signal operates the second internal data bus;
The semiconductor memory according to claim 1, wherein the second clock signal is an inverted signal of the first clock signal. In a semiconductor memory comprising a data input / output circuit for outputting data from a plurality of internal data buses to the external data bus greater than the number of external data buses, and inputting data from the external data bus to the plurality of internal data buses,
During normal operation, a first path for outputting the first data from the first internal data bus to the external data bus based on the first clock signal and a second internal data bus based on the second clock signal A second path for outputting to the external data bus from
In a test operation, the first data is output to the external data bus using the second path. The semiconductor memory according to claim 3, wherein the second clock signal is an inverted signal of the first clock signal. Storing first data in a first area of the memory cell array and storing second data in a second area of the memory cell array;
The first data and the second data are supplied to a first internal data bus based on a test signal, and the first data and the second data are based on a first clock signal corresponding to the first internal data bus. 2 data to the external data bus,
The first data and the second data are supplied to a second internal data bus based on a test signal, and the first data and the second data are based on a second clock signal corresponding to the second internal data bus. 2 data to the external data bus,
A semiconductor memory having the memory cell array is generated by performing a test in which the first data and the second data are output from the first internal data bus and the second data bus to the external data bus. A method for manufacturing a semiconductor memory.

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