JP2010068415A - Pulse width modulation waveform generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a PWM waveform signal without being delayed for change of a duty value by adopting a delay counter to dead time generation and to generate the PWM waveform signal of full duty even by a dead time generation method using the delay counter. <P>SOLUTION: Three single direction counters, a first counter (22), a second counter (23), and a third counter (32) are used, triangle carrier wave is generated by counting signals of the first counter (22) and the second counter (23), these counted values are compared with a target duty value, when a high side PWM signal GH and a low side PWM signal GL are generated or updated, a complementary type PWM waveform signal by which full duty output is possible having dead time conforming to change of the target duty value is generated by a pulse width modulation (PWM) waveform generator of configuration of generating the dead time using the third counter (32). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pulse width modulation (Pulse Width Modulator, hereinafter referred to as PWM) waveform generator.

  As shown in FIG. 18, a three-phase motor (50 using a so-called star connection coil structure in which one ends of a U-phase coil (51), a V-phase coil (52), and a W-phase coil (53) are connected to each other. The PWM inverter (60) is generally used to control the excitation current of the rotor (not shown) of the motor. The PWM inverter (60) is composed of six power transistors (62, 63, 62, 63, 62). 63) and a PWM waveform generator (90) for controlling on / off of the six power transistors (62, 63, 62, 63, 62, 63) of the power module (61). Composed.

  In the power module (61), three arm portions (64) in which two power transistors (62, 63) are connected in series are arranged in parallel, and an intermediate point a of the three arm portions (64), The other ends of the U-phase coil (51), the V-phase coil (52), and the W-phase coil (53) are connected to b and c, respectively. Controlling on / off of the six power transistors (62, 63, 62, 63, 62, 63) connected to the U-phase coil (51), V-phase coil (52), and W-phase coil (53) Thus, the current flowing through the U-phase coil (51), the V-phase coil (52), and the W-phase coil (53) is controlled, and the rotational torque and rotational speed of the rotor (not shown) of the three-phase motor (50) are controlled. Is done.

  When controlling on or off of the six power transistors (62, 63, 62, 63, 62, 63), the high side transistor (62) and the low side transistor (63) of one arm portion (64) are simultaneously turned on. When turned on (called an arm short circuit), the power supply 70 and the ground 80 are short-circuited, and an overcurrent flows through the high-side transistor (62) and the low-side transistor (63). This causes damage to the low-side transistor (63). Therefore, until the low-side transistor (63) is turned on after the high-side transistor (62) is turned off, or until the high-side transistor (62) is turned on after the low-side transistor (63) is turned off. In order to prevent an arm short circuit, it is necessary to provide a so-called dead time for turning off both the high-side transistor (62) and the low-side transistor (63).

  FIG. 19 shows a timing chart for explaining a method of generating a complementary PWM signal having a dead time by the most general PWM waveform generator (90). The method shown in FIG. 19 uses a bidirectional counter capable of performing an operation of “increasing the count value sequentially” (hereinafter referred to as increment) or an operation of “decreasing the count value sequentially” (hereinafter referred to as decrement). Then, the triangular carrier wave signal formed by the count value is compared with the duty value, and a signal for turning on or off the high side transistor (62) based on the comparison result (hereinafter referred to as the high side PWM signal GH) And a signal for turning on or off the low-side transistor (63) (hereinafter referred to as a low-side PWM signal GL) and switching from turning on the high-side transistor (62) to turning on the low-side transistor (63) This is a method of preventing an arm short circuit by using a delay circuit for generating the dead time. In FIG. 19, it is assumed that the PWM waveform generator (90) is configured by a digital circuit, but the PWM waveform generator (90) that realizes the same function can also be configured by an analog circuit.

  In FIG. 19, the bidirectional counter alternately repeats the increment operation and the decrement operation by a clock signal (not shown) and the count direction signal DIR to form a triangular carrier wave with the count value of the bidirectional counter, and the count value ud_cnt of the bidirectional counter The duty values duty are compared, and it is shown that a CMP signal (CMP = 1) is generated when they match (duty = ud_cnt). In this example, the bidirectional counter increments with DIR = 0 and decrements with DIR = 1.

  FIG. 19 shows an example in which a unidirectional counter that performs only a decrement operation (hereinafter referred to as a delay counter and its count value is DTcnt) is used as the delay circuit. When the CMP signal is generated, a count value td corresponding to a predetermined dead time is set as an initial value in the delay counter (DTcnt = td), and a decrement operation is started. When the delay counter counts up (DTcnt = 0), a CMPdly signal (CMPdly = 1) is generated. Based on the DIR signal, the CMP signal, and the CMPdly signal, complementary PWM waveform signals (high-side PWM signal GH, low-side PWM signal GL) having a dead time are generated.

  At time t1 and t3 in FIG. 19, since the CMP signal is generated when DIR = 0, the high-side PWM signal GH is set to “0” and the delay counter starts the decrement operation from the count value DTcnt = td. When the delay counter counts up and the CMPdly signal is generated, the low-side PWM signal GL is set to “1” and the operation of the delay counter is stopped. That is, when the delay time corresponding to the count value td has elapsed since the high-side PWM signal GH is set to “0”, the low-side PWM signal GL is set to “1” and the operation of the delay counter is stopped.

  Further, at time t2 and t4 in FIG. 19, since the CMP signal is generated when DIR = 1, the low-side PWM signal GL is set to “0” and the delay counter is started to decrement from DTcnt = td. When the delay counter counts up and the CMPdly signal is generated, the low-side PWM signal GH is set to “1” and the operation of the delay counter is stopped. That is, after the low side PWM signal GL is set to “0”, when the delay time corresponding to the count value td has elapsed, the high side PWM signal GH is set to “1” and the operation of the delay counter is stopped.

  Thus, the high side transistor (62) is turned on after the high side transistor (62) is turned off until the low side transistor (63) is turned on, or after the low side transistor (63) is turned off. It is possible to provide a dead time before turning on.

  In the example of FIG. 19, when the duty value duty matches the count value ud_cnt of the bidirectional counter (duty = ud_cnt), CMP = 1 is generated and the delay counter is operated at the same time. = 1 is generated, but the duty value duty is compared with the count value ud_cnt of the bidirectional counter, and when the comparison result changes, CMP = 1 is generated based on the comparison result, Activate the delay counter. By doing so, it is possible to output a complementary PWM waveform signal that responds quickly to changes in the duty value duty. Examples thereof are shown at time t1 in FIG. 20 and time t1 in FIG.

  In the method of generating the dead time using such a delay circuit, the dead time is generated even when the duty is 0% or 100%, so that a so-called full-duty PWM waveform signal cannot be generated.

  On the other hand, there is an invention relating to a PWM waveform generator having a dead time and capable of full duty (see Patent Document 1). In the complementary PWM waveform signal, the present invention always has a dead time (no overlap time) at the time of switching between the high-side PWM signal GH and the low-side PWM signal GL, and the duty value ranges from 0% to 100% ( Complementary PWM waveform output capable of full duty output is performed.

  FIG. 22 shows a timing chart for explaining a method for generating a PWM signal of the PWM waveform generator of the present invention. At the same time, the increment operation and the decrement operation are alternately repeated, and two bidirectional counters TCNT3 and TCNT4 having a time difference corresponding to the dead time, a high count value region (Tb1 between TCDR and TGR3) and a low count region (zero and TDDR) During the interval Tb2), the increment and decrement operations are performed only. Otherwise, the count counter TCNTS is used to stop the count. The contents of the TGR4 register storing the duty value and the count values of the three bidirectional counters are respectively used. In comparison, based on the comparison result, a normal phase output signal GH corresponding to the high side PWM signal and a negative phase output signal GL corresponding to the low side PWM signal are generated.

  In this way, the dead time is generated using the two bidirectional counters having a time difference corresponding to the dead time. In the timing chart, the line representing the count value of the two bidirectional counters and the duty value line are arranged in the horizontal direction. The duty value must be maintained during the crossing time, i.e., the dead time period. That is, when the contents of the TGR4 register in which the duty value is stored is changed, an apparent vertical line of TGR4 is generated in the timing chart, and this crosses the count value line of the bidirectional counter. This is because a predetermined dead time cannot be generated.

  Therefore, even if the duty value is changed, it is not immediately set in the TGR4 register, but is temporarily stored in another register Temp_R (not shown), and transferred from the Temp_R register to the TGR4 register at an appropriate timing. It is configured as follows. The transfer timing is the end of the Tb1 section in FIG. 22, or the end of the Tb1 and Tb2 sections. Nevertheless, if the duty value is changed within the interval between Tb1 and Tb2, the changed duty value is stored in the Temp_R register and transferred to the TGR4 register from the Temp_R register at the end of those periods. The PWM waveform signal may not be generated.

Therefore, those periods are defined as Temp_R prohibited sections, and another register BR (not shown) is provided, and the duty value changed in the Temp_R prohibited sections is temporarily stored in the BR register, and at the end of the Temp_R prohibited section, The contents of the Temp_R register are transferred to the TGR4 register, and the contents of the BR register are transferred to the Temp_R register. In the other ta section, when the duty value is changed, the duty value is stored in the Temp_R register at the same time as being stored in the BR register. As a result, the register for storing the duty value has a three-layer structure, and a PWM waveform signal delayed with respect to the change of the duty value is generated.
JP-A-8-263104 (Renesas)

<< Problems of general PWM waveform generator >>
In the dead time generation method using a delay counter adopted in the most general PWM waveform generator (90), the duty value is in the vicinity of the upper limit value (duty 100%) and the lower limit value (duty 0%), There is a problem that a PWM waveform signal having a desired duty cannot be generated. This will be described below with reference to FIGS. 20 and 21. FIG.

  FIG. 20 is a timing chart for explaining a method of generating a PWM waveform signal when the duty value duty is set to the lower limit value 0 (zero). When duty = 0 (duty 0%) is set, the low-side PWM signal GL is always set to “1” and the low-side transistor is continuously turned on. That is, it is desired to eliminate the time when the low-side PWM signal GL is “0”.

  However, at time t2 (t3) in FIG. 20, when duty = ud_cnt = 0 and CMP = 1 is generated, the low-side PWM signal GL once becomes “0”, and the low-side transistor is turned off. At the same time, the delay counter starts a decrement operation from the count value DTcnt = td (dead time value). When the delay counter counts up (DTcnt = 0) and CMPdly = 1 is generated, the operation of the delay counter is stopped and the low side PWM signal GL is set to “1” again to turn on the low side transistor. To. Therefore, even when duty = 0 (duty 0%), the low-side PWM signal GL outputs “0” for the delay time (dead time), and a time for turning off the low-side transistor occurs. That is, the low-side PWM signal GL cannot always be set to “1” and the low-side transistors cannot be continuously turned on.

  FIG. 21 is a timing chart for explaining a PWM waveform signal generated when the duty value duty is set to the upper limit value Tph (a value corresponding to a half cycle of a triangular carrier wave). When duty = Tph (duty 100%) is set, the high-side PWM signal GH is always set to “1” and the high-side transistor is continuously turned on. That is, it is desired to eliminate the time when the high-side PWM signal GH is “0”.

  However, at time t2 (t3) in FIG. 21, when duty = ud_cnt = Tph and CMP = 1 is generated, the high-side PWM signal GH once becomes “0”, and the delay counter counts from the count value DTcnt = td. Start decrement operation. When the delay counter counts up (DTcnt = 0) and CMPdly = 1 is generated, the operation of the delay counter is stopped and the high-side PWM signal GH is set to “1” again. Therefore, even when duty = Tph (duty 100%), the high-side PWM signal GH outputs “0” only for the delay time (dead time value td), and a time for turning off the high-side transistor occurs. That is, the high-side PWM signal GH cannot always be set to “1” and the high-side transistor cannot be continuously turned on.

  As described above, the method using the bidirectional counter that forms the triangular carrier wave and the delay counter that generates the dead time cannot generate the high-side PWM signal GH and the low-side PWM signal GL corresponding to the duty from 0% to 100%. Therefore, there is a problem that a full-duty PWM waveform signal cannot be output.

  In the PWM waveform generator described in Patent Document 1, in order to generate a dead time, a time difference (corresponding to a dead time) of any two bidirectional counters among three bidirectional counters is used. Duty values to be compared with those count values must be set at an appropriate timing. For this reason, the register for storing the duty value has a three-layer structure, and a delay of about one cycle of the PWM carrier wave or about a half cycle of the PWM carrier occurs until the change of the duty value is actually reflected in the output. There is a problem.

  Also, three bidirectional counters are used to generate a complementary PWM waveform signal having a dead time and capable of full duty. A bidirectional counter that can count in both increment and decrement directions has a larger circuit scale than a unidirectional counter that counts only in one direction of increment or decrement. Further, the three-layer structure of the register for storing the duty value complicates the circuit configuration and increases the circuit scale. As the circuit scale increases, there is a demerit that the number of transistors used increases.

  The conventional general PWM waveform generator (90) has only one delay counter (delay circuit) for generating a predetermined dead time, and “the high side transistor is on and the low side transistor is on. The first dead time when changing from “off” to “high-side transistor off and low-side transistor on” and “high-side transistor off and low-side transistor on” to “high-side The second dead time when the transistor is turned on and the low-side transistor is turned off is the same time. This is because the PWM waveform generator described in Patent Document 1 can also set one dead time, and the first dead time and the second dead time are the same time.

  In general, the switching speed of a transistor differs depending on the power device used. Even when the same transistor is used as the high-side transistor and the low-side transistor, the switching speed on the high-side side and the low-side side may be different depending on the circuit configuration. In such a case, for the first dead time and the second dead time, a common dead time is set in accordance with the longer dead time, and “the high side transistor is on and the low side transistor is off. ”To“ High-side transistor off and low-side transistor on ”,“ High-side transistor off and low-side transistor on ”to“ High-side transistor on and low-side transistor on ” When the transistor is turned off, there is a problem that the optimum switching operation cannot be performed for each.

  Therefore, an object of the present invention is to use a delay counter for dead time generation to generate a PWM waveform signal without delay in changing the duty value, and to generate a full-duty PWM waveform signal even in a dead time generation method using the delay counter. And the first dead time and the second dead time are individually set so that the optimum switching operation for the power module can be performed. Furthermore, in the PWM waveform generator which realizes them, the simplification of the configuration and the miniaturization of the circuit are realized.

  In order to solve the problems in the conventional method, the PWM waveform generator (1) of the present invention employs a delay counter to generate a PWM waveform signal without delaying the change of the duty value, and is capable of full duty. Use a counter that performs an increment operation and a counter that performs a decrement operation to generate a waveform signal, and operate them so that they intersect in a period corresponding to the dead time value in two locations, a high count value region and a low count value region. Then, the triangular carrier wave to be compared with the target duty value is formed by these count values. Next, an outline of a method for generating a triangular carrier wave and a PWM waveform signal will be described.

  The PWM waveform generator (1) according to the present invention controls a counter that performs an increment operation and a counter that performs a decrement operation, forms a triangular carrier wave, and outputs a count value of these counters. Compares the count value supplied from the triangular carrier wave control unit (2) with the target duty value supplied from the external control device, and outputs a complementary PWM waveform signal with dead time based on the comparison result And a PWM waveform output control unit (3).

  In order to operate the PWM waveform generator (1), the first set value L1, the second set value L2 smaller than the first set value L1, and the third set value L3 smaller than the second set value L2 (= first The dead time value td1), the second dead time value td2, the PWM control data cmd including the PWM clock mode command value CKM and the PWM start flag, and the target duty value duty need to be stored in the set value register (4). .

[Definition of L1, L2, and L3]
Here, the value corresponding to the triangular carrier wave period is T, and the first dead time corresponding to the dead time when the complementary PWM waveform signal (GH, GL) is “switched from (1, 0) to (0, 1)”. When the value is td1, and the second dead time value corresponding to the dead time when “switching from (0, 1) to (1, 0)” is represented by td2, the first set value L1, the second set value L2, and the second The three set values L3 are defined as L1 = (T + td1 + td2) / 2, L2 = (T + td1−td2) / 2, and L3 = td1, respectively.

  The triangular carrier wave control unit (2) includes a first control unit (21), a first counter (22), a second counter (23), a first selector (24), a second selector (25), and a first comparison. (26) and a second comparator (27), connected to the PWM waveform output control unit (3), the set value register (4), and the PWM clock generation unit (5). From the set value register (4) to the PWM A start signal STR, a PWM clock signal CK0, a first set value L1, a second set value L2, and a third set value L3 are supplied.

  The first counter (22) increments from the zero value to the first set value L1, and outputs the count value ucnt of the first counter (22). The second counter (23) decrements from the first set value L1 or the third set value L3 to the zero value, outputs the count value dcnt of the second counter (23), and the second counter when counted up. Generate and output a zero signal ZC2.

  The first selector (24), based on the first selection command signal SL1 supplied from the first controller (21), the first set value L1 and the second set value L2 supplied from the set value register (4). Is selected and output, and supplied to the first comparator (26). The second selector (25), based on the second selection command signal SL2 supplied from the first controller (2), the first set value L1 and the third set value L3 supplied from the set value register (4). Is selected and output, and supplied to the second comparator (27).

  The first comparator (26) compares the count value ucnt of the first counter (22) during the increment operation with the first set value L1 or the second set value L2 supplied from the first selector (24). When they match, the first comparison signal CM1 is generated and output and supplied to the first controller (21). The second comparator (27) compares the count value dcnt of the second counter (23) during the decrement operation with the third set value L3, and generates and outputs the second comparison signal CM2 when they match. To the first control unit (21).

  When the PWM start signal STR is supplied to start the operation of the first counter (22), or the first control unit (21) uses the second selection command signal SL2 and the second comparison signal CM2 to start the second counter (23 ) And the third set value L3, the first counter control signal SC1 for instructing the first counter (22) to start the increment operation from the zero value and the first counter clock. The signal CK1 is generated or updated and supplied, and the first selection command signal SL1 for instructing the first selector (24) to select the second set value L2 is generated or updated and supplied.

  When the second counter zero signal ZC2 notifying that the second counter (23) has become zero is supplied from the second counter (23) during the decrement operation, the first control unit (21) The decrement operation is stopped with respect to the second counter (23), and a second counter control signal SC2 for instructing reading of the first set value L1 supplied from the second selector (25) is generated or updated and supplied.

  The first controller (21) also supplies the second counter (23) with the PWM start signal STR and starts the operation of the second counter (23) from the third set value L3, or When the first comparison signal CM1 notifying that the first counter (22) during the increment operation has reached the second set value L2 is supplied from the first comparator (26), the first set value L1 The second counter control signal SC2 and the second counter clock signal CK2 for instructing the start of the decrement operation are generated or updated and supplied, and the first selector (24) is instructed to select the first set value L1. The first selection command signal SL1 is generated or updated and supplied.

  The first controller (21) is also supplied with a first comparison signal CM1 from the first comparator (26) for notifying that the first counter (22) during the increment operation has reached the first set value L1. When this occurs, the increment operation is stopped for the first counter (22), and the first counter control signal SC1 that instructs to clear the count value to zero is generated or updated and supplied.

  Thus, the first control unit (21) is set between the zero value and the third set value L3, which are set to be the same as the first dead time value td1, and the same as the second dead time value td2. The first counter (22) and the second counter (23) are operated simultaneously between the second set value L2 and the first set value L1, and between the third set value L3 and the second set value L2, The first counter (22) and the second counter (23) are controlled so that either the first counter (22) or the second counter (23) is operated.

  The first controller (21) also sets and outputs a counter mode value Sm corresponding to the operating states of the first counter (22) and the second counter (23).

  The triangular carrier wave control unit (2) includes the count value ucnt of the first counter (22) forming the triangular carrier wave, the count value dcnt of the second counter (23), and the first counter (22) and the second counter (23 ) Is supplied to the PWM waveform output control unit (3).

  The PWM waveform output control unit (3) is connected to the triangular carrier wave control unit (2), the set value register (4) and the PWM clock generation unit (5), and the first counter (22) from the triangular carrier wave control unit (2). Count value ucnt, the count value dcnt of the second counter (23) and the counter mode value Sm are supplied from the set value register (4), the first dead time value td1, the second dead time value td2, the target duty value The duty and the PWM start signal STR are supplied, and the PWM clock signal CK0 is supplied from the PWM clock generation unit (5).

  The PWM waveform output control unit (3) includes a second control unit (31), a third counter (32), a third selector (33), a third comparator (34), and a fourth comparator (35). The complementary PWM waveform signal is generated or updated and output.

  The third comparator (34) compares the target duty value duty with the count value ucnt of the first counter (22), generates and outputs a third comparison signal CM3 as a result of the magnitude comparison, and a fourth comparator (35) The target duty value duty is compared with the count value dcnt of the second counter (23), and a fourth comparison signal CM4 which is a result of the magnitude comparison is generated and output. The third comparison signal CM3 and the fourth comparison signal CM4 are supplied to the second control unit (31).

  The third selector (33) selects and outputs either the first dead time value td1 or the second dead time value td2 according to the third selection command signal SL3 supplied from the second controller (31). To the third counter (32).

  The third counter (32) is either the first dead time value td1 or the second dead time value td2 according to the third counter control signal SC3 and the third counter clock signal CK3 supplied from the second controller (31). The decrement operation is started from one of the count values. When the count-up is performed, the third counter zero signal ZC3 is generated and output and supplied to the second control unit (31).

[Gm, Pm, Dm]
The second control unit (31) sets, stores and outputs the PWM output mode value Gm associated with the complementary PWM waveform signal to be set and output, and previously outputs the PWM output mode value Gm immediately before entering the dead time operation. Store and output as the output mode value Pm, and set and store the dead time mode value Dm indicating whether the third counter is performing the dead time operation of the first dead time value td1 or the second dead time value td2. Output.

  The second control unit (31) sets and outputs complementary PWM waveform signals (GH, GL) based on the PWM output mode value Gm.

  The second control unit (31) includes a counter mode value Sm, a third comparison signal CM3, a fourth comparison signal CM4, a third counter zero signal ZC3, a PWM output mode value Gm, a prior output mode value Pm, and a dead time mode value Dm. The PWM output mode value Gm, the preliminary output mode value Pm, and the dead time mode value Dm are set and stored based on the above, and the third counter (32) is controlled.

  In the PWM waveform output control unit (3), the complementary PWM waveform signal (GH, GL) is generated between the second set value L2 and the third set value L3 by the first counter (22) or the second counter ( 23) In the section where Sm = 1 and Sm = 3 in which only one of them operates, it is basically the same as the conventional general PWM waveform generator shown in FIG.

  In the section of Sm = 1 in which only the second counter (22) operates, the third counter (32) and the third selector (33) are controlled based on the fourth comparison signal CM4 and the third counter zero signal ZC3. The PWM output mode value Gm, the prior output mode value Pm, and the dead time mode value Dm are set or updated and stored. In the section of Sm = 3 in which only the first counter (22) operates, the third counter (32) and the third selector (33) are controlled based on the third comparison signal CM3 and the third counter zero signal ZC3. The PWM output mode value Gm, the prior output mode value Pm, and the dead time mode value Dm are set or updated and stored. Further, based on the updated and stored PWM output mode value Gm, the complementary PWM is updated and the total signal is output.

  When the third counter (32) counts up and the ZC3 signal is generated, the PWM output mode value Gm is set or updated based on the PWM output mode value Gm and the dead time mode value Dm and stored. The prior output mode value Pm and the dead time mode value Dm are cleared and stored, and the operation of the third counter (32) is stopped. Further, based on the updated and stored PWM output mode value Gm, the complementary PWM is updated and the total signal is output.

  On the other hand, in the sections where Sm = 0 and Sm = 2 in which the first counter (22) and the second counter (23) operate simultaneously, if the target duty value duty is not changed in those sections, the third comparison signal CM3 And the fourth comparison signal CM4 is generated. In these sections, the method for setting or updating the PWM output mode value Gm is different in the order in which the third comparison signal CM3 and the fourth comparison signal CM4 are generated. Next, a case where the target duty value is not changed in those sections will be described.

  In the section where Sm = 0, when Gm = 2, Pm = 0, and Dm = 0, if the third comparison signal CM3 indicating that duty = ucnt is generated first, Gm is stored (Pm = 2) ), Gm = 0, and the third counter (32) starts the decrement operation from the first dead time value td1 (Dm = 1). Next, when the fourth comparison signal CM4 indicating that duty = dcnt is generated, the second dead time value td2 is reset in the third counter (32) without changing Gm and Pm, and the decrement operation is continued. (Dm = 2). When the third counter (32) counts up, Gm = 2, Pm = 0, and Dm = 0 are set, and the operation of the third counter (32) is stopped.

  In the section of Sm = 0, when Gm = 2, Pm = 0, and Dm = 0, if the fourth comparison signal CM4 indicating that duty = dcnt is generated first, Gm and Pm are not changed. The third counter (32) starts the decrement operation from the second dead time value td2 (Dm = 2). Next, when the third comparison signal CM3 indicating that duty = ucnt is generated, Gm is stored (Pm = 2), Gm = 0 is set, and the third counter (32) continues the decrement operation as it is. When the third counter (32) counts up, Gm = 2, Pm = 0, and Dm = 0 are set, and the operation of the third counter (32) is stopped.

  In the section of Sm = 2, when Gm = 1, Pm = 0, and Dm = 0, when the fourth comparison signal CM4 indicating that duty = dcnt is generated first, Gm is stored (Pm = 1 ), Gm = 0, and the third counter (32) starts the decrement operation from the second dead time value td2 (Dm = 2). Next, when the third comparison signal CM3 indicating that duty = ucnt is generated, Gm and Pm are not changed, and the third counter (32) is reset to the first dead time value td1, and the decrement operation is performed. Continue (Dm = 1). When the third counter (32) counts up, Gm = 1, Pm = 0 and Dm = 0 are set, and the operation of the third counter (32) is stopped.

  In the section of Sm = 2, when Gm = 1, Pm = 0, Dm = 0, if the third comparison signal CM3 indicating that duty = ucnt is generated first, Gm and Pm are not changed. The third counter (32) starts the decrement operation from the first dead time value td1 (Dm = 1). Next, when the fourth comparison signal CM4 indicating that duty = dcnt is generated, Gm is stored (Pm = 1), Gm = 0 is set, and the third counter (32) continues the decrement operation as it is. When the third counter (32) counts up, Gm = 1, Pm = 0, and Dm = 0, and the operation of the third counter (32) is stopped.

  By the generation method of the complementary PWM waveform signals (GH, GL) as described above, the present invention is capable of responding to the change of duty and capable of full duty (from 0% to 100%). A PWM waveform generator that generates (GH, GL) is realized.

  Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a system block diagram showing a configuration of a PWM waveform generator (1) according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of the first control unit (21) included in the triangular carrier wave control unit (2). FIG. 3 is a time chart for explaining the triangular carrier wave formed by the triangular carrier wave control unit (2). FIG. 4 is a block diagram illustrating a configuration of the second control unit (31) included in the PWM waveform output control unit (3).

  As shown in FIG. 1, the PWM waveform generator (1) of this embodiment includes a triangular carrier wave control unit (2), a PWM waveform output control unit (3), a set value register (4), and a PWM clock generation unit (5). ), A calculator (6), a carrier dead time setting means (7), and a PWM duty setting means (8).

  The PWM duty setting means (8) commands the target duty value duty of the complementary PWM waveform signal output from the PWM waveform generator (1) of this embodiment. The target duty value duty is set and supplied by a control device (not shown) in which the PWM waveform generator (1) of this embodiment is used.

  The carrier wave dead time setting means (7) includes a PWM operation / clock setting means (7a), a carrier wave period setting means (7b), a first dead time setting means (7c), and a second dead time setting means (7d). The PWM operation / clock setting means (7a) is the PWM start signal STR and the PWM clock mode command value CKM, the carrier wave period setting means (7b) is the triangular carrier wave period value T, and the first dead time setting means (7c) is the first. The dead time value td1, and the second dead time setting means (7d) commands the second dead time value td2. These set values are set and supplied by a control device (not shown) in which the PWM waveform generator (1) of this embodiment is used.

  The carrier wave dead time setting means (7) is connected to the setting value register (4) and the arithmetic unit (6), and the third setting value L3 (= first dead time value td1), second dead time value td2, PWM start The PWM control data cmd including the signal STR and the PWM clock mode command value CKM is supplied to the set value register (4), and the triangular carrier period value T, the first dead time value td1, and the second dead time value td2 are calculated by the calculator (6 ).

  The computing unit (6) is connected to the set value register (4) and the carrier dead time setting means (7). From the carrier dead time setting means (7), the triangular carrier period value T, the first dead time value td1, and the second The dead time value td2 is supplied, and based on these, the first set value L1 and the second set value L2 are calculated and supplied to the set value register (4). Here, half of the carrier wave period value T (T / 2) is represented as Th, half of the first dead time value td1 (td1 / 2) is represented as td1h, and half of the second dead time value td2 (td2 / 2) is represented as td2h. In this embodiment, L1 = Th + td1h + td2f and L2 = L1−td2 = Th + td1h−td2f.

  The set value register (4) is connected to the PWM clock generator (5), the arithmetic unit (6), the carrier wave dead time setting means (7), and the PWM duty setting means (8). Then, the first set value L1 and the second set value L2 are supplied from the computing unit (6), and the third set value L3 (= first dead time value td1), the second dead value are supplied from the carrier wave dead time setting means (7). The time value td2 and the PWM control data cmd (including the PWM clock mode command value CKM and the PWM start signal STR) are supplied, the target duty value duty is supplied from the PWM duty setting means (8), and these set values are stored. Hold.

  The PWM clock generation unit (5) is connected to the triangular carrier wave control unit (2), the PWM waveform output control unit (3), and the set value register (4), and is supplied from the set value register (4). And a PWM clock mode command value CKM, a PWM clock signal commanded from a reference clock signal CLK supplied from a clock generation circuit (not shown) outside or inside the PWM waveform generator (1) of this embodiment. CK0 is generated and supplied to the triangular carrier wave control unit (2) and the PWM waveform output control unit (3). The PWM clock signal CK0 may be composed of a plurality of clock signals having phase differences if necessary for those control units.

  In the control device (not shown) in which the PWM waveform generator (1) of the present embodiment is used, the functions of the carrier wave dead time setting means (7) and the PWM duty setting means (8) are realized. When the first set value L1 and the second set value L2 are also calculated and provided in advance, the carrier wave dead time setting means (7), the calculator (6) and the PWM duty setting means (8) are included in the PWM waveform generator (1). You may make it not prepare for.

  In addition, when a suitable PWM clock signal CK0 is generated and supplied by a clock pulse generator (not shown) outside or inside the PWM waveform generator (1) of this embodiment, the PWM clock generator (5 ) And PWM clock mode command value CKM may be omitted.

  Next, the configuration of the triangular carrier wave control unit (2) will be described with reference to FIG. The triangular carrier wave control unit (2) includes a first control unit (21), a first counter (22), a second counter (23), a first selector (24), a second selector (25), and a first comparison. (26) and a second comparator (27), connected to the PWM waveform output controller (3), the set value register (4), and the PWM clock generator (5). From the set value register (4) to the PWM The start signal STR, the first set value L1, the second set value L2, and the third set value L3 are supplied with the PWM clock signal CK0 from the PWM clock generator (5), and the count values of the two counters forming the triangular carrier wave And a carrier wave counter state signal Sm representing these operation states are supplied to the PWM waveform output control section (3).

  The first control unit (21) includes a PWM clock generation unit (5), a first counter (22), a second counter (23), a first selector (24), a second selector (25), and a first comparison. Connected to the comparator (26) and the second comparator, and supplied from the PWM clock generator (5), the second counter (23), the first comparator (26) and the second comparator (27), respectively. Based on the above, the first counter (22), the second counter (23), the first selector (24), and the second selector (25) are supplied with a command signal for controlling or generating them. .

  The first counter (22) is connected to the first controller (21), the first comparator (26), and the PWM waveform output controller (3), and is supplied from the first controller (21). In response to the control signal SC1 and the first counter clock signal CK1, an increment operation from the count value zero to the first set value L1 is performed, the count value ucnt of the first counter (22) is output, and the first comparator (26) and The PWM waveform output control unit (3) is supplied.

  The second counter (23) is connected to the first controller (21), the second selector (25), the second comparator (27), and the PWM waveform output controller (3), and the first controller (21 ) Supplied from the second counter control signal SC2 and the second counter clock signal CK2, either the first set value L1 or the third set value L3 supplied from the second selector (25) ( The count value is decremented, the count value dcnt of the second counter (23) is output, and supplied to the second comparator (27) and the PWM waveform output controller (3). The second counter (23) also generates a second counter zero signal ZC2 and supplies the second counter zero signal ZC2 to the first control unit when it counts up by the decrement operation (dcnt = 0).

  The first selector (24) is connected to the set value register (4), the first controller (21), and the first comparator (26), and the first set value L1 and the second set value L2 from the set register 7 are connected. Is supplied from the first control unit (21), the first selection command signal SL1 for commanding the selection of either the first set value L1 or the second set value L2 is supplied to the first selection command signal SL1. Based on this, one of the first set value L1 and the second set value L2 is selected, outputted, and supplied to the first comparator (26).

  The second selector (25) is connected to the set value register (4), the first control unit (21), and the second counter (23), and the first set value L1 and the third set value are set from the set value register (4). A value L3 is supplied, and a second selection command signal SL2 is supplied from the first control unit (21) to command selection of either the first set value L1 or the third set value L3. Based on SL2, one of the first set value L1 and the third set value L3 is selected, outputted, and supplied to the second counter (23).

  The first comparator (26) is connected to the first controller (21), the first selector (24) and the first counter (22), and the count value ucnt is supplied from the first counter (22), Either the first set value L1 or the second set value L2 is supplied from the first selector (24), and is supplied from the count value ucnt of the first counter (22) and the first selector (24). When the set values are compared with each other, the first comparison signal CM1 is generated and output and supplied to the first control unit (21).

  The second comparator (27) is connected to the set value register (4), the first control unit (21) and the second counter (23), and the third set value L3 is supplied from the set value register (4). The count value dcnt is supplied from the second counter (23), and when the two values are compared with each other, the second comparison signal CM2 is generated and output to be supplied to the first controller (21).

  Next, the configuration and function of the first control unit (21) will be described with reference to FIG. The first control unit (21) includes a triangular carrier wave generating means (21a) and a first status register (21b), and includes a set value register (4), a PWM clock generation unit (5), a first counter (22), a first counter 2 counters (23), a first selector (24), a second selector (25), a first comparator (26), a second comparator (27) and a PWM waveform output controller (3). .

  Signals input from outside the triangular carrier wave control unit (2) and supplied to the first control unit (21) include a PWM start signal STR from the set value register (4) and a PWM clock generation unit (5). PWM clock signal CK0. A signal output from the first control unit (21) and supplied to the outside of the triangular carrier wave control unit (2) includes a counter mode value Sm to the PWM waveform output control unit (3).

  The triangular carrier wave generating means (21a) includes a set value register (4), a PWM clock generator (5), a first status register (21b), a first counter (22), a second counter (23), and a first selector. (24), a PWM start signal STR that is connected to the second selector (25), the first comparator (26), and the second comparator (27) and commands the start of the operation of the PWM waveform generator (1); When the PWM clock signal CK0 is supplied, the operations of the first counter (22) and the second counter (23) are started, and a count signal that forms a predetermined triangular carrier wave is generated and output.

  The triangular carrier wave generating means (21a) includes a PWM start signal STR from the set value register (4), a PWM clock signal CK0 from the PWM clock generator (5), a first comparison signal CM1 from the first comparator (26), and a second comparison signal CM1. A second comparison signal CM2 is supplied from the comparator (27), and a second counter zero signal ZC2 is supplied from the second counter (23). Based on these signals, the first counter (22) and the second counter (23 ), Command signals for controlling the respective operations are set or updated and supplied to the first selector (24), the second selector (25), and the first status register (21b). The triangular carrier wave generation means (21a) also sets or updates the counter mode value Sm indicating the operation state of the first counter (22) and the second counter (23), and stores it in the first state register (21b).

  In this embodiment, the counter mode value Sm is an interval in which the first counter (22) and the second counter (23) operate simultaneously when the count value is between the first set value L1 and the second set value L2. Sm = 1 during the interval in which only the second counter (23) operates between the second set value L2 and the third set value L3, and the first value between the third set value L3 and the zero value. A section in which the counter (22) and the second counter (23) operate simultaneously is Sm = 2, and a section in which only the first counter (23) operates between the count value of the second set value L2 and the third set value L3. It is defined as Sm = 3.

  The first state register (21b) is connected to the triangular carrier wave generating means (21a) and the PWM waveform output control unit (3), and outputs the counter mode value Sm set or updated by the triangular carrier wave generating means (21a). The PWM waveform output control unit (3) is supplied.

  Hereinafter, the operation of the triangular carrier wave control unit (2) will be described along the time series (from time t0 to time t9 in FIG. 3) based on FIGS. In FIG. 3, the horizontal axis indicates time, the vertical axis indicates the count value, the broken line indicates the count value ucnt of the first counter (22), and the solid line indicates the count value dcnt of the second counter (23). Indicates.

  When the PWM carrier signal (21a) is supplied with the PWM start signal STR and the PWM clock signal CK0 for instructing the start of the operation of the PWM waveform generator (1), the triangular carrier wave generator (21a) is set to the third selector (25). A second selection command signal SL2 for commanding selection of the value L3 is set and supplied.

  The second selector (25) is supplied with the first setting value L1 and the third setting supplied from the setting value register (4) when the second selection command signal SL2 for instructing the selection of the third setting value L3 is supplied. The third set value L3 is selected from the values L3 and supplied to the second counter (23).

  Then, at time t0 in FIG. 3, the triangular carrier wave generating means (21a) starts the increment operation from the count value zero to the first counter (22), and the first counter control signal SC1 and the first counter clock signal CK1. Is generated and supplied to the first counter (22), and the decrementing operation is started by reading the third set value L3 supplied from the second selector (25) to the second counter (23). The second counter control signal SC2 and the second counter clock signal CK2 are generated and supplied to the second counter (23).

  At this time, the triangular carrier wave generation means (21a) sets the counter mode value Sm to “2” and stores it in the first state register (21b).

  When the first counter control signal SC1 and the first counter clock signal CK1 are supplied, the first counter (22) clears the count value to zero (ucnt = 0) and starts an increment operation. When the second counter control signal SC2 and the second counter clock signal CK2 are supplied, the second counter (23) reads the third set value L3 supplied from the second selector (25) and starts a decrement operation. To do. In this way, from time t0 in FIG. 3, the first counter (22) starts the increment operation from the count value zero, and the second counter (23) starts the decrement operation from the count value of the third set value L3. .

  When the second counter (23) starts the decrement operation from the third set value L3, the triangular carrier wave generating means (21a) is configured to select the first set value L1 for the second selector (25). The selection command signal SL2 is updated and supplied to the second selector (25).

  When the second selection command signal SL2 for commanding selection of the first set value L1 is supplied to the second selector (25), the first set value L1 and the third set value supplied from the set value register (4). Among the values L3, the first set value L1 is selected and supplied to the second counter (23). Thereafter, the second selection command signal SL2 is not updated until the operation of the triangular carrier wave control unit (2) is stopped, and the second selector (25) continues to output the first set value L1.

  Next, at time t1 in FIG. 3, when the count value dcnt becomes zero by the decrement operation, the second counter (23) generates a second counter zero signal ZC2 for notifying that the count has been incremented, thereby generating a triangular carrier wave. (21a).

  When the second counter zero signal ZC2 is supplied, the triangular carrier wave generating means (21a) stops the decrement operation to the second counter (23) and is supplied from the second selector (25). The second counter control signal SC2 is generated or updated so as to read the value L2, and supplied to the second counter (23). At this time, the triangular carrier wave generating means (21a) sets the counter mode value Sm to “3” and stores it in the first state register (21b).

  When the second counter control signal SC2 is supplied, the second counter (23) stops the decrement operation and reads the second set value L2. At this time, the decrement operation of the second counter (23) may be stopped, and the second set value L2 may be read at the start of the next decrement operation.

  Next, at time t2 in FIG. 3, the first comparator (26) counts the count value ucnt of the first counter (22) during the increment operation and the second set value supplied from the first selector (24). When it is detected that L2 matches, a first comparison signal CM1 for notifying that ucnt = L2 is generated and supplied to the triangular carrier wave generation means (21a).

  When the first comparison signal CM1 is supplied, the triangular carrier wave generation means (21a) determines that ucnt = L2 by the first selection signal SL1 supplied to the first selector (24), and the second A second counter control signal SC2 is generated or updated so as to start the decrement operation from the first set value L1 to the counter (23) and is supplied to the second counter (23), and also to the first selector (24). On the other hand, the first selection command signal SL1 is set so as to select the first set value L1, and is supplied to the first selector (24).

  At this time, the triangular carrier wave generating means (21a) sets the counter mode value Sm to “0” and stores it in the first state register (21b).

  The second counter (23) starts the decrement operation from the already read first set value L1 when the second counter control signal SC2 instructing the start of the decrement operation from the first set value L1 is supplied. To do. At this time, the second counter (23) may read the first set value L1 and then start the decrement operation.

  Next, at time t3 in FIG. 3, the first comparator (26) counts the count value ucnt of the first counter (22) during the increment operation and the first set value supplied from the first selector (24). When it is detected that L1 matches, a first comparison signal CM1 for notifying that ucnt = L1 is generated and supplied to the triangular carrier wave generation means (21a).

  When the first comparison signal CM1 is supplied, the triangular carrier wave generation means (21a) determines that ucnt = L1 by the first selection signal SL1 supplied to the first selector (24), The increment operation is stopped for the counter (22), and the first counter control signal SC1 is generated or updated so as to clear the count value (ucnt = 0).

  At this time, the triangular carrier wave generation means (21a) sets the counter mode value Sm to “1” and stores it in the first state register (21b).

  When the first counter (22) is supplied with the first counter control signal SC1 that instructs to stop the increment operation and clear the count value, the first counter (22) stops the count operation and clears the count value. (Ucnt = 0). Here, the increment operation of the first counter (22) may only be stopped, and the count value may be cleared at the start of the next increment operation.

  Next, at time t4 in FIG. 3, when the second comparator (27) detects that the count value dcnt of the second counter (23) during the decrement operation matches the third set value L3, dcnt = L3 Is generated and supplied to the triangular carrier wave generation means (21a).

  When the second comparison signal CM2 is supplied, the triangular carrier wave generation means (21a) determines that dcnt = L3 and starts the increment operation from the count value zero to the first counter (22). A counter control signal SC1 is generated or updated and supplied to the first counter (22). At this time, the triangular carrier wave generation means (21a) sets the counter mode value Sm to “2” and stores it in the first state register (21b).

  When the first counter control signal SC1 for instructing the start of the increment operation from the count value zero is supplied, the first counter (22) starts the increment operation from the zero value because the count value has already been cleared. At this point, the second counter (23) may be cleared to zero before starting the increment operation.

  The above is the operation of one cycle of the generated triangular carrier wave, and after time t5 in FIG. 3, the operations from time 1 to time 4 are repeated. That is, time t5 is the same as time 1, time 6 is time 2, time 7 is time 3, time 8 is time 4, and time 9 is time 1 again.

  As shown in FIG. 3, in the interval between the counter modes Sm = 0 and Sm = 2, a triangular carrier wave in which the count values of the first counter (22) and the second counter (23) intersect is generated. If the first dead time td1 is zero (td1 = 0), the section of Sm = 2 disappears, and the first counter (22) and the second counter (23) are in contact with each other with a count value of 0 (zero). Become. If the second dead time td2 is zero (td2 = 0), the section of Sm = 0 disappears, and the count values of the first counter (22) and the second counter (23) are in contact with the first set value L1. Become a shape.

  Next, the configuration of the PWM waveform output control unit (3) will be described with reference to FIG. The PWM waveform output control unit (3) includes a second control unit (31), a third counter (32), a third selector (33), a third comparator (34), and a fourth comparator (35). The triangular carrier wave control unit (2), the set value register (4) and the PWM clock generation unit (5) are connected to output complementary PWM waveform signals (GH, GL).

  The second control unit (31) is connected to the third counter (32), the third selector (33), the third comparator (34), the fourth comparator (35), and the first control unit (21). The third counter zero signal ZC3 from the third counter (32), the third comparison signal CM3 from the third comparator (34), the fourth comparison signal CM4 from the fourth comparator (35), and the first control. The counter mode value Sm is supplied from the unit (21), and based on these signals, the high-side PWM signal GH and the low-side PWM signal GL are generated or updated and output.

  The third selector (33) is connected to the set value register (4), the second control unit (31), and the third counter (32), and the first deadline of the third set value L3 from the set value register (4). The time value td1 and the second dead time value td2 are supplied, and a third selection command signal SL3 for commanding selection of either the first dead time value td1 or the second dead time value td2 from the second control unit (31). Is selected, and either the first dead time value td1 or the second dead time value td2 is selected and output by the third selection command signal SL3, and supplied to the third counter (32).

  The third counter (32) is connected to the second controller (31) and the third selector (33), and the third counter control signal SC3 and the third counter clock signal CK3 are supplied from the second controller (31). Is done. In the present embodiment, when the third counter control signal SC3 is supplied to the third counter (32), the third counter (32) receives the first dead time value td1 or the second dead time value td2 supplied from the third selector (33). Decrement operation is started with either one as an initial value, and when the count-up is performed (when the count value becomes zero), a third counter zero signal ZC3 is generated (ZC3 = 1) and output, and the second control unit (31) To supply.

  In the present embodiment, an example in which a counter that performs a decrement operation is used as the third counter (32) is shown, but a counter that performs an increment operation can also be used as the third counter (32). In that case, either the first dead time value td1 or the second dead time value td2 supplied from the third selector (33) is compared with the count value of the third counter (32). A comparator is added, and when they match, a match signal is generated and output and supplied to the second control unit (31). This coincidence signal has the same role as the third counter zero signal ZC3 when a counter that performs a decrement operation is used for the third counter.

  The third comparator (34) is connected to the set value register (4), the first counter (22), and the second control unit (31), and the target duty value duty is supplied from the set value register (4). The count value ucnt is supplied from the first counter (22), the duty and ucnt are compared, a third comparison signal CM3 as a result of the comparison is generated or updated, and is output to the second control unit (31). .

  The magnitude comparison relationship between the target duty value duty [comparison input A] input to the third comparator (34) and the count value ucnt [comparison input B] of the first counter (22) is as follows: a) duty and ucnt match When (A = B), (b) when duty is smaller than ucnt (A <B), c) there are three cases where duty is larger than ucnt (A> B). The third comparator (34) generates or updates the third comparison signal CM3 corresponding to these three states.

  For example, if the third comparator 34 outputs CM3 = 1 if A = B, CM3 = 2 if A <B, and CM3 = 0 if A> B, The second control unit 31 determines that duty = ucnt if CM3 = 1, duty <ucnt if CM3 = 2, and duty> ucnt if CM3 = 0.

  In addition, individual comparison signals corresponding to these three states may be generated or updated and output. For example, if A = B, a CM31 signal is generated, if A <B, a CM32 signal is generated, and if A> B, a CM33 signal is generated or updated and output. Further, for example, the CM33 signal may be omitted, and A> B may be determined when the CM31 signal and the CM32 signal are not output.

  The fourth comparator (35) is connected to the set value register (4), the second counter (23), and the second control unit (31). In the fourth comparator (35), the set value register (4). The target duty value duty [comparison input A] supplied from the second counter 22 and the count value dcnt [comparison input B] of the second counter (23) supplied from the second counter 22 are compared, and a fourth comparison result is compared. The signal CM4 is generated or updated, outputted, and supplied to the second control unit (31).

  The magnitude comparison relationship between the target duty value duty [comparison input A] input to the fourth comparator (35) and the count value dcnt [comparison input B] of the second counter (23) is as follows: a) duty and dcnt match In the case of (A = B), b) in the case where the duty is smaller than dcnt (A <B), and c) in the case where the duty is larger than dcnt (A> B). The fourth comparator (35) generates or updates the fourth comparison signal CM4 corresponding to these three states and outputs it.

  For example, if A = B, CM4 = 1 is output, if A <B, CM4 = 2, and if A> B, CM4 = 0 is output, the second control unit (31) receives CM4. If = 1, it is determined that duty = ucnt. If CM4 = 2, it is determined that duty <ucnt. If CM4 = 0, it is determined that duty> ucnt.

  In addition, individual comparison signals corresponding to these three states may be generated or updated and output. For example, if A = B, a CM41 signal is generated, if A <B, a CM42 signal is generated, and if A> B, a CM43 signal is generated or updated and output. Further, for example, the CM43 signal may be omitted, and A> B may be determined when the CM41 signal and the CM42 signal are not generated.

  Next, the configuration and function of the second control unit (31) will be described with reference to FIG. The second control unit (31) includes a PWM waveform generation unit (31a) and a second state register (31b). The triangular carrier control unit (2), the set value register (4), the PWM clock generation unit (5), The third counter (32), the third selector (33), the third comparator (34) and the fourth comparator (35) are connected.

  A signal input from the outside of the PWM waveform output control unit (3) and supplied to the second control unit (31) includes a PWM start signal STR from the set value register (4) and a PWM clock generation unit (5). From the PWM clock signal CK0. The signals generated by the second control unit (31) and output to the outside of the PWM waveform output control unit (3) include complementary PWM waveform signals (GH, GL).

  When the PWM start signal STR and the PWM clock signal CK0 are supplied, the PWM waveform generation means (31a) receives the counter mode value Sm from the triangular carrier wave control unit (2) and the third counter zero from the third counter (32). Dead signal ZC3, third comparison signal CM3 from third comparator (34), fourth comparison signal CM4 from fourth comparator (35), and PWM output mode value Gm from second state register (31b) Based on the time mode value Dm and the prior output mode value Pm, the PWM output mode value Gm, the dead time mode value Dm, and the prior output mode value Pm are set or updated and stored in the second state register (31b).

  The PWM waveform generation means (31a) also sets and outputs complementary PWM waveform signals (GH, GL) corresponding to the PWM output mode value Gm. The complementary PWM waveform signals (GH, GL) are generally output to the outside of the PWM waveform generator (1) via an output buffer circuit (not shown).

  The second state register (31b) is connected to the PWM waveform generation means (31a), and is set or updated by the PWM waveform generation means (31a), the PWM output mode value Gm, the dead time mode value Dm, and the prior output mode value. Pm is output, and the PWM output mode value Gm, the dead time mode value Dm, and the prior output mode value Pm are supplied to the PWM waveform generation means (31a).

  In this embodiment, the relationship between the PWM output mode value Gm and the complementary PWM waveform signal (GH, GL) is as follows: if Gm = 0, the PWM waveform signal (0, 0); if Gm = 1, the PWM waveform signal (0 , 1) is defined to output a PWM waveform signal (1, 0) if Gm = 2. The setting of Gm = 3 is prohibited, and the PWM waveform signal (1, 1) is not output.

  When the PWM waveform generation means (31a) sets or updates Gm = 1 or Gm = 2 to Gm = 0 and enters the dead time state, the prior output mode value Pm is set to Gm = 1 before the update or The value of Gm = 2. The prior output mode value Pm is a parameter provided for returning without the dead time operation when the PWM duty value duty is changed during the dead time operation and it is desired to return to the original PWM output mode value Gm. Therefore, the dead time mode value Dm may be reset by changing the PWM duty value duty during the dead time operation, and the prior output mode value Pm may be omitted.

  The dead time mode value Dm corresponds to a count value set as an initial value of the third counter (32) when the PWM waveform generating means (31a) generates a dead time. In this embodiment, when the third counter (32) starts or restarts the decrement operation from the first dead time value td1, Dm = 1, and the third counter (32) performs the decrement operation from the second dead time value td2. Dm = 2 is set when starting or restarting, and Dm = 0 is set when the third counter (32) is not operating.

  The above example shows an example in which a counter that performs a decrement operation is used for the third counter (32). However, if a counter that performs an increment operation is used for the third counter (32), the first dead time value is used. The third selection signal SL3 that commands selection of either td1 or the second dead time value td2 corresponds to the dead time mode value Dm. When selecting the first dead time value td1 and performing the dead time operation, Dm = 1, when selecting the second dead time value td2 and performing the dead time operation, Dm = 2, and not performing the dead time operation. In this case, Dm = 0 is set.

  Next, the operation of the second control unit (31) will be described. The PWM waveform generation means (31a) is supplied to the PWM waveform generation means (31a), and includes a counter mode value Sm, a third counter zero signal ZC3, a third comparison signal CM3, a fourth comparison signal CM4, and a PWM output mode value Gm. Based on the dead time mode value Dm and the prior output mode value Pm, the third counter (32) and the third selector (33) are controlled to set or update the contents of the second state register (31b).

  In the present embodiment, the first comparison signal CM1, which is a comparison result between the target duty value duty and the count value ucnt of the first counter (22), and the comparison of the target duty value duty and the count value dcnt of the second counter (23). From the resulting at least one of the second comparison signals CM2, the counter mode value Sm, the PWM output mode value Gm, the dead time mode value Dm, and the prior output mode value Pm, an event that leads to generation or update of the PWM waveform signal and FIGS. 5 to 9 show lists in which occurrence of a state is an event, priorities are assigned to those events, and further classified by the counter mode value Sm.

  The columns on the left side of the tables of FIGS. 5 to 9 show the counter mode value Sm, the target duty value duty, the comparison result of the first counter (22), and the target duty value duty, which are the cause of the event. And the count value of the second counter (23), there are items of the PWM output mode value Gm, the prior output mode value Pm, and the dead time mode value Dm before the update indicating the operation state at the time of event occurrence. In the right column of the list, there are items of a PWM output mode value Gm, a dead time mode value Dm, and a prior output mode value Pm that are updated by an event.

  For the event occurrence requirement (left column of the list), first check the counter mode value Sm, then check the cause of the event according to the priority in the list for each counter mode value Sm, If the event and the state that generate the error are found, the update contents of the corresponding event No (the right column in the list) are executed.

  Further, the first dead time value td1 and the second dead time value td2 are included in the update conditions at the time of occurrence of the event shown in FIGS. This is because it is possible to cope with the case where at least one of the first dead time value td1 and the second dead time value td2 is zero. When td1 = 0 or td2 = 0, only Gm is updated without corresponding dead time operation, and both Pm and Dm are set to “0”.

  Since a dead time is indispensable in a general PWM power inverter, an event including td1 = 0 and td2 = 0 may be omitted. In order to prevent an arm short circuit, there is basically a dead time, so in the following explanation, an event with a dead time of zero is omitted.

  First, in order to explain the basic operation, a section of Sm = 1 in which only the first counter (22) operates, and then Sm = 3 in which only the second counter (23) operates will be described. In those sections, an operation example of the conventional general PWM waveform generator is basically shown as the operation from time 1 to time 4 in FIG. 19, time 1 in time 1 in FIG. 20, and time 1 in FIG. The same.

  FIG. 6 shows this embodiment in the section where Sm = 1. In the section of Sm = 1, only the comparison result between the target duty value duty and the count value dcnt of the second counter (23) is used, and the event associated with duty = dcnt has the highest priority. The basic control of this section is to turn off the low-side PWM signal GL and turn on the high-side PWM signal GH when it is determined that duty ≧ dcnt. When it is determined that duty <dcnt, The high-side PWM signal GH is turned off and the low-side PWM signal GL is turned on.

  When Sm = 1 and Gm = 1, when duty = dcnt, the PWM waveform generation means (31a) instructs the third selector (33) to select the second dead time value td2. 3 selection command signal SL3 is generated or updated and supplied. When the third selector (33) is supplied with the third selection command signal SL3 for instructing the selection of the second dead time value td2, the third selector (33) selects the second dead time value td2 and supplies it to the third counter (32). To do. The PWM waveform generation means (31a) stores Pm = 1 in the second state register (31b), sets Gm = 0 and Dm = 2, and selects the third counter (32) with the third selection. The third counter control signal SC3 and the third counter clock signal CK3 are generated or updated so as to start the decrement operation by reading the count value output from the counter (33), in this case, the second dead time value td2. 3 is supplied to the counter (32). When the third counter (32) is supplied with the third counter control signal SC3 and the third counter clock signal CK3, the third counter (32) outputs the count value output from the three selector (33), in this case, the second dead time value td2. Read and start decrementing. This corresponds to event No. 30 in FIG.

  The operation procedure as described above will be described below. “When Sm = 1 and Gm = 1, when duty = dcnt, it corresponds to event No30, so Pm = 1 is stored and Gm = 0. And start the dead time operation of Dm = 1 ”.

  When duty> dcnt when Sm = 1 and Gm = 1, it corresponds to event No. 39, so Pm = 1 is stored and Gm = 0 is set, and a dead time operation of Dm = 1 is started. .

  In the case of Sm = 1 and Gm = 0, if duty = dcnt, it corresponds to event No. 32. By the way, if Gm = 0, the dead time operation of either Dm = 1 or Dm = 2 is in progress. However, in either case, Gm and Pm are not changed, and Dm = 2 is set. The count value td2 is reset in the counter (32) and the dead time operation is continued. Hereinafter, this is expressed as “Gm and Pm are not changed and the operation is switched to the dead time operation of Dm = 2”.

  In the case of Sm = 1 and Gm = 0, if duty> dcnt, it corresponds to event No41. At this time, only when the dead time operation of Dm = 1 is being performed, Gm and Pm are not changed, and the operation is switched to the dead time operation of Dm = 2. Therefore, when the dead time operation of Dm = 2 is being performed, the dead time operation of Dm = 2 is continued without resetting the count value td2 in the third counter (32).

  In the case of Sm = 1 and Gm = 0, when duty <dcnt, if Dm ≠ 1 and Pm = 2, it corresponds to event No. 35 in FIG. 6, so Gm and Pm are not changed and Dm = 1 Switch to the dead time operation. At this time, if Dm ≠ 1 and Pm ≠ 2, since it corresponds to event No. 36 in FIG. 6, Gm = 1, Pm = 0 and Dm = 0 are set, and the dead time operation is stopped.

  When duty = dcnt when Sm = 1 and Gm = 2, since it corresponds to event No. 28, Pm = 2 is stored and Gm = 0 is set, and a dead time operation of Dm = 2 is started. . This is an event that occurs when duty> dcnt is changed to duty = dcnt at that timing. In the embodiment of FIG. 6, the subsequent processing is the same as the PWM waveform signal of event No. 30 of FIG. 6 when Sm = 1, Gm = 1, and duty = dcnt.

  If duty <dcnt when Sm = 1 and Gm = 2, it corresponds to event No. 34, so Pm = 2 is stored and Gm = 0 is set, and a dead time operation of Dm = 1 is started. .

  If Sm = 1 and Gm = 2, if duty> dcnt, there is no need to change Gm, so basically no event occurs (thus not in FIG. 6).

  Next, this embodiment in the section of Sm = 3 is shown in FIG. In the section of Sm = 3, only the comparison result between the target duty value duty and the count value ucnt of the first counter (23) is used, and the event associated with duty = ucnt has the highest priority. The basic control of this section is to turn off the high-side PWM signal GH and turn on the low-side PWM signal GL when it is determined that duty ≦ ucnt, and to turn on the low-side PWM signal GL when it is determined that duty> dcnt. Turns off and turns on the high-side PWM signal GH.

  When duty = ucnt when Sm = 3 and Gm = 2, it corresponds to event No. 70, so Pm = 2 is stored and Gm = 0 is set, and a dead time operation of Dm = 1 is started. .

  If duty <ucnt when Sm = 3 and Gm = 2, it corresponds to event No. 72, so Pm = 2 is stored and Gm = 0 is set, and a dead time operation of Dm = 1 is started. .

  When Sm = 3 and Gm = 1, if duty = ucnt, it corresponds to event No. 71, so Pm = 1 is stored and Gm = 0 and a dead time operation of Dm = 1 is started. To do. This is an event that occurs when duty <dcnt is changed to duty = dcnt at that timing. In this embodiment, the subsequent events are Sm = 3 and Gm = 2, duty = The same PWM waveform signal as in the case of ucnt is generated.

  When duty> dcnt in the case of Sm = 3 and Gm = 1, it corresponds to event No. 75, so Pm = 1 is stored and Gm = 0 and a dead time operation of Dm = 2 is started. .

  In the case of Sm = 3 and Gm = 1, if duty <ucnt, there is no need to change Gm, so basically no event occurs.

  In the case of Sm = 3 and Gm = 0, if duty = dcnt, it corresponds to event No. 73, so Gm and Pm are not changed regardless of the Dm value, and the operation is switched to the dead time operation of Dm = 1.

  When Sm = 3 and Gm = 0, if duty> dcnt, if Dm ≠ 2 and Pm = 1, it corresponds to event No. 76, so Gm and Pm are not changed, and the dead time of Dm = 2 Switch to operation. At this time, if Dm ≠ 2 and Pm ≠ 1, since it corresponds to event No. 77, Gm = 2, Pm = 0 and Dm = 0 are set, and the dead time operation is stopped.

  When Sm = 3 and Gm = 0, if duty <dcnt, it corresponds to event No. 82. Therefore, only when Dm = 2, Gm and Pm are not changed, and the operation is switched to the dead time operation of Dm = 1. .

  If Sm = 3 and Gm = 1, if duty <ucnt, there is no need to change Gm, so basically no event occurs (thus not in FIG. 8).

  Next, this embodiment in the section where Sm = 0 is shown in FIG. In this section, if the PWM duty value duty is not changed, both events of duty = dcnt and duty = ucnt occur, and the PWM output mode value Gm, the prior output mode value Pm, and the dead time mode occur in the order in which they occur. The updating method of the value Dm is different. In this section, the event associated with duty = dcnt has the highest priority.

  When duty = dcnt occurs first in the case of Sm = 0 and Gm = 2, if duty> ucnt at this time, since it corresponds to event No. 2 in FIG. 5, Gm and Pm are not changed. The dead time operation of Dm = 2 is started. After that, when duty = ucnt occurs, if duty> dcnt, it corresponds to event No. 8 in FIG. 5, so the dead time operation of Dm = 2 is continued as it is, and Pm = 2 is stored and Gm = 0 And

  In the case of Sm = 0 and Gm = 2, when duty = ucnt occurs first, if duty <dcnt, it corresponds to event No7, so Pm = 2 is stored and Gm = 0. The Dm = 1 dead time operation is started. After that, when duty = dcnt occurs, if duty <ucnt, it corresponds to event No5, so Gm and Pm are not changed, and the operation is switched to the dead time operation of Dm = 2.

  When duty = dcnt and duty = ucnt occur at the same time in the case of Sm = 0 and Gm = 2, it corresponds to event No1, so Pm = 2 is stored and Gm = 0 is set, and Dm = 2 Start dead time operation.

  Other events at Sm = 0 are basically caused by a change in duty.

  When duty = dcnt occurs when Sm = 0 and Gm = 2, if duty <ucnt, it corresponds to event No1, so Pm = 2 is stored and Gm = 0, and Dm = 2 dead time operation is started. This is an event that can occur when the duty is changed during the dead time operation of Dm = 2 activated by event No2.

  When duty <ucnt when Sm = 0 and Gm = 2, if duty <dcnt, it corresponds to event No16, so Pm = 2 is stored, Gm = 0 is set, and Dm = 1 is dead Start time operation. On the other hand, if duty> dcnt at this time, since it corresponds to event No17, Pm = 2 is stored, Gm = 0 is set, and a dead time operation of Dm = 2 is started.

  When duty = dcnt when Sm = 0 and Gm = 1, it corresponds to event No3, so Pm = 1 is stored and Gm = 0 is set, and a dead time operation of Dm = 2 is started. .

  When duty = ucnt when Sm = 0 and Gm = 1, if duty <dcnt, it corresponds to event No. 10, so Pm = 1 is stored, Gm = 0, and Dm = 1 dead Start time operation. On the other hand, if duty> dcnt at this time, since it corresponds to event No11, Pm = 1 is stored, Gm = 0 is set, and a dead time operation of Dm = 2 is started.

  When duty> ucnt when Sm = 0 and Gm = 1, if duty ≠ dcnt, it corresponds to event No20, so Pm = 1 is stored and Gm = 0 and Dm = 2 Start dead time operation.

  When duty> dcnt when Sm = 0 and Gm = 1, if duty ≠ ucnt, it corresponds to event No21, so Pm = 1 is stored and Gm = 0 and Dm = 2 Start dead time operation.

  In the case of Sm = 0 and Gm = 0, when duty> ucnt, if Pm ≠ 1, it corresponds to event No. 22 in FIG. 5, and therefore Gm = 2 and Pm = 0. Further, at this time, if Dm = 1 and duty> dcnt, it corresponds to the event No. 23 in FIG. 5, so that the operation is switched to the dead time operation of Dm = 2. On the other hand, if Dm = 1 and duty <dcnt at this time, since it corresponds to event No. 24 in FIG. 5, Dm = 0 is set and the dead time operation is stopped. Here, event No22 may be executed simultaneously with event No23 or event No24.

  Description of other events with Sm = 0 (FIG. 5) is omitted.

  Next, this embodiment in the section of Sm = 2 is shown in FIG. In this section, if the PWM duty value duty is not changed, both events of duty = dcnt and duty = ucnt occur, and the PWM output mode value Gm, the prior output mode value Pm, and the dead time mode occur in the order in which they occur. The updating method of the value Dm is different. In this section, the event associated with duty = dcnt has the highest priority.

  In the case of Sm = 2 and Gm = 1, if duty = ucnt occurs first, if duty <dcnt, it corresponds to event No 44, so Gm and Pm are not changed, and Dm = 1 dead Start time operation. After that, when duty = dcnt occurs, if duty <ucnt, it corresponds to event No. 51. Therefore, the dead time operation of Dm = 1 is continued and Pm = 1 is stored and Gm = 0 is set.

  In the case of Sm = 2 and Gm = 1, if duty = dcnt occurs first, if duty> ucnt, it corresponds to event No50, so Pm = 1 is stored and Gm = 0 is set. The dead time operation of Dm = 2 is started. Thereafter, when duty = ucnt occurs, if duty> dcnt, it corresponds to event No. 46, so Gm and Pm are not changed, and the operation is switched to the dead time operation of Dm = 1.

  When duty = dcnt and duty = ucnt occur at the same time in the case of Sm = 2 and Gm = 1, it corresponds to event No 43, so Pm = 1 is stored and Gm = 0 and Dm = 1. Start dead time operation.

  Other events at Sm = 2 are basically caused by a change in the duty.

  When duty = ucnt occurs in the case of Sm = 2 and Gm = 1, if duty> dcnt, it corresponds to event No 43, so Pm = 1 is stored and Gm = 0, and Dm = 1 dead time operation is started. This is an event that can occur when the duty is changed during the dead time operation of Dm = 1 started by event No44.

  In case of Sm = 2 and Gm = 1, if duty> dcnt, if duty> ucnt, it corresponds to event No. 59, so Pm = 1 is stored, Gm = 0 is set, and Dm = 2 dead Start time operation. On the other hand, if duty <ucnt at this time, since it corresponds to event No. 60, Pm = 1 is stored, Gm = 0 is set, and a dead time operation of Dm = 1 is started.

  When Sm = 2 and Gm = 2, when duty = ucnt, it corresponds to event No. 42, so Pm = 2 is stored and Gm = 0 is set, and a dead time operation of Dm = 1 is started. .

  When duty = dcnt in the case of Sm = 2 and Gm = 2, if duty> ucnt, it corresponds to event No. 47, so Pm = 2 is stored, Gm = 0 is set, and Dm = 2 dead Start time operation. On the other hand, if duty <dcnt at this time, since it corresponds to event No. 48, Pm = 2 is stored, Gm = 0 is set, and a dead time operation of Dm = 1 is started.

  In the case of Sm = 2 and Gm = 2, if duty <dcnt, if duty ≠ ucnt, it corresponds to event No. 56, so Pm = 2 is stored and Gm = 0 and Dm = 1 Start dead time operation.

  When duty <ucnt when Sm = 2 and Gm = 2, if duty ≠ dcnt, this corresponds to event No57, so Pm = 2 is stored and Gm = 0. The Dm = 1 dead time operation is started.

  In the case of Sm = 2 and Gm = 0, if duty <dcnt, if Pm ≠ 2, the event corresponds to event No 63, so Gm = 1 and Pm = 0. Further, at this time, if Dm = 2 and duty <ucnt, the event corresponds to event No. 64, and the operation is switched to the dead time operation of Dm = 1. On the other hand, if Dm = 2 and duty> ucnt at this time, since it corresponds to event No. 65, Dm = 0 is set and the dead time operation is stopped. Here, event No 63 and event No 64 or event No 65 may be performed simultaneously.

  Description of other events with Sm = 2 (FIG. 7) is omitted.

  FIG. 9 shows that when an event corresponding to events No1 to No82 has not occurred, when the third counter (32) counts up and ZC3 = 1 occurs, PWM output mode value Gm, dead time mode value It is a table | surface which shows the rule which updates Dm and prior output mode value Pm. As shown in the figure, when Gm = 0 and Dm = 2, if ZC3 = 1 occurs, it corresponds to event No. 83, so Gm = 2, Pm = 0, Dm = 0 and dead time operation To stop. When Gm = 0 and Dm = 1 and ZC3 = 1 occurs, it corresponds to event No. 84, Gm = 1, Pm = 0, Dm = 0, and the dead time operation is stopped. When Gm ≠ 0 and ZC3 = 1 occurs, it corresponds to event No. 85, Gm and Pm are not changed, Dm = 0 is set, and the dead time operation is stopped.

  (Description of Operation) Next, a specific operation example in the PWM waveform generator (1) shown in the embodiment of the present invention will be described with reference to FIGS. 10 to FIG. 15, the timing chart showing the operations of the count value ucnt of the first counter (22) and the count value dcnt of the second counter (23) is shown at the top. In this timing chart, the horizontal axis indicates the time, the vertical axis indicates the count value, and the count value ucnt output from the first counter (22) is output from the second counter (23) by a broken line. The counted value dcnt is indicated by a solid line. Below that, a counter mode value Sm, a PWM output mode value Gm, a dead time mode value Dm, and a prior output mode value Pm are displayed. Furthermore, the event occurrence factor that has occurred is displayed as an event number in FIGS. 5 to 9 below, and below that is from the count value DTcnt representing the operation of the third counter (32) and the PWM output state section (31c). A timing chart showing the complementary PWM waveform signals (GH, GL) to be output is displayed.

  FIG. 10 shows the operation of the PWM waveform generator (1) when the target duty value duty is set to a value between the third set value L3 and the second set value L2 and does not change.

  At time t1 (t5) in FIG. 10, since Sm = 3, duty = dcnt, Gm = 2, Pm = 0, and Dm = 0, it corresponds to event No. 70, Pm = 2 is stored, and Gm = 0. At the same time, the dead time operation of Dm = 1 is started. At time t2 (t6) in the figure, since Sm = 3, Gm = 0, Pm = 2, Dm = 1, and ZC3 = 1, it corresponds to event No. 84, and Gm = 1, Pm = 0, and Dm = 0. Stop dead time operation.

  At time t3 (t7) in FIG. 10, since Sm = 1, duty = ucnt, and Gm = 1, it corresponds to event No. 30 and is updated to Gm = 0, Dm = 2, and Pm = 1, and the third counter ( 32) starts the decrement operation from the count value td2. At time t4 (t8) in the figure, since Gm = 0, Pm = 1, Dm = 2, and ZC3 = 1, it corresponds to event No. 83 and is updated to Gm = 2, Pm = 0, Dm = 0, The 3 counter (32) stops the decrement operation.

  FIG. 11 shows the operation of the PWM waveform generator (1) when the target duty value duty is set to a value between the third set value L3 and the second set value L2, and changes. Here, the duty is changed at time t5 and time t7 in the figure, and the comparison result between the duty and ucnt or the duty and dcnt is changed. The operation of the PWM waveform generator (1) by event generation at time t5 and time t7 will be described below.

  At time t5 in FIG. 11, since Sm = 3, duty <ucnt, Gm = 2, it corresponds to event No. 80, updated to Gm = 0, Pm = 2, Dm = 1, and the third counter (32) is updated. The decrement operation is started from the count value td1. At time t6 in the figure, Gm = 0, Pm = 2, Dm = 1, ZC3 = 1, corresponding to event No. 84, updated to Gm = 1, Pm = 0, Dm = 0, and the third counter ( 32) stops the decrement operation.

  At time t7 in FIG. 11, Sm = 1, duty> dcnt, Gm = 1, which corresponds to event No39. Accordingly, Gm = 0, Pm = 1, and Dm = 2 are updated, and the third counter (32) starts the decrement operation from the count value td2. At time t8 in the figure, Gm = 0, Pm = 1, Dm = 2, ZC3 = 1, corresponding to event No. 83, updated to Gm = 2, Pm = 0, Dm = 0, and the third counter (32) Stops decrementing.

  Subsequently, an operation when Gm = 0 is set by an event and the next event occurs during the dead time operation after the start of the dead time operation will be described with reference to FIGS.

  In FIG. 12, at time t3, the duty line intersects the dcnt line in the horizontal direction, and at the time t4 during the dead time operation started thereby, the duty changes, and the dcnt line In contrast, the duty lines intersect again in the vertical direction. Also, at time t8 in the figure, the duty changes, and the duty line intersects the ucnt line in the vertical direction, and at the time t9 in the figure during the dead time started thereby, the ucnt line In contrast, the duty line intersects again in the horizontal direction. The operation in such a case will be described below.

  At time t3 in FIG. 12, when Sm = 1 and Gm = 1, duty = dcnt, so event No. 30 corresponds, Pm = 1 is stored, Gm = 0 is set, and Dm = 2 dead time operation is performed. Start.

  Thereafter, at time 4 in the figure, the duty is changed to a small value, and duty <dcnt. At this time, since Gm = 0, Pm = 1, and Dm = 2, it corresponds to event No. 36, Gm = 1, Pm = 0, and Dm = 0, and the dead time operation is stopped.

  In the present embodiment, the setting is made as described above. When it is determined that duty <dcnt during the decrement operation of Dm = 2 in the state of Sm = 1, Gm = 0, Pm = 1, Gm and Pm May be switched to a dead time operation of Dm = 1 without changing.

  At time t9 in FIG. 12, when Sm = 3 and Gm = 1, the duty is changed to a large value and duty> ucnt, so that it corresponds to event No75, Pm = 1 is stored and Gm is stored, and Dm = 2 dead time operation is started.

  Thereafter, at time t10, when Sm = 3, Gm = 0, Pm = 1, and Dm = 2, duty = ucnt is satisfied, so that it corresponds to event No. 73, and Gm and Pm are not changed, and Dm = 1 Switch to dead time operation. This is because the subsequent PWM waveform signal is the same as the PWM waveform signal generated by event 70 when duty = ucnt when Sm = 3 and Gm = 2.

  In this embodiment, the setting is made as described above. However, when duty = ucnt is determined when Sm = 3, Gm = 0, Pm = 1, and Dm = 2, Gm = 1 is returned to Pm. = 0 and Dm = 0, and the dead time operation may be stopped.

  FIG. 13 shows an operation example when an event occurs continuously within a short time, as in FIG. In FIG. 13, the occurrence order of the event due to the change of the duty and the event due to the duty = ucnt or the duty = dcnt is reversed from the case of FIG.

  At time t5 in FIG. 13, when Sm = 1 and Gm = 2, the duty is changed to a small value and duty <dcnt, so that it corresponds to the event 34, Pm = 2 is stored, Gm = 0 is set, The decrement operation of Dm = 1 is started.

  At time t6 in the figure, when Sm = 1, Gm = 0, Pm = 2, and Dm = 1, duty = dcnt, which corresponds to event No. 32, Gm and Pm remain unchanged, and Dm = 2 Switch to the dead time operation. This is because the subsequent PWM waveform signal is the same as the PWM waveform signal generated by event 30 when duty = dcnt when Sm = 1 and Gm = 1.

  In this embodiment, the setting is made as described above, but when Sm = 1, Gm = 0, Pm = 2, and Dm = 1, if it is determined that duty = dcnt, the setting is returned to Gm = 2, and Pm = 0 and Dm = 0, and the dead time operation may be stopped.

  At time t8 in FIG. 13, when Sm = 3 and Gm = 2, since duty = ucnt, it corresponds to event No. 70, Pm = 2 is stored, Gm = 0 is set, and Dm = 1 dead time operation is performed. Start.

  At time t9 in the figure, the duty is changed to a large value, and duty> ucnt is satisfied. At this time, since Sm = 3, Gm = 0, Pm = 2, and Dm = 1, corresponding to event No. 77, Gm = 2 is restored, Pm = 0 and Dm = 0 are set, and the dead time operation is stopped. .

  In this embodiment, the setting is made as described above. However, when duty> dcnt is determined when Sm = 3, Gm = 0, Pm = 2, and Dm = 1, Gm and Pm are not changed. , Dm = 2 may be switched to the dead time operation.

  14 and 15 are diagrams illustrating an operation when the duty is set to a high value (between the second set value L2 and the first set value L1). This means that an event occurs in a section where Sm = 0. The conventional PWM waveform generator has a problem that a PWM waveform signal corresponding to such a high PWM duty value cannot be generated.

  In the interval of Sm = 0, the count value ucnt line output from the first counter (22) and the count value dcnt line output from the second counter (23) are second dead from the first set value L1. It intersects at a value obtained by subtracting half of the time value td2h, that is, a count value LCH (= Th + td1h).

  In FIG. 14, the duty is initially set to L2, and after passing through the first Sm = 0 section, before entering the second Sm = 0 section, the value of L2 <duty <LCH is set. In addition, after passing through the second Sm = 0 section and before entering the third Sm = 0 section, it is changed to LCH. The operation in this embodiment will be described below with reference to FIG.

  At time t1 in FIG. 14, ucnt = L2, the second counter (23) starts the increment operation from the first set value L1, and is the starting point of the section of Sm = 0. At the same time, duty = ucnt, and at this time, Gm = 2 and duty <dcnt, so it corresponds to event No7, Pm = 2 is stored, Gm = 0 is set, and dead time operation of Dm = 1 is started. To do.

  At time t2 in the figure, ucnt = L1, the first counter (22) stops the increment operation, and is the starting point of the section of Sm = 1. At the same time, duty = dcnt, and Gm = 0, Pm = 2, and Dm = 1. Therefore, it corresponds to event No. 32, and Gm and Pm are not changed, and Dm = 2 dead time operation. Switch to.

  At time t3 in the figure, when Gm = 0 and Dm = 2, ZC3 = 1 occurs, so it corresponds to event No. 83, Gm = 2, Pm = 0, Dm = 0, and dead time operation is performed. Stop.

  At time t4 in FIG. 14, when Sm = 0, Gm = 2, and duty <dcnt, since duty = ucnt, it corresponds to event No7, Pm = 2 is stored, Gm = 0 is set, and Dm = 1 dead time operation is started.

  At time t5 in the figure, when Sm = 0, Gm = 0, Pm = 2, Dm = 1, and duty> ucnt, duty = dcnt is satisfied, so that it corresponds to event No. 5, and Gm and Pm must be changed. Without switching to the dead time operation of Dm = 2.

  At time t6 in the figure, when Gm = 0 and Dm = 2, ZC3 = 1 occurs, so it corresponds to event No. 83, Gm = 2, Pm = 0, Dm = 0, and dead time operation is performed. Stop.

  At time t7 in FIG. 14, duty = dcnt and at the same time duty = ucnt. At this time, since Sm = 0 and Gm = 2, it corresponds to event No.1, Pm = 2 is stored, Gm = 0 is set, and a dead time operation of Dm = 2 is started.

  At time t8 in the figure, when Gm = 0 and Dm = 2, ZC3 = 1 occurs, so it corresponds to event No. 83, Gm = 2, Pm = 0, Dm = 0, and dead time operation is performed. Stop.

  Next, FIG. 15 shows an operation when the target duty value duty is changed to the first set value L1 (duty 100%) which is the upper limit value. In the figure, the duty is initially set to a value of LCH <duty <L1, and after passing the first Sm = 0 section and before entering the second Sm = 0 section, the duty = L1 Has been changed.

  At time t1 in FIG. 15, when Sm = 0, duty> ucnt, and Gm = 2, since duty = dcnt, it corresponds to event No. 2, Gm = 2 remains, and Dm = 2 dead time operation To start.

  At time t2 in the figure, when Sm = 0, Gm = 2, Pm = 0, Dm = 2, and duty> dcnt, since duty = ucnt, it corresponds to event No. 8, and Pm = 2 is stored. The dead time operation of Gm = 0 and Dm = 2 is continued as it is.

  At time t3 in the figure, when Gm = 0 and Dm = 2, ZC3 = 1 occurs, so it corresponds to event No. 83, Gm = 2, Pm = 0, Dm = 0, and dead time operation is performed. Stop.

  At time t4 in FIG. 15, the duty is changed to L1 (the upper limit value of the count value, corresponding to the duty of 100%), but since Sm = 2, Gm = 2, duty> ucnt, and duty> dcnt, There is no occurrence.

  At time t5 in FIG. 15, ucnt = L2, the second count (23) starts the decrement operation from the count value L1, and is the starting point of the section of Sm = 0. At the same time, duty = dcnt, and at this time, since duty> ucnt and Gm = 2, it corresponds to the event No. 2 and the dead time operation of Dm = 2 is started while Gm = 2.

  At time t6 in the figure, the duty becomes ucnt, the first counter (22) stops the increment operation, and becomes the start point of the section of Sm = 1. At the same time, ZC3 = 1 occurs. At this time, since Gm = 2 and Dm = 2, it corresponds to event No. 85, Gm = 2 is maintained, Dm = 0 is set, and the dead time operation is stopped.

  At time t7 in FIG. 15, the operation of event No. 2 is the same as that at time 5 in FIG. In this way, when the duty is the upper limit value (duty 100%), only the third counter (32) operates and Gm = 0 does not occur. Therefore, the state that “the high-side PWM signal GH is on (GH = 1) and the low-side PWM signal GL is off (GL = 0)” is continuously output.

  Thus, the PWM waveform generator (1) of the present embodiment linearly increases the on-time of the high-side PWM signal GH as the target duty value duty approaches the upper limit value (duty 100%), and duty = While the L1 (duty 100%) is continuously turned on, the on-time of the low-side PWM signal GL decreases linearly, and a complementary PWM waveform signal that continuously turns off can be generated when duty ≧ Th.

  16 and 17 are diagrams illustrating an operation when the duty is set to a low value (between the zero value and the third set value L3). This means that an event occurs in the section of Sm = 2. The conventional PWM waveform generator has a problem that a PWM signal corresponding to such a low duty value cannot be generated.

  In the section of Sm = 2, the count value ucnt line output from the first counter (22) and the count value dcnt line output from the second counter (23) are half of the first dead time value td1h. The values intersect, that is, the count value LCL (= td1h).

  In FIG. 16, the duty is initially set to L3, and after it passes the first Sm = 2 interval and before entering the second Sm = 2 interval, the value of 0 <duty <LCL is set. In addition, after passing the second Sm = 2 section and before entering the third Sm = 2 section, it is changed to LCL. The operation in this embodiment will be described below with reference to FIG.

  At time t1 in FIG. 16, dcnt = L3 is established, and the first counter (22) starts the increment operation from the count value zero, which is the start point of the section of Sm = 2. At the same time, since duty = dcnt and Gm = 1 and duty> ucnt, it corresponds to event No. 50, Pm = 1 is stored, Gm = 0 is set, and a dead time operation of Dm = 2 is started. To do.

  At time t2 in the figure, when Sm = 2, Gm = 0, and Dm = 2, ZC3 = 1 occurs, so it corresponds to event No. 83, Gm = 2, Pm = 0, Dm = 0, and dead time Stop operation.

  At time t3 in the figure, dcnt = 0 and the second count (23) is the start point of the section of Sm = 3 where the decrement operation is stopped. At the same time, duty = ucnt. At this time, since Gm = 2, it corresponds to event No. 70, Pm = 2 is stored, Gm = 0 is set, and a dead time operation of Dm = 1 is started.

  At time t4 in the figure, when Sm = 3, Gm = 0, and Dm = 1, ZC3 = 1 occurs, so it corresponds to event No. 84, Gm = 1, Pm = 0, Dm = 0, and dead time Stop operation.

  At time t5 in FIG. 16, when Sm = 2, Gm = 1, and duty> ucnt, since duty = dcnt, it corresponds to event No50, Pm = 1 is stored, Gm = 0 is set, and Dm = 2 dead time operation is started.

  At time t6 in the figure, while ZC3 = 1 occurs, duty = ucnt. At this time, since Sm = 2, duty> dcnt, Gm = 0, Pm = 1, and Dm = 2, it corresponds to the event 46. In such a case, since the event due to ZC3 = 1 is invalidated, Gm and Pm are not changed, and the operation is switched to the dead time operation of Dm = 1.

  At time t7 in the figure, when Gm = 0 and Dm = 1, ZC3 = 1 occurs. Therefore, it corresponds to event No. 84, Gm = 1, Pm = 0, Dm = 0, and dead time operation is stopped. .

  At time t8 in FIG. 16, duty = dcnt and at the same time duty = ucnt. At this time, since Sm = 2 and Gm = 1, it corresponds to event No. 43, Pm = 1 is stored, Gm = 0 is set, and a dead time operation of Dm = 1 is started.

  At time t9 in the figure, when Gm = 0 and Dm = 1, ZC3 = 1 occurs, so it corresponds to event No. 84, Gm = 1, Pm = 0, Dm = 0, and dead time operation is performed. Stop.

  Next, FIG. 17 shows an operation when the target duty value duty is changed to zero (duty 0%) which is the lower limit value. In the figure, the value of duty is initially set to 0 <duty <LCL, and after passing through the first Sm = 2 section, before entering the second Sm = 2 section, duty = 0. Has been changed.

  At time t1 in FIG. 17, when Sm = 2, Gm = 1, and duty <dcnt, since duty = ucnt, it corresponds to event No. 44, Gm = 1, Dm = 1 dead time operation To start.

  At time t2 in the figure, when Sm = 2, Gm = 1, Dm = 1, and duty <ucnt, duty = dcnt, so it corresponds to event No. 51, Gm = 0, Pm = 1, and Dm = 1 dead time operation continues.

  At time t3 in FIG. 17, when Gm = 0 and Dm = 1, ZC3 = 1 occurs, so it corresponds to event No. 84, Gm = 1, Pm = 0, Dm = 0, and dead time Stop operation.

  At time t4 in FIG. 17, the duty is changed to 0 (the lower limit value of the count value and corresponds to 0% duty). However, since Gm = 1, duty <ucnt, and duty <dcnt, no event occurs.

  At time t5 in FIG. 17, dcnt = L3, the first count (22) starts the increment operation from the count value zero, and is the starting point of the section of Sm = 2. At the same time, duty = ucnt, and at this time, duty <dcnt, Gm = 1, so that it corresponds to event No. 44, and the dead time operation of Dm = 1 is started while Gm = 1.

  At time t6 in the figure, ZC2 = 1 occurs, the second counter (23) stops the decrement operation, and is the starting point of the section of Sm = 3. At the same time, ZC3 = 1 occurs. At this time, since Gm = 1 and Dm = 1, it corresponds to event No. 85, Dm = 0 is set, and the dead time operation is stopped.

  At time t7 in FIG. 17, the operation of event No. 44 is the same as that at time 5 in FIG. 17, and at time t8 in FIG. In this way, when the duty is the lower limit value (duty 0%), only the third counter (32) operates and Gm = 0 does not occur. Therefore, “a state where the high-side PWM signal GH is off (GH = 0) and the low-side PWM signal GL is on (GL = 1) is continuously output.

  Thus, the PWM waveform generator (1) of the present embodiment linearly decreases the ON time of the high side PWM signal GH as the target duty value duty approaches the lower limit value (duty 0%), and duty ≦ While it is continuously turned off at td1h + td2h, the on-time of the low-side PWM signal GL increases linearly, and it is possible to generate a complementary PWM waveform signal that is continuously turned on at duty = 0 (duty 0%).

  As described above, the PWM waveform generator (1) according to the embodiment of the present invention can generate complementary PWM waveform signals (GH, GL) corresponding to duty 0% to 100% and generate full duty PWM waveform signals. The PWM waveform generator (1) is realized.

  Also, by using a delay counter to generate the dead time, a PWM waveform generator (1) that can generate a complementary PWM waveform signal (GH, GL) in response to a change in duty value is realized. Yes.

  In addition, in the complementary PWM waveform signal (GH, GL) to be output, the first dead time when “(GH, GL) = (1,0) is switched to (GH, GL) = (0, 1)”, In addition, it is possible to set a different time for the second dead time when “switching from (GH, GL) = (0, 1) to (GH, GL) = (1, 0)”. A PWM waveform generator (1) capable of generating complementary PWM waveform signals (GH, GL) capable of performing an optimal complementary switching operation for a module is realized.

  Further, as the first counter, the second counter, and the delay counter, a unidirectional counter having a circuit scale smaller than that of the bi-directional counter is adopted, and furthermore, the register for storing the target duty value is limited to one so that the circuit configuration Simplification and circuit size reduction.

It is a system block diagram which shows the structure of the PWM waveform generator (1) of the Example of this invention. It is a block diagram which shows the structure of the 1st control part with which a triangular carrier wave control part is equipped. It is a timing chart figure explaining the triangular carrier wave formed in a triangular carrier wave control part. It is a block diagram which shows the structure of the 2nd control part with which a PWM waveform generator (1) is equipped. It is a table | surface which shows the predetermined rule regarding the update of Gm, Dm, and Pm when Sm = 0. It is a table | surface which shows the predetermined rule regarding the update of Gm, Dm, and Pm when Sm = 1. It is a table | surface which shows the predetermined rule regarding the update of Gm, Dm, and Pm when Sm = 2. It is a table | surface which shows the predetermined rule regarding the update of Gm, Dm, and Pm when Sm = 3. FIG. 9 is a table showing predetermined rules for updating Gm, Dm, and Pm when the third counter (32) counts up without occurrence of an event from FIG. 5 to FIG. It is a figure explaining operation | movement of the PWM waveform generator (1) when the target duty value duty is set to the value of L3 <duty <L2, and does not change. It is a figure explaining operation | movement of the PWM waveform generator (1) when the target duty value duty is set to the value between L3 <duty <L2, and changes. When the target duty value duty is set and changed to a value of L3 <duty <L2, and the target duty value duty crosses a short time within the dead time twice with respect to the count signal ( It is a figure explaining operation | movement of 1). When the target duty value duty is set and changed to a value of L3 <duty <L2, and the target duty value duty crosses a short time within the dead time twice with respect to the count signal ( It is a figure explaining operation | movement of 1). It is a figure explaining operation | movement of the PWM waveform generator (1) in case the target duty value duty is set to the value of L2 <= duty <= L1. It is a figure explaining operation | movement of the PWM waveform generator (1) in case the target duty value duty is set to L1 (duty 100%). It is a figure explaining operation | movement of the PWM waveform generator (1) in case the target duty value duty is set to the value of 0 <duty <L3. It is a figure explaining operation | movement of the PWM waveform generator (1) in case the target duty value duty is set to 0 (duty 0%). It is a figure explaining the PWM waveform generator connected to a motor and a motor. It is a timing chart explaining the method of producing | generating a PWM signal with the PWM waveform generator of a prior art example. It is a timing chart for demonstrating the PWM signal in which a target duty value is a lower limit (duty 0%) by the PWM waveform generator of a prior art example. It is a timing chart for demonstrating the PWM signal in which the target duty value is an upper limit (duty 100%) by the conventional PWM waveform generator. Time chart for explaining the basic operation of Renesas PWM waveform generator

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse width modulation (PWM) waveform generator 2 Triangular carrier control part 3 PWM waveform output control part 4 Set value register 5 PWM clock generation part 6 Calculator 7 Carrier dead time setting means 7a PWM operation / clock setting means 7b Carrier wave period setting Means 7c first dead time setting means 7d second dead time setting means 8 PWM duty setting means 21 first control unit 21a triangular carrier wave generating means 21b first state register 22 first counter 23 second counter 24 first selector 25 first 2 selector 26 1st comparator 27 2nd comparator 31 2nd control part 31a PWM waveform generation means 31b 2nd state register 32 3rd counter 33 3rd selector 34 3rd comparator 35 4th comparator 50 3 phase Motor 51 U-phase coil 52 V-phase coil 53 W-phase coil 60 Pulse width modulation (PWM) inverter 1 power module 62 the high-side transistor 63 low-side transistor 90 pulse width modulation (PWM) waveform generator

Claims (4)

A first counter that performs an increment operation and outputs a count value corresponding thereto; and a second counter that performs a decrement operation and outputs a count value corresponding to the first counter, and the count value of the first counter and the second counter A triangular carrier wave control unit that forms a triangular carrier wave according to the count value of the counter, a third counter that performs an increment or decrement operation and generates a predetermined dead time, and a target duty value supplied from an external control device; The count value of the first counter and the count value of the second counter supplied from the triangular wave conveyance control unit are respectively compared, and based on the comparison result, a dead time is generated by the third counter, Generates high-side and low-side PWM signals that form complementary pulse-width modulated waveform signals In pulse-width modulation waveform generator and a PWM waveform output controller for outputting,
The pulse width modulation waveform generation device starts from the state that “the high-side PWM signal is on and the low-side PWM signal is off” from “the high-side PWM signal is off and the low-side PWM signal is on”. The first dead time value corresponding to the time of “the high-side PWM signal is off and the low-side PWM signal is off” provided when changing to the state, “the high-side PWM signal is off” The low side PWM signal is turned on "to change from the state where the high side PWM signal is on and the low side PWM signal is off. The high side PWM signal is off. The second dead time value corresponding to the time in the state where the low-side PWM signal is OFF, and the period of the triangular carrier wave When the first dead time value is td1 and the second dead time value is td2, a first set value represented by (T + td1 + td2) / 2, a second set value represented by (T + td1−td2) / 2, and The target duty value is stored, the stored first set value and the second set value, and the stored first dead time are supplied to the triangular wave control unit as a third set value, and the stored A set value register for supplying the first dead time, the second dead time, and the target duty value to the PWM waveform output control unit;
The triangular carrier wave control unit provided in the pulse width modulation waveform generator sets and stores a counter mode value corresponding to the operating state of the first counter and the second counter, and the count value of the second counter The third set value is compared, and when the count value of the second counter matches the third set value, the first counter starts to increment from the count value zero and sets the counter mode value. And the count value of the first counter is compared with the first set value, and when the count value of the first counter matches the first set value, the increment operation of the first counter is stopped. The counter mode value is set, the count value of the first counter is compared with the second set value, and the count value of the first counter matches the second set value. The second counter starts to decrement from the first set value, sets the counter mode value, monitors the count value of the second counter, and the count value of the second counter is zero. The decrementing operation of the second counter is stopped and the counter mode value is set, and the count value of the first counter, the count value of the second counter, and the stored counter mode value are set to the PWM waveform. To the output controller,
The PWM waveform output control unit provided in the pulse width modulation waveform generator sets and stores a PWM output mode value associated with a complementary pulse width modulation waveform signal to be output, and changes the PWM output mode value. When the dead time operation is started, the PWM output mode value before the change is stored as a prior output mode value, and the dead time operation corresponding to the first dead time value or the second dead time value is indicated. The time mode value is set and stored, the counter mode value, the comparison result of the target duty value and the count value of the first counter, the comparison result of the target duty value and the count value of the second counter, the PWM output Based on the mode value, the advance output mode value, and the dead time mode value, the PWM output mode value, the advance output mode value m and renews the dead time mode value, a pulse width modulated waveform generator and outputs the complementary PWM waveform signal based on the PWM output mode value.   The pulse width modulation waveform generator according to claim 1, further comprising a PWM clock generator that generates a PWM clock signal used in the triangular carrier wave controller and the PWM waveform output controller, and the PWM clock generator The PWM clock mode command value for controlling the PWM clock mode is stored in the set value register, and the PWM clock generation unit generates a PWM clock signal according to the PWM clock mode command value output from the set value register, and the triangular carrier wave control And a PWM waveform output controller for supplying a pulse width modulation waveform.   The pulse width modulation waveform generator according to claim 2, further comprising a calculator that calculates the first set value and the second set value, wherein the first set value and the first set output from the calculator. 2 sets values are stored in the set value register, and the first set value and the second set value output from the set value register are supplied to the triangular carrier wave control unit, apparatus. 2. The pulse width modulation waveform generator according to claim 1, wherein the carrier wave period, the first dead time value, and the second dead time value are set, the triangular carrier control unit, and the PWM waveform output control unit. Generating means for generating a PWM clock signal, means for setting a PWM start signal for commanding start or stop of operation of the triangular carrier wave control unit and the PWM waveform output control unit, a first set value and a second set value And a means for setting the target duty value. A pulse width modulation waveform generator.

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