JP2010066914A - Integrated memory management device and memory management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily attain the optimization of a memory access operation by decreasing the number of memory hierarchies related with the access of a memory. <P>SOLUTION: The integrated memory management device 2 is provided with: a first MMU (Memory Management Unit) 7 of a processor 1 for converting a logical address showing the access destination of a cache 3 into a physical address; a cache controller 8 of a processor 1 for performing access to the cache 3 based on a physical address showing the access destination of the cache 3; a history storage part 10 of a processor 1 for storing history data showing an access status to a main memory 4 outside the processor 1; a relation storage part 23 of the processor 1 for storing relation data showing a relation between the logical address and the physical address in the main memory 4; and a second MMU 9 of the processor 1 for performing access to the main memory 4 based on the physical address by converting the logical address for performing access to the main memory 4 into the physical address based on the access history data and the address relation data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an apparatus and a memory management method for managing writing or reading with respect to a cache memory and a main memory.

  Conventionally, the management function of the NAND flash memory is implemented in a file system.

  When a cache memory is provided in an MPU (Micro Processing Unit), a DRAM (Dynamic Random Access Memory) is used as a main memory, and the MPU accesses a NAND flash memory, conventionally, the following is used: Operations along the memory hierarchy are performed.

  First, the MPU converts a logical address to a physical address and accesses a cache memory by using an MMU (Memory Management Unit).

  Here, the MPU accesses a DRAM which is a main memory for a part of data by virtual storage management of an operating system (OS).

  In addition, when the NAND type flash memory needs to be accessed, the MPU uses the flash file system to control avoiding defective blocks in the NAND type flash memory and to make all blocks of the NAND type flash memory accessible without any gaps. Control is performed to determine the physical position of the NAND flash memory.

  The MPU accesses the NAND flash memory based on the determined physical position.

  In the conventional MPU, as the number of memory hierarchies increases, operations included in different hierarchies increase, and it is difficult to perform optimization between operations in different hierarchies. For example, when the MPU replaces data in the cache memory, control such as performing bad block management peculiar to the NAND flash memory is difficult to implement because each operation belongs to a different memory hierarchy.

  Japanese Patent Laid-Open No. 2001-266580 discloses an invention that allows different types of semiconductor memory devices to be connected to a common bus.

The semiconductor memory device of Patent Document 1 includes a random access memory chip and a package including the random access memory chip. The package includes a plurality of pins that electrically connect the random access memory chip to an external device. The plurality of pins provide a memory function in common to the random access memory and the electrically erasable and programmable nonvolatile semiconductor memory. Each of the plurality of pins is arranged at a corresponding pin position of the nonvolatile semiconductor memory.
JP 2001-266580 A

  The present invention has been made in view of the above circumstances, and a memory management device and memory management for reducing the number of memory hierarchies related to memory access and easily realizing optimization of memory access operations. It aims to provide a method.

  An integrated memory management device according to a first aspect of the present invention includes a first memory management unit provided in a processor, which converts a logical address for accessing a cache memory into a physical address for accessing the cache memory, and A cache controller provided in the processor for accessing the cache memory based on a physical address for accessing the cache memory, and an access provided in the processor for storing access history data indicating an access state to the main memory outside the processor Based on the history storage unit, the address relationship storage unit provided in the processor for storing the address relationship data indicating the relationship between the logical address and the physical address in the main memory, the access history data and the address relationship data. And converting a logical address for accessing the main memory into a physical address for accessing the main memory, and accessing the main memory based on the physical address for accessing the main memory. 2 memory management units.

  An integrated memory management device according to a second aspect of the present invention includes: a first memory management unit provided in a processor that converts a logical address for accessing a cache memory into a physical address for accessing the cache memory; Storing an access history data indicating an access state to the main memory outside the processor; storing an access history storage unit provided in the processor; and storing address relation data indicating a relationship between a logical address and a physical address in the main memory. Provided in a processor that converts a logical address for accessing the main memory into a physical address for accessing the main memory based on the provided address relation storage unit, the access history data, and the address relation data. Second menu A cache controller provided in a processor for accessing the cache memory based on the physical address for accessing the re-management unit and the cache memory, and accessing the main memory based on the physical address for accessing the main memory It comprises.

  An integrated memory management device according to a third aspect of the present invention includes an acquisition unit that acquires a read destination logical address from a first processor included in at least one processor, and a read destination logic acquired by the acquisition unit. Address conversion means for converting the address into a read destination physical address of the nonvolatile main memory, and data corresponding to the read destination physical address of an integer multiple of the page size of the nonvolatile main memory or the block size are read from the nonvolatile main memory. Access means and transfer means for transferring the read data to the cache memory of the first processor having a cache size depending on an integer multiple of the page size of the nonvolatile main memory or the block size.

  The integrated memory management device according to the fourth aspect of the present invention is divided into an area having a plurality of group attributes, and is included in at least one processor and a nonvolatile main memory that holds each group attribute as memory specific information. Acquisition means for acquiring a write destination logical address from the first processor, and address conversion means for converting the write destination logical address acquired by the acquisition means into a write destination physical address of the nonvolatile main memory. . The address conversion means refers to the data-specific read / write frequency information defined by the file management program operating on the first processor and the memory-specific information, and within the group attribute area corresponding to the data-specific read / write frequency information Is associated with the write destination physical address.

  The memory management method according to the fifth aspect of the present invention includes an access history data indicating an access state to a nonvolatile main memory outside the processor, a logical address and a physical in the nonvolatile main memory by an integrated memory management device provided in the processor. The address relation data indicating the relation with the address is referred to, and the logical address for accessing the nonvolatile main memory is determined by the integrated memory management device based on the access history data and the address relation data. It converts into the physical address for access, and accesses a non-volatile main memory based on the physical address for accessing a non-volatile main memory.

  In the memory management method according to the sixth aspect of the present invention, a read destination logical address is acquired from a first processor included in at least one processor by an integrated memory management device, and acquired by the integrated memory management device. The read destination logical address is converted into a read destination physical address of the nonvolatile main memory, and the unified memory management device converts the read destination physical address from the nonvolatile main memory to an integer multiple of the page size of the nonvolatile main memory or a block size. The data corresponding to the address is read, and the data read by the integrated memory management device is transferred to the cache memory of the first processor having a cache size that depends on an integer multiple of the page size of the nonvolatile main memory or the block size. Forward.

  According to the present invention, the number of memory hierarchies related to memory access can be reduced, and optimization of memory access operation can be easily realized.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, substantially or substantially the same functions and components are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
The integrated memory management device (flat memory management device) of the present embodiment is provided in the MPU and performs memory management for the cache memory and the main memory. The integrated memory management device can reduce the number of memory hierarchies related to memory access and easily realize optimization of memory access.

  In this embodiment, an integrated memory management device that integrates an MPU MMU, an MPU cache controller, and a main memory MMU will be described.

  FIG. 1 is a block diagram showing an example of an integrated memory management device according to the present embodiment. In this embodiment, the case where the main memory is a NAND flash memory will be described as an example. However, other storage devices may be used. In this embodiment, the access includes at least one of reading and writing of data (or program).

  The MPU 1 includes an integrated memory management device 2 and accesses the NAND flash main memory 4.

  The NAND flash main memory 4 stores therein an address conversion table 5 and rewrite count data 6. The rewrite count data 6 corresponds to main memory history data indicating the access state of the main memory.

  The address conversion table 5 is data in which a logical address and a physical location or a physical address in the NAND flash main memory 4 are associated with each other.

  The rewrite count data 6 represents the rewrite count of each page or block of the NAND flash main memory 4.

  The integrated memory management device 2 includes an MMU 7, a cache controller 8, a primary cache memory 3, a secondary cache memory 22, a main memory MMU 9, and an access history storage unit (NAND Information Registers) 10. The cache controller 8 also includes a first cache controller 8 a for the primary cache memory 3 and a second cache controller 8 b for the secondary cache memory 22. Further, the main memory MMU 9 includes an address relation storage unit 23. The main memory MMU 9 and the address relation storage unit 23 may be separated.

  In this embodiment, a case where there are two cache memories will be described as an example, but the number of cache memories may be one or three or more.

  The MMU 7 converts the logical address of the cache memory 3 into a physical address.

  The primary cache memory 3 has a tag storage area 3a and a line storage area 3b.

  The secondary cache memory 22 has a tag storage area 22a and a line storage area 22b.

  In the present embodiment, the line size of the primary cache memory 3 and the line size of the secondary cache memory 22 are the same size (for example, 256 kilobytes) as the block of the NAND flash main memory 4 or the NAND flash main memory 4 The size is a multiple of the page size. As a result, the operation of moving the data in the NAND flash main memory 4 to the primary cache memory 3 or the secondary cache memory 22 and the data in the primary cache memory 3 or the secondary cache memory 22 to the NAND flash main memory 4 are performed. The movement operation can be performed in units of pages, in units of integer multiples of the page size, or in units of blocks, and data movement can be simplified.

  In the present embodiment, it is assumed that the primary cache memory 3 and the secondary cache memory 22 are, for example, a write-back type. The secondary cache memory 22 has a larger storage capacity than the primary cache memory, but is slower.

  The first cache controller 8 a controls access to the primary cache memory 3.

  More specifically, when the first cache controller 8a reads data from the primary cache memory 3, the data corresponding to the physical address in the primary cache memory 3 along the physical address obtained from the MMU 7 is used. Is read. Further, when writing data to the primary cache memory 3, the first cache controller 8 a writes data at a position corresponding to the physical address in the primary cache memory 3 along the physical address obtained from the MMU 7. Write the data.

  The second cache controller 8b controls access to the secondary cache memory 22.

  More specifically, when the second cache controller 8b reads data from the secondary cache memory 22, the data corresponding to the physical address in the secondary cache memory 22 along the physical address obtained from the MMU 7 is read. Is read. Further, when writing data to the secondary cache memory 22, the second cache controller 8b writes data at a position corresponding to the physical address in the secondary cache memory 22 along the physical address obtained from the MMU 7. Write the data.

  The main memory MMU 9 controls access to the NAND flash main memory 4.

  The main memory MMU 9 stores part or all of the address conversion table 5 of the NAND type flash main memory 4 in the address relation storage unit 23 as address relation data as necessary. Further, the main memory MMU 9 stores a part or all of the rewrite count data 6 of the NAND flash main memory 4 in the access history storage unit 10 as access history data as necessary.

  The main memory MMU 9 converts the logical address of the NAND flash main memory 4 into a physical position.

  The main memory MMU 9 reads data from the NAND flash main memory 4 based on the physical position of the NAND flash main memory 4, and passes through the first cache controller 8a or the second cache controller 8b. Data is stored in the primary cache memory 3 or the secondary cache memory 22.

  When the main memory MMU 9 reads new data from the NAND flash main memory 4, it reads the address conversion table data and rewrite count data related to the new data, and stores the address relationship storage unit 23 and the access history, respectively. Store in the storage unit 10.

  When the main memory MMU 9 writes data to the NAND flash main memory 4, the NAND type flash main memory 4 is configured to access all areas or all blocks of the NAND flash main memory 4 based on the address-related data and the access history data. Control for equalizing the number of rewrites of each area or block of the flash main memory 4 and control for avoiding a defective area or a defective block are performed. Further, the main memory MMU 9 acquires the data stored in the primary cache memory 3 or the secondary cache memory 22 via the first cache controller 8a or the second cache controller 8b, and acquires the acquired data. Data is stored in the NAND flash main memory 4 based on the physical position of the NAND flash main memory 4.

  When the data is written in the NAND flash main memory 4, the main memory MMU 9 updates the address relation data in the address relation storage unit 23 based on the relation between the logical address and the physical position relating to the written data, Further, the access history data in the access history storage unit 10 is updated.

  The main memory MMU 9, if necessary, converts the address related data stored in the main memory MMU 9 and the access history data stored in the access history storage unit 10 into addresses of the NAND flash main memory 4. This is reflected in the conversion table 5 and the rewrite count data 6. That is, the main memory MMU 9 matches the address relation data stored in the MPU 1 with the address conversion table 5 stored in the NAND flash main memory 4. The main memory MMU 9 matches the access history data in the access history storage unit 10 with the rewrite count data 6 in the NAND flash main memory 4.

  The access history storage unit 10 stores a history of access states of pages or blocks (physical positions) of the NAND flash main memory 4. In the present embodiment, the access history storage unit 10 stores the rewrite frequency data for some or all pages or blocks of the rewrite frequency data 6 for each page or block in the NAND flash main memory 4.

  For example, the rewrite count of each block is recorded as 4 bytes, and each block size is 256 kilobytes. In this case, assuming that the storage capacity of the NAND flash main memory 4 is 1 megabyte, the number of blocks stored in the NAND flash main memory 4 is 4, and is necessary for storing the number of rewrites of each block. The storage capacity is 16 bytes. In the same case, if the storage capacity of the NAND flash main memory 4 is 1 gigabyte, the number of blocks stored in the NAND flash main memory 4 is 4096 blocks, and the number of rewrites of each block is stored. The required storage capacity is 16 kilobytes. Furthermore, in the same case, assuming that the storage capacity of the NAND flash main memory 4 is 16 gigabytes, the storage capacity necessary for storing the number of rewrites of each block is 64 kilobytes.

  For example, when the storage capacity of the NAND flash main memory 4 becomes large, for example, 128 gigabytes, the access history storage unit 10 stores a part of the rewrite count data 6 in the NAND flash main memory 4. In this way, since the access history storage unit 10 stores a part of the rewrite count data 6, pos is added to the rewrite count. pos is used in the same manner as a cache tag.

  An outline of an operation example of the main memory MMU 9 will be described.

  The main memory MMU 9 stores a part of the address conversion table 5 of the NAND flash main memory 4 in the address relation storage unit 23 and a part of the rewrite count data 6 in the access history storage unit 10.

  The main memory MMU 9 does not store data to be read in the cache memories 3 and 22, and reads data from the NAND flash main memory 4 when reading data from the NAND flash main memory 4. The main memory MMU 9 stores the data related to the read data in the address conversion table 5 in the address relation storage unit 23. The main memory MMU 9 stores data related to the read data among the rewrite count data 6 in the access history storage unit 10.

  When writing data from the MPU 1 to the NAND flash main memory 4, the main memory MMU 9 converts the logical address in the NAND flash main memory 4 into a physical location, and converts the data to be written in the cache lines 3 b and 22 b. Write to the NAND flash main memory 4. In addition, the main memory MMU 9 updates the address relationship data stored in the address relationship storage unit 23 and the access history data stored in the access history storage unit 10.

  Then, the main memory MMU 9 updates the address conversion table 5 and the rewrite count data 6 based on the address relation data in the address relation storage unit 23 and the access history data in the access history storage part 10, respectively.

  For example, when the primary cache memory 3 is read only, there is no writing from the MPU 1 to the cache line 3b. In this case, the main memory MMU 9 overwrites the primary cache memory 3 with the data read from the NAND flash main memory 4 by using the first cache controller 8a. When the data stored in the primary cache memory 3 is read, the first cache controller 8 a reads the data from the primary cache memory 3.

  On the other hand, when the primary cache memory 3 is not read-only, the MPU 1 writes data obtained by executing the program to the cache memory 3. When data is written from the MPU 1 to the cache line 3b, the data on the cache line 3b is written back to the NAND flash main memory 4. In this case, the main memory MMU 9 reads the data to be written back from the cache memory 3 via the first cache controller 8a. Then, the MMU 9 for main memory selects a page or block having a smaller number of rewrites than a predetermined number as a write back position in the NAND flash main memory 4 based on the access history data in the access history storage unit 10. The main memory MMU 9 stores data to be written back to the selected page or block, and shows the conversion relationship between the logical address and the physical position for the NAND flash main memory 4 for the selected page or block. The address relation data is updated, and the number of rewrites in the access history storage unit 10 is updated for the selected page or block.

  Thereafter, the address conversion table 5 and the rewrite count data 6 are updated according to the contents of the address relation storage unit 23 and the access history storage unit 10 as necessary.

  FIG. 2 is a diagram illustrating an example of a memory hierarchy of the integrated memory management device 2 according to the present embodiment.

  The memory hierarchy in this example has a hierarchy to which the MMU 7 belongs and a hierarchy to which the main memory MMU 9 and the cache controller 8 belong.

  In the hierarchy of the MMU 7, the logical address is converted into a physical address.

  In the hierarchy to which the main memory MMU 9 belongs, for example, the physical location or physical address of the NAND flash main memory 4 to be accessed is determined. In the hierarchy to which the main memory MMU 9 belongs, control is performed to access a page or block whose write count is equal to or less than a predetermined number (for example, the minimum).

  Then, the integrated memory management device 2 accesses the NAND flash main memory 4 based on the determined physical position.

  FIG. 3 shows a case where the MPU 1 provided with the integrated memory management device 2 according to the present embodiment stores data of the NAND flash main memory 4, part of the rewrite count data 6, and part of the address conversion table 5. It is a flowchart which shows an example of operation | movement.

  In step S1, the MMU 9 for main memory reads part of the data of the NAND flash main memory 4 used by the MPU 1 (initially, it may be 1 gigabyte from the beginning). The cache controller 8 writes the read data to the cache lines 3 b and 8 b of the cache memories 3 and 8.

  In step S2, the MMU 9 for main memory uses a part of the rewrite count data 6 stored in the NAND flash main memory 4 (such as the block rewrite count for the data stored in the cache memories 3 and 8, etc. 1 gigabyte or the like from the head may be copied to the access history storage unit 10 in the MPU 1.

  In step S3, the MMU 9 for main memory uses a part of the address conversion table 5 stored in the NAND flash main memory 4 (the logical address and physical position of the block corresponding to the data stored in the cache memories 3 and 8). (First, it may be 1 gigabyte from the beginning) is copied to the address relationship storage unit 23 of the main memory MMU 9 in the MPU 1.

  In addition, these steps S1-S3 may be performed in a free order and may be performed in parallel.

  FIG. 4 is a flowchart showing an example of an operation when data is read from the primary cache memory 3 or the NAND flash main memory 4 in the MPU 1 provided with the integrated memory management device 2 according to the present embodiment. The case of reading data from the secondary cache memory 22 is the same as that of the primary cache memory 3.

  In step T1, the MMU 7 and the main memory MMU 9 convert the logical address to be read into a physical address.

  When the physical address to be read indicates the primary cache memory 3, in step T2a, the first cache controller 8a reads the data to be read from the primary cache memory 3 based on the physical address.

  When the physical address (physical position) to be read indicates the NAND flash main memory 4, the main memory MMU 9 reads data corresponding to the physical address from the NAND flash main memory 4 in step T2b.

  In Step T3b, the main memory MMU 9 overwrites the primary cache memory 3 with the data read from the NAND flash main memory 4 via the first cache controller 8a.

  Note that the main memory MMU 9 is NAND-type when the address-related data and the access history data corresponding to the data newly read from the NAND flash main memory 4 are not stored in the address-related storage unit and the access history storage unit, respectively. Data corresponding to the newly read data is stored in the address relation storage unit and the access history storage unit based on the address conversion table 5 and the rewrite count data 6 of the flash main memory 4.

  FIG. 5 shows that overwriting to the cache line 3b of the primary cache memory 3 occurs from the MPU 1 provided with the integrated memory management device 2 according to the present embodiment, and the data in the primary cache memory 3 is further transferred to the NAND flash main. 5 is a flowchart showing an example of an operation when storing in a memory 4; The case where overwriting to the secondary cache memory 22 occurs is the same as in the case of the primary cache memory 3.

  In step U1, the MMU 7 performs conversion from a logical address to a physical address.

  In step U2, the first cache controller 8a stores the write target data in the primary cache memory 3 according to the physical address.

  In step U3, the MMU 9 for main memory uses the address relation data in the address relation storage unit 23 and the access history data in the access history storage part 10 to determine the position of the block having the smaller number of rewrites or the most rewritten number. The positions of few blocks are selected as write positions in the NAND flash main memory 4.

  In step U4, the main memory MMU 9 stores the data to be written at the selected position in the NAND flash main memory 4.

  In step U5, the main memory MMU 9 updates the address relationship data in the address relationship storage unit 23 and updates the access history data in the access history storage unit 10 so as to correspond to the cache line 3b after overwriting.

  In step U6, the main memory MMU 9 updates the address conversion table 5 of the NAND flash main memory 4 so as to be consistent with the address relation data stored in the main memory MMU 9, and the access history storage unit 10 The rewrite count data 6 of the NAND flash main memory 4 is updated so as to be consistent with the address history data stored in the memory. For example, the rewrite count data of the NAND flash main memory 4 is updated when the MPU 1 is powered off or when the access history storage unit 10 of the MPU 1 is rewritten.

  In the present embodiment, the integrated memory management device 2 selects a physical position of a block to be rewritten based on the number of rewrites. However, instead of this, the integrated memory management device 2 performs control to avoid a defective area or block, control to access all areas or all blocks of the NAND flash main memory 4 without any separation, and position of an access destination area or block It is also possible to perform control so as to be distributed. In this case, the access history storage unit 10 stores data such as the occurrence positions of defective areas or defective blocks stored in the NAND flash main memory 4 and the distribution of rewrite positions in the NAND flash main memory 4. In addition, the integrated memory management device 2 may select a region or a block position to be rewritten by freely combining various controls.

  In the present embodiment, the integrated memory management device 2 may perform control for garbage collection processing or erasure of the NAND flash main memory 4 when data in the cache memory 3 is exchanged.

  In the present embodiment, at least one of the address relationship storage unit 23 and the access history storage unit 10 of the main memory MMU 9 may store data using a secondary cache memory. That is, the address relation data stored in the address relation storage unit 23 may be stored in the secondary cache memory 22. Further, the access history data including the number of times of writing stored in the access history storage unit 10 may be stored in the secondary cache memory 22.

  In the integrated memory management device 2 of the MPU 1 according to the present embodiment, the physical location of the NAND flash main memory 4 to be written is selected using the data stored in the access history storage unit 10, and the write is performed. A back-up algorithm can be employed and a program that executes this algorithm can be used. For example, it is possible to use an advanced algorithm such as avoiding rewriting of a region or block having a large number of rewrites.

  In the integrated memory management device 2 according to the present embodiment described above, within the MPU 1, the MMU 7, the first cache controller 8a, the first cache controller 8b, the cache memory 3, the cache memory 22, the main memory MMU 9, A configuration in which the access history storage unit 10 is integrated is employed. That is, in the present embodiment, an architecture is realized in which the memory mapping management of the NAND flash main memory 4 is executed by the integrated memory management device 2 of the MPU 1.

  Thereby, a hierarchy with a large overhead can be deleted in the memory hierarchy.

  In the present embodiment, the operation of a memory controller provided in a general NAND flash memory is executed on the MPU 1 side. Thus, memory control can be coordinated by combining the operation of the MPU and the operation of the memory controller and executing them in the MPU 1.

  In this embodiment, it is possible to simplify the multi-layered memory hierarchy, and it is possible to reduce various costs such as time required for access, time required for manufacturing, and cost required for manufacturing. .

  In this embodiment, since the memory hierarchy is simplified, it is easy for the programmer to grasp where the MMU conversion and cache memory replacement occur, and program optimization can be performed easily. it can.

  In the present embodiment, optimization can be easily realized between the cache operation of the MPU 1 and the access operation of the main memory.

(Second Embodiment)
In the present embodiment, a modification of the first embodiment will be described.

  FIG. 6 is a block diagram showing an example of the integrated memory management device according to the present embodiment.

  The MPU 11 is provided with an integrated memory management device 12 according to the present embodiment. The integrated MMU 13 implements a function that integrates the MMU 7 and the main memory MMU 9 according to the first embodiment.

  In the present embodiment, the tag of the primary cache memory 3 and the tag of the secondary cache memory 22 are used for managing the primary cache memory 3 and the secondary cache memory 22 with the process ID and the logical address, respectively. .

  In the present embodiment, the memory mapping management of the primary cache memory 3, the secondary cache memory 22, and the NAND flash main memory 4 is performed by the integrated MMU 13 of the MPU 11, which is a processor, and various memories are collectively managed. .

  FIG. 7 is a diagram showing an example of a memory hierarchy of the integrated memory management device 12 according to the present embodiment.

  In the memory hierarchy in this example, the integrated MMU 13 and the cache controller 8 belong to the same hierarchy. The integrated memory management device 12 integrates address conversion for the primary cache memory 3 and the secondary cache memory 22 and address conversion for the NAND flash main memory 4 and handles them in an equivalent memory hierarchy. The integrated memory management device 2 determines which area of the cache memory 3, the cache memory 22, and the NAND flash main memory 4 is to be accessed according to a certain standard.

  In this memory hierarchy, when a logical address is converted into a physical position of the NAND flash main memory 4, control is performed to access an area or block whose number of writings is a predetermined number or less.

  Then, the integrated memory management device 2 accesses the NAND flash main memory 4 based on the determined physical position.

  In the present embodiment described above, the configuration is simplified by integrating the MMU 7 according to the first embodiment and the MMU 9 for main memory, the time cost required for access, and the economy required for manufacturing. Various costs such as cost can be reduced.

  By using the integrated MMU 13, the address conversion for the primary cache memory 3 and the secondary cache memory 22 and the address conversion for the NAND flash main memory 4 can be integrated. For example, high-speed access is possible by storing the storage contents related to a certain process as close to the NAND flash main memory 4 as possible. Further, for example, it is possible to select only an area or block with a small number of rewrites and assign it to one process.

(Third embodiment)
In the present embodiment, a modified example of the integrated memory management devices 2 and 12 according to the first or second embodiment will be described.

  FIG. 8 is a diagram showing a modification of the integrated memory management device 2 according to the first embodiment shown in FIG.

  In the first embodiment, the access to the NAND flash main memory 4 based on the physical position is executed by the main memory MMU 9. However, the cache controller 8 may access the NAND flash main memory 4 based on the physical position.

  In this case, the main memory MMU 9 performs control to convert the logical address into a physical location, and the cache controller 8 accesses the NAND flash main memory 4 based on the physical location selected by the main memory MMU 9. . In this embodiment, the cache controller 8 may read and update the address conversion table 5 of the NAND flash main memory 4 and read and update the rewrite count data 6 in place of the main memory MMU 9. .

  FIG. 9 is a diagram showing a modification of the integrated memory management device 12 according to the first embodiment shown in FIG.

  In the second embodiment, the access to the NAND flash main memory 4 based on the physical position is executed by the integrated MMU 13. However, the cache controller 8 may access the NAND flash main memory 4 based on the physical position.

  In this case, the integrated MMU 13 performs control to convert the logical address into a physical location, and the cache controller 8 accesses the NAND flash main memory 4 based on the physical location selected by the integrated MMU 13. In the present embodiment, the cache controller 8 may read and update the address conversion table 5 of the NAND flash main memory 4 and read and update the rewrite count data 6.

(Fourth embodiment)
In the present embodiment, application examples of the integrated memory management devices 2 and 12 according to the first to third embodiments will be described.

  FIG. 10 is a block diagram illustrating an application example of the integrated memory management device according to the present embodiment.

  For example, in a game machine or a car navigation system, data or a program read by a disk drive is written once in the main memory, and then the data or program written in the main memory is read many times. In the present embodiment, the case where the integrated memory management device 20 is applied to a game machine will be described, but the same applies to the case where it is applied to other devices such as a car navigation system. Instead of the integrated memory management device 20, the integrated memory management devices 2 and 12 according to the first embodiment may be used.

  The portable game console processor 14 includes a graphics processor 15 and a processor 16.

  The graphics processor 15, processor 16, secondary cache memory 17, NAND flash main memory 4, and disk drive 18 are connected to a bus 19.

  The processor 16 includes a secondary cache tag 21 for accessing the primary cache memory 3 and the secondary cache memory 17, a cache controller 8, and an integrated MMU 13.

  Further, the processor 16 includes a rewrite count storage unit 10, which is omitted in FIG. The processor 16 may use the primary cache memory 3 or the secondary cache memory 17 as the rewrite count storage unit 10.

  The cache controller 8 controls access to the primary cache memory 3 and the secondary cache memory 17. For example, a DRAM can be used as the secondary cache memory 17. In the present embodiment, the secondary cache memory 17 is separated from the portable game console processor 14.

  The bandwidth for the secondary cache memory 17 is about 10 times that of the NAND flash main memory 4. As the disk drive 18, for example, an optical disk drive can be used.

  In the present embodiment, writing to the NAND flash main memory 4 is performed when the game cartridge is replaced, and the NAND flash main memory 4 is used read-only at other times. Frequently written data or program code and frequently read data or program code are stored in the secondary cache memory 17. Further, frequently read data or program code is stored in the primary cache memory 3.

  For example, among data or program codes stored in the primary cache memory 3 or the secondary cache memory 17, data or program codes that are not frequently used are written in the NAND flash main memory 4, and the NAND flash main memory Of the data or program code stored in the memory 4, data or program code that is frequently used may be stored in the primary cache memory 3 or the secondary cache memory 17.

  In the present embodiment, for example, the primary cache memory 3 is about 64 kilobytes, the secondary cache memory 17 is about 16 to 128 megabytes, and the NAND flash main memory 4 is about 1 gigabyte.

  For example, the processing capacity of the graphics processor 15 matches the speed of the NAND flash main memory 4 having a 1/10 bandwidth, or is about two to three times the capacity. It is assumed that infrequently used data is read from the NAND flash main memory 4 and frequently used data is read from the primary cache memory 3 or the secondary cache memory 17.

  In the present embodiment, it is possible to provide a processor 16 capable of realizing optimization such as garbage collection processing or erasing of the NAND flash main memory 4 at the time of cache replacement (cache miss or the like). And advanced optimization can be performed.

  If the entry size of the secondary cache memory 17 is about 1 megabyte, compatibility with the NAND flash main memory 4 is improved.

  In the present embodiment, it is possible to prevent the overhead from being increased due to, for example, double virtual memory conversion.

  In the present embodiment, the integrated MMU 13 is provided in the processor 16, whereby the primary cache memory 3, the secondary cache memory 17, and the NAND flash main memory 4 can be collectively managed.

  In this embodiment, the amount of data to be saved at the time of resume can be reduced.

  In the present embodiment, by storing data or programs in the NAND flash main memory 4, it is possible to reduce access to the disk drive 18, reduce waiting time, and improve user operability and satisfaction. Can do.

  In the present embodiment, more data or programs can be accessed at high speed by using the NAND type flash main memory 4 whose unit cost is lower than that of the secondary cache memory 17 (DRAM).

(Fifth embodiment)
In the present embodiment, an integrated memory management device provided between the processor and the main memory will be described.

  FIG. 11 is a block diagram showing an example of the integrated memory management device according to the present embodiment.

  The integrated memory management device 24 according to the present embodiment is connected to a plurality of processors (including, for example, Codec IP and Graphic IP) 251 to 254 via the system bus 30. The integrated memory management device 24 is applied to a multiprocessor configuration. The integrated memory management device 24 is connected to a nonvolatile main memory 26 such as a NAND flash memory. In the present embodiment, the number of processors can be freely changed by 1 or 2 or more.

  In the main memory 26, writing and reading are performed in units of a plurality of bits called pages. Erasing is performed in a batch called a block, which is a unit of a plurality of pages.

  Some of the plurality of processors 251 to 254 execute processes including logical addresses. In this example, processes 271, 272, and 274 are executed by the processors 251, 252, and 254. Note that the processes 271, 272, and 274 may be operating systems.

  Each of the plurality of processors 251 to 254 includes primary cache memories 281 to 284 and secondary cache memories 291 to 294.

  The integrated memory management device 24 performs wear leveling and conversion from a logical address to a physical address.

  The integrated memory management device 24 performs wear leveling in units of pages of the main memory 26, in units of integer multiples of the page size, or in units of blocks. The wear leveling counter is stored in the redundancy area 26a of the main memory. The redundancy area 26 a is a redundant area provided for each page or block of the main memory 26. The integrated memory management device 24 secures memory in consideration of wear leveling when mapping to the memory space.

  The integrated memory management device 24 treats the removable memory as the main memory and maps it to the memory space.

  The integrated memory management device 24 is provided on the main memory 26 side rather than the plurality of processors 271 to 274 side. However, the integrated memory management device 24 may be provided on the plurality of processors 271 to 274 side.

  The integrated memory management device 24 switches the page size between an instruction and data. For example, the instruction page size is set to a small size such as 16 kilobytes, and the data page size is set to a large size such as 512 kilobytes.

  The main memory 26 has the same memory page size as the page size (process or OS) of the integrated memory management device 24 or a memory page size that is a multiple of the page size of the integrated memory management device 34.

  Page transfer is performed collectively between the primary cache memories 281 to 284 and the secondary cache memories 291 to 294 and the main memory 26. This batch transfer is performed, for example, in units of main memory pages, integer multiples of the page size, or block units (for example, 256 kilobytes to 512 kilobytes).

  Access to the primary cache memories 281 to 284 and access to the secondary cache memories 291 to 294 are performed based on logical addresses. A logical address is also used on the system bus 30.

  The unified integrated memory management device 24 converts a plurality of processors 271 to 274 from a process level logical address to a physical address, and further, a page unit of the main memory 26, an integer multiple of a page size, or a block. The conversion from the logical page or logical block to the physical page or physical block for wear leveling in units is comprehensively performed.

  In the present embodiment, a system logical address 31 having the format shown in FIG. 12 is used. The system logical address 31 includes a processor ID, a process ID, and an in-process logical address. Note that at least one of the processor ID and the process ID is converted (for example, the length of the ID is shortened by using hashing or the like), and the system logical address 31 may include the content after conversion. For example, the processor ID and the process ID may be converted by hashing, and the system logical address 31 may include the bit converted by the hashing and the in-process logical address.

  The main memory 26 stores a single page table 26b for the entire system. That is, the main memory 26 does not have a page table for each of the processes 271, 272, and 274, but has a page table 26b that is unified throughout the processes 271, 272, and 274.

  In the present embodiment, the main memory 26 having the same capacity as a hard disk drive (HDD) is used as the main memory 26. In this case, it is not necessary to use secondary storage (swap out) in order to use a larger memory space than physical memory. Conventionally, the physical main memory is, for example, a DRAM and the storage capacity is about 1 GB. However, when a 4 GB logical memory space is to be used for each process, a secondary storage area is provided on a hard disk drive having a larger storage capacity. It was necessary to secure and swap-in / swap-out. However, in this embodiment, since the main memory 26 has a storage capacity equal to or higher than that of the hard disk drive, it is not necessary to use secondary storage.

  Therefore, the apparatus configuration and operation can be simplified.

  In the present embodiment, instant ON / OFF can be performed, and the speed of resume or the like can be increased.

  In the past, it was necessary to load a file before execution. On the other hand, in this embodiment, it is only necessary to jump to the execution address on the cache memories 281 to 284, 291 to 294 or the main memory 26, and it is not necessary to load a file before executing.

(Sixth embodiment)
In the present embodiment, a modification of the fifth embodiment will be described.

  FIG. 13 is a block diagram illustrating an example of a storage device according to this embodiment.

  In the storage device according to the present embodiment, the plurality of integrated memory management devices 241 and 242 are connected to a plurality of processors (including Codec IP and Graphic IP) 251 to 254 via the network 33. The integrated memory management devices 241 and 242 are connected to a plurality of nonvolatile main memories 261 and 262 such as NAND flash memories, for example.

  The number of integrated memory management devices and the number of main memories can be freely changed.

  The main memory 261 has the same characteristics as the main memory 26 in the fifth embodiment, and has a redundancy area 261a for storing a wear leveling counter and a page table 261b unified for the entire processes 271, 272, and 274. The main memory 262 has the same characteristics as the main memory 261.

  As shown in FIG. 14, the logical address 34 used in the present embodiment includes an IP address or IPv6 address of the network 33, a processor ID and a process ID, and an in-process logical address. Note that at least one of each address and ID is converted (for example, the length of the ID is shortened using hashing or the like), and the logical address 34 may include the content after conversion. For example, the IP address or the IPv6 address, the processor ID and the process ID may be converted by hashing, and the logical address 34 may include the bit converted by the hashing and the in-process logical address.

  The main memories 261 and 262 have the same memory page size as the page size of the integrated memory management devices 241 and 242 or a memory page size that is an integral multiple of the page size of the MMUs 241 and 242.

  Page transfer is performed in a batch between the primary cache memories 281 to 284 and the secondary cache memories 291 to 294 and the main memories 261 and 262. This batch transfer is performed, for example, in page units of the main memory, integer multiples of the page size, or block units (for example, 256 kilobytes to 512 kilobytes).

  In the present embodiment, access to the primary cache memories 281 to 284 and access to the secondary cache memories 291 to 294 are executed based on logical addresses. Logical addresses are also used on the network 33.

  The unified integrated memory management devices 241 and 242 convert a plurality of processors 271 to 274 from process level logical addresses to physical addresses, and further, page units and page sizes of the nonvolatile main memories 261 and 242. The conversion from a logical page or logical block to a physical page or physical block for wear leveling in an integer multiple unit or block unit is comprehensively performed.

  In the present embodiment, an effect similar to that of the fifth embodiment can be obtained in a vast memory space via the network 33.

(Seventh embodiment)
In the present embodiment, modified examples of the fifth and sixth embodiments will be described. In the following, a modification of the fifth embodiment will be described, but the sixth embodiment can be similarly modified.

  FIG. 15 is a block diagram illustrating an example of the integrated memory management device according to the present embodiment.

  The plurality of processors 351 to 354 are connected to the main memory 26 via the system bus 30. In the present embodiment, the number of processors can be freely changed.

  In some of the plurality of processors 351 to 354, a process including a logical address is executed. In this example, processes 271, 272, and 274 are executed by the processors 351, 352, and 354. Processes 271, 272, and 274 may be operating systems.

  Each of the plurality of processors 351 to 354 includes primary cache memories 361 to 364, secondary cache memories 371 to 374, and integrated memory management devices 381 to 384.

  The integrated memory management devices 381 to 384 perform wear leveling and conversion from a logical address to a physical address. The integrated memory management devices 381 to 384 are provided on the plurality of processors 351 to 354 side.

  The main memory 26 has a memory page size that is the same as the page size of the integrated memory management devices 381 to 384 or an integer number of the page size of the integrated memory management devices 381 to 384.

  Page transfer is performed collectively between the primary cache memories 361 to 364 and the secondary cache memories 371 to 374 and the main memory 26. This batch transfer is performed, for example, in blocks (an integer multiple of a page) of the main memory (for example, 256 kilobytes to 512 kilobytes).

  In the present embodiment, physical addresses are used for access to the primary cache memories 361 to 364 and access to the secondary cache memories 371 to 374. A physical address is also used on the system bus 30.

  The integrated memory management devices 381 to 384 provided for each of the plurality of processors 351 to 354 convert process level logical addresses to physical addresses, and further, in units of pages of the main memory 26, in units of integer multiples of pages, or in units of blocks. Conversion from a logical page or logical block for wear leveling to a physical page or physical block is performed.

  In the present embodiment described above, even when the integrated memory management devices 381 to 384 are provided on the processors 351 to 354 side, the same effect as the fifth aspect can be obtained.

(Eighth embodiment)
In the present embodiment, details of the fifth embodiment will be described.

  FIG. 16 is a block diagram showing an example of the configuration of the integrated memory management device 24 according to the present embodiment.

  The NAND flash main memory 26 includes a physical block 39 corresponding to a physical address, a page table 26b, memory usage information 40, and memory specific information 41.

  The cache line sizes of the primary cache memories 281 to 284 and the secondary cache memories 291 to 294 of each of the processors 251 to 254 and the integer multiple of the block size or page size of the NAND flash main memory 26 are the same size. Data transfer efficiency is improved.

  In the NAND flash main memory 26, various data may exist across a plurality of physical blocks 39, for example, data D1. Further, for example, a plurality of data may exist in one physical block 39, such as a plurality of data D1 and D2.

  Each data D1, D2 may have unique read / write frequency information E1, E2. For example, each data D1 and D2 includes at least one of static information and dynamic information. The static information is a value determined from the beginning. The dynamic information includes the number of times the data has been actually rewritten and the number of times the data has been read.

  For example, as static information of image data of a digital camera, information that reading and writing are performed once every two hours immediately after being photographed, reading is performed once every two weeks after three days have passed since photographing, Information not to be performed is stored. In addition, for example, as static information of cache information of a web browser, information that writing and reading are performed once every several minutes, information that information of sites accessed for a certain degree or more is written once a day, cycle If there is a specific access pattern, information indicating that the information is written, information indicating that there are many writes in a predetermined time, and the like are stored.

  The static information needs to be set to an effective value for various types of data. The static information setting file may be shared on the network.

  There may be only one page table 26b in all systems. Alternatively, the page table 26b may not be provided.

  The memory usage information 40 includes the number of times of reading / writing of each memory area and the number of times of reading / writing of each data. More specifically, for example, the memory usage information 40 includes, for each memory area (page or block), the number of rewrites, the number of reads, the data information existing in this area (number, type, number of reads specific to each data, Including the number of rewrites).

  The memory unique information 41 includes the page size, block size, the number of rewritable times, the number of readable times, etc. of the NAND flash main memory 26. More specifically, for example, the memory specific information 41 includes the page size, block size, total storage capacity, and SLC (Single Level Cell) area information (block position, size, number of reads possible, write) of the NAND flash main memory 26. MLC (Multi Level Cell) area information (including block position, size, number of times of reading, number of times of writing, etc.).

  The integrated memory management device 24 converts the logical address for each process (which may be an OS) into a physical address, and converts the logical address for the NAND flash main memory 26 into a physical address.

  Further, the memory management device 24 performs optimum wear leveling based on the read / write frequency information E1 and E2 unique to the data D1 and D2, the memory usage information 40, and the memory unique information 41.

  The memory management device 24 includes a microprocessor 42, a work memory 43, an information register 44, and a cache memory 45.

  The microprocessor 42 executes memory management while using the information register 44 and the work memory 43. The cache memory 45 is used for temporary storage of data from the processors 271 to 274 and data from the NAND flash main memory 26. The cache memory 45 may be an external DRAM.

  FIG. 17 is a block diagram illustrating an example of the functions of the microprocessor 42.

  The microprocessor 42 includes an acquisition function 42a, an address conversion function 42b, an access function 42c, and a transfer function 42d.

  When any of the plurality of processors 251 to 254 reads data from the NAND flash main memory 26, the acquisition function 42a acquires a read logical address from any of the plurality of processors 251 to 254.

  The address conversion function 42 b converts the read destination logical address acquired by the acquisition function 42 a into a read destination physical address of the NAND flash main memory 26. For example, it is assumed that the NAND flash main memory 26 is divided into areas having a plurality of group attributes, and each group attribute is held as memory specific information 41. In this case, the address conversion function 42b refers to the data D1, D2 specific read / write frequency information E1, E2 defined by the file management program (process) operating on any processor, and the memory specific information 41. The write destination physical address is associated with the group attribute area corresponding to the read / write frequency information E1, E2 unique to the data D1, D2.

  The access function 42 c reads data corresponding to the read destination physical address from the NAND flash main memory 26. Here, the data size of the read data is an integer multiple of the page size of the NAND flash main memory 26 or a block size.

  The transfer function 42d transfers the read data to the cache memory of the processor that issued the read logical address. Here, the cache size of the cache memory of the processor that issued the read logical address depends on an integer multiple of the page size of the NAND flash main memory 26 or a block size.

  When any of the plurality of processors 251 to 254 writes data to the NAND flash main memory 26, the acquisition function 42a acquires a write destination logical address and write data from the processor. Here, the size of the write data is the cache size.

  The address conversion function 42 b converts the write destination logical address acquired by the acquisition function 42 a into a write destination physical address of the NAND flash main memory 26.

  The access function 42 c writes write data at a position corresponding to the write destination physical address of the NAND flash main memory 26.

  The address conversion function 42b of the microprocessor 42 performs wear leveling based on at least one of the data-specific read / write frequency information, the memory usage information 40, and the memory-specific information 41.

  FIG. 18 is a diagram illustrating an example of a first operation of the transfer algorithm of the memory management device 24.

  The microprocessor 42 of the memory management device 24 reads the memory usage information 40 and the memory specific information 41 and stores them in the information register 44 at startup. The memory unique information 41 includes the page size and block size of the NAND flash main memory 26. The cache size of each of the processors 271 to 274 is an integral multiple of the block size or page size of the NAND flash main memory 26.

  When the memory management device 24 is applied to a conventionally used processor and the cache size cannot be changed for the conventional processor, the microprocessor 42 performs buffering in the cache memory 45, and the processor 271 The difference between the cache size of ˜274 and the integer multiple of the block size or page size of the NAND flash main memory 26 is adjusted. For example, the microprocessor 42 reads the data for the page size 256 kilobytes into the cache memory 45 and outputs the data for the cache line 4 kilobytes to any of the processors 271 to 274.

  FIG. 19 is a diagram illustrating an example of a second operation of the transfer algorithm of the memory management device 24.

  The microprocessor 42 of the memory management device 24 receives an access request for one cache line from any of the processors 252 (Tr19A).

  Next, the microprocessor 42 reads data that is an integral multiple of the block or page corresponding to the access request from the NAND flash main memory 26 and stores it in the cache memory 45 (Tr19B).

  Next, the microprocessor 42 transmits data corresponding to the access request from the cache memory 45 to the processor 252 (Tr19C).

  FIG. 20 is a diagram illustrating a third operation example of the transfer algorithm of the memory management device 24.

  One of the processors 252 rewrites the data in the cache memory 282 or the cache memory 292 (Tr20A).

  Next, the microprocessor 42 of the memory management device 24 caches the rewritten data in the cache memory 282 or the cache memory 292, and transfers it to the cache memory 45 (Tr20B).

  Then, the microprocessor 42 performs wear leveling based on the read / write frequency information held by this data, the memory use information 40 and the memory specific information 41 stored in the information register 44, and performs a plurality of NAND flash main memory 26. The physical block 39 to be written is determined from among the physical blocks.

  The microprocessor 42 stores the rewritten data stored in the cache memory 45 in the determined physical block 39 (Tr20C).

  In this writing, a memory block is moved and a garpage is collected as necessary.

  FIG. 21 is a block diagram illustrating an example of wear leveling.

  The NAND flash main memory 26 includes two or more banks 46a and 46b.

  The microprocessor 42 additionally stores data (blocks or pages) sequentially in one bank 46a.

  When data deletion occurs, the microprocessor 42 deletes data to be deleted on the bank 46a. However, the additional storage is sequentially continued until data is stored in the last area in the bank 46a. In the bank 46a to be written, writing is not performed on the part deleted midway. Therefore, when data is deleted in the bank 46a to be written, data in the deleted area is lost.

  When the microprocessor 42 stores the data up to the last area of the one bank 46a, the valid data that has not been deleted is copied from the bank 46a to the other bank 46b while being garbage collected, and the other bank 48b. Then, new data is additionally stored after the copied data. Further, after copying the data of one bank 46a to the other bank 46b, the microprocessor 42 clears the one bank 46a. Thereafter, the same processing is repeated.

  Here, a specific operation example of the wear leveling algorithm used in the microprocessor 42 of the memory management device 24 will be described.

  First, the microprocessor 42 receives data to be written from any processor or OS. When there are a plurality of data to be written, the data with the highest writing frequency is used as a reference. When the processor or OS is a conventional type, the microprocessor 42 examines the top of data and determines the type of data.

  For example, in the case of image data in which the type of data to be written is compressed, the microprocessor 42 determines the MLC area as the rewrite area because the writing frequency of the written data is low. Alternatively, in the case of image data in which the type of data to be written is compressed, the microprocessor 42 determines an empty area where the number of rewrites has already increased as the rewrite area.

  For example, when the type of data to be written is cache data of a web browser, the microprocessor 42 determines the SLC area as the rewrite area because the writing frequency is high.

  For example, the microprocessor 42 determines an empty block with the smallest number of rewrites from the SLC area or the MLC area as the writing area.

  For example, when the number of rewrites of all free areas (for example, free blocks) in the NAND flash main memory 26 has reached a predetermined ratio (for example, 80%) of the maximum writable number, the microprocessor 42 has already Of the areas in which data is written, an area having a low rewrite frequency based on static information and a low rewrite frequency based on dynamic information is selected, and the data of the selected area is stored in a free area. Then, the microprocessor 42 deletes the data in the selected area. That is, the data is exchanged between the empty area and the selected area.

  In the present embodiment, the microprocessor 42 of the memory management device 24 may manage a plurality of NAND flash main memories 26.

  FIG. 22 is a perspective view showing an example of an integrated memory management device 24 that manages a plurality of NAND flash main memories 26.

  One integrated memory management device 24 and a plurality of NAND flash main memories 26 form one memory unit 47. In the example of FIG. 22, three memory units 47 are formed.

  The integrated memory management device 24 manages access to a plurality of NAND flash main memories 26 belonging to the same memory unit 47.

  Furthermore, the plurality of integrated memory management devices 24 provided in the plurality of memory units 47 operate in cooperation with each other as one memory management device.

  The integrated memory management device 24 of the memory unit 47 includes an ECC function and a RAID function for the plurality of NAND type flash main memories 26 in the memory unit 47, and performs mirroring and striping.

  Each NAND flash main memory 26 can be hot swapped (replaced) even when the memory unit 47 is energized (operating). Each of the plurality of NAND flash main memories 26 includes a button 48.

  The button 48 includes a warning output unit (for example, an LED). For example, when the warning output unit is the first color (green), it indicates a normal state, and when it is the second color (red), it indicates a state that needs to be replaced.

  When the button 48 is pressed, a notification is sent to the process and the OS, and access is not generated. When it is safe to remove, the button 48 is in the third color (blue), and the NAND type corresponding to this button 48 is displayed. The flash main memory 26 can be hot swapped.

  When hot swap is executed, after the button 48 for requesting hot swap is pressed, when the write-back is completed, a lamp indicating that replacement is possible is turned on, and the NAND flash main memory 26 is replaced.

  The microprocessor 42 of the memory management device 26 refers to the memory usage information 40 and the memory specific information 41 stored in the information register 44, and the number of times of rewriting or reading of each NAND flash main memory 26 is determined as the memory specific. It is determined whether the upper limit described in the information 41 has been reached. Then, when the number of rewrites or the number of reads reaches the upper limit, the microprocessor 42 notifies or warns of the memory replacement.

  In the present embodiment, preloading is effective when the page size or block size of the NAND flash main memory 26 is large.

  When preloading is performed, the microprocessor 42 of the integrated memory management device 24 refers to the data unique information E1 and E2 in the NAND flash main memory 26 and stores data that is likely to be frequently accessed to the cache memory 45 in advance. Preload it.

  Alternatively, the microprocessor 42 preloads data having periodicity, which is highly likely to be accessed at a predetermined time, before the predetermined time.

  FIG. 23 is a block diagram showing an example of a multiprocessor system using the integrated memory management device 24 according to the present embodiment for an existing processor having an MMU.

  The processor 255 is an existing processor, and includes the MMU 495, the primary cache memory 285, and the secondary cache memory 295, and executes the process 275. In the system of FIG. 23, address translation by the normal MMU 495 and address translation by the integrated memory management device 24 according to the present embodiment are mixed. In this case, when accessing the NAND flash main memory 26, the MMU 495 of the processor 255 first accesses the page table 26b of the NAND flash main memory 26. However, the page table 26b has a content to pass through the conversion without performing the address conversion. For example, in the page table 26b, the address before conversion and the address after conversion are set to be the same. Thereby, the address conversion is not performed in the MMU 495 of the processor 255, and the address conversion can be performed in the memory management device 24.

  Differences between the system using the memory management device 24 according to the present embodiment shown in FIG. 16 and the conventional multiprocessor system will be described below.

  FIG. 24 is a block diagram showing an example of a general conventional multiprocessor system.

  In a conventional multiprocessor system, existing processors 255 to 258, a main memory 50, and a secondary storage device 51 are connected by a system bus 30.

  Each of the processors 255 to 258 includes MMUs 495 to 498, primary cache memories 285 to 288, and secondary cache memories 295 to 298, respectively. Each processor 255-258 executes processes 275-277, respectively.

  The MMUs 495 to 498 perform conversion between logical addresses and physical addresses. Access from the processors 255 to 258 to the primary cache memories 285 to 288, the secondary cache memories 295 to 298, the main memory 50, and the secondary storage device 51 is performed based on the physical address.

  For the main memory 50, for example, a volatile storage device such as a DRAM is used. The main memory 50 includes page tables 525 to 528 for the processes 275 to 277, respectively.

  As the secondary storage device 51, for example, a hard disk drive, an SSD (Solid State Drive), a NAND flash memory, or the like is used.

  In the conventional multiprocessor system, DRAM or the like is used as the main memory, whereas in the multiprocessor system according to the present embodiment, the NAND flash main memory 26 is used as the main memory. Usually, the bit unit price of the DRAM is higher than the bit unit price of the NAND flash main memory 26. Therefore, in this embodiment, the cost can be reduced.

  In the conventional multiprocessor system, the main memory is volatile, whereas in the multiprocessor system according to the present embodiment, the nonvolatile NAND flash main memory 26 is used as the main memory. Thereby, in the present embodiment, instant-on is possible, the load time of programs or data or the like can be deleted in the main memory, and the operation speed can be improved.

  In a conventional multiprocessor system, both a volatile main memory 50 and a non-volatile secondary storage device 51 are mounted. On the other hand, in the multiprocessor system according to the present embodiment, by installing the NAND flash main memory 26, the main memory can be made non-volatile, and a secondary storage device such as a hard disk is removed. can do. In this embodiment, it is not necessary to mount a DRAM as the main memory. In this embodiment, when a DRAM is mounted as a cache, the storage capacity of the cache may be small. Therefore, in this embodiment, the system configuration and memory management can be simplified, and the cost can be reduced.

In the conventional multiprocessor system, the page tables 525 to 528 must be shared, and an access neck occurs. On the other hand, in the multiprocessor system according to the present embodiment, it is not necessary to share the page table, and the access bottleneck can be eliminated.
When a DRAM or SSD is used as a secondary storage device as in the past, concepts such as a file and SATA (Serial ATA) are used. In this case, there is always overhead. On the other hand, in the present embodiment, data is not abstracted by a file, and the memory is directly accessed. Therefore, in this embodiment, access to data can be made efficient.

  Compared to the case where a DRAM or SSD is used for the secondary storage device as in the prior art, in this embodiment, since no disk search time is required at the time of startup, the startup time can be shortened. In the present embodiment, the application startup speed can also be increased. In the present embodiment, the search speed and the application execution speed can be increased. In this embodiment, an application can be operated for each of a plurality of processors. In this embodiment, since the nonvolatile main memory is used, it is not necessary to consider the battery life when the system sleeps. In the present embodiment, the number of parts can be reduced and the cost can be suppressed. This embodiment can be easily adapted to a multiprocessor environment. In this embodiment, no installation is required and process migration can be eliminated.

  In the present embodiment, optimal wear leveling is performed by the memory management device 24 based on the data-specific read / write frequency information E1, E2, the memory usage information 40, and the memory specific information 41. In the present embodiment, wear leveling can be performed more efficiently than SSD by performing wear leveling based on data-specific read / write frequency information E1, E2.

  Generally, when the generation of NAND flash memory is different, the page size and block size are also different. In the present embodiment, the memory management device 24 reads the memory specific information 41 from the NAND flash main memory 26 and performs processing according to the page size or block size indicated by the memory specific information 41. As a result, various generations of NAND flash memories can be used as the NAND flash main memory 26. In the present embodiment, the main memory management device 24 reads the memory specific information 41 including the page size or block size from the NAND flash main memory 26, the page size or block size of the NAND flash main memory 26, and each processor. The cache line size can be matched.

  In the present embodiment, the memory management device 24 performs life management of the NAND flash main memory 26 and issues a warning. Thereby, generation | occurrence | production of a malfunction can be prevented.

  In the present embodiment, the memory management device 24 has a RAID function for a plurality of NAND flash main memories 26 and can implement hot swap of the NAND flash main memory 26 to be replaced. This makes it possible to easily replace the NAND flash main memory 26 having a lifetime.

  Here, an example of virtual memory access when a plurality of NAND flash main memories are provided for a plurality of processors will be described.

  FIG. 25 is a block diagram illustrating an example of processing for obtaining a pointer for a wide address space.

  The pointer 53 includes a pointer 53a for a narrow address space and a pointer 53b for a narrow address space.

  The segment table 54 is provided for each process ID 55 and includes a pointer 56 for a wide address space.

  For example, the wide address space pointer 57 is obtained by combining the narrow address space pointer 53b and the wide address space pointer 56 on the segment table 54 specified by the narrow address space pointer 53a. . The wide address space pointer 57 may be generated by combining the narrow address space pointer 53b, the narrow address space pointer 53a, and the wide address space pointer 56 on the segment table 54. Good.

  FIG. 26 is a block diagram showing an example of a virtual storage space formed by a plurality of cache memories and a plurality of NAND flash main memories.

  The wide address space pointer 57 indicates one of the virtual storage spaces 60 constituted by the processor cache memories 581 to 58n and a plurality of NAND flash main memories 591 to 59m.

  As a result, the cache memories 581 to 58n of the processor and the plurality of NAND flash main memories 591 to 59m can be handled in an integrated manner.

  In each of the above embodiments, other nonvolatile memory may be used as the main memory instead of the NAND flash memory.

  The integrated memory management device according to each of the above embodiments can be applied to both cases where the cache is a write-back type and a write-through type.

1 is a block diagram showing an example of an integrated memory management device according to a first embodiment of the present invention. The figure which shows the 1st example of the memory hierarchy of the integrated memory management apparatus which concerns on 1st Embodiment. The flowchart which shows an example of operation | movement in case MPU provided with the integrated memory management apparatus which concerns on 1st Embodiment memorize | stores the data of NAND type flash main memory, a part of rewrite frequency data, and a part of address conversion table. . 6 is a flowchart illustrating an example of an operation when data is read from a primary cache memory or a NAND flash main memory in the MPU including the integrated memory management device according to the first embodiment. The MPU having the integrated memory management device according to the first embodiment overwrites the cache line of the primary cache memory, and further stores the data of the primary cache memory 3 in the NAND flash main memory 4 The flowchart which shows an example of operation | movement in a case. The block diagram which shows an example of the integrated memory management apparatus which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the memory hierarchy of the integrated memory management apparatus which concerns on 2nd Embodiment. The block diagram which shows the 1st example of the integrated memory management apparatus which concerns on the 3rd Embodiment of this invention. The block diagram which shows the 2nd example of the integrated memory management apparatus which concerns on 3rd Embodiment. The block diagram which shows the example of application of the integrated memory management apparatus which concerns on the 4th Embodiment of this invention. The block diagram which shows an example of the memory | storage device which concerns on the 5th Embodiment of this invention. The figure which shows an example of the system logical address which concerns on 5th Embodiment. The block diagram which shows an example of the memory | storage device which concerns on the 6th Embodiment of this invention. The figure which shows an example of the system logical address which concerns on 6th Embodiment. The block diagram which shows an example of the integrated memory management apparatus which concerns on the 7th Embodiment of this invention. The block diagram which shows an example of a structure of the integrated memory management apparatus which concerns on the 8th Embodiment of this invention. The block diagram which shows an example of the function of the microprocessor of the integrated memory management apparatus which concerns on 8th Embodiment. The block diagram which shows the example of the 1st operation | movement of the transfer algorithm of the integrated memory management apparatus which concerns on 8th Embodiment. The block diagram which shows the example of the 2nd operation | movement of the transfer algorithm of the integrated memory management apparatus which concerns on 8th Embodiment. The block diagram which shows the example of the 3rd operation | movement of the transfer algorithm of the integrated memory management apparatus which concerns on 8th Embodiment. The block diagram which shows an example of wear leveling. The perspective view which shows an example of the integrated memory management apparatus which manages several NAND type flash main memories. The block diagram which shows an example of the multiprocessor system using the integrated memory management apparatus which concerns on 8th Embodiment with respect to the existing processor provided with MMU. 1 is a block diagram showing an example of a conventional multiprocessor system. The block diagram which shows an example of the process which calculates | requires the pointer for wide address spaces. FIG. 3 is a block diagram showing an example of a virtual storage space formed by a plurality of cache memories and a plurality of NAND flash main memories.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,11 ... MPU, 2,12,24,381-384 ... Unified memory management apparatus, 3,281-284 ... Primary cache memory, 3a, 22a ... Tag storage area, 3b, 22b ... Line storage area, 4, 26, 261, 262 ... NAND type flash main memory, 5 ... address conversion table, 6 ... rewrite count data, 7 ... MMU, 8 ... cache controller, 8a ... first cache controller, 8b ... second cache controller, 9 ... MMU for main memory, 10 ... Access history storage unit, 13 ... Integrated MMU, 16, 251-254 ... Processor, 17, 22,291-294 ... Secondary cache memory, 23 ... Address relation storage unit, 271-274 ... Process 30 ... System bus 33 ... Network 40 ... Memory usage information 41 ... Memory specific information 42 ... Microprocessor 42a ... Acquisition function 42b ... Address conversion function 42c ... Access function 42d ... Transfer function 43 ... Work memory 44 ... Information register 45 ... Cache memory E1, E2 ... Read / write Frequency information, 39 ... physical block

Claims (9)

A first memory management unit provided in a processor for converting a logical address for accessing the cache memory into a physical address for accessing the cache memory;
A cache controller provided in the processor for accessing the cache memory based on a physical address for accessing the cache memory;
An access history storage unit provided in the processor for storing access history data indicating an access state to the main memory outside the processor;
An address relationship storage unit provided in the processor for storing address relationship data indicating a relationship between a logical address and a physical address in the main memory;
Based on the access history data and the address relation data, a logical address for accessing the main memory is converted into a physical address for accessing the main memory, and a physical address for accessing the main memory And a second memory management unit provided in the processor for accessing the main memory based on the integrated memory management device. A first memory management unit provided in a processor for converting a logical address for accessing the cache memory into a physical address for accessing the cache memory;
An access history storage unit provided in the processor for storing access history data indicating an access state to the main memory outside the processor;
An address relationship storage unit provided in the processor for storing address relationship data indicating a relationship between a logical address and a physical address in the main memory;
Second memory management provided in the processor, which converts a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data Unit,
A cache controller provided in the processor for accessing the cache memory based on a physical address for accessing the cache memory and accessing the main memory based on a physical address for accessing the main memory An integrated memory management device comprising: The integrated memory management device according to claim 1 or 2,
The integrated memory management device, wherein the main memory is a nonvolatile storage device. Obtaining means for obtaining a read destination logical address from a first processor included in at least one processor;
Address conversion means for converting the read destination logical address acquired by the acquisition means into a read destination physical address of the nonvolatile main memory;
Access means for reading data corresponding to the read destination physical address of an integer multiple of the page size of the nonvolatile main memory or a block size from the nonvolatile main memory;
An integrated memory management device comprising transfer means for transferring the read data to the cache memory of the first processor having a cache size depending on an integer multiple of the page size of the nonvolatile main memory or a block size . The integrated memory management device according to claim 4.
The acquisition means acquires a write destination logical address and write data of the cache size from the first processor,
The address conversion unit converts the write destination logical address acquired by the acquisition unit into a write destination physical address of the nonvolatile main memory,
The integrated memory management device, wherein the access means writes the write data at a position corresponding to the write destination physical address of the nonvolatile main memory. The integrated memory management device according to claim 5.
The address conversion means can rewrite data-specific read / write frequency information, memory usage information including the number of read / write times of each area of the nonvolatile main memory, and the page size, block size, and storage area of the nonvolatile main memory. An integrated memory management device, characterized in that wear leveling is performed based on at least one of the number of times and the memory specific information including the number of readable times. A nonvolatile main memory that is divided into areas having a plurality of group attributes and each group attribute is stored as memory specific information;
Obtaining means for obtaining a write destination logical address from a first processor included in at least one processor;
An address conversion unit that converts a write destination logical address acquired by the acquisition unit into a write destination physical address of the nonvolatile main memory, and
The address conversion unit refers to the data-specific read / write frequency information defined by the file management program operating on the first processor and the memory-specific information, and corresponds to the data-specific read / write frequency information An integrated memory management device, wherein a write destination physical address is associated with an attribute area. The integrated memory management device provided in the processor refers to access history data indicating an access state to the nonvolatile main memory outside the processor, and address relation data indicating a relationship between a logical address and a physical address in the nonvolatile main memory. And
Based on the access history data and the address relation data, the integrated memory management device converts a logical address for accessing the nonvolatile main memory into a physical address for accessing the nonvolatile main memory. A memory management method of accessing the nonvolatile main memory based on a physical address for accessing the nonvolatile main memory. The integrated memory management device acquires a read destination logical address from a first processor included in at least one processor,
The integrated memory management device converts the acquired read destination logical address into a read destination physical address of a nonvolatile main memory,
The integrated memory management device reads from the nonvolatile main memory data corresponding to the read destination physical address of an integer multiple of the page size of the nonvolatile main memory or a block size,
The integrated memory management device transfers the read data to the cache memory of the first processor having a cache size that depends on an integer multiple of the page size of the nonvolatile main memory or a block size. Memory management method.

Images