JP2010062804A - Clock regeneration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-power consumption clock regeneration circuit which performs edge detection and clock component extraction by a differential circuit, makes a delay means unnecessary, whose chip area is reduced, by which a bit rate free operation is achieved. <P>SOLUTION: The clock regeneration circuit is constituted of: at least one differential circuit which amplifies two input data to output differential data; and a clock component generation circuit which is cascaded with the differential circuit and extracts clock signal components based on difference of intersection voltage between reference voltage and differential output data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a clock recovery circuit, and more particularly to edge detection in a clock recovery circuit in high-speed optical communication.

  In an optical communication system having a large transmission capacity, for example, a WDM system, a receiving unit receives only a data signal, extracts a clock component from the data signal, and processes the data signal using the extracted clock component. ing. This function is called CDR (Clock Data Recovery).

  FIG. 11 is a block diagram showing an example of a conventional open loop CDR. In FIG. 11A, input data Din (t) is input to the edge detector 1 and also input to one input terminal of the determination circuit 4. The output signal of the edge detector 1 is input to the phase adjuster 3 via the band pass filter 2. The output signal of the phase adjuster 3 is input to the other input terminal of the determination circuit 4 and also output to the outside as the clock CK. Output data Dout (t) is output from the determination circuit 4.

  FIG. 11B is a configuration diagram illustrating an example of the edge detector 1. The edge detector 1 excludes the phase delay unit 1a that gives a predetermined delay time to the input data Din (t), and the input signal Din (t) and the output signal D′ in (t) of the phase delay unit 1a as inputs. And an exclusive OR operation (EXOR) circuit 1b for performing a logical OR operation.

  FIG. 12 is a time chart showing an example of the operation of FIG. (A) is input data Din (t), for example, 40 Gbps. (B) is an output signal D'in (t) of the phase delay unit 1a, and it is assumed that a delay amount of 12.5 ps, which is half of the time 25 ps in which 1 bit is transmitted, is given. (C) is an EXOR output D'out (t) of these D'in (t) and Din (t). (D) is the target clock signal Dper (t), and (e) is the noise Dnoise (t).

  Since the EXOR output D′ out (t) shown in (c) is a superposition of the clock signal Dper (t) shown in (d) and the noise Dnoise (t) shown in (e), it is shown in (c). By inputting D′ out (t) to the bandpass filter 2, the noise Dnoise (t) shown in (e) can be filtered out, and the clock signal Dper (t) shown in (d) can be obtained. .

As the EXOR circuit, for example, a conventionally known Gilbert cell circuit as shown in FIG. 13 is used. In FIG. 13, the data input terminal A ^* is connected to the base of the transistor Q21, the data output terminal Q ^* is connected to the collector of the transistor Q21, and the GND is connected via the resistor R12. The data input terminal A is connected to the base of the transistor Q22, the data output terminal Q is connected to the collector of the transistor Q22, and the GND is connected via the resistor R11. The emitters of the transistors Q21 and Q22 are commonly connected to the collector of the transistor Q23. The data input terminal B is connected to the base of the transistor Q23, and the emitter of the transistor Q23 is connected to the collector of the transistor Q27. A voltage terminal Vcs is connected to the base of the transistor Q27, and GND is connected to the emitter of the transistor Q27 via a resistor R13.

The base of the transistor Q24 and the data input terminal A are connected to the base of the transistor Q24, the collector of the transistor Q24 is connected to the collector of the transistor Q21 and the data output terminal Q ^*, and the GND is connected through the resistor R12. Yes.
The base of the transistor Q25 is connected to the base of the transistor Q21 and the data input terminal A ^* , the collector of the transistor Q25 is connected to the collector of the transistor Q22 and the data output terminal Q, and GND is connected via the resistor R11. Yes. The emitters of the transistors Q24 and Q25 are commonly connected to the collector of the transistor Q26. A data input terminal B ^* is connected to the base of the transistor Q26, and the emitter of the transistor Q26 is connected to the emitter of the transistor Q23 and to the collector of the transistor Q27.

  Patent Document 1 relates to a clock recovery circuit and method, and a high-speed data transmission / reception circuit using the same.

JP 2006-25417 A

  However, in the conventional edge detector 1 as shown in FIG. 11, it is necessary to set the delay amount for detecting the edge to half of the time required to transmit 1 bit. When the bit rate changes significantly, the delay amount is proportional to the bit rate, so it is difficult to cope with the change when the bit rate is fixed on the transmission line, and the chip area increases. There is also a problem.

  Further, in the Gilbert cell circuit used as the EXOR circuit, it is necessary to adjust the logic level including the delay. In order to turn on one of the differential inputs, transistors Q21 and Q22 in FIG. 13 must be connected in cascade with Q23, and Q24 and Q25 must be connected with Q26, respectively. There is also a problem that increases.

  The present invention solves these problems, and performs edge detection and clock component extraction with a differential circuit, eliminates the need for delay means, reduces the chip area, and enables bit-rate-free operation and low performance. An object of the present invention is to provide a power recovery clock recovery circuit.

In order to achieve the above object, claim 1 of the present invention provides:
At least one differential circuit for amplifying two input data and outputting differential data;
A clock component generation circuit that is connected in cascade with the differential circuit and extracts a clock signal component based on the difference in the intersection voltage between the reference voltage and the differential output data,
And a clock recovery circuit characterized by comprising:

A second aspect of the present invention provides the clock recovery circuit according to the first aspect,
The clock component generation circuit includes:
It has two pairs of transistors, one pair transistor detects the intersection voltage of the reference voltage and the positive data of the differential output, and the other pair transistor detects the intersection point of the reference voltage and the negative data of the differential output The voltage is detected.

Claim 3 is the clock recovery circuit according to claim 1,
The clock component generation circuit includes:
A first transistor in which a positive output voltage for differential output is input to the base, a second transistor in which a negative output data voltage for differential output is input to the base, and a reference voltage is input to the base A third transistor, and by connecting the emitters of these three transistors in common, an intersection voltage between the reference voltage and the positive side data of the differential output, and a negative side data of the reference voltage and the differential output It is characterized by detecting a crossing voltage with.

According to a fourth aspect of the present invention, in the clock recovery circuit according to the first aspect,
The clock component generation circuit includes:
A first field effect transistor in which a positive output data voltage of differential output is input to the gate; a second field effect transistor in which a negative output data voltage of differential output is input to the gate; and a reference voltage to the gate And a third field effect transistor to which is inputted, and by connecting sources of these three field effect transistors in common, an intersection voltage and a reference voltage between the reference voltage and the positive side data of the differential output And the intersection voltage of the negative output data of the differential output is detected.

A fifth aspect of the present invention provides the clock recovery circuit according to any one of the first to fourth aspects,
The clock recovery circuit is configured as a one-chip integrated circuit.

  Such a configuration eliminates the need for delay means, so that it is possible to reduce the chip area and operate at a bit rate free, and to realize a clock recovery circuit that can be driven with low power consumption.

  The clock recovery circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Two stages of differential circuits 10a and 10b are connected in cascade so that the rising and falling edges of a differential signal can be extracted. A clock component generation circuit 20 is connected to the differential circuit 10b. Here, the reason why the two-stage differential circuits 10a and 10b are provided is to increase the symmetry of the output signal. That is, the more differential circuits 10 are provided, the better the symmetry of the output signal. If the input signal is a differential signal with good symmetry, the differential circuit 10 is not necessary.

  In general, an NRZ (Non Return to Zero) signal is input as a single signal, and the signal can be converted into a (complementary) symmetric differential signal by passing through the differential circuit 10.

FIG. 2 is a circuit diagram showing a specific example of the differential circuit 10.
Data input terminals INP and INN are connected to the bases of the transistors Q1 and Q2 of the differential pair, respectively, GND is connected to the collector of the transistor Q1 via the resistor R1, and GND is connected to the collector of the transistor Q2 via the resistor R2. Is connected. The emitters of the transistors Q1 and Q2 are connected in common and connected to the negative power supply terminal VEE via the resistor R3. The collector of the transistor Q1 is connected to the base of the transistor Q3, and the collector of the transistor Q2 is connected to the base of the transistor Q4. The data output terminal OUTN is connected to the emitter of the transistor Q3 and is connected to the power supply terminal VEE via the transistor Q5 and the resistor R4. The data output terminal OUTP is connected to the emitter of the transistor Q4 and the transistor Q6 and the resistor R5 are connected. Is connected to the power supply terminal VEE. The collectors of the transistors Q3 and Q4 are connected to GND. Although a voltage is applied so that a potential difference is generated between both ends of the GND and the power supply terminal VEE, the potential difference may be generated by replacing the GND and the VEE in FIG.

FIG. 3 is a circuit diagram showing a first specific example 20A of the clock component generation circuit.
A data input terminal mid_inp is connected to the base of the transistor Q7, and GND is connected to the collector of the transistor Q7 via a resistor R6. A reference voltage input terminal REF is connected to the base of the transistor Q9, and GND is connected to the collector of the transistor Q9 via a resistor R7. The emitters of the transistors Q7 and Q9 are connected in common and connected to the negative power supply terminal VEE via the resistor R10. The collector of the transistor Q7 is connected to the base of the transistor Q11, and the collector of the transistor Q9 is connected to the base of the transistor Q12.

  The data output terminal outN is connected to the emitter of the transistor Q11 and is connected to the power supply terminal VEE via the transistor Q13 and the resistor R12. The data output terminal outP is connected to the emitter of the transistor Q12 and the transistor Q14 and the resistor R13 are connected to the emitter. Is connected to the power supply terminal VEE. The data input terminal mid_inn is connected to the base of the transistor Q8, and the collector of the transistor Q8 is connected to the base of the transistor Q12. The reference voltage input terminal REF and the base of the transistor Q9 are connected to the base of the transistor Q10, and the collector of the transistor Q10 is connected to the base of the transistor Q11. The emitters of the transistors Q8 and Q10 are connected in common and connected to the power supply terminal VEE via the resistor R11.

  FIG. 4 is a waveform diagram showing an example of the DC component analysis result (reference voltage REF is about −0.89 V) in FIG. 3. FIG. 4A shows changes in three input voltages to the clock component generation circuit 20A corresponding to each voltage value, that is, the voltages doutp2, doutn2, and REF inputted to the data input terminals INP and INN and the reference voltage input terminal REF. 4B shows changes in collector currents Q7_IC, Q8_IC, Q9_IC, and Q10_IC of the four heterojunction bipolar transistors (hereinafter referred to as HBTs) Q7, Q8, Q9, and Q10 of FIG. 3 corresponding to the respective voltage values. FIG. 4C shows changes in the output voltage corresponding to each voltage value, that is, the voltages outp and outn output from the data output terminals OUTP and OUTN.

  4 (a) and 4 (c), when the input differential voltages dotp2 and doutn2 change monotonously, one differential output outn protrudes upward, and the other differential output outp protrudes downward. It can be confirmed that the following pulse is generated. The amplitude of this output pulse varies depending on the reference voltage value REF.

  That is, when the intersections of the waveforms of the reference voltage input terminal REF and the positive side input terminal INP and the reference voltage input terminal REF and the negative side input terminal INN, that is, the voltage values doutp2 and doutn2 at the intersections are different, the collector current of FIG. In this waveform, HBTQ7 and Q9, and HBTQ8 and Q10 are asymmetric with the input voltage -1V as an axis.

  The waveform of this collector current is such that HBTQ7 and Q9 in FIG. 3 and Q9 and Q10 form a differential input pair. Therefore, when the intersections of the reference voltage REF and the input voltages doutp2 and doutn2 are different, HBTQ7 and Q9, HBTQ8 And Q10 are asymmetric with respect to the input voltage of -1V, respectively. When the waveform of the collector current is asymmetric, when the input waveform changes with time, a pulse is generated in the output waveform.

  Note that when the intersection voltages doutp2 and doutn2 of the positive input voltage and the negative input voltage are substantially equal to the reference voltage REF, the circuit is balanced, and no pulse is generated in the output waveform.

  From FIG. 4C, when attention is paid to one of the output waveforms, for example, outn, the INP of the input waveform changes from -1.15 V to -0.85 V or from -0.85 V to -1.15 V. In both cases, it is clear that a convex pulse is generated above.

  Further, since the levels of outp and outn shown in FIG. 4C do not match, they cannot be used as differential signals as they are. However, since the high-speed signal is usually single, one of the differential outputs can be used as a single. Further, the level can be adjusted by using the bias tee and used as a differential signal.

  FIG. 5 is a circuit diagram showing a second specific example 20B of the clock component generation circuit. Similarly to the first specific example 20A, the second specific example 20B has data input terminals INP and INN, reference voltage input terminals REF, and data output terminals OUTP and OUTN.

  The data input terminal INP is connected to the base of the transistor Q15, the data input terminal INN is connected to the base of the transistor Q16, and the reference voltage input terminal REF is connected to the base of the transistor Q17. The emitters of the transistors Q15 to Q17 are connected in common and connected to the power supply terminal VEE via the resistor R17. The collectors of the transistors Q15 and Q16 are connected in common and connected to the base of the transistor Q18, and GND is connected via the resistor R15. The collector of the transistor Q17 is connected to the base of the transistor Q19, and GND is connected via the resistor R16.

  The data output terminal outP is connected to the emitter of the transistor Q18 and is connected to the power supply terminal VEE via the transistor Q20 and the resistor R18. The data output terminal outN is connected to the emitter of the transistor Q19 and the transistor Q21 and the resistor R19 are connected. Is connected to the power supply terminal VEE.

  When the differential circuit 10 is used in the next stage of FIG. 5, the high-frequency coupling via the bias tee as described above or the voltage at the upper ends of the resistors R15 and R16 is changed to a value other than GND. The plus or minus may be adjusted according to the input signal.

  FIG. 6 is a waveform diagram showing an example of the DC component analysis result (reference voltage REF is about −0.89 V) in FIG. 5. FIG. 6A shows changes in three input voltages to the clock component generation circuit 20B corresponding to the respective voltage values, that is, the data input terminals INP and INN and the voltages doutp2, doutn2 and REF inputted to the reference voltage input terminal REF. 6B shows changes in the collector currents Q15_IC, Q16_IC, and Q17_IC of the three HBTs Q15, Q16, and Q17 of FIG. 5 corresponding to each voltage value, and FIG. 6C corresponds to each voltage value. A change in the output voltage, that is, the voltages outp and outn output from the data output terminals OUTP and OUTN is shown.

  6 (a) and 6 (c), when the input differential voltages dotp2 and doutn2 change monotonously, one outn of the differential output is a convex pulse on the upper side, and the other outp of the differential output is convex on the lower side. It can be confirmed that the following pulse is generated. The amplitude of this output pulse varies depending on the reference voltage value REF.

  That is, when the intersections of the waveforms of the reference voltage input terminal REF and the positive input terminal INP and the reference voltage input terminal REF and the negative input terminal INN, that is, the voltage values doutp2 and doutn2 at the intersections are different, FIG. ) Collector current waveform becomes asymmetric.

  Since the collector current waveform of FIG. 5 is a differential input pair, the collector current waveform becomes asymmetric when the intersection of the reference voltage REF and the input voltages doutp2 and doutn2 is different. When the collector current waveform is asymmetric, a pulse occurs in the output waveform.

  Note that when the intersection voltages doutp2 and doutn2 of the positive input voltage and the negative input voltage are substantially equal to the reference voltage REF, the circuit is balanced and no pulse is generated in the output waveform.

  As in FIG. 3, when the reference voltage REF is changed, it can be confirmed that the pulse of the output waveform also changes. 6A and 6C, when the reference voltage REF is set to about −0.89 V, the cross point of the positive and negative input voltage waveforms is the middle point of the output waveform pulse. I can confirm that.

  The cross-point of the input voltage waveform is the middle point of the output waveform pulse, that is, the input waveform of the circuit connected to the next stage has a good symmetry. When used, the differential circuit 10 can be directly connected.

FIG. 7A is a waveform example diagram showing changes in the positive and negative input voltages inp and inn corresponding to changes in time. The circuit input of FIG. 1 gives a PRBS signal of 40 Gbps, for example (2 ⁴ −1), to INP, and gives the center level of the PRBS signal, that is, the reference voltage REF, to INN.

  FIG. 7B is a spectrum example diagram of the PRBS signal. It can be confirmed that the waveform level is lowered by about 20 dB at 40 GHz. Note that when the number of stages of the PRBS signal is sufficiently long, a sinc function is used, and thus a 40 GHz signal hardly appears.

  FIG. 8 is an output waveform example diagram of the first stage and the second stage of the differential circuit 10 of FIG. As for symmetry, it can be confirmed that the output waveform of the differential circuit 10 in the second stage in FIG. 8B is improved over the output waveform of the differential circuit 10 in the first stage in FIG. That is, it can be seen that the greater the number of differential circuits 10 used, the better the symmetry of the differential output waveform.

  FIG. 9A is an output waveform example diagram of the clock component generation circuit 20A. This figure is shown on the same graph in order to compare the output waveforms outp and outn of the data output terminals OUTP and OUTN with the data output waveform doutp2 of the second stage of the differential circuit 10.

  FIG. 9B is a spectrum example diagram when the difference between the output waveforms outp and outn of the data output terminal OUTP and the data output terminal OUTN of the output waveform is taken. A peak of about 10 dB at a frequency of 40 GHz and a gentle peak at a frequency of 20 GHz can be confirmed. A clock signal is obtained by extracting the spectrum in the 40 GHz band with a band pass filter.

In addition, since the actual signal has higher randomness than the PRBS signal of (2 ⁴ −1) described in the above embodiment, the noise envelope becomes smooth and the spectrum of the clock component becomes remarkable. Therefore, the level is low and the clock signal can be easily extracted.

  FIG. 10A is an output waveform example diagram of the clock component generation circuit 20B. In order to compare the output waveforms outp and outn of the data output terminal OUTP and data output terminal OUTN of the output waveform of the clock component generation circuit 20B with the data output waveform doutp2 of the second stage of the differential circuit 10, they are represented on the same graph, and the reference voltage The REF value was set to -0.85V. The amplitude of the output waveform is about 80 mVpp for both the output waveforms outp and outn of the data output terminal OUTP and the data output terminal OUTN, and it can be confirmed that the output amplitude is substantially equivalent to that of the clock component generation circuit 20A.

  FIG. 10B is a spectrum example when the difference between the output waveforms outp and outn of the data output terminal OUTP and the data output terminal OUTN of the output waveform is taken. Similar to the clock component generation circuit 20A, a peak of about 10 dB can be confirmed at a frequency of 40 GHz. A clock signal is obtained by extracting this spectrum with a band pass filter.

  As described above, according to the present invention, the conventional delay means can be dispensed with, the chip area can be reduced, the bit rate free operation can be performed, and the clock recovery circuit that can be driven with low power consumption can be realized. .

It is a circuit diagram which shows one Example of this invention. It is a circuit diagram which shows the specific example of the differential circuit 10 of this invention. It is a circuit diagram showing a first specific example 20A of the clock component generation circuit of the present invention. It is a waveform which shows an example of the direct-current component analysis result (REF which is a reference voltage is about -0.89V) of FIG. 3 of this invention. FIG. 10 is a circuit diagram showing a second specific example 20B of the clock component generation circuit of the present invention. It is a waveform which shows an example of the direct-current component analysis result (REF which is a reference voltage is about -0.89V) of FIG. 5 of this invention. (A) is a waveform example diagram showing positive and negative side input voltage changes corresponding to time changes, and (b) is a spectrum example diagram of a PRBS signal. FIG. 2 is an output waveform example diagram of a first stage and a second stage of the differential circuit 10 of FIG. 1. (A) is an example of an output waveform of the clock component generation circuit 20A, and (b) is an example of a spectrum when the difference between the output waveforms outp and outn of the data output terminal OUTP and the data output terminal OUTN of the output waveform is taken. is there. (A) is an example of an output waveform of the clock component generation circuit 20B, and (b) is an example of a spectrum when the difference between the output waveforms outp and outn of the data output terminal OUTP and the data output terminal OUTN of the output waveform is taken. It is. It is a block diagram which shows an example of the conventional open loop type CDR. It is a time chart which shows an example of the principle which a clock generate | occur | produces with the conventional clock reproduction circuit and a band pass filter. It is a circuit diagram which shows an example of the conventional EXOR circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock reproduction circuit 1a Phase delay part 1b Exclusive OR operation (EXOR) circuit 2 Band pass filter 3 Phase adjuster 4 Judgment circuit 10 Differential circuit 20 Clock component generation circuit

Claims (5)

At least one differential circuit for amplifying two input data and outputting differential data;
A clock component generation circuit that is connected in cascade with the differential circuit and extracts a clock signal component based on the difference in the intersection voltage between the reference voltage and the differential output data,
A clock recovery circuit comprising: The clock component generation circuit includes:
It has two pairs of transistors, one pair transistor detects the intersection voltage of the reference voltage and the positive data of the differential output, and the other pair transistor detects the intersection point of the reference voltage and the negative data of the differential output 2. The clock recovery circuit according to claim 1, wherein the voltage is detected. The clock component generation circuit includes:
A first transistor in which a positive output voltage for differential output is input to the base, a second transistor in which a negative output data voltage for differential output is input to the base, and a reference voltage is input to the base A third transistor, and by connecting the emitters of these three transistors in common, an intersection voltage between the reference voltage and the positive side data of the differential output, and a negative side data of the reference voltage and the differential output The clock recovery circuit according to claim 1, wherein the voltage at the crossing point is detected. The clock component generation circuit includes:
A first field effect transistor in which a positive output data voltage of differential output is input to the gate; a second field effect transistor in which a negative output data voltage of differential output is input to the gate; and a reference voltage to the gate And a third field effect transistor to which is inputted, and by connecting sources of these three field effect transistors in common, an intersection voltage and a reference voltage between the reference voltage and the positive side data of the differential output 2. The clock recovery circuit according to claim 1, wherein an intersection voltage between the negative side data and the negative output data of the differential output is detected.   5. The clock recovery circuit according to claim 1, wherein the clock recovery circuit is configured as a one-chip integrated circuit.