JP2010056910A - Current source control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect a circuit element from big current generated upon output short-circuitting of an output circuit and improve reliability of operation of the circuit. <P>SOLUTION: The base current variations of output transistors of an output circuit 1 or eighth and ninth transistors 18, 19 are detected by a base current detecting unit 42 and when the current variation is greater than or equal to a predetermined value for more than or equal to a predetermined period of time, a predetermined determination signal which detects an abnormal current generated in the output stage of the output circuit 1 is outputted from the determination unit 44 and a predetermined control signal for stopping the operation of current source circuits 6, 7 is outputted from a control signal output circuit 37 in accordance with the output whereby the operation of the output circuit 1 and the signal processing circuit 2 is stopped and the abnormal current in the output stage of the output circuit 1 can be intercepted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an operation control circuit for a current source used in a signal output circuit or the like, and more particularly to a circuit for improving a short circuit protection function.

As a circuit for outputting a signal subjected to a desired process or the like, a circuit having a configuration as shown in FIG. 3 is conventionally known.
Hereinafter, this conventional circuit will be described with reference to the same figure. In this conventional circuit, an externally applied input signal is converted into a current by a conductance amplifier gm AMP and applied to an output stage via a transistor Q1. The output stage is configured by push-pull connection of transistors Q8 and Q9.

The output circuit includes an npn-type fifth transistor Q5, a pnp-type sixth transistor Q6, a constant current source I5, and a constant current source I6 for supplying an idling current to the transistors Q8 and Q9 in the output stage. An idling current supply unit 41A configured as a main component is provided.
In FIG. 3, a current source circuit 7A is a circuit that supplies a current necessary for the operation of the output circuit. Specifically, the current source circuit 7A includes a current source I2 connected to the transistor Q1, and the idling current supply unit described above. In addition to the current source I5 and the current source I6 provided in 41A, other current sources (not shown) such as a current source (not shown) for supplying a current to the conductance amplifier gm AMP are generally shown. Is.
An example of this type of output circuit is disclosed in Patent Document 1 or the like.
US Pat. No. 5,311,145

  By the way, in such a conventional circuit, when the signal output terminal 5A, which is the connection point between the output transistors Q8 and Q9, is short-circuited to ground or the like for some reason, a large current may flow continuously through the output transistors Q8 and Q9. However, since this conventional circuit is not provided with a short-circuit protection circuit that can cope with such a case, in the worst case, the output transistors Q8 and Q9 may be destroyed.

  The present invention has been made in view of the above circumstances, and provides a current source control circuit that improves circuit operation reliability while protecting circuit elements from a large current generated when an output terminal of an output circuit is short-circuited. .

In order to achieve the above object of the present invention, a current source control circuit according to the present invention includes:
An abnormal current in the output stage is detected in an output circuit comprising an output stage that is push-pull connected and a current source circuit that supplies a current necessary for circuit operation, and the current source circuit is stopped. A current source control circuit comprising:
A base current detection unit for detecting a base current of an output transistor constituting the output stage;
A determination unit that outputs a predetermined determination signal that an abnormal current has occurred in the output stage when the base current detected by the base current detection unit is equal to or greater than a predetermined value over a predetermined time;
And a control signal output unit that outputs a predetermined control signal for stopping the operation of the current source circuit according to the output of the determination unit.
In such a configuration, a signal processing circuit is provided in the preceding stage of the output circuit, and the signal processing circuit includes a current source circuit that supplies a current necessary for circuit operation.
The control signal of the control signal output unit is applied to the current source circuit provided in the signal processing circuit together with the current source circuit provided in the output circuit, so that the two current source circuits can be stopped. Is also suitable.
Further, in the above configuration, the base current detection unit is provided with detection transistors that detect base currents of two output transistors that are push-pull connected to form an output stage, and the two detection transistors are While each transistor is formed in a small transistor size with a predetermined ratio to the transistor size of the corresponding output transistor, the corresponding output transistor and base are connected to each other,
It is preferable that a current mirror circuit for current mirroring the collector currents of the two detection transistors to the determination unit is provided.

According to the present invention, when the signal output terminal is short-circuited and a large current flows through the output transistor for a certain time or more, the output circuit can be brought into an operation stop state, so that the transistor element in the semiconductor device is destroyed. Alternatively, the semiconductor device can be prevented from being destroyed, and the current consumption can be reduced when the output circuit is in the operation stop state, thereby contributing to power saving.
In particular, when only the current source circuit of the output circuit is stopped while the previous circuit of the output circuit is in an operating state, the output circuit has a simpler circuit configuration than the previous circuit, so the operation is restored. The time required for this is relatively short, and smooth operation recovery can be realized.
In addition, by using a current mirror circuit that can be configured with a relatively small number of elements for detecting the base current of the output transistor, it is easy to reduce the size of the chip when forming an integrated circuit.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the current source control circuit according to the embodiment of the present invention will be described with reference to FIG.
A current source control circuit 3 according to an embodiment of the present invention includes a signal processing circuit 2 that performs predetermined signal processing on an input signal, and an output circuit configured to be able to output the output of the signal processing circuit 2 with a full swing. 1, a current source circuit (indicated as “I-SOURCE1” in FIG. 1) 6 provided in the signal processing circuit 2 and a current source circuit (in FIG. 1) provided in the output circuit 1. Is expressed as “I-SOURCE2”).

First, the signal processing circuit 2 is configured to perform predetermined signal processing on an externally applied signal to the signal input terminal 4 and output the signal. The current source circuit 6 supplies the current.
The current source circuit 6 can be controlled to start and stop its operation by applying a predetermined control signal from the outside.
The output circuit 1 has basically the same configuration as the conventional circuit, and is a conductance amplifier that converts an input signal applied from the outside into a current and outputs it (indicated as “gm AMP” in FIG. 1). 20 and the output of the conductance amplifier 20 are converted into current and voltage, and output transistors are configured as eighth and ninth transistors (indicated as “Q8” and “Q9” in FIG. 1, respectively)). The first transistor (indicated as “Q1” in FIG. 1) 11 for driving the final output stage, the eighth and ninth transistors 18 and 19 constituting the final output stage, and the idling current supply unit 41 are mainly used. It is configured as a component.

The connection configuration will be specifically described below.
The output terminal of the conductance amplifier 20 is connected to the base of the pnp-type first transistor 11, and the emitter of the first transistor 11 is a first constant current source 21 that outputs a constant current I2 and a constant current. It is connected to a second constant current source 22 that outputs I5. Furthermore, the emitter of the first transistor 11 is the collector of an npn-type fifth transistor (denoted as “Q5” in FIG. 1) 15 and the sixth transistor of the pnp-type (“Q6” in FIG. 1). And the pnp-type seventh and eighth transistors (indicated as “Q7” and “Q8” in FIG. 1) 17 and 18, respectively.

On the other hand, the collector of the first transistor 11 is connected to the collector of an npn-type second transistor (denoted as “Q2” in FIG. 1) 12.
The second transistor 12 constitutes a current mirror circuit together with an npn-type third transistor (denoted as “Q3” in FIG. 1) 13.
That is, in the second and third transistors 12 and 13, the bases of the second transistor 12 and the collector of the second transistor 12 are connected to each other, and the second transistor 12 is in a so-called diode-connected state. The emitters of the second and third transistors 12 and 13 are both connected to the ground.

  The collector of the third transistor 13 is connected to the input stage IN of a second current mirror circuit (indicated as “CUR2” in FIG. 1) 32 provided in the current source control circuit 3 to be described later. It has become. Note that the current mirror circuit including the second and third transistors 12 and 13 constitutes the sub-base current detection unit 43 together with the second current mirror circuit 32 of the current source control circuit 3 as described later. However, for convenience of circuit notation, FIG. 1 shows the output circuit 1.

On the other hand, a predetermined constant voltage V1 is applied to the base of the fifth transistor 15, while the emitter is the base of the ninth transistor 19 and the collector of the sixth transistor 16. A third constant current source 23 that outputs a constant current I6 is connected between the connection point of the fourth transistor 14 and the ground.
The collector of the fourth transistor 14 is connected to the input stage IN of a first current mirror circuit (indicated as “CUR1” in FIG. 1) 31 provided in the current control circuit 3 described later, and the emitter is grounded. Is connected to.

  The sixth transistor 16 is configured such that a predetermined constant voltage V2 is applied to its base. The seventh transistor 17 has a power supply voltage VCC applied to its emitter, while the collector is a third current mirror circuit (in FIG. 1) provided in a current control circuit 3 to be described later. It is connected to the input stage IN 33 (denoted as “CUR3”).

The portion constituted by the fifth and sixth transistors 15 and 16 and the second and third constant current sources 22 and 23 is the idling current of the output circuit 1, that is, the eighth stage constituting the output stage. In the steady operation state where the ninth transistors 18 and 19 are not outputting signals, the idling current supply unit 41 functions to set and supply currents flowing through the eighth and ninth transistors 18 and 19. Yes.
The fourth and seventh transistors 14 and 17 together with the first and third current mirror circuits 31 and 33 constitute a base current detection unit 42 of the current source control circuit 3 as will be described later. The fourth transistor 14 and the first current mirror circuit 31 detect the base current of the ninth transistor 19, and the seventh transistor 17 and the third current mirror circuit 33 detect the eighth transistor 18. Each of the base currents is detected. Note that the fourth and seventh transistors 14 and 17 constitute the base current detection unit 42 in the current source control circuit 3, but are shown in the output circuit 1 for convenience of circuit notation in FIG. 1. It is.

In the eighth and ninth transistors 18 and 19 constituting the output stage, the emitter of the eighth transistor 18 and the collector of the ninth transistor 19 are both connected to the signal output terminal 5, while the eighth transistor The power supply voltage VCC is applied to the collector 18. The emitter of the ninth transistor 19 is connected to the ground, and the eighth and ninth transistors 18 and 19 are push-pull connected.
The output circuit 1 is provided with a current source circuit 7 for supplying a current necessary for the circuit operation. Here, the current source circuit 7 in the embodiment of the present invention includes the first to third constants described above in addition to a current source (not shown) for supplying a current to the conductance amplifier 20. The current sources 21 to 23 are also included, and these are generally expressed.
The current source circuit 7 can control the start and stop of its operation by applying a predetermined control signal from the outside.

The current source control circuit 3 according to the embodiment of the present invention is roughly divided into a base current detection unit 42, a sub base current detection unit 43, a determination unit 44, and a control signal output circuit 37 as a control signal output unit. It is configured.
The base current detection unit 42 includes the fourth transistor 14, the first current mirror circuit 31 connected to the collector of the fourth transistor 14, the seventh transistor 17, and the collector of the seventh transistor 17. And a third current mirror circuit 33 connected to each other.

  The sub-base current detection unit 43 includes second and third transistors 12 and 13 provided to form a current mirror circuit, and a second current mirror in which the input stage IN is connected to the collector of the third transistor 13. The circuit 32 is provided. As will be described later, the sub-base current detector 43 detects a state in which the base current of the eighth transistor 18 has become extremely large so that the operation of the current source circuits 6 and 7 can be stopped. Is.

The determination unit 44 includes a current / voltage conversion circuit (indicated as “I / V” in FIG. 1) 34, a comparator circuit (indicated as “COMP” in FIG. 1) 35, and a timing signal generation circuit (in FIG. 1). Is expressed as “TIME”) 36. As will be described in detail later, the determination unit 44 outputs a predetermined signal (timing signal) to the control signal output circuit 37 when the base currents of the eighth and ninth transistors 18 and 19 become larger than a predetermined current. To output to.
The output stage OUT of each of the first to third current mirror circuits 31 to 33 is connected to the input stage of the current / voltage conversion circuit 34 so that the input current is output as a voltage signal. ing.

In the comparator circuit 35, the output voltage of the current / voltage conversion circuit 34 is applied to one input terminal, while a predetermined reference voltage V3 is applied to the other input terminal. The output voltage of the conversion circuit 34 is compared with the reference voltage V3, and a signal corresponding to the comparison result is output.
The timing signal generation circuit 36 is used as a determination signal correspondingly while a predetermined signal is output from the comparator circuit 35 after a predetermined time has elapsed since a predetermined signal (details will be described later) is output from the comparator circuit 35. , Configured to output a timing signal.

  A control signal output circuit (noted as “CONT-SIG” in FIG. 1) 37 serving as a control signal output unit stops the operation of the current source circuits 6 and 7 in synchronization with the timing signal from the timing signal generation circuit 36. It is configured to output a predetermined control signal for damaging.

Next, the operation in the above configuration will be described.
When a signal is input to the signal input terminal 4, predetermined signal processing is performed by the signal processing circuit 2, and the output signal is applied to the conductance amplifier 20 constituting the input stage of the output circuit 1 and converted into a current output. Thus, the signal is input to the base of the first transistor 11.
The signal input to the base of the first transistor 11 is output from its emitter, and is output from the signal output terminal 5 via the fifth, sixth, eighth and ninth transistors 15, 16, 18 and 19. The

    Here, when the constant current I5 output from the second constant current source 22 and the constant current I6 output from the third constant current source 23 are set to substantially the same current, the constant current output from the first constant current source 21 is set. The current I2 is equal to the current I1 flowing through the first transistor 11.

The current I9 flowing through the eighth transistor 18 has a value corresponding to the magnitude of the base-emitter voltage Vbe8 of the eighth transistor 18, and such Vbe8 can be determined by the following equation.
Vbe8 = Vcc- (desired constant voltage V2) -Vbe6
Here, Vbe6 is the base-emitter voltage of the sixth transistor 16.

Similarly, the current I10 flowing through the ninth transistor 19 has a value corresponding to the magnitude of the base-emitter voltage Vbe9 of the ninth transistor 19, and Vbe9 can be determined by the following equation.
Vbe9 = (desired constant voltage V1) −Vbe5
Here, Vbe5 is the base-emitter voltage of the fifth transistor 15.

  Further, the current flowing through the fourth transistor 14 is I3, the current flowing through the fifth transistor 15 is I4, the current flowing through the sixth transistor 16 is I7, the current flowing through the seventh transistor 17 is I8, and the third transistor Assuming that the current flowing through 13 is I11, a relationship represented by the following equation is established between them.

  I5 = I4 + I7

  I6 = I4 + I7

  I2 = I1 = I11

  The transistor sizes of the fourth and ninth transistors 14 and 19 and the seventh and eighth transistors 17 and 18 are preferably set to satisfy the following relationship.

  Q4: Q9 = 1: m

  Q7: Q8 = 1: n

  In such a setting, the current I3 of the fourth transistor 14 and the current I8 of the seventh transistor 17 have the following magnitudes.

  I3 = I10 / m

  I8 = I9 / n

  That is, the current I3 of the fourth transistor 14 is extracted as 1 / m of the current I10 of the ninth transistor 19, and the current I8 of the seventh transistor 17 is 1 of the current I9 of the eighth transistor 18. / N is taken out.

The current I3 flowing through the fourth transistor 14, the current I11 flowing through the third transistor 13, and the current I8 flowing through the seventh transistor 17 are input to the first to third current mirror circuits 31 to 33, respectively. The currents are current mirrored, output from the respective output stages OUT as the same or N times current, and input to the current / voltage conversion circuit 34. Then, the currents of the first to third current mirror circuits 31 to 33 input to the current / voltage conversion circuit 34 are converted into voltage signals by the current / voltage conversion circuit 34 and input to the comparator circuit 35, and the reference It is compared with the voltage V3.
That is, for example, when the output of the current / voltage conversion circuit 34 becomes a voltage corresponding to the abnormality of the currents I9 and I10 of the eighth and ninth transistors 18 and 19, the comparison result with the reference voltage V3 of the comparator circuit 35 is Then, a predetermined logic state (logic value High or logic value Low) corresponding to the abnormality of the currents I9 and I10 is obtained.

  In the timing signal generation circuit 36, when a predetermined logical value is output from the comparator circuit 35 for a predetermined time or more in response to the abnormality of the currents I9 and I10 as described above, the predetermined timing corresponding to the logical value High or the logical value Low. A level signal is output while a predetermined logical value is output from the comparator circuit 35. Accordingly, a predetermined control signal for stopping the operation of the current source circuits 6 and 7 is output from the control signal output circuit 37, and each current supply operation by the current source circuits 6 and 7 is stopped. The abnormal current flow in the eighth and ninth transistors 18 and 19 in the output stage is cut off.

Here, it is assumed that the signal output terminal 5 is short-circuited for some reason or a specific voltage is applied, and the circuit operation in that case will be further described.
When the current I9 flowing through the eighth transistor 18 becomes large due to a short circuit of the signal output terminal 5 or application of a specific voltage, the current I7 of the sixth transistor 16 decreases, while the current of the fifth transistor 15 decreases. I4 and the current I8 of the seventh transistor 17 increase.

The increase in the current I8 is amplified and output by the third current mirror circuit 33 with the set amplification degree, and is input to the current / voltage conversion circuit 34. From the current / voltage conversion circuit 34, the output current I9 is increased. A voltage signal corresponding to a predetermined logical value (logical value High or logical value Low) corresponding to the abnormality is output.
The output signal of the current / voltage conversion circuit 34 is compared with the reference voltage V3 in the comparator circuit 35. For example, when the output signal of the current / voltage conversion circuit 34 exceeds the reference voltage V3, the output current I9 is abnormal. Assuming that there is an output, the output of the comparator circuit 35 is in a state of a predetermined logical value, that is, for example, a logical value High. As a result of comparison between the output signal of the current / voltage conversion circuit 34 and the reference voltage V3, it is assumed that the output current I9 is abnormal, and the logical value of the signal output from the comparator circuit 35 is the logical value High as described above. There is no need to be limited, and the logical value Low is of course good.

As described above, the timing signal generation circuit 36 has a level corresponding to the logical value High or the logical value Low when a signal corresponding to the determination that the output current I9 is abnormal is output for a predetermined time or more in the comparator circuit 35. A signal is output, and the signal is input to the control signal output circuit 37.
As a result, the control signal output circuit 37 outputs a predetermined control signal for stopping the operation of the current source circuits 6 and 7. As a result, the operations of the current source circuits 6 and 7 are stopped, and the operations of the signal processing circuit 2 and the output circuit 1 are stopped.
In the timing signal generating circuit 36, the timing signal is output after a signal corresponding to the determination that the output current I9 is abnormal is output from the comparator circuit 35 for a predetermined time or more. This is to prevent the timing signal from being output.

Next, as in the case of I9 described above, when the current I10 of the ninth transistor 19 becomes a large current due to a short circuit of the signal output terminal 5 or application of a specific voltage, the fifth transistor 15 Current I4 decreases, while the current I7 of the sixth transistor 16 and the current I3 of the fourth transistor 14 increase.
The increase in the current I3 is amplified and output in the first current mirror circuit 31 with the set amplification degree, and is input to the current / voltage conversion circuit 34. The current / voltage conversion circuit 34 outputs the output current I10. Thus, a voltage signal corresponding to a predetermined logical value (logical value High or logical value Low) corresponding to the abnormality is output.
As a result, as in the case of the increase in the current I8, the control signal output circuit 37 outputs a predetermined control signal for stopping the operation of the current source circuits 6 and 7, and the operation of the current source circuits 6 and 7 is performed. It will be stopped.

Here, for example, when the base current of the eighth transistor 18 does not become extremely large, the change of the current I8 is usually detected by the third current mirror circuit 33 as described above. Thus, the operation of the current source circuits 6 and 7 can be stopped.
However, when the base current of the eighth transistor 18 becomes an extremely large current at a stroke from the idling state, for example, the current I9 becomes an abnormally large current at a stroke from the idling state. For this reason, the eighth transistor 18 In the case where the current amplification factor hfe of 18 is drastically reduced and, as a result, an abnormal increase in the base current occurs, the base current is the current I4 in the fifth and sixth transistors 15 and 16, as described above. Since the current I7 is out of balance and is too large to flow into the fifth transistor 15, it flows into the first transistor 11.

  Therefore, the second current mirror circuit 32 is provided to detect an increase in the current I11 of the first transistor 11 and thereby stop the operation of the current source circuit 7 as described above. Therefore, the operation of the second current mirror circuit 32 is basically the same as that of the first current mirror circuit 31 and the third current mirror circuit 33. Therefore, the detailed description here will be repeated. It will be omitted.

Next, transistor sizes of the eighth and ninth transistors 18 and 19 as output transistors will be described.
In general, in applications where a heavy load is connected to the output, the output transistor size is increased in order to improve the driving capability. For this reason, when laying out the output transistors, transistor cells that are normally used in the circuit are not arranged so as to have the required output transistor size, but are unique so that the output transistor size is as small as possible. Often laid out in the shape of.
When the layout is made in a unique shape so as to reduce the output transistor size in this way, in order to ensure an accurate transistor ratio, the detection transistors (in FIG. 1, the fourth transistor 14 and the seventh transistor 17 are It is possible to accurately detect a desired current by using a shape similar to that of an output transistor, instead of using a transistor cell that is used as a standard in the circuit.

Next, a second configuration example will be described with reference to FIG.
The same components as those in the first configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points are mainly described below. And
This second configuration example is different from the configuration example shown in FIG. 1 above in that the controlled object of the current source control circuit 3 is limited to the current source circuit 7 of the output circuit 1. The portion is the same as the configuration example shown in FIG.
Therefore, the operation is basically the same as that of the configuration example shown in FIG. 1, and detailed description thereof is omitted here.

  In the case of this second configuration example, unlike the first configuration example shown in FIG. 1, only the current source circuit 7 is controlled to operate, and the output stage current I9 becomes an abnormal magnitude due to a short circuit or the like. Since the signal processing circuit 2 is always in the operation state and only the output circuit 1 is stopped, the time required for the return of the operation is compared with the case of the first configuration example shown in FIG. Therefore, the circuit operation as a whole can be quickly restored. This is because the output circuit 1 has relatively few components as compared with the signal processing circuit 2, so that the time required for the operation recovery is shorter than the time required for the operation recovery of the signal processing circuit 2. .

It is a block diagram which shows the 1st structural example of the current source control circuit in embodiment of this invention. It is a block diagram which shows the 2nd structural example of the current source control circuit in embodiment of this invention. It is a circuit diagram which shows one structural example of the conventional signal output circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Output circuit 2 ... Signal processing circuit 3 ... Current source control circuit 4 ... Signal input terminal 5 ... Signal output terminal 6 ... Current source circuit 7 ... Current source circuit 31 ... First current mirror circuit 32 ... Second current mirror Circuit 33 ... Third current mirror circuit 34 ... Current / voltage conversion circuit 35 ... Comparator circuit 36 ... Timing signal generation circuit 37 ... Control signal output circuit

Claims (3)

An abnormal current in the output stage is detected in an output circuit comprising an output stage that is push-pull connected and a current source circuit that supplies a current necessary for circuit operation, and the current source circuit is stopped. A current source control circuit comprising:
A base current detection unit for detecting a base current of an output transistor constituting the output stage;
A determination unit that outputs a predetermined determination signal that an abnormal current has occurred in the output stage when the base current detected by the base current detection unit is equal to or greater than a predetermined value over a predetermined time;
A control signal output unit that outputs a predetermined control signal for stopping the operation of the current source circuit according to the output of the determination unit;
A current source control circuit comprising: A signal processing circuit is provided in the preceding stage of the output circuit, and the signal processing circuit has a current source circuit that supplies a current necessary for circuit operation.
The control signal of the control signal output unit is applied to the current source circuit provided in the signal processing circuit together with the current source circuit provided in the output circuit, so that the two current source circuits can be stopped. The current source control circuit according to claim 1, wherein: The base current detection unit is provided with detection transistors that detect base currents of two output transistors that are push-pull connected and constitute an output stage, and the two detection transistors are transistors of the corresponding output transistors. Each transistor is formed in a small transistor size with a predetermined ratio to the size, and the corresponding output transistor and base are connected to each other,
3. The current source control circuit according to claim 1, further comprising a current mirror circuit that current mirrors the collector currents of the two detection transistors to the determination unit.

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