JP2010056758A - Dll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DLL circuit having high-accuracy synchronous characteristics. <P>SOLUTION: The DLL circuit includes: a variable delay circuit 11 to which a first clock signal CLK1 is inputted, which outputs a second clock signal CLK2 generated by delaying the first clock signal CLK1, and whose delay time is varied by a control signal Vc; a phase detection circuit 12 to which the first clock signal CLK1 and the second clock signal CLK2 are inputted and which compares the phase of the first clock signal CLK1 with that of the second clock signal CLK2 so as to output a signal according to the phase difference ΔΦ; an integration circuit 13 for integrating output V1 of the phase detection circuit 12; a comparison circuit 14 which compares output V2 of the integration circuit 13 with a predetermined reference value Vref so as to output the comparison result; and a low-pass filter 15 which averages output V3 of the comparison circuit 14 so as to output a signal, whose high-frequency component is removed, to the variable delay circuit 11 as the control signal Vc. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a DLL circuit.

  A DLL (Delay Locked Loop) circuit is a circuit that generates a pulse signal whose phase is divided in synchronization with a clock signal. For example, a DLL (Delay Locked Loop) circuit is provided in a semiconductor integrated circuit such as a synchronous DRAM (Dynamic Random Access Memory). Are used in a synchronous signal generating circuit for generating an internal clock signal synchronized with the external clock signal.

Conventionally, a DLL circuit in which a charge pump circuit is connected between a phase detection circuit and a loop filter is known.
However, a DLL circuit using a charge pump circuit has a clock signal and a clock signal due to variations in characteristics of the charge pump circuit due to a manufacturing process, a use voltage, an operating temperature, and the like when the circuit is integrated. There is a problem that a static phase error (Static Phase Error: SPE) indicating a steady deviation with respect to a clock signal synchronized with the signal becomes large.

  In particular, when an analog charge pump circuit is integrated using a digital manufacturing process, the digital process has a larger process variation than the analog process, resulting in an increase in characteristic variation.

On the other hand, a DLL circuit using a charge pump circuit that suppresses the influence of a manufacturing process or the like is known (for example, see Patent Document 1).
The DLL circuit disclosed in Patent Document 1 is a mirror type DLL circuit, and uses a plurality of replicas, so that there is a problem that the circuit configuration is complicated and large.

Also, a DLL circuit that does not use a charge pump circuit is known (see, for example, Patent Document 2).
The DLL circuit disclosed in Patent Document 2 is a high-speed clock delay circuit, which has first and second delay elements each having an input connected to a common clock input, and is connected to the first and second delay elements, respectively. First and second integrators, a differential amplifier having first and second inputs connected to the outputs of the first and second integrators, respectively, and control of one delay element from the output of the differential amplifier A control loop connected to the port.

However, since the DLL circuit disclosed in Patent Document 2 uses a plurality of delay elements and integrators, there is a problem that the circuit configuration becomes large and is easily affected by noise.
JP 2001-332086 A JP-T-2002-517133

  The present invention provides a DLL circuit having highly accurate synchronization characteristics.

  A DLL circuit of one embodiment of the present invention includes a variable delay circuit that receives a first clock signal, outputs a second clock signal obtained by delaying the first clock signal, and has a delay time variable by a control signal; A phase detection circuit that receives the first clock signal and the second clock signal, compares the phases of the first clock signal and the second clock signal, and outputs a signal corresponding to the phase difference; and An integration circuit that integrates the output of the detection circuit, a comparison circuit that compares the output of the integration circuit with a predetermined reference value, outputs a comparison result, and a signal obtained by averaging the output of the comparison circuit and removing high-frequency components And a low-pass filter that outputs the control signal as the control signal to the variable delay circuit.

  According to the present invention, a DLL circuit having highly accurate synchronization characteristics can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A DLL circuit according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing the DLL circuit of this embodiment, FIG. 2 is a diagram showing the synchronization characteristics of the DLL circuit of this embodiment in comparison with the comparative example, and the solid line in the figure shows the synchronization characteristics of this embodiment. The broken line in the figure shows the synchronization characteristic of the comparative example.

  As shown in FIG. 1, the DLL circuit 10 of this embodiment receives a first clock signal CLK1, outputs a second clock signal CLK2 obtained by delaying the first clock signal CLK1, and delays by a control signal Vc. The variable delay circuit 11 to be varied, the first clock signal CLK1 and the second clock signal CLK2 are input, the phases Φ1 and Φ2 of the first clock signal CLK1 and the second clock signal CLK2 are compared, and the phase difference ΔΦ The phase detection circuit 12 that outputs a signal V1 according to the above, the integration circuit 13 that integrates the output V1 of the phase detection circuit 12, and the output V2 of the integration circuit 13 are compared with a predetermined reference value Vref, and the comparison result is output. The comparison circuit 14 and the output V3 of the comparison circuit 14 are averaged, and the signal from which the high frequency component is removed is output to the variable delay circuit 11 as the control signal Vc. A low pass filter 15 which is provided with a.

The variable delay circuit 11 is a series circuit of a buffer or an inverter configured to control the delay time by changing the control voltage Vc applied to the gate of the MOS transistor, for example, and controlling the discharge time of the charge. This is a circuit with delay time control.
By extracting the tap from the middle of the buffer or inverter series circuit, a pulse signal having a divided phase can be obtained.

  The phase detection circuit 12 includes a phase frequency comparison circuit 16 and a phase addition circuit 17. The phase frequency comparison output circuit 16 includes, for example, a flip-flop and a NAND circuit. When a signal having a phase difference is added to the first input terminal Ref and the second input terminal Fb, the phase frequency comparison output circuit 16 detects the phase difference at the falling edge of the signal. A pulse having a duty ratio corresponding to the phase difference between the first input terminal Ref and the second input terminal Fb is output to the first output terminal Up and the second output terminal Dn.

The phase addition circuit 17 is an addition circuit having a resistor R1, a series circuit of an inverter 18 and a resistor R2. One end of the resistor R1 is connected to the first output terminal Up, one end of the inverter 18 is connected to the second output terminal Dn, and the resistors R1 and R2 are commonly connected to the integrating circuit 13. Here, the resistors R1 and R2 are set equal.
As a result, the difference between the output signals of the first output terminal Up and the second output terminal Dn is input to the integration circuit 13 as the output V1 of the phase detection circuit 12.

The integrating circuit 13 includes an operational amplifier 19 and a capacitor C1 connected to the negative feedback loop of the operational amplifier 19.
Since the integration circuit 13 charges the capacitor C1 according to the output signal of the first output terminal Up and discharges it according to the output signal of the second output terminal Dn, the output obtained by integrating the output V1 of the phase detection circuit 12 V2 is output to the comparison circuit 14.

The comparison circuit 14 is a synchronous digital comparator that operates in synchronization with the first clock signal CLK1.
The comparison circuit 14 compares the output V2 of the integration circuit 13 with a reference value Vref, for example, the reference potential GND, and outputs an “L” level when the output V2 is greater than or equal to the reference value Vref, and the output V2 is the reference value. When it is smaller than Vref, “H” level is output.

  The comparison circuit 14 also serves as an analog-to-digital conversion function that converts an analog output V2 that is necessary when a low-pass filter 15 described later is realized with a digital filter into a digital value.

  The low-pass filter 15 is a lag type primary filter having a resistor Rf and a capacitor Cf, and is also called a loop filter.

  When the first clock signal CLK1 is input to the first input terminal Ref as a reference signal and the second clock signal CLK2 is input to the second input terminal Fb as a feedback signal, the phase detection circuit 16 receives the first clock signal CLK1. And a pulse corresponding to the edge difference between the second clock signal CLK2 and the second clock signal CLK2.

When the phase of the second clock signal CLK2 is delayed with respect to the first clock signal CLK1 (ΔΦ = Φ2-Φ1> 0), the phase detection circuit 16 sets the first output terminal Up to the first amount corresponding to the edge difference. Output a pulse.
On the other hand, when the phase of the second clock signal CLK2 is advanced with respect to the first clock signal CLK1 (ΔΦ = Φ2−Φ1 <0), the phase detection circuit 16 supplies the second output terminal Dn to the amount corresponding to the edge difference. The second pulse is output.
The first pulse and the second pulse are added by the phase addition circuit 17, and a signal V1 corresponding to the phase difference ΔΦ is output.

FIG. 2 is a diagram showing the synchronization characteristics of the DLL circuit 10 in comparison with the comparative example, in which the solid line shows the synchronization characteristics of this embodiment, and the broken line shows the synchronization characteristics of the comparative example.
Here, the synchronization characteristic of the DLL circuit means the relationship between the intermediate output of the variable delay circuit 11 shown in FIG. 3 and the delay amount. The comparative example means a DLL circuit using the charge pump circuit shown in FIG.

  As shown in FIG. 3, when the variable delay circuit 11 is a series circuit of six-stage inverters whose delay amount is variable by, for example, the control signal Vc, the output of each inverter is externally output as an intermediate output by taps T1 to T6. Has been drawn to.

  As shown in FIG. 4, the charge pump circuit 30 of the DLL circuit of the comparative example includes a capacitor C2, a constant current source 31 that charges the capacitor C2 with a constant current Ip1 via a switch S1, and a capacitor C2 via a switch S2. And a constant current source 32 for discharging at a constant current Ip2. The constant current Ip1 and the constant current Ip2 are set equal.

  The capacitor C2 is charged with the constant current Ip1 according to the output signal of the first output terminal Up of the phase frequency comparison circuit 16, and the capacitor C2 is discharged with the constant current Ip2 according to the output signal of the second output terminal Dn. A signal obtained by integrating the signal corresponding to ΔΦ is output as the control signal Vc.

Here, when integrating the DLL circuit, the constant current Ip1 and the constant current Ip2 are not necessarily equal due to variations in the manufacturing process, the operating voltage, the operating temperature, and the like.
The offset between the constant current Ip1 and the constant current Ip2 causes an offset in the output Vc of the charge pump circuit 30.

  As shown in FIG. 2, in the comparative example, since the feedback loop of the second clock signal CLK2 operates so as to cancel the offset of the control signal Vc described above, for example, when the constant current Ip1 is larger than the constant current Ip2, the synchronization is performed. The characteristic becomes a characteristic indicated by a broken line 35, and a static phase error SPE2 indicating a steady phase deviation between the first clock signal CLK1 and the second clock signal CLK2 occurs.

  On the other hand, in the present embodiment, the offset by the operational amplifier 19 of the integrating circuit 13 is basically canceled in the DLL circuit 10, so that no offset occurs in the control signal Vc. Specifically, for the following reason.

  First, assuming that the DLL circuit 10 is in a locked state and the phase frequency comparison circuit 16 is in an ideal case where there is no offset, the offset of the operational amplifier 19 is equivalently applied to the negative input terminal of the operational amplifier 19. Let it be represented by an offset voltage source Vos connected in series.

  The Up signal output to the first output terminal Up and the Dn signal output to the second output terminal Dn cancel each other, and the potential V1 input to the operational amplifier 19 is equal to the potential Vref (for example, the power supply voltage) of the positive input terminal. V1 = Vref.

At this time, since no current flows into the negative input terminal of the operational amplifier 19, the output V2 as the integrator 13 is kept constant. That is, when the DLL circuit 19 is locked, the charge charged in the capacitor C1 is constant.
The output V2 of the integrator output 13 is V2 = − (Vos + Vc1) when the potential of the capacitor C1 is Vc1. The negative sign of V2 is determined by the definition of which one of the potentials of the offset voltage source Vos and the capacitor C1 is set to the positive side.

Assuming that the control signal Vc when the DLL circuit 10 is locked is V *, in the locked state, the DLL circuit 10 operates so that both the output V2 and the output V3 maintain a potential equal to V *. For example, if the average value of the output V3 is V * for simplicity, the average value of the output V2 is − (Vos + Vc1).
In other words, the voltage at the time of locking the output V2 is determined, and V2 = − (Vos + Vc1) is always obtained.

As a result, even if the output V2 and the offset voltage source Vos vary depending on the manufacturing process, the system operates so that Vc1 = − (V * −Vos) because the output V2 when the DLL circuit 10 is locked is V *. The capacitor C1 is charged.
As a result, the DLL circuit 10 can be locked within the operating range of the operational amplifier 19 regardless of the offset voltage source Vos.

Therefore, the synchronization characteristic of the present embodiment has the characteristic indicated by the solid line 36, and the static phase error SPE1 can be suppressed.
Here, in the variable delay circuit 11, there is no variation in the delay circuit of each inverter and no gain error.

  As described above, the DLL circuit of this embodiment is connected between the phase detection circuit 12 and the low-pass filter 15, and the signal V1 corresponding to the phase difference ΔΦ between the first clock signal CLK1 and the second clock signal CLK2. Are integrated, and a comparison circuit 14 that compares the output V2 of the integration circuit 13 with a predetermined reference value Vref and outputs a comparison result is provided.

As a result, even if the DLL circuit is integrated, no offset occurs in the control signal Vc, so that the static phase error SPE can be suppressed.
Further, since the configuration of the DLL circuit is simpler than that of a DLL circuit using a plurality of delay elements and integrators, noise resistance is improved, and the DLL circuit can be operated stably. Therefore, the DLL circuit 10 having a highly accurate synchronization characteristic can be obtained.

  Although the case where the low-pass filter 15 is a primary filter having a resistor Rf and a capacitor C1 has been described here, it may be a secondary filter. Since the secondary filter can obtain a steeper high frequency cut characteristic than the primary filter, there is an advantage that noise resistance is improved.

Furthermore, in integrating the DLL circuit, a digital filter is more suitable as a low-pass filter than an analog filter.
In the digital filter, since the input V3 is digital stream data, 1) it is easy to determine the cutoff frequency of the filter, and a stable cutoff frequency can be obtained (not affected by variations in C and R). 2) DLL circuit There are advantages such as easy operation as a notch filter for blocking the passage of the first clock signal CLK1 component and its harmonics, which are factors that increase the jitter.

FIG. 5 is a circuit diagram showing a main part of a DLL circuit using a digital filter as a low-pass filter.
As shown in FIG. 5, the DLL circuit 40 converts the digital output of the secondary digital filter 41 connected between the integrating circuit 13 and the variable delay circuit 11 and the digital output of the digital filter 41 into an analog voltage for control. And a digital analog conversion circuit 42 for obtaining the signal Vc.
The digital filter 41 is not particularly limited. For example, a moving average filter that can be configured by a shift register and an adder is simple and suitable.

  Although the case where the phase detection circuit 12 includes the phase frequency comparison circuit 16 has been described, a phase comparison circuit (PD) such as an XOR circuit or a JK flip-flop may be used.

Although the case where the integration circuit 13 is an analog circuit having the operational amplifier 19 and the capacitor C1 has been described, a filter using a switched capacitor circuit that opens and closes a switch with a control pulse having a constant period and repeatedly charges and discharges the capacitor. It is also possible to use a digital circuit such as
The switched capacitor circuit requires a long time for settling, but is characterized by being robust against variations, and is therefore suitable when accuracy is required from the operating speed compared to the analog integration circuit 13. ing.

The phase detection circuit 12, the integration circuit 13, the comparison circuit 14, and the low-pass filter 15 can also be applied to a PLL (Phase Locked Loop) circuit.
In that case, a VCO (Voltage Controlled Oscillator) may be connected after the low-pass filter 15 instead of the variable delay circuit 11.

A DLL circuit according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a main part of the DLL circuit. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.
This embodiment differs from the first embodiment in that the control signal is converted into a current and transmitted from the low-pass filter to the variable delay circuit.

  That is, as shown in FIG. 6, the DLL circuit 50 of this embodiment is a voltage current that converts the output voltage (control signal Vc) of the low-pass filter 15 into a current Ic between the low-pass filter 15 and the variable delay circuit 11. A conversion circuit 51; a current path 52 that transmits the current Ic; and a current-voltage conversion circuit 53 that converts the current Ic transmitted through the current path 52 into a voltage and outputs the voltage again to the variable delay circuit 11 as a control signal Vc. It has.

  When the DLL circuit 50 is integrated, if the wiring connecting the low-pass filter 15 and the variable delay circuit 11 is drawn variously due to the layout, noise is mixed in the wiring and the operation of the variable delay circuit 11 is affected. There is a risk.

  Since the DLL circuit 50 converts the control signal Vc into the current Ic and transmits it, the influence of noise can be suppressed even if the current path 52 is drawn variously due to the layout.

  As is well known, the voltage-current conversion circuit 51 and the current-voltage conversion circuit 53 can be used in various circuit configurations having an operational amplifier and a resistor.

  As described above, the DLL circuit 50 of the present embodiment converts the control signal Vc into the current Ic and transmits it, and returns the current Ic back to the control signal Vc before inputting it to the variable delay circuit 11. There is an advantage that the influence of noise during transmission can be suppressed.

1 is a circuit diagram showing a DLL circuit according to Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating delay characteristics of the DLL circuit according to the first embodiment of the invention in comparison with a comparative example. 1 is a circuit diagram showing a main part of a DLL circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing the main part of a DLL circuit of a comparative example according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram showing another DLL circuit according to Embodiment 1 of the present invention. The circuit diagram which shows the DLL circuit which concerns on Example 2 of this invention.

Explanation of symbols

10, 40, 50 DLL circuit 11 Variable delay circuit 12 Phase detection circuit 13 Integration circuit 14 Comparison circuit 15 Low-pass filter 16 Phase frequency comparison circuit 17 Phase addition circuit 18 Inverter 19 Operational amplifier 30 Charge pump circuit 31, 32 Constant current source 41 Digital filter 42 DA conversion circuit 51 voltage current conversion circuit 52 current path 53 current voltage conversion circuit C1, C2, Cf capacitor R1, Rf resistance S1, S2 switch

Claims (3)

A variable delay circuit that receives a first clock signal, outputs a second clock signal obtained by delaying the first clock signal, and has a delay time variable by a control signal;
A phase detection circuit that receives the first clock signal and the second clock signal, compares the phases of the first clock signal and the second clock signal, and outputs a signal corresponding to the phase difference;
An integration circuit for integrating the output of the phase detection circuit;
A comparison circuit that compares the output of the integration circuit with a predetermined reference value and outputs a comparison result;
A low-pass filter that averages the output of the comparison circuit and outputs a signal from which a high-frequency component has been removed to the variable delay circuit as the control signal;
A DLL circuit comprising:   The DLL circuit according to claim 1, wherein the low-pass filter is a second-order or higher-order digital filter.   Between the low-pass filter and the variable delay circuit, a voltage-current conversion circuit for converting a voltage output from the low-pass filter into a current, a current path for transmitting the current, and a current transmitted by the current path The DLL circuit according to claim 1, further comprising: a current-voltage conversion circuit that converts the voltage into a voltage and outputs the voltage to the variable delay circuit as the control signal.

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