JP2010056688A - Method and program for processing synchronous operation of digital signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and program for processing a synchronous operation of a digital signal, which reduce error without changing a given sample frequency even if the synchronous period, i.e. the ratio of the analog input signal frequency and the sampling frequency, is not an integer in the synchronous operation of the digital signal. <P>SOLUTION: With regard to the synchronous operation of the digital signal, the ratio of the analog input signal frequency and the sampling frequency, i.e. the synchronous period, is divided into an integer part and a fraction, and the numeric values of the integer part and fraction are used directly as weights in synchronous operation for sample values separated by the sampling period. A digital signal synchronous operation processing program performs digital signal synchronous operation continuously every sampling period on a computer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a digital signal processing and a digital signal processing program for extracting or removing signal components.

In the field of digital signal processing, arithmetic processing synchronized with signal components is desired.

  For example, in the conventional synchronous addition process, a process of adding the impulse response as many times as necessary is performed in order to generate an impulse response corresponding to the impulse signal, which is a synchronization signal, and to increase the signal-to-noise ratio of the signal. (For example, see Non-Patent Documents 1 to 3).

  As a technique using the synchronous addition method, there is a technique relating to a specific device used for synchronous detection of an electrocardiogram and a magnetocardiogram (Patent Document 1).

  In addition, regarding the synchronous subtraction method, as the signal processing of the apparatus, the same stimulus is repeatedly added twice, and only the voluntary myoelectricity is extracted by performing synchronous subtraction with the subsequent two stimuli. There is a technique similar to the processing (Patent Document 2). The synchronous subtraction process is equivalent to a process for obtaining an interpolated value between two sample values.

Wherein in the synchronization processing are both the ratio of the analog signal frequency f _p and the sampling frequency f _s to be the synchronization processing (number 1) is problematic.

Synchronization processing of the are both process synchronization period N _p of the digital signal processing is regarded as an integer, when the synchronization period N _p is not an integer occurs an error in the synchronization processing.

If the synchronization period N _p is larger, that is, when the sampling frequency is relatively large enough may be regarded as the influence of rounding by rounding off the decimal point of the synchronization period N _p is small with respect to the synchronization processing.

On the other hand, if the synchronization period N _p is small, that is, when the sampling frequency is not relatively large enough, the effect of integer rounding rounding off after the decimal point of the synchronization period N _p is not negligible with respect to the synchronization processing . That results in an error in the synchronization processing by rounding the synchronization period N _p.

  In the case where an error occurs in the digital signal synchronization calculation processing, in the conventional technique, the apparent sampling frequency is increased by interpolating between sample values.

  However, since the interpolation processing related to the signal sampling involves complicated calculation, there is a problem that it is difficult to process in real time with respect to a high frequency or with a device having low calculation capability.

Therefore, there is a demand for a technique that uses only given sample conditions without using the interpolation processing related to the signal sampling, and improves the accuracy of the synchronous calculation processing for the digital signal.

Miyagawa Hiroshi et al., “Digital Signal Processing”, IEICE, 1975 Shinji Ozawa, "Digital Signal Processing", Jikkyo Publishing, 1979 Tetsuya Shimamura, Nobunobu Kuroiwa, “LPC analysis based on noise reduction using pitch-synchronized addition processing,” IEICE theory, Vol. J87-A, pp. 458-469, 2004 Japanese Examined Patent Publication No. 7-67440 JP 2004-255104 A

In the digital signal synchronization calculation processing, the given sampling frequency is changed even when the ratio of the analog signal frequency f _p to be processed and the sampling frequency f _s , that is, the synchronization period (the above equation 1) is not an integer. It is another object of the present invention to provide a digital signal synchronous calculation processing method and a synchronous calculation processing program with little error.

In the digital signal synchronization calculation processing according to the present invention, even when the ratio between the target analog signal frequency and the sampling frequency is not an integer, the synchronization period is expressed by (Expression 2) without changing the sampling frequency. In this way, it is divided into an integer part and a decimal part, and the synchronization calculation processing is performed on sample values separated by a direct sampling period by using the numerical values of the integer part and the decimal part as weights.

In the case of the synchronous addition process or the synchronous subtraction process, two sample values x (N) and x (N + 1) sampled at an arbitrary time are used with appropriate weights added by the numerical value F of the decimal part, and the synchronization is performed. A feature is that a sample value x (N _p ) relating to the period N _p is obtained, and synchronous addition or synchronous subtraction processing is performed on the two digital signals.

In the case of cumulative addition processing or cumulative subtraction processing, the corresponding sample values between two points separated by N or N + 1 sampled at an arbitrary time are synchronously added or synchronously subtracted over one period. At that time, the corresponding sample values adjusted by the numerical F of the fraction, it is a feature of performing cumulative synchronous addition or accumulation synchronization subtraction between two points spaced N _p as average.

  In particular, with regard to cumulative synchronous addition, accuracy is limited in the process of obtaining an interpolation value. A feature is that two points corresponding to the synchronization period are synchronously added over one period, and the synchronization period is averaged to a theoretical value.

The digital signal synchronization calculation processing program is characterized in that the digital signal synchronization calculation processing is continuously performed on a computer every sampling period.

According to the present invention, it is possible to reduce an error with respect to the accuracy of the synchronization calculation processing due to the fact that the synchronization period, that is, (Equation 1) is a non-integer, using only a given sampling frequency.

A block diagram of a synchronous arithmetic processing system for carrying out the present invention is shown in FIG. The synchronous arithmetic processing system is a digital signal synchronous arithmetic processing program stored in an external storage device on the computer shown in FIG. However, the configuration is not limited to that shown in FIG. 2 as long as the computer operates the synchronous calculation processing program.

  1 and 2 will be described in association with each other. The synchronous calculation processing program is stored in the external storage device 8 in advance. During operation, the computer 7 is read into the memory 7 through the computer system bus 5 and the computer interface 6 and the arithmetic unit 9 are used to perform the synchronous arithmetic processing according to the present invention.

Input unit 1, the analog signal x (t) of frequency f _p at time t, and or temporarily stored in a part of the external storage device 8 and the memory 7 via the interface, used as input signal of the synchronization processing program . Further, an analog signal to be subjected to arithmetic processing may be stored in advance in the external storage device 8 as an input.

The sampling processing section 2, the analog input signal x (t), the sampling frequency is f _s, is sampled into a digital signal x (n). The sampled signal x (n) is temporarily stored in a part of the external storage device 8 or a part of the memory 7.

  The synchronization processing unit 3 uses a computer arithmetic unit 9 and a memory 7 or an external storage unit 8 for the sampled digital signal x (n) to obtain a ratio between a target analog signal frequency and a sampling frequency. Even when the synchronization period is not an integer, the sampling value in the sampling processing unit 2 is not changed and the sampling process is performed again. Synchronous calculation processing is performed, which is divided into decimal parts, and the numerical values of the integer part and the decimal part are directly used as weights.

In the case of synchronous addition or synchronous subtraction, the precision is almost determined by how many digits are used to express the numerical value of the decimal part. For example, when the number of decimal places is two digits, x (N _p ) is determined as follows.

This process corresponds to obtaining an interpolation value of two points x (N) and x (N + 1). Further, in the case of cumulative synchronous addition or cumulative synchronous subtraction, sample values x (n) and x (n + N) between two points separated by one cycle are sampled corresponding to each other for one cycle (100-F) cycles. Addition / subtraction is performed over the F period, and the corresponding two sample values are added / subtracted as x (n) and x (n + N + 1). Incidentally, (100-F) and if F is possible lowest terms, is performed as much as possible averaged even above synchronization processing, one cycle average is set to be the N _p. For example, when the reduced result is 9/2, processing such as 4 cycles, 1 cycle, 5 cycles, and 1 cycle is performed.

The result y (n) after the synchronous calculation process is stored in the external storage device 8 by the output unit 4. The format of the data to be stored simply describes the value of y (n) for a certain value of n.

As a first embodiment, FIG. 3 shows the synchronous subtraction processing of the notch comb filter 10 whose system function is represented by (Equation 4).

Assuming that f _p is 100 Hz and f _s is 1025 Hz, N _p is 10.25, N is 10 and F is 25 according to (Equation 1). First, at this time, the characteristics when the synchronous subtraction processing is realized by the following two equations (Equation 5) and (Equation 6) and (Equation 7), that is, (Equation 8) and (Equation 9) are compared.

(Equation 5) is obtained by approximating the value of x (N _p ) using N = 10 obtained by converting N _p = 10.25 into an integer, that is, N _p = 10, to obtain a notch comb filter (Equation 6 ) Is realized.

  FIG. 5 shows a flow of an algorithm related to the synchronous arithmetic processing program according to the embodiment of the present invention. In the flow in FIG. 5, first, the number of calculations (S1) is set. The variable n is a discrete-time variable related to the sampling time, and the number of operations M needs to be a value sufficient to process the analog input signal. After calculation of the synchronization period (S2), an integer part N and a fractional part F of the synchronization period are obtained (S3). In the flow in FIG. 5, synchronous subtraction processing (S4) to (S6) and cumulative synchronous addition processing (S7) to (S9) are performed at the same time, but two processing (S4) to (S6) or (S7) are performed. Through (S9) may be a single flow. In addition, although the calculation accuracy of the following embodiments is two digits after the decimal point, the present invention is not limited to this and can be simply expanded even if it is three digits or more after the decimal point.

On the other hand, in (Expression 8), not only the numerical value of the integer part N = 10 but also the numerical value F = 25 of the decimal part is considered in the result (S3) of the calculation (S2) shown in FIG. In FIG. 5 (S5), the weight of x (n-10) is 3/4, the weight of x (n-11) is 1/4, and the value of x (N _p ) is obtained to obtain a notch comb filter ( Equation 9) is realized.

FIG. 6 shows an input signal x (n) = sin {2π × (100/1025) n} (solid line in FIG. 6) and each comb having the system functions represented by the above (Equation 6) and (Equation 9). The output signal of a filter is shown. The former filter output is indicated by a dotted line, and the latter filter output is indicated by a broken line. Ideally, when a notch filter performs subtraction processing in complete synchronization, its output becomes zero. In the comb filter (broken line in FIG. 6) using (Equation 9) according to the present invention, a value with a smaller error closer to zero output is obtained.

Next, as a second embodiment, a cumulative synchronous addition process of the resonance type comb filter 12 whose system function is represented by (Equation 10) is shown in FIG.

As the cumulative synchronous addition processing, the same conditions as in the first embodiment, that is, N _p = 10.25 is approximated by N = 10, that is, N _p = 10 is used (Equation 11) and (Equation 12), and decimal The processes (Formula 13) and (Formula 14) using the part F = 25 are compared.

In this case, in FIG. 5 (S8), the processing corresponding to N _p = 10 is (100−F) = 75 cycles. On the other hand, since the processing corresponding to N _p = 11 is F = 25 cycles, the processing of N _p = 10 (Equation 13) is calculated for three cycles, and then the processing of N _p = 11 (Equation 14) is performed in one cycle. What is necessary is just to add synchronously as minutes.

  The cumulative synchronous addition process is averaged by repeatedly calculating the synchronous addition process for a necessary period. Note that (Equation 13) and (Equation 14) are characterized in that two corresponding sample values separated by one cycle are synchronously added over one cycle.

FIG. 7 shows the input signal x (n) = sin {2π × (100/1025) n}. Example 1 in the same manner as in the signal frequency _{f p} is 100 Hz, the sampling frequency _{f s} is a periodic signal of 1025Hz.

  FIG. 8 shows an output signal of a resonant comb filter that performs cumulative synchronous addition processing with a synchronous period approximated by N = 10. On the other hand, FIG. 9 shows an output signal of a resonant comb filter that performs cumulative synchronous addition processing according to the present invention, in which the synchronous addition is repeatedly calculated for a necessary period using the fractional part F = 25.

Hereinafter, FIG. 8 and FIG. 9 will be compared. In (Equation 11), since the synchronization is slightly shifted, the accumulated value y (n) has a characteristic of hitting a beat. On the other hand, in (Equation 13) and (Equation 14), y (n) increases linearly. Ideally, it has been found that the output of the cumulative addition resonant comb filter for a periodic input signal increases linearly when the signal is perfectly synchronized. Therefore, it can be said that the cumulative synchronous addition processing according to the present invention is almost completely synchronized.

In addition, an embodiment relating to synchronous subtraction processing when a single tone signal is used as an input signal will be described. Figure 10 is an input signal of the fundamental frequency _f p = 1174.65Hz and its harmonics piano D6. 11 and 12 show output signals obtained by subjecting the input signal to synchronous subtraction processing with a notch comb filter (Equation 4). Since the sampling frequency is 44.1 kHz, the synchronization period N _p = 37.5. Further, when the value of the synchronization period is approximated as an integer, N = 38. The output signal of FIG. 11 is an output signal of a notch comb filter that performs a synchronization operation approximated as an integer as in the prior art, and the output signal of FIG. 12 is the fractional part F = 5 of the synchronization period according to the present invention. Is an output signal of a notch-type comb filter that performs a synchronous calculation considering the above. Next, the synchronization subtraction processing outputs obtained by the two synchronization methods are compared.

FIG. 13 compares the powers of the filter output signals related to the synchronous subtraction processing by the two methods. The synchronous subtraction process using the fractional part F = 5 in the synchronization period has a smaller power, and considering that the power is proportional to the square of the signal amplitude, the comb filter using the synchronization method according to the present invention is used. However, it can be said that a signal with a smaller error closer to zero output is obtained.

Finally, an embodiment relating to cumulative synchronous addition processing when a single tone signal is used as an input signal will be described. Figure 14 is an input signal of the fundamental frequency _f p = 4185.98Hz and its harmonics piano C8. Cumulative synchronous addition is performed using a resonant comb filter (Equation 10) for the input signal. The sampling frequency is f _s = 44.1 kHz. Therefore, the synchronization period is approximately N _p = 10.3, and the synchronization period N = 10 approximated as an integer.

  FIG. 15 shows an output signal of a resonant comb filter that performs cumulative synchronous addition processing in a synchronous cycle approximated by N = 10. On the other hand, FIG. 16 shows an output signal of a resonant comb filter that performs cumulative synchronous addition processing according to the present invention, in which the synchronous addition is repeatedly calculated for a necessary period using the fractional part F = 3.

  Hereinafter, FIG. 15 and FIG. 16 will be compared. In the synchronization calculation using the approximated synchronization cycle, since the synchronization is slightly shifted, the accumulated value has a significant beat. On the other hand, in the synchronization calculation using the synchronization period according to the present invention, the accumulated value has few beats and increases almost linearly. Ideally, the output of a cumulative addition resonant comb filter with respect to a periodic input signal may increase linearly if the input signal is a stationary periodic signal, if it is perfectly synchronized. I know it. Therefore, it can be said that the cumulative synchronous addition processing according to the present invention is almost synchronized. However, the input signal of the fourth embodiment (FIG. 14) is a periodic decay signal, and its accumulated value is finally saturated. Therefore, in FIG. 16, when the number of samples increases, it gradually deviates from the linear increase.

According to the present invention, accurate synchronous addition and subtraction processing or cumulative synchronous addition and subtraction processing can be performed without changing the sampling frequency, which is effective for extracting or removing a specific frequency signal component from an actual sound.

It is a block diagram of the synchronous arithmetic processing system which concerns on this invention. It is a schematic diagram of the computer for implementing a synchronous arithmetic processing system. It is a schematic diagram of the notch type | mold comb filter which performs the synchronous subtraction process which concerns on Example 1 of this invention. It is a schematic diagram of the resonance type | mold comb filter which performs the accumulation synchronous addition process which concerns on Example 2 of this invention. It is a flow showing the algorithm of the synchronous calculation process which concerns on Example 1 and Example 2 of this invention. It is an input / output signal of synchronous subtraction processing according to Embodiment 1 of the present invention. It is an input signal of the accumulation synchronous addition process which concerns on Example 2 of this invention. FIG. 8 is an output signal of cumulative synchronization addition processing approximating the synchronization period for the input signal of FIG. 7 according to Embodiment 2 of the present invention. It is an output signal of the cumulative synchronous addition process in consideration of the decimal part of the synchronous period with respect to the input signal of FIG. 7 according to Embodiment 2 of the present invention. It is an input signal of the synchronous subtraction process with respect to the one tone signal which concerns on Example 3 of this invention. FIG. 10 is an output signal of a synchronous subtraction process approximating a synchronous period for the input signal of FIG. 10 according to Embodiment 3 of the present invention. FIG. 10 is an output signal of a synchronous subtraction process in consideration of the decimal part of the synchronous period for the input signal of FIG. 10 according to Embodiment 3 of the present invention. It is the power of the output signal with respect to two synchronous periods of the synchronous subtraction process with respect to the one tone signal which concerns on Example 3 of this invention. It is an input signal of the accumulation synchronous addition process with respect to the one musical tone signal which concerns on Example 4 of this invention. FIG. 15 is an output signal of cumulative synchronization addition processing approximating the synchronization period for the input signal of FIG. 14 according to Embodiment 4 of the present invention. FIG. FIG. 15 is an output signal of cumulative synchronous addition processing in consideration of the fractional part of the synchronous period with respect to the input signal of FIG. 14 according to Embodiment 4 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input part 2 Sampling process part 3 Synchronization process part 4 Output part 5 Computer system bus 6 Interface 7 Memory 8 External storage device 9 Arithmetic apparatus 10 Notch type comb filter 11 Cascade type filter system 12 Resonance type comb filter 13 Parallel Comb filter system

Claims (4)

Synchronous calculation processing of a digital signal, and when the ratio between the target analog signal frequency and the sampling frequency is not an integer, the value of the ratio between the analog signal frequency and the sampling frequency is changed to an integer part without changing the sampling frequency. A digital signal synchronization calculation processing method, wherein the digital signal synchronization calculation processing is performed immediately on sample values separated by a sampling period by directly using the numerical values of the integer part and the decimal part as weights. 2. The digital signal synchronous calculation processing method according to claim 1, wherein synchronous addition or synchronous subtraction processing is performed on two digital signals sampled at an arbitrary time. 2. The digital signal synchronization calculation processing method according to claim 1, wherein cumulative synchronization addition or accumulation synchronization subtraction is performed on a digital signal sampled at an arbitrary time. 4. The digital signal synchronization calculation processing method according to claim 1, wherein the digital signal synchronization calculation processing is performed continuously for each sampling period.

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