JP2010056246A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves both a high breakdown voltage and a quick operation. <P>SOLUTION: The semiconductor device has a pn junction type diode including an N-type semiconductor layer 2 formed on an N-type semiconductor 1, a P-type first diffusion layer 4 formed on a surface of the semiconductor layer 2, a P-type second diffusion layer 4 formed on the surface of the semiconductor layer 2 apart from the first diffusion layer 4 and enclosing the first diffusion layer 4, a P-type third diffusion layer 5 formed on a surface of the first diffusion layer 4, a P-type fourth diffusion layer 7 formed on a surface of the second diffusion layer 4, an N-type fifth diffusion layer 6 formed on the surface of the first diffusion layer 4 and electrically connected to the third diffusion layer 5, and an N-type sixth diffusion layer 8 formed straddling the surface of the second diffusion layer 4 and the surface of the semiconductor layer 2 and electrically connected to the fourth diffusion layer 7. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a diode or a transistor that requires a high breakdown voltage.

Vertical PN diodes and vertical DMOSFETs (double diffused field effect transistors) are generally known as high voltage power devices for high voltage power electronics applications.
The vertical DMOSFET ensures a high breakdown voltage by the thickness (depth) of the drift region in the vertical direction and the impurity concentration.

Further, in the vertical PN diode and the vertical DMOSFET, there is a so-called super junction structure as a device structure that achieves both high breakdown voltage and low on-resistance of the element.
In this super junction structure, usually, drift regions and pillar regions are alternately and repeatedly formed (see, for example, Patent Document 1).

A sectional view of an example of a vertical PN diode having a super junction structure is shown in FIG.
As shown in FIG. 8, an N ⁻ epitaxial layer 52 is formed on an N ⁺ substrate 51, and a columnar P ⁻ pillar region 53 is formed in the epitaxial layer 52. The remaining N ⁻ epitaxial layer 52 other than the portion where the P ⁻ pillar region 53 is formed is called a drift region.
On the pillar region 53, a P-type body region 54 is formed up to the surface of the epitaxial layer 52, and the P-type body region 54 is formed with a width wider than the pillar region 53.
A P-type potential extraction region (PSD) 55 is formed on the central surface of the body region 54. A P-type potential extraction region (PSD) 55 of each body region 54 is connected by wiring to form an anode 62. On the other hand, the substrate 51 side is a cathode 61.

FIG. 9 shows a cross-sectional view of an example of a vertical DMOSFET having a super junction structure.
As shown in FIG. 9, the N ⁺ substrate 51 to the body region 54 have the same configuration as the vertical PN diode of FIG.
In this vertical DMOSFET, a central P-type potential extraction region (PSD) 55 and a right or left N-type potential extraction region (NSD) 56 are further formed on the surface of the body region 54. Yes.
A gate electrode 57 is formed on the NSD 56 between the two body regions 54 via a gate insulating film (not shown).
The gate electrode 57, the gate insulating film, the body region 54, the PSD 55, the NSD 56, and the drift region 52 constitute a MOS transistor. The surface of the body region 54 under the gate electrode 57 becomes a channel of the MOS transistor.

In the vertical PN diode of FIG. 8 and the vertical DMOSFET of FIG. 9, the P ⁻ pillar region 53 and the N ⁻ drift region 52 are designed to have the same impurity amount.
Therefore, when a reverse bias is applied to the vertical PN diode of FIG. 8 or when the vertical DMOSFET of FIG. 9 is in an OFF state and a reverse bias is applied between the drain and the source, the pillar region 53 and the drift are drifted. The region 52 is completely depleted and the electric field distribution becomes uniform.
Thereby, as compared with the case where the super junction structure is not used, a high breakdown voltage can be ensured even if the impurity concentration in the drift region is increased.
In addition, since the impurity concentration in the drift region can be increased, the on-resistance when the transistor is on can be reduced.
That is, it is possible to realize both high breakdown voltage and low on-resistance of the element.

  In the output stage circuit or the like of the boost converter, since the vertical PN diode is used as a pair with the vertical DMOSFET, a vertical PN diode having a structure having an NSD and a gate electrode is configured like the vertical DMOSFET. There is a case.

JP 2006-351985 A

  By the way, if the bias direction changes instantaneously from the state in which the diode is energized with a forward bias, the reverse is performed transiently until the depletion layer at the anode-cathode junction expands to a stable state. Directional current flows. The time until this stable state is reached is called reverse recovery time (reverse recovery time).

  If the reverse recovery time of the diode is long, the circuit operation becomes slow and the current consumption due to the reverse current increases.

  Also in the vertical PN junction diode and the vertical DMOSFET as shown in FIGS. 8 and 9, if the reverse recovery time is long, the circuit operation is slowed down, and the consumption current due to the reverse current is increased and the efficiency is lowered. There was a problem such as.

  In order to solve the above-described problem, the present invention provides a semiconductor device capable of realizing both a high breakdown voltage and a fast operation.

The first semiconductor device of the present invention is a semiconductor device having a PN junction type diode, and the PN junction type diode includes the following layers.
(A) A semiconductor layer containing a first conductivity type impurity formed on a semiconductor substrate of a first conductivity type (B) A first diffusion layer containing a second conductivity type impurity (B) formed on the surface of the semiconductor layer C) Second diffusion layer (D) first diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer so as to be separated from the first diffusion layer and to surround the first diffusion layer The third diffusion layer (E) containing the second conductivity type impurity formed on the surface of the second diffusion layer (F) containing the second conductivity type impurity formed on the surface of the second diffusion layer (E) A fifth diffusion layer (G) formed on the surface of the diffusion layer and electrically connected to the third diffusion layer and containing the first conductivity type impurity (G) straddles the surface of the second diffusion layer and the surface of the semiconductor layer. And a sixth diffusion layer containing a first conductivity type impurity, electrically connected to the fourth diffusion layer

A second semiconductor device of the present invention is a semiconductor device having a double diffusion field effect transistor, and the double diffusion field effect transistor includes the following layers.
(A) A semiconductor layer containing a first conductivity type impurity formed on a semiconductor substrate of a first conductivity type (B) A first diffusion layer containing a second conductivity type impurity (B) formed on the surface of the semiconductor layer C) Second diffusion layer (D) first diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer so as to be separated from the first diffusion layer and to surround the first diffusion layer The third diffusion layer (E) containing the second conductivity type impurity formed on the surface of the second diffusion layer (F) containing the second conductivity type impurity formed on the surface of the second diffusion layer (E) A fifth diffusion layer (G) formed on the surface of the diffusion layer and electrically connected to the third diffusion layer and containing the first conductivity type impurity (G) straddles the surface of the second diffusion layer and the surface of the semiconductor layer. A sixth diffusion layer (H), which is formed on the first diffusion layer and is electrically connected to the fourth diffusion layer and containing a first conductivity type impurity; To span a portion of the surface and the gate insulating film formed on the surface of the semiconductor layer (I) surface and a portion of the semiconductor layer on the surface of the first diffusion layer, which is formed on the gate insulating film, a gate electrode

According to the above-described configuration of the semiconductor device of the present invention, the sixth diffusion layer (first conductivity type) includes the surface of the second diffusion layer (second conductivity type) and the surface of the semiconductor layer (first conductivity type). Therefore, the second diffusion layer and the semiconductor layer are equipotential.
Further, the transistor constituted by the semiconductor layer, the first diffusion layer, and the second diffusion layer is different from the transistor constituted by the semiconductor layer, the first diffusion layer, and the fifth diffusion layer. Thus, a thyristor structure is constituted by these two transistors.
Thereby, the operation of the two transistors constituting the thyristor makes it possible to quickly extract minority carriers (electrons and holes) in the anode and the cathode, and the reverse recovery time can be shortened.

According to the above-described present invention, the reverse recovery time can be shortened, so that the circuit operation can be speeded up. Further, it is possible to reduce the current consumption due to the reverse current and to operate efficiently.
In addition, a high breakdown voltage is obtained at the junction between the first conductivity type and the second conductivity type.
Therefore, according to the present invention, a semiconductor device capable of realizing both a high breakdown voltage and a fast operation can be configured.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. 1. First embodiment of the present invention 2. Second embodiment of the present invention Modified example

<1. First embodiment of the present invention>
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of the semiconductor device according to the first embodiment of the present invention.
In the present embodiment, the present invention is applied to a semiconductor device having a vertical PN junction diode (hereinafter referred to as a vertical PN diode).

As shown in FIG. 1, a drift region composed of an N ⁻ epitaxial layer 2 and a P ⁻ pillar region 3 are alternately and repeatedly formed on an N ⁺ substrate 1 to form a super junction structure. .

A P-type body region 4 is formed up to the surface of the epitaxial layer 2 on the P ⁻ pillar region 3. The P-type body region 4 is formed with a width wider than that of the pillar region 3.
A P-type potential extraction region (PSD) 5 and an N-type potential extraction region (NSD) 6 that are potential extraction regions of the body region 4 are formed on the surface of the body region 4, respectively. N-type potential extraction region (NSD) 6 is formed on the central surface of the body region. The P-type potential extraction region (PSD) 5 is formed on the left and right sides, that is, outside the N-type potential extraction region (NSD) 6.
In each body region 4, a P-type potential extraction region (PSD) 5 and an N-type potential extraction region (NSD) 6 are connected by wiring to form an anode 12. In contrast, the substrate 1 side is a cathode 11.

  With this configuration, in the vertical PN diode, the N-type potential extraction region (NSD) 6 is the emitter, the P-type body region 4 and the pillar region 3 are the base, and the N-type substrate 1 and the epitaxial layer 2 are the collectors. Thus, an NPN transistor is formed.

Further, in the semiconductor device shown in FIG. 1, a super junction structure vertical type in which the structure of the surface of the body region is different from the central three vertical PN diodes on the outer side of the central three vertical PN diodes. A PN diode is arranged.
In this outer vertical PN diode, a P-type potential extraction region (PSD) 7 is formed on the surface of the central portion of the body region 4, and on the left and right sides of the P-type potential extraction region (PSD) 7, that is, outside. An N-type potential extraction region (NSD) 8 is formed. The N-type potential extraction region (NSD) 8 is formed so as to straddle the surface of the body region 4 and the surface of the drift region 2. The P-type potential extraction region (PSD) 7 and the N-type potential extraction region (NSD) 8 are electrically connected by wiring.

In the outer vertical PN diode, since the P-type potential extraction region (PSD) 7 and the N-type potential extraction region (NSD) 8 are configured as described above, the P-type body region 4 and the pillar region 3 are formed. And the N-type drift region 2 are equipotential.
A PNP transistor is formed by using the body region 4 and pillar region 3 of the outer vertical PN diode as an emitter, the semiconductor substrate 1 and the drift region 2 as a base, and the body region 4 and pillar region 3 constituting the NPN transistor described above as a collector. Is done. The PNP transistor is formed so as to surround the NPN transistor described above.
A thyristor structure is formed by these NPN transistor and PNP transistor.

  Here, in the semiconductor device of the present embodiment, it is assumed that the vertical PN diode shown in FIG. 1 is used and the output stage circuit of the boost converter as shown in the circuit configuration diagram of FIG. 2A is configured. The operation of the vertical PN diode shown in FIG. 1 will be described.

As shown in FIG. 2A, the drain terminal of the transistor Tr and the inductor (coil) L are connected to the anode side of the diode D. The source terminal side of the transistor Tr is grounded. The cathode side of the diode D is connected to the ground potential via the capacitor C.
The vertical PN diode shown in FIG. 1 is used as the diode D shown in FIG. 2A.

In FIG. 2A, the transistor Tr is on, and a current flows from the input terminal to the transistor Tr through the inductor L.
Here, as shown in FIG. 2B, when the transistor Tr is turned off, the input terminal and the ground are disconnected, so that the potential of the drain terminal of the transistor Tr is increased by the back electromotive force of the inductor L.
At this time, since the drain terminal of the transistor Tr and the anode of the diode D are connected, a forward voltage is applied between the anode and the cathode of the diode D. Therefore, a current flows through the diode D and charges the capacitor C.

When the forward bias voltage is applied to the vertical PN diode of FIG. 1, the above-described NPN transistor formed in the central three vertical PN diodes is as shown in FIG. , Operates as a diode 32.
Further, the above-described PNP transistor formed by the outer vertical PN diode operates as the PNP transistor 31 as it is, as shown in FIG.
Since the cathode of the diode 32 is connected to the base of the PNP transistor 31, the operation of the PNP transistor 31 can increase the current drive capability during forward bias.

On the other hand, as shown in FIG. 2C, when the transistor Tr is turned on and current flows from the input terminal through the inductor L to the ground through the transistor Tr, the drain terminal of the transistor Tr suddenly drops to the ground potential.
At this time, since the anode potential of the diode D is also lowered to the ground potential, a reverse bias voltage is suddenly applied between the anode and cathode of the diode D.

When the reverse bias voltage is applied to the vertical PN diode of FIG. 1, the NPN transistor formed in the three vertical PN diodes at the center is as shown in FIG. The NPN transistor 34 operates as it is.
Further, the above-described PNP transistor formed by the outer vertical PN junction diode operates as the PNP transistor 33 as it is, as shown in FIG. However, the relationship between the emitter and collector of the PNP transistor is opposite to that in FIG.

At this time, by the operation of the NPN transistor 34, the holes 21 which are minority carriers in the cathode 11 are extracted from the collector through the base to the emitter.
That is, the hole 21 passes from the drift region 2 that is the collector of the NPN transistor 34 to the N-type potential extraction region (NSD) 6 that is the emitter of the NPN transistor 34 through the pillar region 3 and the body region 4 that are the bases. Pulled out.
Further, by the operation of the PNP transistor 33, the electrons 22 which are minority carriers in the anode 12 are extracted from the collector through the base to the emitter.
That is, the electrons 22 pass from the pillar region 3 and the body region 4 which are the collectors of the PNP transistor 33 through the drift region 2 which is the base, and the pillar region 3 and the body region 4 of the outer vertical PN junction diode which is the emitter. Pulled out. The body region 4 of the outer vertical PN junction diode is equipotential with the drift region 2 by the N-type potential extraction region (NSD) 8 on the surface, so that the electrons 22 are further extracted to the drift region 2. .
In this way, the minority carriers of the cathode 11 and the anode 12 are quickly extracted, so that the reverse recovery time _trr can be shortened.

The semiconductor layer containing the first conductivity type impurity of the present invention is an N ⁻ epitaxial layer 2 in the present embodiment.
In the present embodiment, the first diffusion layer of the present invention is the body region 4 of the central vertical PN diode.
In the present embodiment, the second diffusion layer of the present invention is the body region 4 of the outer vertical PN diode.
In the present embodiment, the third diffusion layer of the present invention is a P-type potential extraction region (PSD) 5 of the central vertical PN diode.
In the present embodiment, the fourth diffusion layer of the present invention is a P-type potential extraction region (PSD) 7 of the outer vertical PN diode.
In the present embodiment, the fifth diffusion layer of the present invention is an N-type potential extraction region (NSD) 6 of the central vertical PN diode.
In the present embodiment, the sixth diffusion layer of the present invention is a P-type potential extraction region (PSD) 8 of the outer vertical PN diode.
In the present embodiment, the first pillar layer of the present invention is the N-type drift region 2 between the vertical PN diodes. In the present embodiment, the second pillar layer of the present invention is the pillar region 3 of the central vertical PN diode. In the present embodiment, the third pillar layer of the present invention is the pillar region 3 of the outer vertical PN diode.

According to the configuration of the semiconductor device of the present embodiment described above, the N-type potential extraction region (NSD) 8 on the surface of the body region 4 extends from the surface of the body region 4 to the drift region outside the central vertical PN diode. A vertical PN diode formed so as to straddle the surface of 2 is disposed.
A PNP transistor 33 is formed by the outer vertical PN diode. The PNP transistor 33 and the NPN transistor 34 formed by the central vertical PN diode constitute a thyristor. Thereby, when a reverse bias is applied to the vertical PN diode, the holes 21 and the electrons 22 can be quickly extracted, and the reverse recovery time _trr can be shortened.

Since the reverse recovery time _trr can be shortened in this way, the circuit operation can be speeded up. Further, it is possible to reduce the current consumption due to the reverse current and to operate efficiently.
A high breakdown voltage is obtained by the vertical PN diode having a super junction structure.

Further, according to the configuration of the semiconductor device of the present embodiment, when a forward bias voltage is applied, the NPN transistor operates as the diode 32, and the cathode of the diode 32 is connected to the base of the PNP transistor 31. Yes.
For this reason, the operation of the PNP transistor 31 can increase the current drive capability during forward bias.

  Therefore, according to this embodiment, a semiconductor device capable of realizing both a high breakdown voltage and a fast operation can be configured.

In the above-described embodiment, the case where the present invention is applied to a vertical PN diode having a super junction structure has been described.
The present invention is similarly applied to a vertical PN diode not using a super junction structure, a vertical DMOSFET (double diffusion field effect transistor) having a super junction structure, and a vertical DMOSFET not using a super junction structure. It is possible.
In addition, the present invention can be applied to a configuration including these configurations in which a high breakdown voltage is obtained by a PN junction.

In the output stage circuit of the step-up converter shown in FIGS. 2A to 2C, a transistor may be used instead of the diode D to obtain a circuit configuration as shown in FIG. In FIG. 5, a second transistor Tr2 made of a MOSFET is connected between the drain terminal of the first transistor Tr1 for switching and the capacitor C.
The present invention can also be applied to the second transistor Tr2 having the circuit configuration shown in FIG.

<2. Second embodiment of the present invention>
FIG. 6 shows a schematic configuration diagram (cross-sectional view) of the semiconductor device according to the second embodiment of the present invention.
In this embodiment, the present invention is applied to a semiconductor device having a vertical DMOSFET (hereinafter referred to as a vertical DMOSFET).
The schematic configuration of the semiconductor device of the present embodiment is the same as that of the previous embodiment shown in FIG. 1 (in the case of a vertical PN diode), and therefore, different parts from the semiconductor device of FIG. To do.
As shown in FIG. 6, in the three body regions 4 in the central portion, the arrangement of the P-type potential extraction region 5 and the N-type potential extraction region (NSD) 6 is opposite to that in the first embodiment. A P-type potential extraction region (PSD) 5 is formed on the center surface of the body region 4. Further, a gate electrode 9 is formed across the N-type potential extraction region (NSD) 6 of the two body regions 4 via a gate insulating film (not shown) thereon. Another wiring that is electrically independent from the wiring connected to the anode 12 is connected to the gate electrode 9. As a result, a vertical DMOSFET having the surface of the body region 4 under the gate electrode 9 as a channel is formed.
Also in this vertical DMOSFET, since the pillar region 3, the body region 4, and the drift region 2 are formed in a super junction structure, the breakdown voltage can be increased.

Also in this embodiment, as in the previous embodiment shown in FIG. 1, an N-type potential extraction region (stretched across the body region 4 and the drift region 2) outside the central vertical DMOSFET ( A vertical PN diode with NSD) 8 is arranged.
For this reason, when a reverse bias is applied to the vertical DMOSFET, minority carriers can be quickly extracted, and the circuit operation can be accelerated.
Therefore, according to this embodiment, a semiconductor device capable of realizing both a high breakdown voltage and a fast operation can be configured.

<3. Modification>
As modifications of the present invention, for example, the following configurations can be considered.
(1) Structure that realizes high breakdown voltage by the structure of the joint part other than the super junction structure (2) No pillar region, only the body region (3) The body region and the pillar region are integrated with the same width Configuration (4) Configuration in which the gate electrode of the vertical DMOSFET is a trench structure embedded in the substrate (5) Configuration having a non-vertical (for example, horizontal) junction portion In addition to these, various modifications Is possible.

In the semiconductor device of the present invention, germanium or a compound semiconductor can be used as the semiconductor in addition to silicon.
In the semiconductor device of the present invention, a semiconductor substrate, a semiconductor substrate, a semiconductor substrate, and a semiconductor epitaxial layer thereon can be used.

In each of the above-described embodiments, the substrate 1 and the drift region 2 are N-type, and the pillar region 3 and the body region 4 are P-type.
In the present invention, it is also possible to constitute a semiconductor device in which each of these regions has the opposite conductivity type.

Further, in a semiconductor device having both a vertical DMOSFET and a vertical PN diode, it is conceivable to make the configurations of the vertical DMOSFET and the vertical PN diode as common as possible.
As one modification of the present invention, FIG. 7 shows a schematic configuration diagram (cross-sectional view) of a vertical PN diode portion in the case of common use as described above. In FIG. 7, the reference numerals and component configurations are the same as those in the embodiments shown in FIGS. 1 and 6.
As shown in FIG. 7, the gate electrode 9 is formed on the two body regions 4 as in the vertical DMOSFET shown in FIG.
However, in the case of FIG. 7, the gate electrode 9 is connected to the wiring connected to the P-type potential extraction region (PSD) 6 and the N-type potential extraction region (NSD) 5. As a result, the DMOSFET operates as a diode.
In this manner, by forming the vertical PN diode with the same configuration as the vertical DMOSFET, in the semiconductor device having both the vertical DMOSFET and the vertical PN diode, the number of masks and the number of processes can be reduced when manufacturing the semiconductor device. It becomes possible. In addition, since the DMOSFET and the PN diode can be separately formed by simply changing the wiring connection, the manufacturing process is simplified.

In the present invention, the planar shape and the planar arrangement of the first diffusion layer and the second diffusion layer formed so as to surround the first diffusion layer can be variously configured and are particularly limited. is not.
Examples of the planar shape include island shapes, stripe shapes, and ring shapes that are individually independent.
Examples of the planar arrangement include an arrangement in which the second diffusion layer is provided around the entire first diffusion layer, and an arrangement in which the second diffusion layer is provided on both outer sides (front and rear or left and right) in the one-dimensional direction of the first diffusion layer. Can be mentioned.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to a first embodiment of the present invention. FIGS. 2A to 2C are diagrams illustrating the configuration and operation of a boost converter to which the diode of FIG. 1 is applied. It is a figure which shows a state when a forward bias is applied to the diode of FIG. It is a figure which shows a state when a reverse bias is applied to the diode of FIG. FIG. 3 is a diagram illustrating a configuration of an output stage circuit of a boost converter using a transistor instead of the diode of FIG. 2. It is a schematic block diagram (sectional drawing) of the semiconductor device of the 2nd Embodiment of this invention. It is a schematic block diagram (sectional drawing) of the part of the vertical PN diode when the configurations of the vertical DMOSFET and the vertical PN diode are shared. It is sectional drawing of an example of the conventional vertical PN diode. It is sectional drawing of an example of the conventional vertical DMOSFET. A, B It is a figure which shows a state when the bias of a forward direction and a reverse direction is applied to the diode of FIG. It is a figure explaining the change of the electric current of a diode, and reverse recovery time.

Explanation of symbols

  1 substrate, 2 epitaxial layer (drift region), 3 pillar region, 4 body region, 5, 7 P-type potential extraction region (PSD), 6,8 N-type potential extraction region (NSD), 9 gate electrode, 11 Cathode, 12 Anode, 21 Hole, 22 Electron, 31 PNP transistor, 32 Diode, 33 PNP transistor, 34 NPN transistor, C capacitor, D diode, L Inductor (coil), Tr transistor, Tr1 First transistor, Tr2 Second Transistor

Claims (5)

A semiconductor device having a PN junction diode,
A semiconductor layer containing a first conductivity type impurity formed on a first conductivity type semiconductor substrate;
A first diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer;
A second diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer so as to be spaced apart from the first diffusion layer and surrounding the first diffusion layer;
A third diffusion layer containing a second conductivity type impurity formed on the surface of the first diffusion layer;
A fourth diffusion layer containing a second conductivity type impurity formed on the surface of the second diffusion layer;
A fifth diffusion layer containing a first conductivity type impurity formed on a surface of the first diffusion layer and electrically connected to the third diffusion layer;
A sixth diffusion layer containing a first conductivity type impurity, formed to straddle the surface of the second diffusion layer and the surface of the semiconductor layer, and electrically connected to the fourth diffusion layer; A semiconductor device comprising the PN junction diode. A first pillar layer including a first conductivity type impurity formed on the first conductivity type semiconductor substrate;
A second pillar layer including a second conductivity type impurity, which is alternately disposed with the first pillar layer and is formed to extend below the first diffusion layer;
The semiconductor device according to claim 1, further comprising a third pillar layer formed so as to extend below the second diffusion layer, to form the PN junction diode. A semiconductor device having a double diffusion field effect transistor,
A semiconductor layer containing a first conductivity type impurity formed on a first conductivity type semiconductor substrate;
A first diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer;
A second diffusion layer containing a second conductivity type impurity formed on the surface of the semiconductor layer so as to be spaced apart from the first diffusion layer and surrounding the first diffusion layer;
A third diffusion layer containing a second conductivity type impurity formed on the surface of the first diffusion layer;
A fourth diffusion layer containing a second conductivity type impurity formed on the surface of the second diffusion layer;
A fifth diffusion layer containing a first conductivity type impurity formed on a surface of the first diffusion layer and electrically connected to the third diffusion layer;
A sixth diffusion layer containing a first conductivity type impurity, formed so as to straddle the surface of the second diffusion layer and the surface of the semiconductor layer, and electrically connected to the fourth diffusion layer;
A gate insulating film formed on the surface of the first diffusion layer and the surface of the semiconductor layer;
The double diffusion field effect transistor includes a gate electrode formed on the gate insulating film so as to straddle part of the surface of the first diffusion layer and part of the surface of the semiconductor layer. Configured semiconductor device. A first pillar layer including a first conductivity type impurity formed on the first conductivity type semiconductor substrate;
A second pillar layer including a second conductivity type impurity, which is alternately disposed with the first pillar layer and is formed to extend below the first diffusion layer;
The semiconductor device according to claim 3, further comprising a third pillar layer formed so as to extend below the second diffusion layer, to form the double diffusion field effect transistor.   The semiconductor layer, the first diffusion layer, the second diffusion layer, the third diffusion layer, the fourth diffusion layer, and the fifth diffusion layer of the double diffusion field effect transistor; The semiconductor device further includes a PN junction diode having the same configuration as the gate insulating film and the gate electrode, wherein the gate electrode is electrically connected to the third diffusion layer and the fifth diffusion layer. Item 4. The semiconductor device according to Item 3.

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