JP2010056234A - Method of manufacturing nitride semiconductor light-emitting element and method of manufacturing epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nitride based semiconductor light emitting element which can grow an InGaN well layer of sufficient crystal quality on a gallium nitride based semiconductor face with a comparatively small-off angle. <P>SOLUTION: A condition in a following range is used in the growth of the well layer 25a. When a growth temperature T<SB>W</SB>is not lower than 640°C and lower than 710°C, an upper limit of growth speed V<SB>G</SB>is given by a following formula V<SB>G</SB>=α1×T<SB>W</SB>+β1. Regarding α1, β1 in the formula, α1=0.12 and β1=-71.3 are satisfied. When the growth temperature T<SB>W</SB>is 710°C to 750°C, the upper limit of growth speed V<SB>G</SB>is not larger than 13.9 nm/min. When the growth temperature T<SB>W</SB>is not lower than 640°C and lower than 690°C, a lower limit of growth speed V<SB>G</SB>is not smaller than 5.5 nm/min. When the growth temperature T<SB>W</SB>is not lower than 690°C and lower than 750°C, the lower limit of growth speed V<SB>G</SB>is given by the following formula V<SB>G</SB>=α2×T<SB>W</SB>+β2. Herein, α2=0.14 and β2=-91.1 are satisfied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for producing a nitride-based semiconductor light-emitting device and a method for producing an epitaxial wafer.

  Patent Document 1 describes the growth of InGaN. After growing the buffer layer on the sapphire substrate, a semiconductor layer made of GaN or AlGaN is grown on the buffer layer at a temperature higher than the growth temperature of the buffer layer. On this semiconductor, an InGaN layer is grown under specific conditions described in Patent Document 1. The maximum growth rate is 6 nm / min at a temperature of 900 degrees Celsius. The peak wavelength in the photoluminescence spectrum is 406 nm.

Patent Document 2 describes a method for manufacturing an element having an active layer made of InGaN. In this method, the growth conditions are determined based on a characteristic diagram relating to the molar ratio TMI / (TMG + TMI) of the source gas in the growth of InGaN, the crystal growth temperature, and the wavelength. After growing a buffer layer on the a-plane of the sapphire substrate, an n-type GaN layer is grown on the buffer layer at a growth temperature of 1150 degrees Celsius. After the barrier layer is grown on the GaN layer, an InGaN well layer is grown at a growth temperature of 700 degrees Celsius at a predetermined raw material molar ratio described in Patent Document 2. Using a molar ratio of source gas of 0.79, the peak wavelength is 470 nm.
Japanese Patent Laid-Open No. 06-209122 Japanese Patent Laid-Open No. 11-8407

  When a quantum well structure is manufactured using a substrate having a c-plane principal surface, electrons and holes are spatially separated in the well layer by a piezo electric field caused by the polarity of the c-plane. For this reason, the overlap between the electron wave function and the hole wave function does not increase, and the internal quantum efficiency of the light-emitting element decreases. Therefore, when a light emitting device is manufactured using the InGaN layer in Patent Documents 1 and 2, a decrease in internal quantum efficiency is inevitable.

  According to the knowledge of the inventors, in a light-emitting device manufactured on a GaN substrate having a main surface inclined from the c-plane, the influence of the piezoelectric field is weakened. When the wafer main surface is inclined with a small off angle from the c-plane, it is considered easy to manufacture a wafer having a relatively large diameter.

  However, according to experiments by the inventors, crystal growth on a GaN wafer with an off-angle was different from crystal growth on a c-plane GaN wafer. Under the film formation conditions of the active layer that generates light having a wavelength of 480 nm on the c-plane GaN wafer, the active layer formed on the off-angle GaN wafer generated light having a wavelength shorter than the wavelength of 480 nm. Therefore, it is necessary to examine the film forming conditions to compensate for this wavelength shift. However, as understood from the above experiment, the relationship between the emission wavelength of the active layer formed on the off-angled GaN wafer and the film formation conditions is unknown.

  An object of the present invention is to provide a method for manufacturing a nitride-based semiconductor light-emitting device. According to this method, an InGaN well layer having a good crystal quality is formed on a gallium nitride-based semiconductor main surface having a relatively small off angle. Can grow. Another object of the present invention is to provide a method for producing an epitaxial wafer for a nitride semiconductor light emitting device.

The invention according to one aspect of the present invention is a method of manufacturing a nitride-based semiconductor light-emitting device having an active layer having a quantum well structure. This method includes (a) a step of forming an epitaxial semiconductor region made of a gallium nitride-based semiconductor, and (b) a growth temperature T _W within a temperature range of 640 degrees Celsius or more and 750 degrees Celsius or less on the epitaxial semiconductor region, and And a step of growing the well layer having the quantum well structure at a growth rate V _G (nm / min). The epitaxial semiconductor region has a main surface inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. The active layer is provided so as to generate an emission spectrum having a peak wavelength in a wavelength region of 480 nm or more and 550 nm or less, and the well layer includes In _X Ga _1-X N (indium composition X: 0 <X <1 , X is a strain composition).
When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 710 degrees Celsius, the upper limit of the growth rate V _G is the following formula (1)
V _G = α1 × T _W + β1 (1)
Equation (1) satisfies (growth temperature T _W , growth rate V _G ) = (710 degrees Celsius, 13.9 nm / min), (640 degrees Celsius, 5.5 nm / min).
When the growth temperature _{T W} is the temperature below 710 degrees 750 degrees centigrade, the upper limit of the growth rate _{V G} is less 13.9 nm / min.
When the growth temperature _{T W} is the temperature of less than 690 degrees 640 degrees centigrade, the lower limit of the growth rate _{V G} is 5.5 nm / min or more.
Wherein when the growth temperature _{T W} is the temperature below 750 degrees 690 degrees centigrade, the lower limit of the growth rate _{V G,} the following equation (2)
V _G = α2 × T _W + β2 (2)
Equation (2) satisfies (growth temperature T _W , growth rate V _G ) = (640 degrees Celsius, 13.9 nm / min), (690 degrees Celsius, 5.5 nm / min).

According to this method, on the epitaxial semiconductor main surface inclined at an angle in the range from c-plane of the gallium nitride-based semiconductor of 10 to 45 degrees, with a growth rate V _G and the growth temperature T _W in terms of the range of the Thus, when an InGaN well layer is grown, an InGaN well layer having a good crystal quality can be grown on a gallium nitride semiconductor main surface having a relatively small off angle.

When the region has a relatively high growth temperature, that is, when the growth temperature _TW is not less than 690 degrees Celsius and not more than 750 degrees Celsius, the growth of the well layer has a lower limit of the growth rate defined by the equation (2). As the growth temperature increases, the lower limit of the growth rate increases. This is because, in a relatively high growth temperature region, the In incorporation efficiency is low, so that a desired wavelength cannot be obtained if the growth rate is low. Even when the growth temperature _TW is a temperature of 640 ° C. or more and 690 ° C. or less, the growth rate has a lower limit of 5.5 nm / min. This is because, even in a relatively low growth temperature region, if the growth rate is too low, the In incorporation efficiency becomes low, and a desired wavelength cannot be obtained.

When the growth temperature _{T W} is the temperature below 750 degrees 700 degrees Celsius, the growth rate _{V G} has an upper limit of 13.9 nm / min. This is because if the growth rate is too fast, the crystal quality of InGaN deteriorates and the light emission characteristics deteriorate. Moreover, the relatively low growth temperature range, that is, when the growth temperature T _W is the temperature of less than 640 degrees 710 degrees Celsius, the growth of the well layer, an upper limit of the growth rate defined by Equation (1) . As the growth temperature decreases, the upper limit of the growth rate decreases. This is because unless the growth rate is lowered as the growth temperature is lowered, the crystal quality of InGaN deteriorates and the light emission characteristics deteriorate.

The method according to the present invention, the epitaxial semiconductor region, in the above growth temperature T _W growth temperature T _B of the well layer, can further comprise the step of growing the barrier layer of the quantum well structure. The barrier layer is made of In _Y Ga _1-Y N (indium composition Y: 0 ≦ Y ≦ 0.05, Y is a strained composition), and the growth temperature T _{W of the} well layer and the growth temperature T of the barrier layer The difference from _B is not less than 60 degrees and not more than 230 degrees.

According to this method, since the indium composition X of the well layer is larger than the indium composition Y (0 ≦ Y ≦ 0.05) of the barrier layer, the well layer can be grown with InGaN having a desired indium composition. while the temperature is necessary, in order to form the barrier layer of good crystal quality, growth temperature T _B is required to be higher than the growth temperature T _W of the well layer. When the difference between the growth temperature T _W and a growth temperature T _B is less than 60 degrees, the barrier layer of the desired quality can not be obtained. Further, in the growth subsequent to the growth of the active layer, the crystal quality of the well layer is degraded. When exceeding difference 230 degrees between the growth temperature T _W and the growth temperature T _B, the crystal quality of the well layer is lowered during the growth of the barrier layer.

The method according to the present invention may further include a step of growing a second conductivity type gallium nitride based semiconductor layer on the active layer. The growth temperature T _W of the well layer, the second conductive type lower than the growth temperature T2 of the gallium nitride-based semiconductor layer, the growth temperature T _W and the second conductive type gallium nitride based semiconductor layer of the well layer The difference from the growth temperature T2 is 140 degrees or more and 510 degrees or less.

According to this method, when the growth temperature T _W and the growth temperature T2 of the growth temperature T2 so that the difference is less than 140 degrees and is set, the second conductive type gallium nitride based semiconductor layer having good conductivity I can't get it. When the growth temperature T _W and a growth temperature T _B and difference of 510 degrees growth temperature T2 to exceed a is set, the crystal quality of the well layer is lowered during the growth of the second conductive type gallium nitride-based semiconductor layer.

  The method according to the present invention may further include a step of growing another second conductivity type gallium nitride based semiconductor layer on the second conductivity type gallium nitride based semiconductor layer. The second conductivity type gallium nitride based semiconductor layer includes an electron block layer, and the growth rate of the other second conductivity type gallium nitride based semiconductor layer is higher than the growth rates of the well layer and the barrier layer.

  According to this method, the growth time of another second-conductivity-type gallium nitride semiconductor layer that is performed at a temperature higher than the growth temperature of the well layer after forming the active layer can be shortened.

In the method according to the present invention, the indium composition X of the In _X Ga _1-X N of the well layer may be greater than 0.15. The In _X Ga _1-X N of the well layer may be less than 0.4. InGaN having an indium composition in this range can be grown, and a light-emitting element with a wavelength of 480 nm to 550 nm can be obtained.

  In the method according to the present invention, the direction of inclination of the main surface of the semiconductor region may be the a-axis direction of the gallium nitride semiconductor. According to this method, the m-plane can be used as a cleavage plane.

The method according to the present invention, further a step of preparing a substrate composed of hexagonal semiconductor _{In S Al T Ga 1-S} -T N (0 ≦ S ≦ 1,0 ≦ T ≦ 1,0 ≦ S + T ≦ 1) Can be provided. The main surface of the substrate is inclined at an angle in a range of 10 degrees to 45 degrees from a plane orthogonal to the c-axis of the hexagonal semiconductor.

  In order to form the epitaxial semiconductor region so that the main surface of the epitaxial semiconductor region is inclined at an angle in the range of 10 degrees to 45 degrees with respect to the c-plane of the gallium nitride semiconductor, the substrate of the main surface having the above inclination angle is formed. Can be used.

  The method according to the present invention may further include a step of forming a modified main surface on the substrate by performing a heat treatment on the main surface of the substrate prior to the film formation. The heat treatment is performed in an atmosphere of a gas containing ammonia and hydrogen. According to this method, microsteps are formed on the main surface of the substrate by this heat treatment.

  The method according to the present invention may further include a step of epitaxially growing a first conductivity type gallium nitride based semiconductor region on the substrate after the heat treatment. The main surface of the first conductivity type gallium nitride based semiconductor region is inclined at an angle in the range of greater than 10 degrees and less than 45 degrees from the c-plane of the gallium nitride based semiconductor.

  According to this method, the crystal plane is inherited also to the main surface of the first conductivity type gallium nitride based semiconductor region by epitaxial growth. The microstep of the main surface of the substrate is also inherited by the main surface of the first conductivity type gallium nitride based semiconductor region and the epitaxial semiconductor region.

  In the method according to the present invention, the direction of inclination of the main surface of the substrate may be the direction of the a-axis of the gallium nitride semiconductor. According to this method, the main surface of the substrate is inclined in the a-axis direction from the {0001} plane, and the incorporation of In into InGaN is larger than the inclination in the m-axis direction. Therefore, the InGaN well layer can be grown at a higher growth temperature, and the light emission characteristics are improved.

  The method according to the present invention may further comprise a step of performing m-plane cleavage to produce a resonator surface. According to this method, it is possible to manufacture a semiconductor laser in which the m-plane formed by cleavage is a resonator plane.

  In the method according to the present invention, the direction of the inclination and the direction of the m-axis of the gallium nitride based semiconductor may be in the range of 89 degrees to 91 degrees. When the angle variation in the direction of inclination exceeds the range of −1 degree or more and +1 degree or less, the deterioration of the characteristics as a laser becomes remarkable.

  In the method according to the present invention, the substrate has a plurality of first regions in which the density of threading dislocations extending in the c-axis direction is higher than the first threading dislocation density, and the density of threading dislocations extending in the c-axis direction is the first. And a plurality of second regions smaller than the threading dislocation density. The first and second regions are alternately arranged, and the first and second regions appear on the main surface of the substrate.

  The first region is a high-dislocation semiconductor region, and the second region is a low-dislocation semiconductor region. By producing a nitride-based semiconductor light emitting device in a low dislocation region of the substrate, the light emitting efficiency and reliability of the light emitting device can be improved.

In the method according to the present invention, the density of the threading dislocations in the second region may be less than 1 × 10 ⁷ cm ⁻² . When the density of threading dislocations in the second region is less than 1 × 10 ⁷ cm ⁻² , a semiconductor laser having sufficient reliability for practical use can be obtained.

The method according to the present invention, after growing the well layer, prior to growing the barrier layer, while changing the temperature at the growth temperature T _B from the growth temperature T _W, growing gallium nitride based semiconductor layer A process can be further provided. The gallium nitride based semiconductor layer is thinner than the barrier layer. According to this method, following the growth of the well layer, the temperature of the growth furnace is changed to the growth temperature of the barrier layer. Since the gallium nitride based semiconductor layer is grown on the well layer after the growth of the well layer, the deterioration of the well layer during the temperature rise can be reduced.

  In the method according to the present invention, the growth rate in the growth of the gallium nitride based semiconductor layer can be smaller than the growth rate in the growth of the barrier layer. According to this method, the growth of the gallium nitride based semiconductor layer is performed at a temperature lower than the growth temperature of the barrier layer. Therefore, in order to obtain a sufficient time until the temperature rise is completed, it is preferable to adjust the growth rate of the gallium nitride based semiconductor layer as described above.

  In the method according to the present invention, the gallium nitride based semiconductor layer may be thinner than the barrier layer. According to this method, the thickness of the gallium nitride based semiconductor layer formed during the temperature rise can be reduced, and the region different from the well layer and the barrier layer can be reduced. As a result, the thickness of the barrier layer can be formed to a sufficient value.

  In the method according to the present invention, the first conductive type gallium nitride based semiconductor region, the active layer, and the second conductive type gallium nitride based semiconductor layer are arranged in a direction of a normal line of the main surface of the substrate. Can be. The direction of the c-axis of the hexagonal semiconductor is different from the normal direction of the main surface of the substrate. According to this method, the crystal is grown in the c-axis direction. The growth direction is different from the stacking direction of the semiconductor layers.

Another aspect of the present invention is a method of fabricating an epitaxial wafer for a nitride semiconductor light emitting device. This method includes (a) a step of epitaxially growing a first conductive type gallium nitride based semiconductor region on a substrate, and (b) an epitaxial layer made of a gallium nitride based semiconductor on the first conductive type gallium nitride based semiconductor region. A step of forming a semiconductor region, and (c) an active layer on the epitaxial semiconductor region at a growth temperature T _W and a growth rate V _G (nm / min) within a temperature range of 640 degrees Celsius or more and 750 degrees Celsius or less. and growing a well layer for the steps of growing a barrier layer for; (d) in the epitaxial semiconductor region, in the above growth temperature T _W growth temperature T _B of the well layer, the active layer (E) Growing a second conductivity type gallium nitride based semiconductor layer on the active layer. The epitaxial semiconductor region has a main surface inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. The active layer is provided so as to generate an emission spectrum having a peak wavelength in a wavelength region of 480 nm or more and 550 nm or less, and the well layer includes In _X Ga _1-X N (indium composition X: 0 <X <1 , X is a strain composition).
When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 710 degrees Celsius, the upper limit of the growth rate V _G is the following formula (1)
V _G = α1 × T _W + β1 (1)
Equation (1) satisfies (growth temperature T _W , growth rate V _G ) = (710 degrees Celsius, 13.9 nm / min), (640 degrees Celsius, 5.5 nm / min), when the growth temperature _{T W} is the temperature below 750 degrees 710 degrees centigrade, the upper limit of the growth rate _{V G} is less than or equal 13.9 nm / min, the growth temperature _{T W} is lower than 690 degrees 640 degrees Celsius when a temperature, the lower limit of the growth rate _{V G} is at 5.5 nm / min or more, when the growth temperature _{T W} is the temperature below 690 degrees 750 degrees centigrade, the lower limit of the growth rate _{V G} Is the following equation (2)
V _G = α2 × T _W + β2 (2)
Equation (2) satisfies (growth temperature T _W , growth rate V _G ) = (640 degrees Celsius, 13.9 nm / min), (690 degrees Celsius, 5.5 nm / min).

According to this method, on the epitaxial semiconductor main surface inclined at an angle in the range from c-plane of the gallium nitride-based semiconductor of 10 to 45 degrees, with a growth rate V _G and the growth temperature T _W in terms of the range of the Thus, when an InGaN well layer is grown, an InGaN well layer having a good crystal quality can be grown on a gallium nitride semiconductor main surface having a relatively small off angle.

When the region has a relatively high growth temperature, that is, when the growth temperature _TW is not less than 690 degrees Celsius and not more than 750 degrees Celsius, there is a lower limit of the growth rate defined by the equation (2). As the growth temperature increases, a large growth rate is required for the growth of the well layer. This is because the In incorporation efficiency decreases as the growth temperature increases. Further, when the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 690 degrees Celsius, the growth rate has a lower limit, and a desired well layer cannot be obtained if the growth rate is too small. This is because if the growth rate is too low, the In incorporation efficiency becomes low and a desired wavelength cannot be obtained.

When the growth temperature T _W is the temperature below 750 degrees 710 degrees Celsius, the growth rate V _G has an upper limit, the growth rate is too large, the desired well layer can not be obtained. This is because the crystal quality of InGaN deteriorates and the light emission characteristics deteriorate. In addition, when the region has a relatively low growth temperature, that is, when the growth temperature _TW is not less than 640 degrees Celsius and less than 700 degrees Celsius, there is an upper limit of the growth rate defined by the equation (1). As the growth temperature increases, the upper limit of the growth rate also increases. This is because as the growth temperature increases, the In incorporation efficiency decreases, and if the growth rate is low, a desired wavelength cannot be obtained.

  The method according to the present invention may further include a step of performing heat treatment on the main surface of the substrate in an atmosphere of a gas containing ammonia and hydrogen prior to the film formation. According to this method, microsteps are formed on the main surface of the substrate by this heat treatment.

In the method according to the present invention, the substrate is made of hexagonal semiconductor _{In S Al T Ga 1-S} -T N (0 ≦ S ≦ 1,0 ≦ T ≦ 1,0 ≦ S + T ≦ 1), the substrate Is inclined at an angle in a range of 10 degrees to 45 degrees from a plane orthogonal to the c-axis of the hexagonal semiconductor.

  In order to form the epitaxial semiconductor region so that the main surface of the epitaxial semiconductor region is inclined from the c-plane of the gallium nitride-based semiconductor at an angle in the range of 10 degrees to 45 degrees, Can be used.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, a method for manufacturing a nitride-based semiconductor light-emitting device is provided. According to another aspect of the present invention, a method for producing an epitaxial wafer for a nitride semiconductor light emitting device is provided. According to these methods, an InGaN well layer having a good crystal quality can be grown on a gallium nitride based semiconductor main surface having a relatively small off angle.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a nitride-based semiconductor light-emitting device of the present invention and a method for producing an epitaxial wafer will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1 is a flowchart showing main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment. 2 to 4 are diagrams showing substrate products in main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment.

In step S101, the substrate 11 is prepared. Substrate 11 is made of a hexagonal semiconductor _{In S Al T Ga 1-S} -T N (0 ≦ S ≦ 1,0 ≦ T ≦ 1,0 ≦ S + T ≦ 1). Referring to FIG. 2A, the substrate 11 can be made of, for example, GaN, InGaN, AlGaN, InAlGaN, or the like. The main surface 11a of the substrate 11 is inclined at an angle of 10 degrees or more from a plane orthogonal to the c-axis of the hexagonal semiconductor. When the inclination angle θ is less than 10 degrees, a sufficient piezoelectric field reduction effect cannot be obtained. The main surface 11a of the substrate 11 is inclined at an angle in a range of 45 degrees or less. When the inclination angle θ exceeds 45 degrees, it becomes difficult to manufacture a wafer having a relatively large diameter. In the cross section of the substrate 11, a representative c-plane S _C , c-axis vector VC, and normal vector VN are shown. The inclination angle θ is defined by an angle formed by the c-axis vector VC and the normal vector VN. The maximum value of the distance between two points on the edge of the substrate 11 can be 45 mm or more, and the back surface 11 b of the substrate 11 can be substantially parallel to the main surface 11 a of the substrate 11. Such a substrate 11 is called a “wafer”.

  In the subsequent process, a semiconductor crystal is epitaxially grown on the main surface 11 a of the substrate 11. An active layer is grown on the underlying epitaxial semiconductor region, and the epitaxial semiconductor region is formed such that the principal surface of the underlying layer is inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. For this purpose, the substrate 11 having the main surface 11a having the above-described inclination angle can be used.

  The direction of inclination of the main surface 11a of the substrate 11 can be, for example, the direction of the a-axis of the gallium nitride semiconductor of the substrate 11. If the main surface 11a of the substrate 11 is inclined in the a-axis direction from the {0001} plane, the incorporation of In into InGaN is larger than the inclination in the m-axis direction. Therefore, the InGaN well layer can be grown at a higher growth temperature, and the light emission characteristics are improved.

The substrate 11 is disposed in the growth furnace 10. In the subsequent crystal growth, metal organic vapor phase epitaxy is used. Prior to film formation, in step S101, subsequently, as shown in FIG. 2B, the main surface 11a of the substrate 11 is subjected to heat treatment to form the modified main surface 11c on the substrate 11. This heat treatment is performed in an atmosphere of a gas containing ammonia and hydrogen or nitrogen. The heat treatment temperature can be, for example, 800 degrees Celsius or more and 1200 degrees Celsius or less. The heat treatment time is, for example, about 10 minutes. According to this method, a microstep is formed on the main surface 11c of the substrate 11 by this heat treatment, and the microstep is composed of a plurality of terraces. The density of the microstep can be, for example, 2.0 × 10 ⁴ cm ⁻¹ or more and 3.3 × 10 ⁷ cm ⁻¹ . The height of the microstep can be, for example, 0.3 nm or more and 10 nm or less. The length of the microstep can be, for example, not less than 0.3 nm and not more than 500 nm.

  In step S102, after the heat treatment, the first conductivity type gallium nitride based semiconductor region 13 is epitaxially grown on the surface 11c of the substrate 11 as shown in FIG. This growth is performed using the growth furnace 10. The main surface 13a of the gallium nitride based semiconductor region 13 is inclined at an angle in the range of 10 degrees to 45 degrees from the c plane of the gallium nitride based semiconductor. Further, the main surface 13a takes over the structure of the main surface 11c of the substrate 11, and the microstep is formed in the same manner. The first conductivity type gallium nitride based semiconductor region 13 may include one or more gallium nitride based semiconductor layers (for example, gallium nitride based semiconductor layers 15, 17, and 19). For example, the gallium nitride based semiconductor layers 15, 17 and 19 can be an n-type AlGaN layer, an n-type GaN layer and an n-type InGaN layer, respectively. The gallium nitride based semiconductor layers 15, 17 and 19 are epitaxially grown in order on the main surface 11 c of the substrate 11. The n-type AlGaN layer is, for example, an intermediate layer covering the entire surface of the substrate 11, the n-type GaN layer is a layer for supplying n-type carriers, for example, and the n-type InGaN layer is a buffer layer for active layers, for example. is there.

In step S103, as shown in FIG. 3A, the active layer 21 of the nitride-based semiconductor light-emitting element is manufactured. The active layer 21 is provided so as to generate an emission spectrum having a peak wavelength in a wavelength region of 480 nm or more and 550 nm or less. Hereinafter, the procedure for producing the quantum well structure of the active layer 21 will be described in detail with reference to FIG. FIG. 5 is a time chart showing changes in the temperature of the source gas and the growth furnace in the formation of the active layer. As the source gas, a gallium source, an indium source, and a nitrogen source are used. The gallium source, the indium source, and the nitrogen source are, for example, TMG, TMI, and NH ₃ , respectively.

In step S104, as shown in FIG. 3B, an epitaxial semiconductor region 23 made of a gallium nitride based semiconductor is formed. The epitaxial semiconductor region 23 is grown on the gallium nitride based semiconductor layer 19 (for example, a buffer layer). The epitaxial semiconductor region 23 is, for example, a first barrier layer for the quantum well structure of the active layer 21. The barrier layer is made of In _Y Ga _1-Y N (indium composition Y: 0 ≦ Y ≦ 0.05, Y is a strained composition), and the first barrier layer can be GaN or InGaN. In this embodiment, a gallium source and a nitrogen source are supplied to the growth reactor 10 to grow GaN. This growth is grown at a growth temperature _{T B} between times t0~t1 in FIG. The thickness _{D B1} of the GaN barrier layer is 15nm for example.

  Since the epitaxial semiconductor region 23 is grown on the main surface 21a, the epitaxial semiconductor region 23 has a main surface 23a inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. The surface of the epitaxial semiconductor region 23 inherits the surface structure of the main surface 21a.

At time t1, the supply of the gallium raw material is stopped. After growing the first barrier layer, in step S105, as shown in FIG. 5, to change the temperature in the growth furnace before the growth of the well layer from the growth temperature T _B to a growth temperature T _W. The temperature is changed during the period from time t1 to t3 in FIG. During this change period, when a nitrogen source such as ammonia is supplied to the growth reactor 10 and the supply amount of the nitrogen source in the growth of the barrier layer is different from the supply amount of the nitrogen source in the growth of the well layer, the supply of the nitrogen source is performed. Change the amount to match the supply for well layer growth. At least during the temperature change period, the flow rate of the nitrogen source is changed from the flow rate of the nitrogen source in the growth of the barrier layer to the flow rate of the nitrogen source in the growth of the well layer. This change is performed between times t1 and t2 in FIG.

At time t3, the temperature in the growth furnace 10 reaches the growth temperature T _W of the well layer. In step S106, as shown in FIG. 3C, a well layer 25a for the quantum well structure is grown on the epitaxial semiconductor region 23 in the period from time t3 to time t4. Well layer 25a is _In X _{Ga 1-X} N (indium composition X: 0 <X <1, X : strained composition) consisting of. As shown in FIG. 5, the growth temperature _{T W} of the well layer 25a is lower than the growth temperature _{T B.} Since the main surface of the well layer 25a is epitaxially grown on the main surface of the epitaxial semiconductor region 23, it is inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. Further, the surface of the well layer 25 a inherits the surface structure of the epitaxial semiconductor region 23. Growth of the well layer 25a is carried out, for example, at the growth temperature _{T W} within the temperature range of 750 degrees 640 degrees Celsius. The thickness _DW of the InGaN well layer is 3 nm, for example.

In the growth of the well layer 25a, a condition is used in which not only the growth temperature _TW but also the growth rate V _G (nm / min) is within a predetermined range. About this condition, it is as follows.

When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 710 degrees Celsius, the upper limit of the growth rate V _G is the following formula (1)
V _G = α1 × T _W + β1 (1)
Is the value of the growth rate given by Α1 and β1 in this formula (1) satisfy (growth temperature T _W , growth rate V _G ) = (710 degrees Celsius, 13.9 nm / min), (640 degrees Celsius, 5.5 nm / min). More specifically, α1 = (13.9−5.5) / (710−640) = 8.4 / 70 = 0.12 when the coefficients α1 and β1 are calculated.
β1 = (640 × 13.9−710 × 5.5) / (640−710) = − 4991/70 = −71.3
It is.

When the growth temperature _{T W} is the temperature below 710 degrees 750 degrees centigrade, the upper limit of the growth rate _{V G} is less 13.9 nm / min.

When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 690 degrees Celsius, the lower limit of the growth rate V _G is 5.5 nm / min or more.

When the growth temperature _{T W} is the temperature below 750 degrees 690 degrees centigrade, the lower limit of the growth rate _{V G,} the following equation (2)
V _G = α2 × T _W + β2 (2)
Is the value of the growth rate given by Α2 and β2 in the formula (2) satisfy (growth temperature T _W , growth rate V _G ) = (750 degrees Celsius, 13.9 nm / min), (690 degrees Celsius, 5.5 nm / min). More specifically, α2 = (13.9−5.5) / (750−690) = 0.14 when the coefficients α1 and β1 are calculated.
β2 = (690 × 13.9−750 × 5.5) / (690−750) = − 5466/60 = −91.1
It is.

According to this method, on the epitaxial semiconductor main surface inclined at an angle in the range from c-plane of the gallium nitride-based semiconductor of 10 to 45 degrees, with a growth rate V _G and the growth temperature T _W in terms of the range of the When the InGaN well layer 25a is grown, the InGaN well layer 25a with good crystal quality can be grown on the gallium nitride based semiconductor main surface with a relatively small off angle.

When the region has a relatively high growth temperature, that is, when the growth temperature _TW is not less than 690 degrees Celsius and not more than 750 degrees Celsius, there is a lower limit of the growth rate defined by the equation (2). As the growth temperature increases, a higher growth rate is required. This is because the In incorporation efficiency decreases as the growth temperature increases. Further, when the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 690 degrees Celsius, the growth rate has a lower limit. This is because if the growth rate is too low, the In incorporation efficiency becomes low and a desired wavelength cannot be obtained.

When the growth temperature _{T W} is the temperature below 710 degrees 750 degrees Celsius, the growth rate _{V G} has an upper limit. This is because if the growth rate is too fast, the crystal quality of InGaN deteriorates and the light emission characteristics deteriorate. In addition, when the growth temperature region is relatively low, that is, when the growth temperature _TW is not less than 640 degrees Celsius and less than 710 degrees Celsius, there is an upper limit of the growth rate defined by the equation (1). As the growth temperature increases, the upper limit of the growth rate increases. This is because as the growth temperature increases, the In incorporation efficiency decreases, and if the growth rate is low, a desired wavelength cannot be obtained.

As shown in FIG. 5, the growth of the well layer 25a is completed at time t4. In step S107, to change the temperature from the temperature _{T W} to the growth temperature _{T B} of the second barrier layer 29a. This temperature increase is performed, for example, during a period from time t4 to time t6. In order to prevent the well layer 25a from deteriorating during the temperature rise, as shown in FIG. 4A, the protective layer 27a can be grown so as to cover the surface of the well layer 25a. The protective layer 27a is made of a gallium nitride based semiconductor having a larger band gap than the material of the well layer 25a. In order to stop the growth of InGaN in the well layer 25a at time t4, the supply of the indium raw material is stopped. The gallium nitride based semiconductor of the protective layer 27a is grown at a growth rate lower than the growth rate of the barrier layer 29a. For example, the growth rate is adjusted by decreasing the supply amount of the gallium raw material, and the supply amount of the nitrogen raw material is decreased in the period of time t4 to t5. In the period from time t4 to time t6, as shown in FIG. 4A, the protective layer 27a made of the gallium nitride based semiconductor is epitaxially grown. The surface of the protective layer 27a inherits the surface structure of the well layer 25a. The protective layer 27a is thinner than the barrier layer 29a. In this embodiment, the protective layer 27a is made of the same material as the barrier layer 29a and is GaN. The thickness _{D P} of the GaN protective layer is 2.5nm, for example. Since the main surface of the protective layer 27a is grown on the main surface of the well layer 25a, it is inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor.

At time t6, the temperature increase of the growth furnace 10 is completed. At time t6 to t7, as shown in FIG. 4 (b), growth of the barrier layer 29a composed of a gallium nitride-based semiconductor at the growth temperature _{T B.} The thickness _{D B2} of the barrier layer 29a is larger than the thickness _{D P} of the protective layer 27a. The thickness of the gallium nitride based semiconductor layer formed during the temperature rise can be reduced, whereby the thickness of the protective layer 27a can be reduced relative to the thickness of the well layer and the barrier layer. Therefore, the thickness of the barrier layer 29a can be formed to a sufficient value. The growth of the protective layer 27a made of the gallium nitride based semiconductor layer is performed at a temperature lower than the growth temperature of the barrier layer 29a. Therefore, in order to obtain a sufficient time until the temperature rise is completed, it is preferable to adjust the growth rate of the protective layer 27a as described above.

Barrier layer 29a is made of GaN for example, a thickness _{D B2} of the barrier layer 29a is 12.5nm example. Since the main surface of the barrier layer 29a is epitaxially grown on the main surface of the protective layer 27a, the main surface of the barrier layer 29a is inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor. The surface of the protective layer 27a inherits the surface structure of the well layer 25a.

Similarly, the formation of the active layer 21 is continued. In step S109, cooling from the temperature _{T B} to a temperature _{T W} (period t7~t8~t9, t13~t14~t15), growth of the well layer (the period t9 to t10), the protective layer growth (period t10 to t11) and heating from the temperature _{T W} to the temperature _{T B} (period t10~t11~t12), and repeating the growth of the barrier layer (period t12 to t13), to complete a quantum well structure. As shown in FIG. 5, the quantum well structure includes barrier layers 23, 29a, 29b, and 29c, well layers 25a, 25b, and 25c, and protective layers 27a, 27b, and 27c.

Well layers 25a, 25b, 25c of the growth temperature _{T W} and the barrier layer 23 and 29a, 29 b, the difference between the growth temperature _{T B} of 29c can be not less 230 degrees 60 degrees. Since the indium composition X of the well layers 25a, 25b, and 25c is larger than the indium composition Y (0 ≦ Y ≦ 0.05) of the barrier layers 23, 29a, 29b, and 29c, the growth of the well layers 25a, 25b, and 25c while it is necessary deposition temperature to grow the InGaN of a desired indium content is a good crystal quality of the barrier layers 23 and 29a, 29 b, to form the 29c, the growth temperature _{T B,} the well layer 25a, 25b , it needs to be higher than the growth temperature _{T W} of 25c. When the difference between the growth temperature _{T W} and a growth temperature _{T B} is less than 60 degrees, in subsequent growth to the growth of the active layer 21, the well layer 25a, 25b, the crystal quality of 25c decreases. When the difference between the growth temperature _{T W} and the growth temperature _{T B} is in excess of 230 degrees, the barrier layer 23 and 29a, 29 b, the well layer 25a during the growth of the 29c, 25b, the crystal quality of 25c decreases.

The film thickness of the well layers 25a, 25b, and 25c can be 2 nm or more and 10 nm or less. Further, the indium composition X of the In _X Ga _1-X N well layers 25a, 25b, and 25c can be larger than 0.15. In _X Ga _1-X N of the well layers 25a, 25b, and 25c can be smaller than 0.4. By following the conditions of the growth temperature and the growth rate, InGaN having an indium composition in the above range can be grown, and a light-emitting element having a wavelength of 480 nm to 550 nm can be obtained.

Referring again to FIG. 1, in step S <b> 110, the second conductivity type gallium nitride based semiconductor region 31 is epitaxially grown on the surface 11 c of the substrate 11 on the active layer 21. This growth is performed by using the growth reactor 10, the growth temperature T2 well layer 25a of the second conductive type gallium nitride based semiconductor layer 31, 25b, higher than the growth temperature _{T W} of 25c. The second conductivity type gallium nitride based semiconductor region 31 can include, for example, an electron block layer 33, a first p-type contact layer 35, and a second p-type contact layer 37. The electron block layer 33 can be made of, for example, AlGaN. The p-type contact layers 35 and 37 can be made of p-type GaN. The dopant concentration N ₃₇ of the second p-type contact layer 37 is higher than the dopant concentration N ₃₅ of the first p-type contact layer 35. In this embodiment, the growth temperature of the electron block layer 33 and the p-type contact layers 35 and 37 is, for example, 1100 degrees Celsius. In the step of forming the second conductivity type gallium nitride semiconductor region 31, the epitaxial wafer E shown in FIG. 4C is completed. If necessary, a pair of light guide layers can be grown for the light guide of the semiconductor laser. The pair of light guide layers sandwich the active layer. These light guide layers can be made of, for example, InGaN or GaN.

The difference between the highest growth temperature T2 in the growth of the well layer 25a, 25b, the growth temperature _{T W} and the second conductivity type gallium nitride based semiconductor region 31 of 25c is less 510 degrees 140 degrees. When the growth temperature T _W and a growth temperature T2 so that the difference is less than 140 degrees between the growth temperature T2 is set, the resistivity of the second conductive type gallium nitride based semiconductor layer 35 and 37 is increased. When the growth temperature _{T W} and a growth temperature T2 growth temperature T2 so that the difference is more than 510 degrees and is set, the second conductive type gallium nitride based semiconductor layers 35 and 37 also show growing the well layer 25a, 25b, 25c The crystal quality of the is reduced.

  The growth rate of the p-type contact layers 35 and 37 is larger than the growth rate of the well layers 25a, 25b, and 25c and the barrier layers 23, 29a, 29b, and 29c. The growth time of the p-type contact layers 35 and 37, which is performed at a temperature higher than the growth temperature of the well layers 25a, 25b, and 25c after the active layer 21 is formed, can be shortened.

  The first conductive type gallium nitride based semiconductor region 13, the active layer 21, and the second conductive type gallium nitride based semiconductor layer 31 may be arranged in the direction of the normal axis of the main surface 11 a of the substrate 11. The direction of the c-axis of the hexagonal semiconductor is different from the direction of the normal axis of the main surface 11 a of the substrate 11. While the growth direction of the epitaxial growth is the c-axis direction, this growth direction is different from the stacking direction of the semiconductor layers 13, 21, and 31.

  In step S111, electrodes are formed on the epitaxial wafer E. A first electrode (for example, an anode electrode) is formed on the contact layer 37, and a second electrode (for example, a cathode electrode) is formed on the substrate back surface 13b (the ground back surface if necessary). .

  After formation of the electrode, m-plane cleavage can be performed to produce a resonator surface. A semiconductor laser having an m-plane formed by cleavage as a resonator surface can be manufactured. Further, the direction of the c-axis inclination in the substrate 11 and the direction of the m-axis of the gallium nitride semiconductor of the substrate 11 can be in the range of 89 degrees to 91 degrees. When the inclination direction of the substrate main surface 11a exceeds the range of −1 degree or more and +1 degree or less with respect to the m-axis direction, the deterioration of the characteristics as a laser becomes remarkable. If the direction of inclination of the main surface 23a of the epitaxial semiconductor region 23 is the a-axis direction of the gallium nitride semiconductor, the m-plane can be used as a cleavage plane.

  FIG. 6 shows a structure of a GaN substrate that can be used in the embodiment. The substrate 11 includes a plurality of first regions 12a having a threading dislocation density extending in the c-axis direction larger than the first threading dislocation density, and a plurality of threading dislocation densities extending in the c-axis direction smaller than the first threading dislocation density. Second region 12b. First and second regions 12 a and 12 b appear on the main surface 11 a of the substrate 11. In the main surface 11a of the substrate 11, the widths of the first and second regions 12a and 12b are, for example, 30 micrometers and 370 micrometers, respectively. The first and second regions 12a and 12b are alternately arranged in a predetermined direction (arrangement direction). When the substrate is made of gallium nitride, the alignment direction can be the a-axis direction of the gallium nitride.

The first region 12a is a semiconductor portion of a defect concentration region having a high dislocation density, and the second region 12b is a semiconductor portion of a defect reduction region having a low dislocation density. By producing a nitride-based semiconductor light-emitting element in the low dislocation density region of the substrate 11, the light emission efficiency and reliability of the light-emitting element can be improved. Further, the threading dislocation density of the second region 12b can be less than 1 × 10 ⁷ cm ⁻² . When the threading dislocation density in the second region 12b is less than 1 × 10 ⁷ cm ⁻² , a semiconductor laser having sufficient reliability for practical use can be obtained.

Example 1
Next, examples of the present embodiment will be described. A light-emitting diode was fabricated using metal organic vapor phase epitaxy. FIG. 7 shows main manufacturing conditions. Trimethylgallium (TMG), trimethylindium (TMI), trimethylaluminum (TMA), and ammonia were used as a gallium source, an indium source, an aluminum source, and a nitrogen source, respectively, for metal organic chemical vapor deposition. SiH ₄ and Cp ₂ Mg were used as n-type and p-type dopants. A GaN wafer 41 was prepared. The main surface of the GaN wafer 41 is inclined at an angle of 18 degrees with respect to the c-plane of the GaN wafer 41. After the GaN wafer 41 was placed in the growth furnace, heat treatment was performed in an atmosphere of ammonia and hydrogen. The heat treatment temperature was 1050 degrees Celsius, and the heat treatment time was about 10 minutes. After the heat treatment, TMG (24.2 μmol / min), TMA (4.3 μmol / min), NH ₃ (5 slm), and SiH ₄ are supplied to the growth furnace to form an n-type AlGaN layer 43 on the GaN wafer 41. It grew at 1100 degrees. The thickness of the n-type AlGaN layer 43 was 50 nm. The growth rate of the n-type AlGaN layer 43 was 9.8 nm / min. The Al composition of the n-type AlGaN layer 43 was 0.12.

TMG (243.8 μmol / min), NH ₃ (7.5 slm), and SiH ₄ were supplied to the growth reactor, and the n-type GaN layer 45 was grown on the n-type AlGaN layer 43 at 1150 degrees Celsius. The thickness of the n-type GaN layer 45 was 2000 nm. The growth rate of the n-type GaN layer 45 was 129.6 nm / min.

TMG (24.4 μmol / min), TMI (24.4 μmol / min), NH ₃ (6 slm), SiH ₄ were supplied to the growth reactor, and the n-type InGaN layer 47 was placed on the n-type GaN layer 45 at 780 degrees Celsius. I grew up. The thickness of the n-type InGaN layer 47 was 100 nm. The growth rate of the n-type InGaN layer 47 was 6.7 nm / min. The In composition of the n-type InGaN layer 47 was 0.04.

An active layer 49 was grown. TMG (24.4 μmol / min) and NH ₃ (6 slm) were supplied to the growth reactor, and the undoped GaN layer 49a was grown on the n-type InGaN layer 47 at 870 degrees Celsius. The thickness of the undoped GaN layer 49a was 15 nm. The growth rate of the GaN layer 49a was 6.7 nm / min.

  Next, the temperature of the growth furnace was changed from 870 degrees Celsius to 660 degrees Celsius.

TMG (24.4 μmol / min), TMI (276.2 μmol / min), and NH ₃ (8 slm) were supplied to the growth reactor, and the undoped InGaN layer 49b was grown on the GaN layer 49a at 660 degrees Celsius. The thickness of the InGaN layer 49b was 4 nm. The growth rate of the InGaN layer 49b was 5.5 nm / min. The In composition of the undoped InGaN layer 49b was 0.20.

While changing the temperature of the growth furnace from 660 degrees Celsius to 870 degrees Celsius, TMG (2.6 μmol / min) and NH ₃ (6 slm) were supplied to the growth furnace to grow the protective layer 49c. The thickness of the protective layer 49c was 2.5 nm. The average growth rate of the GaN layer 49c was 1.0 nm / min.

TMG (24.4 μmol / min) and NH ₃ (6 slm) were supplied to the growth reactor, and the undoped GaN layer 49d was grown on the GaN layer 49c at 870 degrees Celsius. The thickness of the GaN layer 49d was 12.5 nm. The growth rate of the GaN layer 49d was 6.7 nm / min.

The active layer 49 was formed by repeating the growth of the well layer 49b, the protective layer 49c, and the barrier layer 49d. Thereafter, TMG (13.0 μmol / min) and NH ₃ (6 slm) were supplied to the growth reactor, and an undoped GaN layer (N 2 -GaN layer) 51 was grown on the active layer 49 at 870 degrees Celsius. The thickness of the GaN layer 51 was 3 nm. The growth rate of the GaN layer 51 was 4.5 nm / min. Further, TMG (13.0 μmol / min) and NH ₃ (6 slm) were supplied to the growth reactor, and an undoped GaN layer (undoped GaN layer) 53 was grown on the GaN layer 51 at 1100 degrees Celsius. The thickness of the GaN layer 53 was 10 nm. The growth rate of the GaN layer 53 was 60.0 nm / min.

TMG (24.4 μmol / min), TMA (2.3 μmol / min), NH ₃ (6 slm), Cp ₂ Mg were supplied to the growth reactor, and the p-type AlGaN layer 55 was formed on the GaN layer 53 at 1100 degrees Celsius. grown. The thickness of the AlGaN layer 55 was 20 nm. The growth rate of the AlGaN layer 55 was 5.9 nm / min. The Al composition of the p-type AlGaN layer 55 was 0.18.

TMG (98.7 μmol / min), NH ₃ (5 slm), and Cp ₂ Mg were supplied to the growth reactor, and the p-type GaN layer 57 was grown on the p-type AlGaN layer 55 at 1100 degrees Celsius. The thickness of the GaN layer 57 was 25 nm. The growth rate of the GaN layer 57 was 58.2 nm / min. Further, TMG (67.0 μmol / min), NH ₃ (5 slm), and Cp ₂ Mg were supplied to the growth reactor, and the p-type GaN layer 59 was grown on the p-type GaN layer 57 at 1100 degrees Celsius. The thickness of the GaN layer 59 was 25 nm. The growth rate of the GaN layer 59 was 36.3 nm / min. An epitaxial wafer was fabricated by these steps. The anode 61a and the cathode 61b were formed on this epitaxial wafer, and the light emitting device shown in FIG. 8 was obtained. In FIG. 8, a c-plane Sc showing an off angle of 18 degrees is drawn as a representative, and a crystal coordinate system CR shown by the c-axis, a-axis, and m-axis, and a position map showing the X-axis, Y-axis, and Z-axis System S is shown.

  A GaN wafer of the same quality as the GaN wafer 41 was prepared, and the active layer was grown using various growth temperatures and growth rates with respect to the well layer. A number of epitaxial wafers were fabricated using the same conditions as in the above-described example as the deposition conditions of the epitaxial film excluding the active layer. Further, in the same manner as in the above example, an anode and a cathode were formed on these epitaxial wafers to produce a light emitting device. The structure of these light emitting elements is the same as that shown in FIG. 8 except for the structure of the active layer.

FIG. 9 is a drawing showing photoluminescence (PL) spectra PL1, PL2, and PL3 of a light-emitting element manufactured under typical conditions. The PL spectrum PL spectrum and film formation conditions for the well layer are shown.
PL name, film forming temperature T _W , growth rate V _G , full width at half maximum, peak wavelength;
PL 1: 660 degrees, 5.5 nm / min, 54 nm, 524 nm;
PL2: 690 degrees, 9.3 nm / min, 49 nm, 513 nm;
PL3: 710 degrees, 13.9 nm / min, 44 nm, 520 nm.
According to the result of FIG. 9, as the growth rate increases, the PL intensity increases and the PL full width at half maximum decreases. Regarding the growth rate, it became clear that there is a lower limit for obtaining a desired result as well as an upper limit.

FIG. 10 is a graph showing the relationship between the emission wavelength and the growth rate in the production of these light-emitting elements. In the graph, plots EP1 to EP14 and EQ1 to EQ6 are shown. Plots EP1 to EP14 are conditions for manufacturing an element including an active layer that generates a PL spectrum having a peak wavelength in a wavelength region of 480 nm to 550 nm. Regarding the plots EP1 to EP14, the upper limit of the growth rate V _G is given by the equation (1) in the range of the growth temperature of 640 to 710 degrees Celsius, and 13 in the range of the growth temperature of 710 to 750 degrees Celsius. .9 nm / min. Further, the lower limit of the growth rate V _G is 5.5 nm / min in the range of the growth temperature of 640 to 690 degrees Celsius, and is given by the equation (2) in the range of the growth temperature of 690 to 750 degrees Celsius. It is done.

Plot name, film-forming temperature T _W , growth rate V _G , full width at half maximum, peak wavelength;
EP1: 710 degrees Celsius, 13.9 nm / min, 44 nm, 520 nm;
EP2: 730 degrees Celsius, 13.9 nm / min, 46 nm, 506 nm;
EP3: 740 degrees Celsius, 13.9 nm / min, 41 nm, 495 nm;
EP4: 750 degrees Celsius, 13.9 nm / min, 36 nm, 483 nm;
EP5: 700 degrees Celsius, 11.4 nm / min, 49 nm, 510 nm;
EP6: 675 degrees Celsius, 9.3 nm / min, 43 nm, 509 nm;
EP7: 690 degrees Celsius, 9.3 nm / min, 46 nm, 518 nm;
EP8: 700 degrees Celsius, 9.3 nm / min, 45 nm, 523 nm;
EP9: 710 degrees Celsius, 9.3 nm / min, 81 nm, 550 nm;
EP10: 675 degrees Celsius, 7.1 nm / min, 50 nm, 518 nm;
EP11: 640 degrees Celsius, 5.5 nm / min, 67 nm, 510 nm;
EP12: 660 Celsius, 5.5 nm / min, 60 nm, 520 nm;
EP13: 675 degrees Celsius, 5.5 nm / min, 78 nm, 507 nm;
EP14: 690 degrees Celsius, 5.5 nm / min, 52 nm, 502 nm.

The plots EQ1 to EQ6 do not satisfy the above wavelength condition.
Plot name, deposition temperature T _W , growth rate V _G ;
EQ1: 760 degrees Celsius, 13.9 nm / min, 26 nm, 459 nm;
EQ2: 730 degrees Celsius, 9.3 nm / min, 30 nm, 460 nm;
EQ3: 720 degrees Celsius, 9.3 nm / min, 33 nm, 477 nm;
EQ4: 720 degrees Celsius, 5.5 nm / min, 27 nm, 444 nm;
EQ5: 690 degrees Celsius, 3.5 nm / min, 30 nm, 460 nm;
EQ6: 690 degrees Celsius, 2.3 nm / min, 28 nm, 439 nm.

  In the range of the preferable growth temperature and film formation speed in FIG. 10, a sufficiently high PL intensity and a practically sufficiently small PL half-value width can be obtained at a PL emission wavelength of 480 nm or more and 550 nm or less.

The semi-polar plane semiconductor surface with a low off-angle inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane has a higher microstep density and a smaller In incorporation than the c-plane. When a step composed of c-plane and (10-11) plane is formed on the semiconductor surface, In is taken in on the terrace. However, from the viewpoint of the bond of chemical bonds appearing at the terrace edge (microstep end), In atoms are not taken in at the terrace edge. For this reason, a specific InGaN growth condition on the semipolar plane different from that on the c-plane is required on the semipolar plane with a low off-angle.
In addition, a low off-angle semipolar plane semiconductor surface inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane has a higher microstep density than the c-plane, and migration is unlikely to occur. For this reason, even if the growth temperature of the barrier layer is higher than the growth temperature of the well layer, the well layer is less likely to decompose during the growth of the barrier layer than the c-plane.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a flowchart showing main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment. FIG. 2 is a drawing showing substrate products in main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment. FIG. 3 is a drawing showing substrate products in main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment. FIG. 4 is a drawing showing substrate products in main steps of a method for manufacturing a nitride-based semiconductor light-emitting device and a method for manufacturing an epitaxial wafer according to the present embodiment. FIG. 5 is a time chart showing changes in the temperature of the source gas and the growth furnace in the formation of the active layer. FIG. 6 shows a structure of a GaN substrate that can be used in the embodiment. FIG. 7 is a drawing showing main manufacturing conditions in Example 1. FIG. 8 is a drawing showing the structure of a light emitting device and an epitaxial wafer in Example 1 using a GaN wafer having an off angle of 18 degrees. FIG. 9 is a drawing showing photoluminescence (PL) spectra PL1, PL2, and PL3 of a light-emitting element manufactured under typical conditions. FIG. 10 is a graph showing the relationship between the emission wavelength and the growth rate in the production of the light-emitting device of Example 1.

Explanation of symbols

11 ... substrate, 11a ... substrate main surface, 11b ... back surface of the substrate, _{S C} ... c plane, VC ... c-axis vector, VN ... normal vectors, 10 ... growth reactor 13 ... gallium nitride based semiconductor region, 13a ... gallium nitride system semiconductor region major surface, 15, 17, and 19 ... gallium nitride based semiconductor layer, 21 ... active _{layer, D} B1 ... GaN barrier layer, 23 ... epitaxial semiconductor region (first barrier layer), the growth of T B _... barrier layer Temperature, T _W ... Well layer growth temperature, 25a, 25b, 25c ... Well layer, 27a, 27b, 27c ... Protective layer, 23, 29a, 29b, 29c ... Barrier layer, 31 ... Second conductivity type gallium nitride based semiconductor Region, 33 ... electron blocking layer, 35, 37 ... p-type contact layer

Claims (20)

A method for producing a nitride-based semiconductor light-emitting device having an active layer having a quantum well structure,
Forming an epitaxial semiconductor region made of a gallium nitride based semiconductor;
And growing a well layer of the quantum well structure on the epitaxial semiconductor region at a growth temperature T _W and a growth rate V _G (nm / min) within a temperature range of 640 degrees Celsius or more and 750 degrees Celsius or less. ,
The epitaxial semiconductor region has a main surface inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride semiconductor,
The well layer is made of In _X Ga _1-X N (indium composition X: 0 <X <1, X is a strain composition),
The active layer is provided to generate an emission spectrum having a peak wavelength in a wavelength region of 480 nm or more and 550 nm or less,
When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 710 degrees Celsius, the upper limit of the growth rate V _G is the following formula (1)
V _G = α1 × T _W + β1 (1)
Equation (1) satisfies (growth temperature T _W , growth rate V _G ) = (710 degrees Celsius, 13.9 nm / min), (640 degrees Celsius, 5.5 nm / min),
When the growth temperature _{T W} is the temperature below 710 degrees 750 degrees centigrade, the upper limit of the growth rate _{V G} is less than or equal 13.9 nm / min,
When the growth temperature _{T W} is the temperature of less than 690 degrees 640 degrees centigrade, the lower limit of the growth rate _{V G} is at 5.5 nm / min or more,
Wherein when the growth temperature _{T W} is the temperature below 750 degrees 690 degrees centigrade, the lower limit of the growth rate _{V G,} the following equation (2)
V _G = α2 × T _W + β2 (2)
Equation (2) satisfies (growth temperature T _W , growth rate V _G ) = (640 degrees Celsius, 13.9 nm / min), (690 degrees Celsius, 5.5 nm / min), A method characterized by that. Wherein the epitaxial semiconductor region, in the above growth temperature T _W growth temperature T _B of the well layer, further comprising a step of growing the barrier layer of the quantum well structure,
The barrier layer is made of In _Y Ga _1-Y N (indium composition Y: 0 ≦ Y ≦ 0.05, Y is a strain composition),
The method of claim 1, wherein the difference between the growth temperature T _W of the well layer and the growth temperature T _B of the barrier layer is less than 230 degrees 60 degrees, and wherein. A step of growing a second conductivity type gallium nitride based semiconductor layer on the active layer;
The growth temperature T _W of the well layer is lower than the growth temperature T2 of the second conductivity type gallium nitride based semiconductor layer,
The difference between the growth temperature T2 of the growth temperature T _W and the second conductive type gallium nitride-based semiconductor layer of the well layer, according to claim 1 or claim, characterized or less 510 degrees 140 degrees, that 2. The method described in 2. A step of growing another second conductivity type gallium nitride based semiconductor layer on the second conductivity type gallium nitride based semiconductor layer;
The second conductivity type gallium nitride based semiconductor layer includes an electron blocking layer,
4. The method according to claim 3, wherein a growth rate of the second second conductivity type gallium nitride based semiconductor layer is larger than growth rates of the well layer and the barrier layer. 5. The indium composition X in the In _X Ga _1-X N of the well layer is greater than 0.15 and less than 0.4, and is described in any one of claims 1 to 4. Method.   6. The method according to claim 1, wherein a direction of inclination of the main surface of the epitaxial semiconductor region is a direction of an a-axis of the gallium nitride based semiconductor. A step of preparing a substrate made of a hexagonal semiconductor In _S Al _T Ga _1- STN (0 ≦ S ≦ 1, 0 ≦ T ≦ 1, 0 ≦ S + T ≦ 1),
The main surface of the substrate is inclined at an angle in a range of 10 degrees to 45 degrees from a plane orthogonal to the c-axis of the hexagonal semiconductor. The method as described in any one. Prior to the film formation, the substrate further includes a step of performing a heat treatment on the main surface of the substrate to form a modified main surface on the substrate,
The method according to claim 7, wherein the heat treatment is performed in an atmosphere of a gas containing ammonia and hydrogen. A step of epitaxially growing a first conductivity type gallium nitride based semiconductor region on the substrate after the heat treatment;
The main surface of the first conductivity type gallium nitride based semiconductor region is inclined at an angle in the range of 10 degrees to 45 degrees from the c-plane of the gallium nitride based semiconductor. Item 9. The method according to Item 8.   10. The method according to claim 6, wherein the direction of the inclination and the direction of the m-axis of the gallium nitride based semiconductor are in the range of 89 degrees or more and 91 degrees or less. . The substrate includes a plurality of first regions in which threading dislocation density extending in the c-axis direction is larger than the first threading dislocation density, and a plurality of threading dislocation densities extending in the c-axis direction are smaller than the first threading dislocation density. A second region,
The first and second regions are arranged alternately,
The method according to any one of claims 7 to 10, wherein the first and second regions appear on the main surface of the substrate. The method of claim 11, wherein the threading dislocation density in the second region is less than 1 × 10 ⁷ cm ⁻² .   The method according to any one of claims 1 to 12, further comprising the step of performing m-plane cleavage to produce a resonator surface. After the growth of the well layer, prior to growing the barrier layer, while changing the temperature at the growth temperature T _B from the growth temperature T _W, further comprising the step of growing a gallium nitride-based semiconductor layer, that 14. A method as claimed in any one of claims 1 to 13, characterized in that   The method according to claim 14, wherein the thickness of the gallium nitride based semiconductor layer is smaller than the thickness of the barrier layer.   The method according to claim 14 or 15, wherein a growth rate in the growth of the gallium nitride based semiconductor layer is smaller than a growth rate in the growth of the barrier layer. The first conductivity type gallium nitride based semiconductor region, the active layer, and the second conductivity type gallium nitride based semiconductor layer are arranged in a direction of a normal line of the main surface of the substrate,
The method according to any one of claims 7 to 12, wherein the direction of the c-axis of the hexagonal semiconductor is different from the direction of the normal of the main surface of the substrate. A method for producing an epitaxial wafer for a nitride-based semiconductor light-emitting device, comprising:
Epitaxially growing a first conductivity type gallium nitride based semiconductor region on a substrate;
Forming an epitaxial semiconductor region made of a gallium nitride based semiconductor on the first conductivity type gallium nitride based semiconductor region;
Growing a well layer for an active layer on the epitaxial semiconductor region at a growth temperature T _W and a growth rate V _G (nm / min) within a temperature range of 640 degrees Celsius or more and 750 degrees Celsius or less;
On the well layer, with the higher than the growth temperature T _W growth temperature T _B of the well layer, and a step of growing a barrier layer for the active layer,
And growing a second conductivity type gallium nitride based semiconductor layer on the active layer,
The epitaxial semiconductor region has a main surface inclined at an angle in a range of greater than 10 degrees and 45 degrees or less from the c-plane of the gallium nitride based semiconductor,
The well layer is made of In _X Ga _1-X N (indium composition X: 0 <X <1, X is a strain composition),
The active layer is provided to generate an emission spectrum having a peak wavelength in a wavelength region of 480 nm or more and 550 nm or less,
When the growth temperature _TW is a temperature of 640 degrees Celsius or more and less than 710 degrees Celsius, the upper limit of the growth rate V _G is the following formula (1)
V _G = α1 × T _W + β1 (1)
Equation (1) satisfies (growth temperature T _W , growth rate V _G ) = (710 degrees Celsius, 13.9 nm / min), (640 degrees Celsius, 5.5 nm / min),
When the growth temperature _{T W} is the temperature below 710 degrees 750 degrees centigrade, the upper limit of the growth rate _{V G} is less than or equal 13.9 nm / min,
When the growth temperature _{T W} is the temperature of less than 690 degrees 640 degrees centigrade, the lower limit of the growth rate _{V G} is at 5.5 nm / min or more,
Wherein when the growth temperature _{T W} is the temperature below 750 degrees 690 degrees centigrade, the lower limit of the growth rate _{V G,} the following equation (2)
V _G = α2 × T _W + β2 (2)
Equation (2) satisfies (growth temperature T _W , growth rate V _G ) = (640 degrees Celsius, 13.9 nm / min), (690 degrees Celsius, 5.5 nm / min), A method characterized by that. The substrate is made of a hexagonal semiconductor In _S Al _T Ga _1- STN (0 ≦ S ≦ 1, 0 ≦ T ≦ 1, 0 ≦ S + T ≦ 1),
The method according to claim 18, wherein the main surface of the substrate is inclined at an angle in a range of 10 degrees to 45 degrees from a plane orthogonal to the c-axis of the hexagonal semiconductor. .   The method according to claim 18, further comprising a step of performing a heat treatment on the main surface of the substrate in an atmosphere of a gas containing ammonia and hydrogen prior to the film formation.

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