JP2010055276A - Method and apparatus for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus for designing a semiconductor integrated circuit that prevent consideration toward variation from becoming excessive. <P>SOLUTION: The method for designing using the apparatus for designing a semiconductor integrated circuit is disclosed. The method includes: a recognition procedure in which the apparatus recognizes the number of via holes connected in series between a plurality of wiring layers that the semiconductor integrated circuit has, based on information about the parasitic resistance of the semiconductor integrated circuit; a referring procedure in which the apparatus refers to a table where a correction value for correcting the resistance value of via holes is associated with each number of via holes; and a correction procedure in which the apparatus corrects the resistance value of the via holes based on the correction value in the table referred to in the referring procedure. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design method and design apparatus for designing a semiconductor integrated circuit.

  In a semiconductor integrated circuit, a logic design is performed by a CAD (Computer Aided Design) system or the like, and then a layout design is performed based on a net list indicating connection information of logic elements. When a layout is determined by layout design, various verifications are performed as to whether the layout satisfies a design rule indicating a design standard, and whether a device having the layout operates normally.

  Usually, such verification is performed in consideration of variations due to parasitic resistance and parasitic capacitance generated in the manufacturing process of the semiconductor integrated circuit. The parasitic resistance includes a resistance of a via that connects a plurality of wiring layers.

In recent years, variation has increased with the miniaturization of semiconductor integrated circuits, and therefore relaxation of variation has been considered by a technique using statistics or the like. As an example of this technique, the condition that the resistance value per via is the minimum value within the range satisfying the design rule, and the condition that the resistance value per via is the maximum value within the range satisfying the design rule are as follows: There is a method of performing timing verification by applying.
JP-A-5-82647

  However, in the above-described conventional technique, timing verification is performed under a condition in which the maximum width of each via that can be taken for each via is taken into consideration, so that the consideration for the variation becomes excessive.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit design method and design apparatus in which consideration for variation is not excessive.

  In order to solve the above-described problem, a design method using a semiconductor integrated circuit design apparatus, wherein the design apparatus is connected in series between a plurality of wiring layers of the semiconductor integrated circuit based on information on parasitic resistance of the semiconductor integrated circuit. A recognition procedure for recognizing the number of connected vias, a reference procedure for referring to a table in which a correction value for correcting the resistance value of the via for each number of vias is associated, and a correction value of the table referred to in the reference procedure And a correction procedure for correcting the resistance value of the via, and a configuration for executing the correction procedure.

  A program for causing a computer to execute the above procedure as a function, and a computer-readable storage medium storing the program can also be used.

  It is possible to prevent excessive consideration of variation.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  In the present embodiment, attention is paid to the fact that the variation in the resistance of the via is related to the number of vias connected in series. FIG. 1 is a diagram illustrating the relationship between the number of connected vias and variations in via resistance. In the design apparatus of this embodiment, application of the relationship shown in FIG. 1 to timing verification prevents excessive consideration (margin) for variations.

  FIG. 2 is a diagram illustrating a functional configuration example of the design apparatus according to the present embodiment. 2, the design apparatus 100 includes a correction control unit 110, a wired design reading unit 120, an RC file extraction unit 130, a correction table reading unit 140, a correction processing unit 150, an RC file output unit 160, a timing verification unit 170, data A storage unit 310 is included.

  First, the data storage unit 310 will be described. The data storage unit 310 stores a wired design 320 and a variation correction table 330. The wired design 320 is wiring information indicating a wiring for connecting an electronic circuit included in the semiconductor integrated circuit. In addition, the wired design 320 includes layout data including arrangement information of electronic circuits included in the semiconductor integrated circuit, a net list indicating connection between the electronic circuits, and the like.

  The variation correction table 330 is a table created in advance based on the relationship between the number of connected vias and the variation in via resistance (see FIG. 1). Details of the variation correction table 330 will be described later.

  Next, each part which the design apparatus 100 of this embodiment has is demonstrated.

  The verification control unit 110 controls execution of correction of the via resistance value by the design apparatus 100. The wired design reading unit 120 reads the wired design 320 stored in the data storage unit 310. The RC file extraction unit 130 extracts RC data from the wired design 320. RC data is data indicating the parasitic resistance and parasitic capacitance related to the wiring of the wired design 320.

  The correction table reading unit 140 reads the variation correction table 330. The correction processing unit 150 corrects the via resistance value using a correction value corresponding to the number of vias included in the wired design 320 based on the variation correction table 330 read by the correction table reading unit 140. Details of the correction will be described later.

  The RC file output unit 160 outputs the RC data extracted by the RC file extraction unit 130 as an RC file 341 in SPEF format, and stores it in the data storage unit 310. The RC file output unit 160 outputs the corrected RC file reflecting the correction by the correction processing unit 150 as the corrected RC file 350 in the SPEF format, and stores it in the data storage unit 310. The timing verification unit 170 performs timing verification using the corrected RC file 350.

  FIG. 3 is a diagram illustrating a hardware configuration of the design apparatus. 3, the design apparatus 100 includes a central processing unit (hereinafter referred to as CPU) 210, a memory 220, a storage device 230, a display device 240, an input device 250, and a drive device 260 via a bus B. Connected and configured.

  The CPU 210 executes a program using the memory 220 and executes a design process of the semiconductor integrated circuit. The memory 220 stores programs and data necessary for providing various processes. The memory 220 typically includes cache memory, system memory, and display memory.

  The display device 240 is used for displaying a layout display, a parameter input screen, and the like. The display device 240 is realized by, for example, a CRT (Cathode Ray Tube) display, an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), or the like. The input device 250 is used for requests and instructions from a user, input of parameters, and the like. The input device 250 is realized by, for example, a keyboard or a mouse.

  The storage device 230 includes a magnetic disk device, an optical disk device, and a magneto-optical disk device.

  In response to an instruction from the input device 250 or the like, the CPU 210 transfers a program and data to the memory 220, and the CPU 210 executes it. Program data executed by the CPU 210 is provided in the storage medium 270. The drive device 260 drives the storage medium 270 to access the stored contents. The CPU 210 reads program data from the storage medium 270 via the drive device 260 and installs it in the storage device 230.

  As the storage medium 270, any computer-readable storage medium such as a magnetic tape, a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM, etc.), a magneto-optical disk (MO, MD, etc.) can be used. it can. As the storage medium 270, a semiconductor memory, an externally connected hard disk device, or the like may be used. The above-described program data can be stored in the storage medium 270 and loaded into the memory 220 for use as necessary.

  The storage medium 270 includes a storage device such as a medium storing program data uploaded or downloaded via a communication medium, a disk device, and a server device to which the design apparatus 100 is connected via a communication medium. Furthermore, the storage medium 270 is not only a storage medium that stores a program that can be directly executed by a computer, but also a storage medium that stores a program that can be executed once installed on another storage medium (such as a hard disk). In addition, a storage medium storing an encrypted or compressed program is also included.

  Next, programs and data stored in the storage device 230 will be described. The storage device 230 according to the present embodiment includes a program storage unit 300 that stores programs and a data storage unit 310 that stores data.

  FIG. 4 is a diagram illustrating a program storage unit in the storage device. The program storage unit 300 includes a correction control program 310 that functions as the correction control unit 110, a wired design reading program 320 that functions as the wired design reading unit 120, an RC file extraction program 330 that functions as the RC file extraction unit 130, a correction Correction table reading program 340 that functions as the table reading unit 140, correction processing program 350 that functions as the correction processing unit 150, RC file output program 360 that functions as the RC file output unit 160, and timing verification program 370 that functions as the timing verification unit 170 Is remembered.

  FIG. 5 is a diagram illustrating a data storage unit in the storage device. A data storage unit 310 in the storage device stores a wired design 320 and a variation correction table 330. The variation correction table 330 of the present embodiment includes a best side variation correction table 331 and a worst side variation correction table 332.

  The best-side variation correction table 331 is a table used when correcting the resistance value of the via under the condition that the delay time is the shortest in the allowable delay time when performing the timing verification of the semiconductor integrated circuit. The worst-side variation correction table 332 is a table used when correcting the resistance value of the via under the condition that the delay time becomes the longest in the allowable delay time when performing the timing verification of the semiconductor integrated circuit.

  The data storage unit 310 is provided with a work area 340. The work area 340 temporarily stores calculation results and the like when various programs stored in the program storage unit 300 are executed. The work area 340 includes, for example, an RC file 341 output by the RC file output unit 160, a structure 342 used when the correction processing program 350 stored in the program storage unit 300 is executed, and the RC file output unit 160. The corrected RC file 350 output by is stored. The members of the structure 342 are an index 343, a via name 344, a resistance value 345 before correction, and a resistance value 346 after correction. Details of the structure 342 will be described later.

  Details of the variation correction table 330 stored in the data storage unit 310 will be described below with reference to FIGS. 6 and 7.

  FIG. 6 is a diagram for explaining a first example of the variation correction table. In the example shown in FIG. 6, the number of vias connected in series is associated with a correction value for correcting the resistance value of the via.

  In the present embodiment, vias connected in series are vias included in a connection path in which one input terminal is connected to one output terminal.

  In the example of FIG. 6, the correction value for one via is 1.00, the correction value for two vias is 0.80, the correction value for three vias is 0.75, and so on. The number of vias and the correction value corresponding to the number are shown.

  FIG. 7 is a diagram for explaining a second example of the variation correction table. In the example shown in FIG. 7, the correction values corresponding to the number of vias connected in series and the wiring layers connected by the vias are shown.

  A variation correction table 330B shown in FIG. 7A is a table created from the relationship between the number of vias and variations in the second and third layers among a plurality of wiring layers of the semiconductor integrated circuit. In the variation correction table 330B, the number of vias connected in series is associated with a correction value for correcting the via resistance. In the variation correction table 330B, the correction value when there is one via is 1.00, the correction value when there are two vias is 0.80, and the correction value when there are three vias is , 0.75, and the number of vias and the correction value are stored.

  The variation correction table 330C shown in FIG. 7B is a table created from the relationship between the number of vias and variations in the third and fourth layers among the plurality of wiring layers of the semiconductor integrated circuit. In the variation correction table 330C, the number of vias connected in series is associated with a correction value for correcting the via resistance. In the variation correction table 330C, the correction value when there is one via is 1.00, the correction value when there are two vias is 0.75, and the correction value when there are three vias is , 0.70, and the number of vias and the correction value are stored.

  The best-side variation correction table 331 and the worst-side variation correction table 332 included in the variation correction table 330 of the present embodiment include tables as shown in FIGS.

  FIG. 8 is a diagram for explaining a processing flow executed under the control of the correction control unit.

  In FIG. 8, the correction control unit 110 reads the wired design 320 from the data storage unit 310 by the wired design reading unit 120 (step S801). The correction control unit 110 uses the RC file extraction unit 130 to extract RC data from the wired design 320 (step S802). The RC file output unit 160 outputs the extracted RC data as the RC file 341 and temporarily stores it in the work area 340 of the data storage unit 310 (step S803). Details of the RC file 341 will be described later.

  The correction control unit 110 uses the correction table reading unit 140 and the correction processing unit 150 to correct the RC file 341 using the best side variation correction table 331 (step S804). Details of the correction processing will be described later.

  When the correction processing is completed, the correction control unit 110 outputs a corrected RC file 350A that is a corrected RC file by the RC file output unit 160 (step S805). The corrected RC file 350A is temporarily stored in the work area 340. The correction control unit 110 uses the timing verification unit 170 to perform timing verification using the corrected RC file 350A (step S806), and ends the process.

  In addition, the correction control unit 110 performs correction processing of the RC file 341 using the worst-side variation correction table 332 by the correction table reading unit 140 and the correction processing unit 150 (step S807). When the correction process is completed, the correction control unit 110 outputs a corrected RC file 350B that is a corrected RC file by the RC file output unit 160 (step S808). The corrected RC file 350B is temporarily stored in the work area 340. The correction control unit 110 causes the timing verification unit 170 to perform timing verification using the corrected RC file 350B (step S809), and ends the process.

  The RC file 341 will be described below. FIG. 9 is a diagram for explaining an example of the RC file.

  The RC file 341 is output in the SPEF format. The example of FIG. 9 shows a connection path that connects the output terminal 50 and the input terminal 51. When the RC file extraction unit 130 extracts RC data, the RC file extraction unit 130 assigns an index 343 for specifying each parasitic resistance element using the wiring and via serving as the parasitic resistance between the output terminal 50 and the input terminal 51 as the parasitic resistance element. To do. The RC file extraction unit 130 identifies a via based on the wired design 320, and assigns a via name 344 as a comment C to the parasitic resistance element identified as the via as via identification information. A parasitic resistance element to which no comment is given indicates a parasitic resistance of the wiring.

  In the RC file 341 shown in FIG. 9, vias connecting via the second and third layers (via name V = V23) and vias connecting the third and fourth layers of the wiring layers, depending on the number of comments C. It can be seen that a total of four vias are connected in series, two each (via name V = V34). The resistance value 345 before correction of each via is 10Ω.

  The corrected RC file 350 corrected by the correction processing unit 150 will be described below with reference to FIGS.

  FIG. 10 is a diagram for explaining a first example of the corrected RC file. A corrected RC file 350 shown in FIG. 10 is an example in which the RC file 341 is corrected using the variation correction table 330A shown in FIG. In this example, since there are four vias, the correction processing unit 150 acquires a correction value when the number of vias is four in the variation correction table 330A. A value obtained by multiplying the acquired correction value by 10Ω which is the resistance value 345 before correction of the via is set as a resistance value 346 after correction. In the example of FIG. 10, the corrected resistance value of the via is 7Ω.

  FIG. 11 is a diagram for explaining a second example of the corrected RC file. A corrected RC file 350 shown in FIG. 11 is an example in which correction is performed using the variation correction tables 330B and 330C shown in FIG.

  In the example of FIG. 11, the correction processing unit 150 acquires a correction value of 0.70 corresponding to the number of vias from the via variation correction table 330B connecting the second layer and the third layer. Further, the correction processing unit 150 acquires a correction value 0.65 corresponding to the number of vias from the via variation correction table 330C connecting the third layer and the fourth layer.

  The correction processing unit 150 sets a value obtained by multiplying a square average of two acquired correction values (correction coefficient) by 10Ω, which is a resistance value 345 before the via correction, as a resistance value 346 after the via correction.

In the example of FIG. 11, the correction coefficient multiplied by the resistance value 345 before correction is
Correction coefficient = sqrt ((0.70 × 0.70 × 2 + 0.65 × 0.65 × 2) / 4) = 0.67546
It becomes. Therefore, the corrected resistance value is 6.7546Ω. In the example of FIG. 11, the corrected resistance value is 6.755Ω by rounding off the fourth decimal place.

  As described above, according to the present embodiment, variations are taken into account based on the actual connection structure. For this reason, timing verification based on realistic variation can be performed, and consideration for variation can be prevented from being excessive.

  The processing flow executed under the control of the correction control unit 110 of the present embodiment may be executed as follows. FIG. 12 is a diagram for explaining a first modification of the processing flow executed under the control of the correction control unit.

  In the processing flow shown in FIG. 12, the correction process is performed using the RC data extracted by the RC file extraction unit 130, and the RC file 341 is not output. The processes in steps S1201 and S1202 in FIG. 12 are the same as the processes in steps S801 and S802 in FIG.

  The correction control unit 110 reads the best-side variation correction table 331 by the correction table reading unit 140, and the correction processing unit 150 corrects the via resistance value based on the best-side variation correction table 331 and the extracted RC data. Is performed (step S1203). The processing in step S1204 and step S1205 is the same as the processing in step S805 and step S806 in FIG.

  The correction control unit 110 reads the worst-side variation correction table 331 by the correction table reading unit 140, and the correction processing unit 150 calculates the via resistance value based on the worst-side variation correction table 331 and the extracted RC data. Correction processing is performed (step S1206). The processing in steps S1207 and S1208 is the same as the processing in steps S808 and S809 in FIG.

  FIG. 13 is a diagram for explaining a second modification of the processing flow executed under the control of the correction control unit.

  In the example of FIG. 13, the correction process is performed during the timing verification process. The processing from step S1301 to step S1303 in FIG. 13 is the same as the processing from step S801 to step S803 in FIG.

  The correction control unit 110 starts timing verification on the best side by the timing verification unit 170 using the RC file 341 output in step S1303 (step S1304). When the timing verification is started, the correction table reading unit 140 reads the best side variation correction table 331, and the correction processing unit 150 performs correction processing based on the best side variation correction table 331 and the RC file 341 (step S1305). The timing verification unit 170 performs timing verification based on the corrected RC data, and ends the process (step S1306).

  Further, the correction control unit 110 starts the worst-side timing verification by the timing verification unit 170 using the RC file 341 output in step S1303 (step S1307). When the timing verification is started, the correction table reading unit 140 reads the worst side variation correction table 332, and the correction processing unit 150 performs correction processing based on the worst side variation correction table 332 and the RC file 341 (step S1308). The timing verification unit 170 performs timing verification based on the corrected RC data, and ends the process (step S1309).

  Also in the examples shown in FIGS. 12 and 13, the variation is considered based on the actual connection structure. For this reason, timing verification based on realistic variation can be performed, and consideration for variation can be prevented from being excessive.

  In the above description, an example in which a plurality of vias are connected in series, that is, an example in which there is no branch in the connection path from the output terminal to the input terminal is described. Hereinafter, an example in which there is a branch in the connection path from the output terminal to the input terminal will be described. The case where there is a branch in the connection path is a case where a plurality of input terminals are connected to one output terminal.

  FIG. 14 is a diagram showing an RC file when there is a branch in the connection path. In the RC file 341A shown in FIG. 14, an index 343 is assigned to each parasitic resistance element, and a pre-correction resistance value 345 for each parasitic resistance element is associated. In addition, a via name 344 is given as a comment C as via identification information to an element determined as a via in the parasitic resistance element.

  According to the RC file 341A, the output terminal A and the input terminal are connected by a connection path H1 including vias V1, V2, V3, and V12. The output terminal A and the input terminal E are connected by a connection path H2 branched from the connection path H1 by a via V3, and the connection path H2 includes vias V4 to V11. The output terminal A and the input terminal C are connected by a connection path H3 branched from the connection path H2 by a via V7, and the connection path H3 includes a via V13 and a via V14. Vias included in the RC file 341A are thus identified for each connection path.

  FIG. 15 is a diagram for explaining the branching of the connection path. FIG. 15 shows a connection path corresponding to the RC file 341A. The output terminal A is connected to the input terminals B to E. The output terminal A is connected to the input terminal B by a connection path H1 including the vias V1 to V3 and the via V12 branched from the via V3. The output terminal A is connected to the input terminal E by a connection path H2 including vias V4 to V11 branched from the via V3.

  The output terminal A is connected to the input terminal C by a connection path H3 including a via V13 and a via V14 branched from the via V7. The output terminal A is connected to the input terminal D by a connection path H4 including vias V15 to V18 branched from the via V13. The connection path H4 is not shown in FIG.

  Details of the correction processing of this embodiment will be described below. FIG. 16 is a diagram for explaining a correction processing flow by the correction processing unit. In FIG. 16, the correction process of the RC file 341A described in FIG. 14 will be described.

  When the RC file 341A is output, the correction control unit 110 causes the correction processing unit 150 to initialize the structure 342 stored in the work area 340 (step S1601). The correction processing unit 150 acquires the index 343 to which the comment C is added from the RC file 341A as the initialization of the structure 342, inputs the via name 344 and the resistance value 345 before correction for each acquired index 343, and corrects the correction. The initial value 0 is input to the rear resistance value 346.

  The correction processing unit 150 creates a list of vias (via list) that passes from the output terminal A to the input terminals B to E based on the RC file 341A (step S1602). FIG. 17 is a diagram illustrating an example of a via list. In the via list L illustrated in FIG. 17, a connection path indicated by an output terminal and an input terminal connected to each other, the number of vias that pass through the connection path, and a list of vias that pass through the connection path are associated with each other. For example, in the case of a connection path from the output terminal A to the input terminal B, the number of vias that are routed is four, and the via list that is routed is vias V1, V2, V3, and V12. The same applies hereinafter.

  Returning to FIG. 16, the correction processing unit 150 sorts the via list L in order from the smallest via number (step S1603). In the via list L shown in FIG. 17, the smallest number of vias is a connection path for connecting the output terminal A and the input terminal B, and the second smallest number of vias is the connection between the output terminal A and the input terminal C. It becomes a connection route to.

  The correction processing unit 150 reads the variation correction table 330 by the correction table reading unit 140 (step S1604). The correction table reading unit 140 reads the best-side variation correction table 331 when performing the best-side correction, and reads the worst-side variation correction table 332 when performing the worst-side correction.

  The correction processing unit 150 determines whether or not the processing in step S1606 described later has been completed for all connection paths listed in the via list L (step S1605).

  The correction processing unit 150 sets the corrected resistance value 346 corresponding to each via name using the structure 342 (step S1606). The correction processing unit 150 refers to the structure 342 from the via name 344 of the via list corresponding to the connection path of the via list L. If the corrected resistance value 346 is the initial value of 0, the correction processing unit 150 applies the matching correction value from the variation correction table 330. The correction value to be acquired is acquired, the resistance value is corrected, and the result is set to the corrected resistance value 346.

  For example, when the process of step S1606 is executed for the connection path from the output terminal A to the input terminal B, the corrected resistance values 346 of the vias V1 to V3 and V12 are calculated and set. The calculation of the corrected resistance value 346 is as described above.

  Next, the process of step S1606 is performed on the connection path from the output terminal A to the input terminal C. In this case, the corrected resistance value 346 is set for the vias V1 to V3 in the previous process, and the corrected resistance value 346 for the vias other than the vias V1 to V3 is 0 as an initial value. Therefore, the correction processing unit 150 calculates and sets the corrected resistance values 346 of the vias V4 to V7, V13, and V14 whose initial values are 0. The same applies hereinafter.

  In step S1605, when the process of step S1606 is completed for all the connection paths listed in the list L, the correction processing unit 150 corrects the resistance value 345 before correction of the RC file 341A set in the structure 342. The post resistance value 346 is replaced (step S1607). For example, for the via V <b> 3, the pre-correction resistance value of 10Ω at the index 6 portion is replaced with the post-correction resistance value 346 set in the structure 342.

  The correction processing by the correction processing unit 150 ends here. When the correction process ends, the RC file output unit 160 outputs the RC file 341A after the replacement of the resistance value as a corrected RC file 350 and stores it in the work area 340 (step S1608). When the corrected RC file 350 is output, the timing verification unit 170 reads the corrected RC file 350 from the work area 340, performs timing verification (step S1609), and ends the process.

  In the case of a connection path in which vias are connected in series, there is one connection path listed in the via list L created in step S1602. Therefore, the resistance value 345 before correction can be rewritten to the resistance value 346 after correction by executing the process of step S1606 once.

In the embodiment of the present invention, the following configurations described below are conceivable.
(Appendix 1)
A design method using a semiconductor integrated circuit design apparatus,
The design device is
A recognition procedure for recognizing the number of vias connected in series between a plurality of wiring layers of the semiconductor integrated circuit based on information on the parasitic resistance of the semiconductor integrated circuit;
A reference procedure for referring to a table in which correction values for correcting the resistance value of vias are associated with each via number;
A correction procedure for correcting the resistance value of the via based on the correction value of the table referred to by the reference procedure, and a design method to be executed.
(Appendix 2)
When multiple input terminals are connected to one output terminal,
The recognition procedure recognizes the number of vias included in each path from the output terminal to the plurality of input terminals,
The design method according to claim 1, wherein the correction procedure includes correcting the resistance value of the via based on the correction table from a path having the smallest number of recognized vias.
(Appendix 3)
The recognition procedure is:
The design method according to appendix 1 or 2, wherein via identification information is given to a recognized via.
(Appendix 4)
The correction procedure is as follows:
The design method according to supplementary note 3, wherein a list in which the route, the number of vias for each route, and via identification information for each route are associated with each other is generated for each route.
(Appendix 5)
An output procedure for outputting information indicating the resistance value of the via after correction,
5. The design method according to claim 1, wherein a verification procedure for performing timing verification of the semiconductor integrated circuit based on information indicating the resistance value of the via after the correction is performed.
(Appendix 6)
The design method according to attachment 5, wherein the correction procedure is executed as one procedure of the verification procedure.
(Appendix 7)
A device for designing a semiconductor integrated circuit,
Recognizing means for recognizing the number of vias connected in series between a plurality of wiring layers of the semiconductor integrated circuit based on information on the parasitic resistance of the semiconductor integrated circuit;
Reference means for referring to a table in which a correction value for correcting the resistance value of the via is associated with each via number;
And a correction unit that corrects the resistance value of the via based on the correction value of the table referred to by the reference unit.

  The embodiments of the present invention are not limited to the specifically disclosed examples, and various modifications and changes can be made without departing from the scope of the claims.

It is a figure which shows the relationship between the number of connected vias, and the dispersion | variation in via resistance. It is a figure which shows the function structural example of the design apparatus which concerns on this embodiment. It is a figure which shows the hardware constitutions of a design apparatus. It is a figure explaining the program memory | storage part in a memory | storage device. It is a figure explaining the data storage part in a memory | storage device. It is a figure for demonstrating the 1st example of a dispersion | variation correction table. It is a figure for demonstrating the 2nd example of a dispersion | variation correction table. It is a figure for demonstrating the processing flow performed by control of a correction | amendment control part. It is a figure for demonstrating an example of RC file. It is a figure for demonstrating the 1st example of the corrected RC file. It is a figure for demonstrating the 2nd example of the corrected RC file. It is a figure for demonstrating the 1st modification of the processing flow performed by control of a correction control part. It is a figure for demonstrating the 2nd modification of the processing flow performed by control of a correction control part. It is a figure which shows RC file in case a connection path has a branch. It is a figure explaining the branch of a connection path | route. It is a figure for demonstrating the correction processing flow by a correction process part. It is a figure which shows the example of the list | wrist of via | veer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Design apparatus 110 Correction | amendment control part 120 Wired design reading part 130 RC file extraction part 140 Correction table reading part 150 Correction processing part 160 RC file output part 170 Timing verification part 230 Storage device 300 Program storage part 310 Data storage part 320 Wired Design 330 Variation correction table 340 Work area 341 RC file 342 Structure 350 Corrected file

Claims (5)

A design method using a semiconductor integrated circuit design apparatus,
The design device is
A recognition procedure for recognizing the number of vias connected in series between a plurality of wiring layers of the semiconductor integrated circuit based on information on the parasitic resistance of the semiconductor integrated circuit;
A reference procedure for referring to a table in which correction values for correcting the resistance value of vias are associated with each via number;
A correction procedure for correcting the resistance value of the via based on the correction value of the table referred to in the reference procedure, and a design method to be executed. When multiple input terminals are connected to one output terminal,
The recognition procedure recognizes the number of vias included in each path from the output terminal to the plurality of input terminals,
The design method according to claim 1, wherein the correction procedure corrects the resistance value of the via based on the correction table from a path having the smallest number of recognized vias. An output procedure for outputting information indicating the resistance value of the via after correction,
The design method according to claim 1, wherein a verification procedure for performing timing verification of the semiconductor integrated circuit based on information indicating the corrected resistance value of the via is performed.   The design method according to claim 3, wherein the correction procedure is executed as one procedure of the verification procedure. A device for designing a semiconductor integrated circuit,
Recognizing means for recognizing the number of vias connected in series between a plurality of wiring layers of the semiconductor integrated circuit based on information on the parasitic resistance of the semiconductor integrated circuit;
Reference means for referring to a table in which a correction value for correcting the resistance value of the via is associated with each via number;
And a correction unit that corrects the resistance value of the via based on the correction value of the table referred to by the reference unit.

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