JP2010054662A - Display panel module, drive pulse generating device, method of driving pixel array part, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for handling both of two-dimensional images and three-dimensional images. <P>SOLUTION: A display panel module includes: (a) a writing control line drive part for controlling writing for sub-pixels of potential appearing on signal lines based on a first scan clock; (b) a power source supply control part for controlling supply timing of a drive power source regulating an emission period of a spontaneous emission element based on a second scan clock of a high speed rather than the first scan clock in the power source supply control part for controlling supply and stop of the drive power source for the sub-pixels; (c) a lighting period length setting part for setting lighting period length achieving peak brightness levels set successively in a range where display periods are not overlapped between adjacent frames; and (d) a drive timing generation part for generating the second scan clock of a clock speed achieving the set lighting period length and supplying the generated second scan clock to the power source supply control part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The invention described in this specification relates to a driving technique of a pixel circuit that drives a current-driven self-luminous element. The invention proposed in this specification has a display panel module, a driving pulse generation device, a pixel array driving method, and an electronic device on which the display panel module is mounted.

  To date, display panel modules have become popular as display devices for images taken from a single viewpoint (hereinafter referred to as “two-dimensional images”). However, recently, development of a display device that can display an image captured using binocular parallax (hereinafter referred to as a “three-dimensional image”) and allow a user to perceive it as a three-dimensional image has progressed. It has been. However, the existing content amount is overwhelmingly large for two-dimensional images.

For this reason, it is considered that a mechanism capable of displaying both a two-dimensional image and a three-dimensional image is required for future display panel modules.
FIG. 1 shows a construction example of an image system that can display both a two-dimensional image and a three-dimensional image. This image system 1 is a configuration suitable for use when it is desired to display a two-dimensional image and a three-dimensional image with the same screen size.

  The image system 1 includes an image player 3, a display device 5, an infrared light emitting unit 7, and glasses 9 with a liquid crystal shutter. Among these, the image player 3 is a video device equipped with a playback function for both a two-dimensional image and a three-dimensional image, and includes a set-top box and a computer in addition to a so-called image playback device. The display device 5 is an output device for input image data, and includes a monitor in addition to a so-called television receiver.

  The infrared light emitting unit 7 is a device that notifies the display timing of the left-eye image and the right-eye image or the display switching timing when the three-dimensional image is displayed. FIG. 1 shows an example in which the display device 5 is arranged near the center of the upper frame portion. The glasses 9 with a liquid crystal shutter are one of the accessories required to be worn by the user when displaying a three-dimensional image. Of course, when displaying a two-dimensional image, it is not necessary to attach the glasses 9 with a liquid crystal shutter to the user.

  FIG. 2 shows an operation image of the glasses 9 with a liquid crystal shutter. In the drawing, a picture displayed with a white outline represents that the liquid crystal shutter is in an open state, that is, a state in which external light can be transmitted. In addition, a picture displayed in a shaded area represents that the liquid crystal shutter is in a closed state, that is, a state in which external light is not transmitted.

  As shown in FIG. 2, during the display of the three-dimensional image, the two liquid crystal shutters are not simultaneously opened, and only one of them is controlled to be opened in conjunction with the switching of the display image. Specifically, only the left-eye liquid crystal shutter is controlled to be open while the left-eye image is being displayed, and only the right-eye liquid crystal shutter is controlled to be open while the right-eye image is being displayed. In the image system 1, a stereoscopic image can be visually recognized by the complementary opening / closing operation of the liquid crystal shutter.

FIG. 3 shows an equivalent circuit of the electronic circuit portion of the glasses 9 with a liquid crystal shutter. The glasses 9 with a liquid crystal shutter include a battery 11, an infrared light receiving unit 13, a shutter driving unit 15, and liquid crystal shutters 17 and 19.
The battery 11 is a lightweight and small battery such as a button battery. The infrared light receiving unit 13 is an electronic component that is attached to, for example, a front surface portion of glasses and receives infrared light on which display image switching information is superimposed.

The shutter drive unit 15 is an electronic component that controls switching between opening and closing of the liquid crystal shutter 17 for the right eye and the liquid crystal shutter 19 for the left eye so as to synchronize with the display image based on the received switching information.
JP 2007-286623 A

Patent Document 1 discloses an image system in which a driving circuit for displaying a two-dimensional image and a driving circuit for displaying a three-dimensional image are mounted, and the driving circuit used for driving the display panel is switched according to switching of the display image. ing.
FIG. 4 shows a driving method disclosed in Patent Document 1. Note that FIG. 4 shows the relationship between the driving periods focusing on a certain horizontal line.

However, FIG. 4 shows an operation relationship in the case where a two-dimensional image and a three-dimensional image taken at 60 frames / second are displayed on the display panel. Incidentally, it is assumed that the display panel is driven and controlled by an active matrix driving method.
FIG. 4A shows the processing timing of two-dimensional image data focusing on a certain horizontal line. As shown in FIG. 4A, when a two-dimensional image is input, processing operations from writing to lighting of the frame image F are executed within 1/60 [second].

  FIG. 4B shows the processing timing of 3D image data focusing on a certain horizontal line. A period indicated by white is a processing period for the left-eye image L or the right-eye image R, and a period indicated by black painting is a black screen processing period. As shown in FIG. 4B, when a three-dimensional image is input, processing operation from writing to lighting of the left eye image L and processing operation from writing to lighting of the black screen in units of 1/240 [seconds]. Then, the processing operation from writing to lighting of the right-eye image R and the processing operation from writing to lighting of the black screen are executed.

  Here, the reason for inserting the black screen processing period between the left eye image L and the right eye image R is to prevent the left and right images on the screen from being simultaneously displayed and mixed. It is. FIG. 5 shows the operating principle. FIG. 5 shows the relationship between the processing timing of each horizontal line and the display state visually recognized by the user. Also in the case of FIG. 5, the white portion represents the processing period (mainly considered as the lighting period) of the image L for the left eye or the image R for the right eye, and the blacking period is the processing period (mainly the black screen). It is considered a lighting period.)

  As shown in FIG. 5, since the black screen insertion period exists, the display (lighting) start timing of the right eye image R in the horizontal line of the first row is changed to the left eye image L in the horizontal line of the last row. It can be delayed until after the display (lighting) ends. The switching period of the open / close state of the liquid crystal shutter is from the end of the display (lighting) of the left-eye image L on the last horizontal line to the start of the display (lighting) of the right-eye image R on the first horizontal line. Devoted to

  Thus, Patent Document 1 discloses a driving technique for displaying a three-dimensional image. However, in the case of this driving method, it is necessary to drive the display panel at a speed (240 Hz) that is four times the frame rate (60 Hz) that is visually recognized. This means that it is necessary to employ extremely high performance parts for the pixel array section and its drive circuit, which causes an increase in manufacturing cost.

  Further, as shown in FIG. 5, the black screen display period is required as much as the three-dimensional image display period. For this reason, in the case of the prior art in which a black screen is inserted, there is a problem that the screen brightness inevitably decreases.

  In addition, as in the driving method shown in Patent Document 1, in the method of switching the driving method between when displaying a two-dimensional image and when displaying a three-dimensional image, there is a functional configuration that detects a difference in image format and switches the driving method. I need it. Furthermore, the driving method shown in the cited document 1 requires both a two-dimensional image driving circuit and a three-dimensional image driving circuit. Therefore, in addition to the increase in the number of parts, there is a problem that the circuit layout becomes complicated.

Therefore, the inventors
(A) a pixel array unit in which sub-pixels configured by current-driven self-light-emitting elements and pixel circuits that drive and control the self-light-emitting elements are arranged in a matrix;
(B) a signal line driver for driving the signal lines;
(C) a write control line drive unit that controls writing of potentials appearing on the signal lines to the sub-pixels based on a first scan clock;
(D) a power supply control unit that controls supply and stop of the drive power to the sub-pixel, wherein the drive power supply timing that defines the lighting period of the self-light-emitting element in a line-sequential manner is the first scan clock; A power supply control unit that controls based on a second scan clock faster than the second scan clock;
(E) a peak luminance level setting unit that sequentially sets an optimum peak luminance level for input image data;
(F) a lighting period length setting unit that sets a lighting period length that achieves a sequentially set peak luminance level within a range in which display periods do not overlap between adjacent frames;
(G) a drive timing generator that generates the second scan clock at a clock speed that realizes the set lighting period length, and supplies the generated second scan clock to the power supply controller; ) Is proposed.

  In addition, the signal line drive unit, the write control line drive unit, and the power supply control unit in the display panel module described above have a common drive timing regardless of whether a two-dimensional image or a three-dimensional image is displayed on the screen. It is desirable to work with.

  Further, in the display panel module described above, the waiting time from the completion of writing of the signal potential to the start of lighting in each horizontal line is set so that the first horizontal line that completes the writing of the signal potential first is the longest, The second horizontal line that is lastly written with the signal potential is set to be the shortest, and for each horizontal line located between the first and second horizontal lines, the first and second horizontal lines are set. It is desirable that the waiting time length be set linearly according to the positional relationship with the horizontal line.

Note that the period of the first scan clock is desirably set to coincide with the horizontal scanning period.
In addition, the inventors set a peak luminance level setting unit that sequentially sets an optimum peak luminance level for input image data, and a lighting period length that realizes the sequentially set peak luminance level as a display period between adjacent frames. A lighting period length setting unit that is set within a non-overlapping range and a second scan clock having a clock speed that realizes the set lighting period length are generated, and the generated second scan clock is supplied to the power supply control unit. A drive pulse generator having a drive timing generator is proposed.

  In addition, the inventors propose a method of driving the pixel array unit based on the driving conditions described above. In addition, the inventors propose an electronic device equipped with the above-described display panel module. The electronic device here includes a display panel module, a system control unit that controls the operation of the entire system, and an operation input unit that receives an operation input to the system control unit.

  In the case of the invention proposed by the inventors, the second scan clock for controlling the lighting operation is set to be faster than the first scan clock for controlling the writing operation of the signal line potential to the sub-pixel. Due to this difference in clock speed, the display period length from the start of lighting of the horizontal line of the first row to the start of lighting of the horizontal line of the last row can be shortened.

  This means that if the lighting period length of each horizontal line is the same as that of the conventional technique, the display period length from the start of lighting of the first line to the end of lighting of the last line can be shortened as compared with the conventional technique. Accordingly, the degree of freedom of arrangement of the display periods of the frame images is increased, and the display periods of the preceding and succeeding frames can be separated from each other without inserting a black screen as in the prior art.

As a result, a self-luminous display panel module that can display not only a two-dimensional image but also a three-dimensional image at a common drive timing can be realized.
In addition, in the case of the present invention, the start timing and period length of the lighting period can be set so that an optimum peak luminance level is obtained for the input image data. As a result, the display quality of the three-dimensional image can be optimized according to the image content.

Hereinafter, the case where the invention is applied to an active matrix driving type organic EL panel module will be described.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification. Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Appearance Configuration In this specification, the display panel module is used in two meanings. One is a display panel module in which a pixel array unit and a driving circuit (for example, a signal line driving unit, a writing control line driving unit, a power control line driving unit, etc.) are formed on a substrate using a semiconductor process. The other is a display panel module in which a drive circuit manufactured as an application specific IC is mounted on a substrate on which a pixel array portion is formed.

FIG. 6 shows an external configuration example of the organic EL panel module. The organic EL panel module 21 has a structure in which the counter substrate 25 is bonded to the formation region of the pixel array portion of the support substrate 23.
The support substrate 23 is made of glass, plastic or other base material. The counter substrate 25 is also made of glass, plastic or other transparent member as a base material.

The counter substrate 25 is a member that seals the surface of the support substrate 23 with a sealing material interposed therebetween.
Note that the transparency of the substrate only needs to be ensured only on the light emission side, and the other substrate side may be an impermeable substrate. In addition, the organic EL panel module 21 is provided with an FPC (flexible printed circuit) 27 for inputting external signals and driving power.

(B) Form 1
(B-1) System Configuration FIG. 7 shows a system configuration example of the organic EL panel module 31 according to this embodiment.
The organic EL panel module 31 shown in FIG. 7 includes a pixel array unit 33, a signal line drive unit 35 that is a drive circuit thereof, a write control line drive unit 37, a power supply control line drive unit 39, and a timing generator 41. . Among these, the power control line drive unit 39 corresponds to a “power supply control unit” in the claims.

(A) Pixel Array Unit In the case of this embodiment, one pixel constituting the white unit is arranged in the pixel array unit 33 with a prescribed resolution in the vertical direction and the horizontal direction in the screen. FIG. 8 shows an arrangement structure of the sub-pixels 51 constituting the white unit. As shown in FIG. 8, the white unit is configured as an aggregate of R (red) pixels 51, G (green) pixels 51, and B (blue) pixels 51.

When the vertical resolution of the pixel array unit 33 is M and the horizontal resolution is N, the total number of subpixels of the pixel array unit 33 is given by M × N × 3.
FIG. 9 shows a connection relationship between the sub-pixel 51 which is the minimum unit of the pixel structure constituting the pixel array unit 33 and its drive circuit unit.

  In the case of this embodiment, as shown in FIG. 9, the sub-pixel 51 includes N-channel thin film transistors N1, N2, and N3, a storage capacitor Cs that holds gradation information, and an organic EL element OLED. . Incidentally, the thin film transistor N1 is a switch element that controls writing of a potential appearing on the signal line DTL (hereinafter referred to as “signal line potential”). Hereinafter, the thin film transistor N1 is referred to as a sampling transistor N1.

The thin film transistor N2 is a switch element that supplies a driving current having a magnitude corresponding to the potential held in the holding capacitor Cs to the organic EL element OLED. Hereinafter, the thin film transistor N2 is referred to as a drive transistor N2.
The thin film transistor N3 is a switch element that controls supply and stop of supply of the drive voltage VDD to one main electrode of the drive transistor N2. Hereinafter, the thin film transistor N3 is referred to as a power supply control transistor N3.

(B) Configuration of Signal Line Drive Unit The signal line drive unit 35 is a circuit device that drives the signal line DTL. The individual signal lines DTL are wired so as to extend in the vertical direction (Y direction) of the screen, and 3 × N are arranged in the horizontal direction (X direction) of the screen. In the case of this embodiment, the signal line driving unit 35 drives the signal line DTL with three values of the characteristic correction potential Vofs_L, the initialization potential Vofs_H, and the signal potential Vsig.

The characteristic correction potential Vofs_L is a potential corresponding to the black level of the pixel gradation, for example. The characteristic correction potential Vofs_L is used for an operation (hereinafter referred to as “threshold correction operation”) for correcting variation in the threshold voltage Vth of the drive transistor N2.
The initialization potential Vofs_H is a potential for canceling the holding voltage of the holding capacitor Cs. The operation for canceling the holding voltage of the holding capacitor Cs in this way is hereinafter referred to as an initialization operation.

Incidentally, the initialization potential Vofs_H is set to a potential higher than the maximum value that the signal potential Vsig corresponding to the pixel gradation can take. This makes it possible to cancel the holding voltage no matter what potential the signal potential Vsig of the previous frame period is given.
Further, the control line drive unit 35 in this embodiment operates at the same drive timing when displaying a two-dimensional image and when displaying a three-dimensional image.

FIG. 10 shows an internal configuration example of the signal line driving unit 35. The signal line drive unit 35 includes a shift register 61, a latch unit 63, a digital / analog conversion unit 65, a buffer circuit 67, and a selector 69.
The shift register 61 is a circuit device that provides the capture timing of the pixel data Din based on the clock signal CK. In the case of this embodiment, the shift register 61 is configured with 3 × N delay stages corresponding to at least the number of signal lines DTL. Therefore, the clock signal CK having 3 × N pulses within one horizontal scanning period is used.

The latch unit 63 is a storage circuit that captures the pixel data Din into a corresponding storage area based on the timing signal output from the shift register 61.
The digital / analog conversion circuit 65 is a circuit device that converts the pixel data Din fetched by the latch unit 63 into an analog signal voltage Vsig. The conversion characteristics of the digital / analog conversion circuit 65 are defined by the H level reference potential Vref_H and the L level reference potential Vref_L.

The buffer circuit 67 is a circuit device that converts a signal amplitude to a signal level suitable for panel driving.
The selector 69 is a circuit device that selectively outputs any one of the signal potential Vsig corresponding to the pixel gradation, the threshold correction potential Vofs_L, and the initialization potential Vofs_H within one horizontal scanning period. FIG. 11 shows an example of signal line potential output by the selector 69. In the case of this embodiment, the selector 69 outputs in the order of initialization potential Vofs_H → threshold correction potential Vofs_L → signal potential Vsig.

(C) Configuration of Write Control Line Drive Unit The write control line drive unit 37 is a drive device that controls line-sequential writing of signal line potentials to the sub-pixels 51 through the write control line WSL. The write control lines WSL are wired so as to extend in the horizontal direction (X direction) of the screen, and M lines are arranged in the vertical direction (Y direction) of the screen.

  The control line drive unit 37 is a circuit device that designates execution timings of an initialization operation, a threshold correction operation, a signal potential write operation, and a mobility correction operation in units of horizontal lines. The control line drive unit 37 in this embodiment also operates at the same drive timing when displaying a two-dimensional image and when displaying a three-dimensional image.

  FIG. 12 shows a circuit configuration example of the control line drive unit 37. The control line driver 37 is formed by a set shift register 71, a reset shift register 73, a logic gate 75, and a buffer circuit 77.

  The set shift register 71 includes M delay stages corresponding to the vertical resolution. The set shift register 71 operates based on the first shift clock CK1 synchronized with the horizontal scanning clock, and transfers the set pulse to the next delay stage every time the first shift clock CK1 is input. The first shift clock CK1 here corresponds to the “first scan clock” in the claims. The transfer start timing is given by the start pulse st1.

  The reset shift register 73 is also composed of M delay stages corresponding to the vertical resolution. Similarly, the reset shift register 73 operates based on the first shift clock CK1 synchronized with the horizontal scanning clock, and transfers the reset pulse to the next delay stage every time the first shift clock CK1 is input. . The transfer start timing is given by the start pulse st2.

  The logic gate 75 is a circuit device that generates a pulse signal having a pulse width from a set pulse input to a reset pulse input. The logic gates 75 are arranged by the number of write control lines WSL. When it is necessary to provide a plurality of write timings within one horizontal scanning period, a logical product of a pulse waveform that provides a plurality of write timings and a pulse signal defined by a set pulse and a reset pulse. What is necessary is just to obtain a waveform. In this case, the set pulse and the reset pulse serve to specify a horizontal line that outputs a plurality of write timings.

  The buffer circuit 77 is a circuit device that converts a logic level control pulse into a drive level control pulse. The buffer circuit 77 is required to be capable of simultaneously driving N subpixels connected to the write control line WSL.

(D) Configuration of Power Supply Control Line Drive Unit The power supply control line drive unit 39 is a drive device that controls supply and stop of supply of the drive power supply VDD to the sub-pixels 51 through the power supply control line DSL. The power supply control lines DSL are wired so as to extend in the horizontal direction (X direction) of the screen, and M lines are arranged in the vertical direction (Y direction) of the screen.

  The power supply control line drive unit 39 operates to supply the drive power supply VDD during the threshold correction operation and the mobility correction operation execution period in the non-light emission period. This control operation is executed in synchronization with the write control operation of the write control line drive unit 37. Therefore, the operation of the power supply control line driving unit 39 in the non-light emitting period is executed based on the first shift clock CK1 synchronized with the horizontal scanning clock.

  Further, the power supply control line drive unit 39 operates so as to supply the drive power supply VDD only during a period during which the organic EL element OLED is controlled to be turned on in the light emission period. In the case of this embodiment, the control operation during the light emission period by the power control line drive unit 39 is executed at a scan speed higher than the scan speed during the non-light emission period. That is, it is executed using the second shift clock CK2 that is faster than the first shift clock CK. The second shift clock CK2 here corresponds to a “second scan clock” in the claims.

  In this way, increasing the scan speed of the control pulse during the light emission period compresses the length of the period from the start of lighting (display start) at the upper end of the screen to the end of lighting (display end) at the lower end of the screen compared to the conventional method. It is to do. Note that as the ratio of the second shift clock CK2 to the first shift clock CK1 is increased, the spread of the light emission period between the upper and lower sides in the screen can be compressed.

In the case of this embodiment, the second shift clock CK2 is set to 2.77 times the first shift clock CK1 (one horizontal scanning clock).
The power control line drive unit 39 in this embodiment also operates at the same drive timing when displaying a two-dimensional image and when displaying a three-dimensional image.

  FIG. 13 shows a circuit configuration example of the power supply control line drive unit 39. The power control line driver 39 includes a circuit stage for a non-light emission period, a circuit stage for a light emission period, a circuit stage for selectively outputting control pulses for each period, and a logic level control pulse at a drive level. And a circuit stage for converting it into a control pulse.

Among these, the circuit portion for the non-light emission period is formed by a set shift register 81, a reset shift register 83, and a logic gate 85.
The set shift register 81 is configured by M delay stages corresponding to the vertical resolution. The set shift register 81 operates based on the first shift clock CK1 synchronized with the horizontal scanning clock, and transfers the set pulse to the next delay stage each time the first shift clock CK1 is input. The transfer start timing is given by the start pulse st11.

  The reset shift register 83 is also composed of M delay stages corresponding to the vertical resolution. Similarly, the reset shift register 83 operates based on the first shift clock CK1 synchronized with the horizontal scanning clock, and transfers the reset pulse to the next delay stage each time the first shift clock CK1 is input. . The transfer start timing is given by the start pulse st12.

The logic gate 85 is a circuit device that generates a pulse signal having a pulse width from a set pulse input to a reset pulse input. The logic gates 85 are arranged by the number of power supply control lines DSL.
If it is desired to set the edge of the pulse signal during one horizontal scanning period, the logical product waveform of the pulse waveform that gives the timing of the edge and the pulse signal generated by the set pulse and the reset pulse can be obtained. good.

Similarly, the circuit portion for the light emission period is formed by a set shift register 91, a reset shift register 93, and a logic gate 95.
The set shift register 91 is configured by M delay stages corresponding to the vertical resolution. The set shift register 91 operates based on the second shift clock CK2 that is faster than the horizontal scanning clock, and transfers the set pulse to the next delay stage each time the second shift clock CK2 is input. The transfer start timing is given by the start pulse st13.

  The reset shift register 93 is also composed of M delay stages corresponding to the vertical resolution. Similarly, the reset shift register 93 operates based on the second shift clock CK2 that is faster than the horizontal scanning clock, and transfers the reset pulse to the next delay stage each time the second shift clock CK2 is input. To do. The transfer start timing is given by the start pulse st14.

The logic gate 95 is a circuit device that generates a pulse signal having a pulse width from a set pulse input to a reset pulse input. As many logic gates 95 as the number of power supply control lines DSL are arranged.
If it is desired to set the edge of the pulse signal during one horizontal scanning period, the logical product waveform of the pulse waveform that gives the timing of the edge and the pulse signal generated by the set pulse and the reset pulse can be obtained. good.

  The switch circuit 101 executes switching of the pulse signals from the circuit portions provided for these two processing periods. The switch circuit 101 selects the pulse signal input from the logic gate 85 during the non-light emission period, and selects the pulse signal input from the logic gate 95 during the light emission period. Note that the switching of the selection of the pulse signal is realized by a switching signal (not shown). However, the pulse signal of the logic gate 95 can also be used as the switching signal.

  In other words, a technique is used in which the logic level of the logic gate 95 is switched. Of course, when the pulse signal input from the logic gate 95 is switched to the H level, the pulse signal is selected. When the pulse signal is switched to the L level, the pulse signal input from the logic gate 85 is selected.

  A buffer circuit 103 is disposed following the switch circuit 101. The buffer circuit 103 is a circuit device that performs level conversion of a logic level power supply control signal into a drive level power supply control signal. The buffer circuit 103 is required to be capable of simultaneously driving N subpixels connected to the power supply control line DSL.

(E) Configuration of Timing Generator 41 The timing generator 41 is a circuit device that generates a timing control signal and a clock necessary for driving the organic EL panel module 31. For example, a clock signal CK, a first shift clock CK1, a second shift clock CK2, start pulses st1, st2, st11, st12, st13, st14, etc. are generated.

(B-2) Driving Operation (a) Outline of Display Schedule Hereinafter, the display schedule of the organic EL panel module 31 according to this embodiment will be described. In the case of this embodiment, it is assumed that the organic EL panel module 31 is given an image stream of 60 frames / second. That is, it is assumed that an image stream for 2D images and an image stream for 3D images are captured or generated at 60 frames / second.

  FIG. 14 shows an image stream display schedule assumed in this embodiment. As shown in FIG. 14, in the case of this embodiment, a driving method for displaying at 120 frames / second is adopted regardless of the type of input image stream. That is, a driving method for displaying two frames in 1/60 [second] is adopted.

  FIG. 14A shows a display schedule for a two-dimensional image. In the case of a two-dimensional image, frame images having the same image content are displayed in the first half period and the second half period of the display period given in 1/60 [second] units. That is, the frame image is displayed twice, such as F1-> F1-> F2-> F2-> F3-> F3-> F4-> F4. Of course, an image obtained by compensating motion of the input image may be inserted in the latter half of the display period. By inserting a motion compensated image, the display quality of the moving image can be improved. This display corresponds to a so-called double speed display technology.

  FIG. 14B shows a display schedule for a three-dimensional image. In the case of a three-dimensional image, the left eye image L is displayed in the first half period of the display period given in 1/60 [second] units, and the right eye image R is displayed in the second half period. That is, the left eye image and the right eye image are alternately displayed as L 1 → R 1 → L 2 → R 2 → L 3 → R 3 → L 4 → R 4.

(B) Overview of Drive Timing FIGS. 15 and 16 show the relationship between the drive signal waveform focused on the sub-pixel 51 on a certain horizontal line constituting the pixel array section 33 and the potential change of the drive transistor N2. 15 corresponds to the operation of the horizontal line located in the first row, and FIG. 16 corresponds to the operation of the horizontal line located in the last row. As will be described later, the difference between the two operations is a difference in the lengths of the waiting times T1 and TM until the lighting period that appears after the end of the non-light emitting period.

Here, FIG. 15A and FIG. 16A are drive waveforms of the write control line WSL corresponding to the subpixel 51 of interest.
FIG. 15B and FIG. 16B show driving waveforms of the signal line DTL. FIGS. 15C and 16C show driving waveforms of the corresponding power supply control line DSL. FIGS. 15D and 16D show waveforms of the gate potential Vg of the drive transistor N2. FIGS. 15E and 16E show waveforms of the source potential Vs of the drive transistor N2.

As shown in FIGS. 15 and 16, the driving operation of the organic EL panel module 31 can be divided into a driving operation during the non-light emitting period and a driving operation during the light emitting period.
In the non-light emitting period, an initialization operation, a writing operation of the signal potential Vsig to the sub-pixel 51, and an operation (threshold correction operation and mobility correction operation) for correcting the characteristic variation of the drive transistor N2 are executed.

  In the light emission period, based on the signal potential Vsig written in the non-light emission period, an operation for turning on the organic EL element OLED and an operation for temporarily stopping the light emission (that is, a turn-off operation) are performed. In the case of this embodiment, the timing and period length at which the turn-off operation is performed are set to be different for each horizontal line. This is because it is necessary to absorb the difference between the scan speed of the pulse signal that gives the lighting period and the scan speed of the control pulse that gives the control timing of the non-light emission period. Note that the “non-light emitting period” and the “light-out period” in this specification are terms used for convenience of explanation of the operation, and the difference is that the organic EL element OLED is controlled to be in the light-off state during any period. There is no. The same applies to each description to be described later.

  FIG. 17 shows the relationship between the waiting time provided for this speed adjustment and the horizontal line. Note that FIG. 17 shows the case where the number of horizontal lines is “5” so that the correspondence is clear. Incidentally, FIG. 17A shows the input timing of the left-eye image L and the right-eye image R. FIG. 17B shows the correspondence between the input image data and the horizontal line. The positions of the broken lines correspond to the horizontal lines 1-5.

  FIG. 17C shows the relationship between waiting times T1 to T5 from the end of the non-light emission period corresponding to each horizontal line to the start of lighting. As can be seen from the figure, the waiting time T1 of the horizontal line 1 where the lighting period starts first is the longest, and the waiting time T5 of the horizontal line 5 where the lighting period starts last is the minimum (including zero). ) Note that waiting times T2, T3, and T4 obtained by equally dividing the difference between T1 and T5 are assigned to the horizontal lines 2, 3, and 4.

  The reason why the waiting time T can be freely determined is that the lighting start timing and the lighting period length in the organic EL panel module can be freely set by controlling the power supply control line DSL.

  FIG. 17D shows the display timing of the image L for the left eye and the image R for the right eye. As shown in the figure, the display periods of the left eye image L and the right eye image R do not overlap. In addition, there is a free time between the display periods. Therefore, if the opening and closing of the liquid crystal shutter is switched during this idle time, only the necessary images can be input to the left and right eyes.

  FIG. 18 shows a specific numerical example of the relationship of the drive timing described above. FIG. 18A is a waveform diagram of a vertical synchronization pulse giving one frame period. In the case of this embodiment, the vertical synchronization pulse is given to display 120 frames per second. Therefore, in this embodiment, the period length (data length of one frame) from the vertical synchronization pulse to the vertical synchronization pulse is given by 8.33 ms. In the following description, “one frame data length” is also referred to as “frame data length”.

  FIG. 18B shows an image stream. In the drawing, the left-eye image L1 and the right-eye image R1 constituting the first frame, and a part of the left-eye image L2 constituting the second frame are shown. As shown in the figure, each frame image is input between a vertical synchronization pulse and a vertical synchronization pulse.

  FIG. 18C is a diagram illustrating a scan operation of a control pulse for driving the write control line WSL. As shown in the figure, the control pulse is driven in a line-sequential manner based on the first shift clock CK1. In this embodiment, a horizontal scanning clock is used as the first shift clock CK1.

  FIG. 18D is a diagram for explaining the arrangement relationship between the non-light emission period of each horizontal line, and the lighting period and the light extinction period during the light emission period. In the figure, a section indicated by white is a non-light emitting period. Also, in the figure, the filled section is the extinguishing period. On the other hand, the shaded shaded period is the lighting period. As shown in the figure, the extinguishing period is arranged before and after the lighting period. Among these, the length of the extinguishing period provided in front of the lighting period is the above-described waiting time T.

  As shown in FIG. 18, the waiting time T of each horizontal line has the longest waiting time T1 of the horizontal line 1 that is the first row, and the shortest waiting time TM of the horizontal line M that is the last row. On the contrary, in the light-off period provided behind the light-on period, the light-out period of the horizontal line 1 as the first row is the shortest and the light-out period of the horizontal line M as the last row is the longest. The reason for arranging the extinguishing period before and after the lighting period is to make the lighting period length of each horizontal line the same length. That is, this is to prevent a luminance difference from occurring between horizontal lines.

  In the case of FIG. 18D, the scanning speed during the lighting period (that is, the second shift clock CK2) is 2.77 times the first shift clock CK1. This relationship can also be seen from the fact that the slope of the thick dashed arrow indicating the slope of the lighting period is steeper than the slope of the boundary line of the non-light emitting period shown in white. This relationship exhibits the effect of compressing the frame image display period (the period from the start of lighting of the first row to the end of lighting of the last row). In the case of this embodiment, the lighting period length of each horizontal line is 46% of the data period of one frame, which is 3.832 ms.

  In addition, a switching period of 1.5 ms is ensured between the display period of the left eye image L1 and the display period of the right eye image R1. Note that this switching period only needs to be secured for the time required for the opening / closing control of the liquid crystal shutter. Therefore, as long as the necessary minimum time is secured, the length of the lighting period and the scan speed (second shift clock CK2) can be freely adjusted.

(C) Details of Drive Operation Hereinafter, the drive state in the sub-pixel will be described in detail. The drive timing and the change in the potential state of the drive transistor N2 will be described with reference to FIGS.

(C-1) Lighting Operation within Light-Emission Period FIG. 19 shows an operation state within the sub-pixel during the light-emission period. At this time, the write control line WSL is at the L level, and the sampling transistor N1 is controlled to be turned off. For this reason, the gate electrode of the drive transistor N2 is controlled in a floating state.

  On the other hand, the power control line DSL is at the H level, and the power supply control transistor N3 is controlled to be on. As a result, the drive transistor N2 is controlled to operate in the saturation region. That is, the driving transistor N2 operates as a constant current source that supplies a driving current corresponding to the voltage held in the holding capacitor Cs to the organic EL element OLED. Thus, the organic EL element OLED emits light with a luminance corresponding to the pixel gradation. This operation is executed for all the sub-pixels 51 during the light emission period.

(C-2) Turn-off operation within the non-light emission period When the light emission period ends, the non-light emission period starts. In the non-light emitting period, first, an operation of turning off the organic EL element OLED is executed.
FIG. 20 shows an operation state in the sub-pixel during the light-off operation. In the turn-off operation, the power supply control line DSL is switched to the L level, and the power supply control transistor N3 is turned off. Note that the off state of the sampling transistor N1 is maintained.

  By this operation, the supply of the drive current to the organic EL element OLED is stopped. Accordingly, the organic EL element OLED which is a current driving element is turned off. At the same time, the voltage between both electrodes of the organic EL element OLED also decreases to the threshold voltage Vth (oled). As a result, the source potential Vs of the drive transistor N2 is lowered to a potential obtained by adding the threshold voltage Vth (oled) to the cathode potential Vcat. As the source potential decreases, the gate potential Vg of the drive transistor N2 also decreases. Note that the gradation information of the previous frame is still held in the holding capacitor Cs at this time.

(C-3) Initialization Operation within Non-Light Emission Period Next, an initialization operation for initializing gradation information of the previous frame is executed.
FIG. 21 shows an operation state in the sub-pixel during the initialization operation. When the initialization timing arrives, the write control line WSL is controlled to the H level, and the sampling transistor N1 is turned on. In addition, the initialization potential Vofs_H is applied to the signal line DTL in synchronization with the ON operation of the sampling transistor N1. As a result, the initialization potential Vofs_H is written into the gate potential Vg of the driving transistor N2 (FIGS. 15D and 16D).

  As the gate potential Vg rises, the source potential Vs of the drive transistor N2 also rises (FIGS. 15E and 16E). That is, the source potential Vs becomes higher than the potential obtained by adding the threshold voltage Vth (oled) to the cathode potential Vcat. Thereby, the organic EL element OLED is turned on. However, since the power supply control transistor N3 remains in the off state, the organic EL element OLED operates so as to extract charges from the source electrode of the drive transistor N2. Eventually, the source potential Vs of the drive transistor N2 transitions again to Vcat + Vth (oled).

As a result, the voltage (that is, the initialization voltage) given by the difference between “Vofs_H” and “Vcat + Vth (oled)” is written in the storage capacitor Cs. This operation is an initialization operation.
In this initialization process, as described above, the organic EL element OLED can emit light for a moment. However, even if light is emitted, the luminance is low and the light emission period is very short. There is no impact on

When the initialization voltage is written to the storage capacitor Cs, the potential of the signal line DTL is changed to the initialization potential Vofs_H.
To the threshold correction potential Vofs_L. FIG. 22 shows an operation state in the sub-pixel at this time. At this time, the sampling transistor N1 remains on-controlled. As a result, the gate potential Vg of the drive transistor N2 is pushed down from the initialization potential Vofs_H to the threshold correction potential Vofs_L (FIGS. 15D and 16D).

  In conjunction with the potential change of the gate potential Vg, the source potential Vs of the drive transistor N2 is also pushed down (FIGS. 15E and 16E). This is because the initialization voltage is held in the holding capacitor Cs. However, at the time of this depression, the holding voltage of the holding capacitor Cs is slightly compressed from the initialization voltage. Note that the holding voltage of the holding capacitor Cs at the end of initialization is held at a voltage sufficiently higher than the threshold voltage Vth of the driving transistor N2. With the above operation, the preparation for correcting the variation in the threshold voltage Vth of the drive transistor N2 is completed.

(C-4) Threshold correction operation within non-light emission period Next, a threshold correction operation is started. FIG. 23 shows an operation state in the sub-pixel during the threshold correction operation. The threshold value correction operation is started when the power supply control line DSL is controlled to H level and the power supply control transistor N3 is turned on.
At this start time, the gate-source voltage Vgs of the drive transistor N2 is wider than the threshold voltage Vth even if the variation is taken into consideration. Therefore, the drive transistor N2 is also turned on with the on control of the power supply control transistor N3.

Along with this, current starts to flow through the drive transistor N2 so as to charge the storage capacitor Cs and the capacitance component parasitic on the organic EL element OLED.
With this charging operation, the source potential Vs of the driving transistor N2 gradually increases. Note that the gate potential Vg of the drive transistor N2 is fixed to the threshold correction potential Vofs_L. Therefore, while the power supply control transistor N3 is on-controlled, the gate-source voltage Vgs of the drive transistor N2 is gradually reduced from the initialization voltage (FIGS. 15D, 15E, and 16D). , (E)).

Eventually, when the gate-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth, the drive transistor N2 automatically performs a cutoff operation. FIG. 24 shows an operation state in the sub-pixel when the driving transistor N2 is automatically cut off. At this time, writing of the threshold correction potential Vofs_L to the gate electrode of the driving transistor N2 is continued. The source potential Vs of the driving transistor N2 is Vofs_L
-Vth. Thereby, the threshold value correcting operation is completed.

“Vofs_L−Vth” is determined to be lower than “Vcat + Vth (oled)”. Accordingly, even at this time, the organic EL element OLED remains off.
When the threshold correction operation is completed, the sampling transistor N1 and the power supply control transistor N3 are simultaneously turned off as shown in FIG. At this time, both the drive transistor N2 and the organic EL element OLED are in the off state.
Here, if the influence of the off-state current is ignored, the gate potential Vg and the source Vs of the drive transistor N2 continue to hold the potential state at the time when the threshold correction operation is completed.

(C-5) Signal Potential Write Operation within Non-Light-Emitting Period Next, the signal potential Vsig write operation is started. FIG. 26 shows an operation state in the sub-pixel when the write operation of the signal potential Vsig is executed. In the case of this embodiment, this operation is started by turning on the sampling transistor N1 while the power supply control transistor N3 is turned off.

Note that the potential of the signal line DTL is switched to the signal potential Vsig before the sampling transistor N1 is switched on (FIGS. 15A to 15C and FIGS. 16A to 16C).
With the start of this operation, the gate potential Vg of the drive transistor N2 rises to the signal potential Vsig (FIGS. 15D and 16D). That is, the signal potential Vsig is written in the storage capacitor Cs. However, as the gate potential Vg increases, the source potential Vs of the driving transistor N2 also slightly increases (FIGS. 15E and 16E).

  When the signal potential Vsig is thus written, the gate-source voltage Vgs of the drive transistor N2 is larger than the threshold voltage Vth and switched to the on state. However, since the power supply control transistor N3 is in an off state, the drive transistor N2 does not pass a drive current. Therefore, the light-off state of the organic EL element OLED is continued.

(C-6) Mobility operation within non-light-emission period When the writing of the signal potential Vsig is completed, an operation for correcting the variation in mobility μ of the drive transistor N2 is started. FIG. 27 shows an operation state in the sub-pixel during this operation. This operation is started by turning on the power supply control transistor N3.

  As the power supply control transistor N3 is turned on, a drive current having a magnitude corresponding to the gate-source voltage Vgs starts to flow through the drive transistor N2. This drive current flows so as to charge the storage capacitor Cs and the parasitic capacitance of the organic EL element OLED. That is, the source potential Vs of the drive transistor N2 increases. The organic EL element OLED remains off until the source potential Vs exceeds the threshold voltage Vth (oled) of the organic EL element OLED.

  By the way, the driving current flowing during the mobility correction period has a characteristic that the driving transistor N2 having a higher mobility μ is larger and the driving transistor N2 having a lower mobility μ is smaller even if the gate-source voltage Vgs is the same. As a result, the gate-source voltage Vgs decreases as the driving transistor N2 has a higher mobility μ.

  As a result of this correction operation, if the driving gradation N2 has the same pixel gradation, the driving current having the same magnitude is supplied to the organic EL element OLED regardless of the difference in mobility μ. That is, if the pixel gradation is the same, the light emission luminance of the sub-pixel 51 is corrected to be the same regardless of the difference in mobility μ.

  Incidentally, in FIGS. 15A and 16A, the waveform of the control pulse of the write control line WSL used when the mobility μ is corrected is changed nonlinearly. This is to prevent the correction amount from being excessive or insufficient due to the difference in the pixel gradation.

  When the power supply control transistor N3 is kept on even after the mobility correction operation is completed, the source potential Vs of the drive transistor N2 rises to exceed the threshold voltage Vth (oled) of the organic EL element OLED, and the organic EL element OLED lighting is started.

  However, in the case of this embodiment, the scan speed of the control pulse that gives the lighting period is set to be higher than the scan speed of the control pulse that gives the drive timing in the non-light emission period. Therefore, it is necessary to delay the lighting start time by the waiting time T determined for each horizontal line.

Therefore, in the case of this embodiment, the power supply control transistor N3 is turned off until the waiting time T for the corresponding horizontal line elapses (FIGS. 15C and 16C).
Note that FIG. 16 shows a driving waveform of the horizontal line corresponding to the last row (Mth), and since the waiting time TM is set to zero, the lighting period starts immediately from the mobility correction state.

(C-7) Waiting time operation within the light emission period As described above, when all the operations in the non-light emission period are completed, the operation of the light emission period is started. As described above, when the non-light emission period ends, all the processes necessary for lighting the organic EL element OLED have been completed. However, as described above, the clock speed of the second shift clock CK2 used in the light emission period is faster than that of the first shift clock CK1 used in the non-light emission period.

Therefore, as shown in FIG. 18, it is necessary to increase the waiting time T until the organic EL element OLED is turned on as the horizontal line is closer to the first row.
FIG. 28 shows the operation state in the sub-pixel during this waiting time T. As shown in FIG. 28, the power supply control transistor N3 is controlled to be in the OFF state for the waiting time T determined for each horizontal line. Of course, during the waiting time, the display of the horizontal line is black.

(C-8) Lighting operation within light emission period When the waiting time T set for each horizontal line has elapsed, as shown in FIG. 29, the power supply control transistor N3 is switched on, and the organic EL element OLDE is turned on. Be started.

(B-3) Summary As described above, when the driving method according to the embodiment is adopted, the driving frequency necessary for displaying the three-dimensional image can be reduced to half that of the conventional technique. Specifically, a three-dimensional image captured or generated at 60 frames / second can be displayed on the screen at 120 frames / second.

  In this manner, the operation margin of the pixel array unit 33 can be increased by reducing the drive frequency. For this reason, the manufacturing cost of the pixel array part 33 can be reduced. In addition, since the drive frequency is reduced, the operation speed of the timing generator and the drive circuit (for example, shift register) can be reduced. From these viewpoints, the manufacturing cost of the organic EL panel module can be reduced.

  In the case of this embodiment, there is no need to prepare a two-dimensional image driving circuit and a three-dimensional image driving circuit separately. That is, in the case of the driving method according to the embodiment, it is not necessary to distinguish between the two-dimensional image and the three-dimensional image, and these images can be displayed at a single driving timing. For this reason, the layout area of the drive circuit can be made smaller than that of the conventional example. In the case of this embodiment, a circuit for determining the type of image is not necessary. From these viewpoints, it is possible to contribute to cost reduction of the organic EL panel module.

  In the case of this embodiment, it is not necessary to write a full black screen for each frame. Therefore, the lighting period length in the embodiment can be set longer than that in the conventional example. That is, by adopting the driving technique according to the form example, it is not necessary to sacrifice the brightness of the screen even when the three-dimensional image is displayed.

(C) Form example 2
In the case of the above-described embodiment, it is assumed that the lighting period length of each horizontal line is fixedly set. However, in consideration of display quality, it is desirable that the lighting period length of each horizontal line can be variably changed. Below, the organic EL panel module which employ | adopted the optimization technique of lighting period length is demonstrated.

(C-1) System Configuration (a) Overall Configuration FIG. 30 shows a system configuration example of the organic EL panel module 111 according to this embodiment. Note that, in FIG. 30, the same reference numerals are given to portions corresponding to FIG. 7.
The organic EL panel module 111 shown in FIG. 30 includes a pixel array unit 33, a signal line drive unit 35, a write control line drive unit 37, a power supply control line drive unit 39, a drive condition setting unit 113, which are drive circuits thereof, And a timing generator 115.

Here, the drive condition setting unit 113 and the timing generator 115 correspond to a “drive pulse generation device” in the claims. The timing generator 115 corresponds to a “drive timing generator” in the claims.
Below, the drive condition setting part 113 and the timing generator 115 which are the structure peculiar to this form example are demonstrated.

(B) Configuration of Drive Condition Setting Unit The drive condition setting unit 113 sets the optimum peak luminance for the display frame based on the pixel data Din, and controls the lighting period length and its setting control so that the peak luminance can be obtained. This is a circuit device that sets the required scan speed of the second shift clock CK2.

  FIG. 31 shows a configuration example of the drive condition setting unit 113. 31 includes a one-frame average luminance level calculation unit 121, a peak luminance level setting unit 123, a lighting period length setting unit 125, a switching period setting unit 127, and a user setting unit 129.

(B-1) Configuration of 1-Frame Average Brightness Level Calculation Unit The 1-frame average brightness level calculation unit 121 is a processing device that calculates the average brightness level of each frame based on input pixel data Din. FIG. 32 shows an internal configuration example of the 1-frame average luminance level calculation unit 121. The one-frame average luminance level calculation unit 121 includes a pixel-by-pixel luminance level calculation unit 141 and an entire screen average luminance level calculation unit 143.

  Here, the luminance level calculation unit 141 for each pixel is a circuit device that calculates the luminance level of each pixel based on the pixel data Din. Normally, since the pixel data Din is input as primary color data, it is converted into luminance information in units of pixels by this circuit device. The overall screen average luminance level calculation unit 143 is a circuit device that calculates an average value of luminance levels calculated for all pixels constituting one frame. In the case of this embodiment, the calculation of the average luminance level is sequentially performed for each frame. However, the average luminance level may be calculated once every plural frames.

(B-2) Configuration of Peak Luminance Level Setting Unit The peak luminance level setting unit 123 is a circuit device that sets a peak luminance level corresponding to the calculated average luminance level. For example, in a frame image with a low average luminance level, the peak luminance level is set high. Conversely, for a frame image with a high average luminance level, the peak luminance level is set low so as to suppress the screen luminance. FIG. 33 shows the relationship between the peak luminance level and each gradation luminance. As shown in FIG. 33, the peak luminance level means a luminance level corresponding to the maximum gradation value.

(B-3) Configuration of Lighting Period Length Setting Unit The lighting period length setting unit 125 sets the lighting period length that realizes the sequentially set peak luminance level within a range in which the display periods do not overlap between adjacent frames. It is a circuit device. The lighting period length setting unit 125 obtains and holds the maximum value that can be set as the lighting period by internal processing.

  Here, when the lighting period length corresponding to the sequentially set peak luminance level is equal to or less than the maximum value, the lighting period length setting unit 125 sets the sequentially set lighting period length as a value for the corresponding frame. On the other hand, when the lighting period length corresponding to the sequentially set peak luminance level is larger than the maximum value, the lighting period length setting unit 125 sets the held maximum value as the lighting period length for the corresponding frame.

Now, the maximum settable lighting period is determined so as to satisfy the following equation.
Maximum value of lighting period = frame data length−switching period−DS shift period (Formula 1)
The switching period is a period necessary for switching the open / closed state of the liquid crystal shutters 17 and 19 as shown in FIG. In general, the liquid crystal shutter opening control requires a longer time than the closing control. Of course, the required switching period depends on the operating characteristics of the liquid crystal shutters 17 and 19 used by the user.

  In the case of this embodiment, the switching period is given through the switching period setting unit 127. Note that the input of the switching period to the switching period setting unit 127 is executed through the user setting unit 129, for example. Also in this example, the switching period is assumed to be 1.5 ms, the same as in Example 1.

  The DS shift period is a time allocated from the start of light emission of the horizontal line located in the first row to the start of light emission of the horizontal line located in the last row. The DS shift period here corresponds to the power supply control line (DSL) timing shift period in the case of FIG. In the case of FIG. 18D, the length of the DS shift period is given by 2.998 ms.

  Here, the frame data length is 8.33 ms, the switching period is 1.5 ms, and the DS shift period is 2.998 ms. In this case, the maximum value of the lighting period length is obtained as (3.832 ms) from (Equation 1). This lighting period corresponds to 46% of the frame data period. That is, FIG. 18 shows an example in which the lighting period length is the maximum value. The lighting period length setting unit 125 stores the calculated maximum value of the lighting period and uses it for the comparison process with the lighting period corresponding to the peak luminance level.

  FIG. 34 shows an example of setting the lighting period length by the lighting period length setting unit 125. FIGS. 34A and 34B show setting examples when the lighting period length corresponding to the set peak luminance level is equal to or less than the maximum value. FIG. 34C shows a setting example when the lighting period length corresponding to the set peak luminance level exceeds the maximum value or the maximum value.

(C) Configuration of Timing Generator The timing generator 115 is a circuit device that supplies a timing signal to the drive circuit described above. For example, a horizontal scanning clock, a vertical scanning clock, a first shift clock CK1, a second shift clock CK2, a start pulse st, and the like are supplied. Here, a method of setting the second shift clock CK2 that is variably set according to the lighting period length will be described.

When the timing generator 115 receives the information of the lighting period length and the switching period from the driving condition setting unit 113, the timing generator 115 executes the calculation process of the following equation and sets the multiplication number of the second shift clock CK with respect to the first shift clock CK1. To do.
Multiplication number = frame data period / (frame data period− (lighting period + switching period)) (Formula 2)
As described above, the frame data period is 8.33 ms, and the switching period is 1.5 ms. When the lighting period length is given as a maximum value, the value is 3.832 ms.

If this value is substituted into (Equation 2), the multiplication number is 2.77. That is, it can be seen that the second shift clock CK may be set to 2.77 times the speed of the first shift clock CK1. FIG. 18 satisfies this condition.
FIG. 35 shows an example of a driving operation when the lighting period length is given by 1.666 ms (that is, when the lighting period is given by 20% of the frame data period). In this case, using (Equation 2), it can be seen that the second shift clock CK may be set to 1.61 times the speed of the first shift clock CK1.

  FIG. 35 (A) is a waveform diagram of a vertical synchronization pulse giving one frame period. FIG. 35B shows an image stream. FIG. 35C shows a scan operation of a control pulse for driving write control line WSL. FIG. 35D is a diagram for explaining the arrangement relationship between the non-light emitting period of each horizontal line, and the lighting period and the extinguishing period during the light emitting period.

FIG. 35D shows that the lighting period length is shortened. In addition, as shown by the bold arrows in FIG. 35D, it can be seen that the straight line connecting the lighting start timings has a gentler slope than in the case of FIG. This is because the scan speed is relatively low.
Further, since the lighting start timing of each horizontal line is delayed from FIG. 18, the waiting time T is also longer than that in FIG.

  The timing generator 115 generates a second shift clock CK2 having a clock speed set by using (Equation 2), and supplies the second shift clock CK2 to the power supply control line driving unit 39. In addition, the timing generator 115 obtains an optimal waiting time T from the completion of mobility correction for the first row to the start of lighting based on the second shift clock CK2, and sets the set pulse in accordance with the expiration timing of the waiting time. A start pulse st13 giving output timing is output. Similarly, after the lighting period has elapsed from the output of the start pulse st13, a start pulse st14 that gives the output timing of the reset pulse is output.

  In the case of this embodiment, the timing generator 115 sets the output timing of the start pulses st13 and st14 with reference to the lookup table. In the lookup table, for example, output timing information of each pulse is associated with a combination of the switching period and the speed or multiplication number of the second shift clock CK2.

  However, the timing of the start pulses st13 and st14 can also be obtained by calculation. Further, for example, in the lookup table, the output timing information of each pulse may be stored in association with the combination of the switching period and the lighting period.

(C-2) Driving Operation and Summary As described above, in the case of this embodiment, regardless of whether the input image is a two-dimensional image or a three-dimensional image, it is based on the average luminance level of each frame. An optimal peak luminance level is set.
Next, the lighting period length reflecting this peak luminance level is set within a range in which the display periods of two adjacent frames do not overlap.

  Thereafter, the second shift clock CK2 is supplied to the power supply control line drive unit 39 based on the set lighting period length and switching period information, and the power supply control is performed only for the lighting period from the lighting start timing for the horizontal line of the first row. A control pulse for controlling the transistor N3 to be turned on is output.

  As a result, the lighting period of each frame can be set to a luminance level reflecting the contents of the input image. In particular, even when a three-dimensional image is displayed, it is possible to realize brightness control reflecting the contents of the display image while executing switching display between the left-eye image and the right-eye image. That is, the display quality of the three-dimensional image can be improved. Of course, the display quality of a two-dimensional image can also be improved.

(D) Other Embodiments (D-1) Other Structures of Subpixels In the case of the above-described embodiments, the case where the subpixel 51 is configured by three N-channel thin film transistors has been described.
However, the thin film transistor constituting the sub-pixel 51 may be a P-channel thin film transistor.

37 and 38 show examples of this type of circuit. Note that FIG. 37 is an example in which only the thin film transistors are replaced with P-channel thin film transistors while maintaining the connection relationship of the sub-pixels 51 according to the embodiment. On the other hand, FIG. 38 shows a circuit example in which the connection of the storage capacitor Cs is changed. In the case of FIG. 38, one electrode of the storage capacitor Cs is connected to the fixed power supply line (VDD0).
Further, the number of thin film transistors constituting the sub-pixel 51 may be four or more, or two. The driving technique according to the invention can be applied to any circuit configuration of the sub-pixel 51 as long as the supply and stop of the driving power can be controlled in units of horizontal lines.

(D-2) Notification Device for Switching Timing In the case of the above-described embodiment, the case where the switching timing of the liquid crystal shutter is notified to the glasses 9 with the liquid crystal shutter by infrared communication has been described.
However, a wireless communication technique that can be used now or in the future can be applied to the notification of the switching timing.

(D-3) Product Example (a) System Configuration In the above description, the panel structure and driving method of the organic EL panel module alone have been described. However, the organic EL panel module described above is also distributed in the form of products mounted on various electronic devices. Examples of mounting on other electronic devices are shown below.

  FIG. 39 shows a conceptual configuration example of the electronic device 151. The electronic device 151 includes a display panel module 153 equipped with the drive circuit described above, a system control unit 155, an operation input unit 157, and a switching timing notification device 159.

  Here, the processing content executed by the system control unit 155 differs depending on the product form of the electronic device 151. The operation input unit 157 is a device that receives an operation input to the system control unit 155. For the operation input unit 157, for example, a switch, a button, other mechanical interfaces, a graphic interface, or the like is used.

  In addition, as illustrated in FIG. 39, the switching timing notification device 159 may be externally attached to the housing of the electronic device 151 as an independent device, as well as being integrally attached to the housing of the electronic device 151.

(B) Specific Example FIG. 40 shows an example of an external appearance when the electronic apparatus is a television receiver. The television receiver 161 has a structure in which a display screen 165 and a switching timing notification device 167 are arranged on the front surface of the housing 163. The portion of the display screen 165 here corresponds to the organic EL panel module described in the embodiment.

Also, for example, a computer is assumed as this type of electronic apparatus. FIG. 41 shows an example of the appearance of a notebook computer 161.
The notebook computer 161 includes a lower casing 163, an upper casing 165, a keyboard 167, a display screen 169, and a switching timing notification device 171. Among these, the display screen 169 corresponds to the organic EL panel module described in the embodiment.
In addition to these, a game machine, an electronic book, an electronic dictionary, etc. are assumed as an electronic device.

(D-4) Other Display Device Examples In the above-described embodiments, the case where the invention is applied to the organic EL panel module has been described.
However, the configuration of the power supply circuit described above can also be applied to other self-luminous display panel modules.
For example, the present invention can be applied to a display device in which LEDs are arranged in a matrix or a display panel module in which light emitting elements having a diode structure are arranged on a screen. For example, it can be applied to an inorganic EL panel.

(D-5) Others Various modifications can be considered for the above-described embodiments within the scope of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure which shows the conceptual diagram of the image system which can display both a 2-dimensional image and a 3-dimensional image. It is a figure explaining the operation | movement aspect of the spectacles with a liquid-crystal shutter used for visual recognition of a three-dimensional image. It is a figure which shows the equivalent circuit of the electronic function part of spectacles with a liquid-crystal shutter. It is a figure explaining the drive technique of a two-dimensional image and a three-dimensional image (conventional example). It is a figure explaining the relationship between the processing timing for every horizontal line at the time of the display of a three-dimensional image, and a display period (conventional example). It is a figure which shows the external appearance structural example of an organic electroluminescent panel module. It is a figure explaining the system structure of an organic electroluminescent panel module. It is a figure explaining a pixel arrangement. It is a figure explaining the pixel structure example of a sub pixel. It is a figure which shows the circuit structural example of a signal line drive part. It is a figure which shows the drive waveform example of a signal line. It is a figure which shows the circuit structural example of a write-control-line drive part. It is a figure which shows the circuit structural example of a power supply line drive part. It is a figure explaining the drive technique of a two-dimensional image and a three-dimensional image. It is a figure which shows the relationship between the drive waveform example of a sub pixel, and internal potential. It is a figure which shows the relationship between the drive waveform example of a sub pixel, and internal potential. It is a figure explaining the relationship between the waiting time until a lighting start, and a horizontal line. It is a figure explaining the relationship between the processing timing for every horizontal line at the time of the display of a three-dimensional image, and a display period (form example). It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of lighting operation. It is a figure which shows the equivalent circuit of the sub pixel corresponding to the time of light extinction operation | movement during a non-light-emission period. It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of the initialization operation | movement during a non-light-emission period. It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of the initialization operation | movement during a non-light-emission period. It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of the threshold value correction | amendment operation | movement during a non-light emission period. It is a figure which shows the equivalent circuit of the sub pixel corresponding to the completion time of threshold value correction | amendment operation | movement. It is a figure which shows the equivalent circuit of the sub pixel corresponding to operation | movement from the completion of threshold value correction operation to the start of signal potential writing. It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of signal potential write-in operation. It is a figure which shows the equivalent circuit of the sub pixel corresponding at the time of a mobility correction | amendment operation | movement. It is a figure which shows the equivalent circuit of the sub pixel corresponding to the waiting time until lighting start. It is a figure which shows the equivalent circuit of the sub pixel corresponding after lighting start. It is a figure explaining the system structure of an organic electroluminescent panel module. It is a figure which shows the circuit structural example of a drive condition setting part. It is a figure which shows the circuit structural example of a 1 frame average brightness | luminance level calculation part. It is a figure explaining the relationship between a peak luminance level and each gradation luminance. It is a figure which shows the example of a setting of lighting period length. It is a figure explaining the relationship between the processing timing for every horizontal line at the time of the display of a three-dimensional image, and a display period (form example). It is a figure explaining the relationship between the processing timing for every horizontal line at the time of the display of a three-dimensional image, and a display period (another form example). It is a figure explaining the other circuit structural example of a sub pixel. It is a figure explaining the other circuit structural example of a sub pixel. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device.

Explanation of symbols

31 Organic EL Panel Module 33 Pixel Array Unit 35 Signal Line Drive Unit 37 Write Control Line Drive Unit 39 Power Control Line Drive Unit 41 Timing Generator 113 Drive Condition Setting Unit 115 Timing Generator 167 Switching Timing Notification Device

Claims (7)

A pixel array unit in which sub-pixels configured by current-driven self-light-emitting elements and pixel circuits that drive and control the self-light-emitting elements are arranged in a matrix;
A signal line driver for driving the signal line;
A write control line driver that controls writing of the potential appearing on the signal line to the sub-pixel based on a first scan clock;
A power supply control unit for controlling supply and stop of drive power to the sub-pixel, wherein the drive power supply timing for defining the lighting periods of the self-light-emitting elements in a line-sequential manner is faster than the first scan clock. A power supply control unit that controls based on the second scan clock;
A peak luminance level setting unit for sequentially setting an optimum peak luminance level for input image data;
A lighting period length setting unit that sets a lighting period length that achieves a sequentially set peak luminance level within a range in which display periods do not overlap between adjacent frames;
A display timing module that generates the second scan clock at a clock speed that realizes the set lighting period length, and that supplies the generated second scan clock to the power supply control unit. . The signal line drive unit, the write control line drive unit, and the power supply control unit operate at a common drive timing when displaying either a two-dimensional image or a three-dimensional image. Display panel module. The waiting time from the completion of signal potential writing to the start of lighting in each horizontal line is
The first horizontal line that completes signal potential writing first is set to be the longest,
The second horizontal line for which signal potential writing is completed last is set to be the shortest,
For each horizontal line located between the first and second horizontal lines, the length of the waiting time is set to change linearly according to the positional relationship with the first and second horizontal lines. The display panel module according to claim 2. The display module according to claim 3, wherein a period of the first scan clock is set to coincide with a horizontal scanning period. A pixel array unit in which sub-pixels each including a current-driven self-light-emitting element and a pixel circuit that drives and controls the self-light-emitting element are arranged in a matrix; a signal line driver that drives a signal line; and a signal line A write control line drive unit that controls writing of the potential appearing in the sub-pixel based on a first scan clock, and a power supply control unit that controls supply and stop of drive power to the sub-pixel. And a power supply control unit that controls the supply timing of the drive power supply that prescribes the lighting period of the self-light-emitting element line-sequentially based on a second scan clock that is faster than the first scan clock. As a panel module drive pulse generator,
A peak luminance level setting unit for sequentially setting an optimum peak luminance level for input image data;
A lighting period length setting unit that sets a lighting period length that achieves a sequentially set peak luminance level within a range in which display periods do not overlap between adjacent frames;
A drive timing generation unit that generates the second scan clock at a clock speed that realizes the set lighting period length and supplies the generated second scan clock to the power supply control unit. apparatus. A driving method of a pixel array unit in which sub-pixels configured by current-driven self-light-emitting elements and pixel circuits that drive and control the self-light-emitting elements are arranged in a matrix,
A first process for driving a signal line;
A second process for controlling writing of the potential appearing on the signal line to the sub-pixel based on the first scan clock;
A process for controlling the supply and stop of the drive power to the sub-pixel, wherein the drive power supply timing for defining the lighting period of the self-light-emitting element line-sequentially is a second speed higher than that of the first scan clock. A third process controlled based on the scan clock of
A fourth process for sequentially setting an optimum peak luminance level for the input image data;
A fifth process of setting a lighting period length for realizing a sequentially set peak luminance level within a range in which display periods do not overlap between adjacent frames;
And a sixth process for generating the second scan clock at a clock speed that realizes the set lighting period length and supplying the generated second scan clock for the third process. Part driving method. A pixel array unit in which sub-pixels each including a current-driven self-light-emitting element and a pixel circuit that drives and controls the self-light-emitting element are arranged in a matrix; a signal line driver that drives a signal line; and a signal line A write control line drive unit that controls writing of the potential appearing in the sub-pixel based on a first scan clock, and a power supply control unit that controls supply and stop of drive power to the sub-pixel. A power supply control unit that controls the supply timing of the drive power that defines the lighting periods of the self-light-emitting elements line-sequentially based on a second scan clock that is faster than the first scan clock; and an input image The peak brightness level setting section that sequentially sets the optimum peak brightness level for the data and the lighting period length that realizes the sequentially set peak brightness level are displayed between adjacent frames. A lighting period length setting unit that is set within a non-overlapping range, the second scan clock having a clock speed that realizes the set lighting period length is generated, and the generated second scan clock is controlled by the power supply control. A display panel module having a drive timing generation unit to be supplied to the unit;
A system controller that controls the operation of the entire system;
And an operation input unit for the system control unit.