JP2010050316A - Multilayer electronic component and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a tombstone phenomenon occurs and, in the case of a small one, migration tends to occur on the top surface of an element because the dimension of an external terminal on an end surface of a laminate is different from the dimension of an external terminal on a side surface of the laminate. <P>SOLUTION: In a laminate, which is formed by alternately laminating insulator layers and conductor patterns, a circuit element is formed by the conductor patterns, and the circuit element is connected to between multiple external terminals formed in outside surfaces of the laminate. The multiple external terminals are formed by forming conductors from the bottom surface to side surfaces of the laminate and from the bottom surface to end surfaces of the laminate through a photolithographic technique so that the width of the external terminal formed in each side surface of the laminate is the same as the width of the external terminal formed in each end surface of the laminate and that the length of each external terminal is smaller than the thickness of the laminate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention is a laminated type in which an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. The present invention relates to an electronic component and a manufacturing method thereof.

  As shown in FIG. 10, an insulating layer 101 and a conductor pattern 102 are laminated on a conventional multilayer electronic component, and a coil and a capacitor are formed in the laminate, and the coil and the capacitor are formed on the outer surface of the laminate. Some are connected between the formed external terminals. FIG. 11A shows the appearance of such a conventional multilayer electronic component. The external terminals 111 and 112 are formed by applying a conductive paste to the end face and side face of the laminate 110 by dipping, transferring, printing, or the like. These are formed by firing them together and plating them.

  In such a conventional multilayer electronic component, since the size of the external terminal 111 formed on the end face of the multilayer body and the external terminal 112 formed on the side surface of the multilayer body are different, the plating thickness differs depending on the external terminal. When this multilayer electronic component is mounted on a mounting substrate and connected with solder, there is a problem that chip standing (tombstone phenomenon) occurs. In addition, such a conventional multilayer electronic component is difficult to hold with a jig or the like after being divided into elements due to the downsizing of the shape, and the dimensions of the external terminals are likely to vary due to sagging or bleeding of the conductive paste. .

In order to prevent this chip standing (tombstone phenomenon), as shown in FIG. 11B, an external terminal 111 formed on the end surface of the multilayer body 110 and an external terminal 112 formed on the side surface of the multilayer body 110 are formed. In order to have the same size, a conductive paste is applied to the end face and the side face of the laminated body, and plating is performed on this.
However, since such conventional multilayer electronic components also have external terminals formed on the top surface, those with a reduced size have a narrow spacing between the external terminals on the top surface and are affected by humidity and other factors. Migration was likely to occur between external terminals on the top surface. Moreover, such a conventional multilayer electronic component cannot solve the problem that it is difficult to hold it with a jig or the like after being divided into elements due to the downsizing of the shape.

In order to improve the difficulty of holding the element with a jig or the like, as shown in FIG. 11 (C), after forming the laminated body, a through hole is provided in a portion where the external terminal of the laminated body is formed, After filling the through-hole with a conductive paste and dividing it into each element 110 to form the external terminals 111 and 112 with the conductive paste in the through-hole, or after forming the laminate as shown in FIG. A through hole is formed in a portion of the laminate that forms the external terminal, a conductor is formed on the inner surface of the through hole, and the external terminals 111 and 112 are formed by the conductor formed on the inner surface of the through hole by being divided into each element 110. (For example, refer to Patent Document 1).
However, in such a conventional multilayer electronic component, it is necessary to form one or several through-holes in the multilayer body with a processing machine before each element is divided, and the processing time in the processing machine However, there is a problem that the cost increases correspondingly. In addition, when a drill or punch is used to form a through hole, the current processing machine has a diameter of 200 to 100 μm, and a through hole smaller than that cannot be formed, and the 0603 size (0.6 mm × 0.3 mm) × 0.3 mm) and 0402 size (0.4 mm × 0.2 mm × 0.2 mm) and other multilayer electronic components that have been reduced in size have not been able to secure a sufficient distance between external terminals. . Furthermore, when a laser is used to form a through hole, it is necessary to irradiate multiple times in order to penetrate the thickness of the element, which increases the cost and increases the diameter of the through hole from the difference in depth of focus. A difference in the lower diameter occurred, and a high-precision external terminal could not be formed.

  In order to solve such a problem, a through hole is formed in the ceramic sheet, a terminal electrode is formed in the through hole, and a laminate is formed by laminating a plurality of ceramic sheets on which the terminal electrode is formed. The laminated body is divided into each element to form an external terminal on the element, or a through hole is formed in the ceramic layer, a conductor paste is printed in the through hole to form a terminal electrode, and these are stacked. A laminated body is formed, and this laminated body is divided into elements to form external terminals on the elements (see, for example, Patent Document 2 and Patent Document 3).

Japanese Unexamined Patent Publication No. 7-297080 JP-A-6-181141 Japanese Patent Laid-Open No. 11-214235

  However, such a conventional multilayer electronic component forms a through hole in the ceramic sheet for each layer using a processing machine such as a drill, a punch, or a laser. There was a problem of increasing. In addition, when a laser is used to form a through hole, a difference occurs in the upper and lower diameters of the through holes of each ceramic sheet due to the difference in depth of focus. Concavities and convexities corresponding to the number of layers were generated, resulting in a sawtooth shape, and a highly accurate external terminal could not be formed. Furthermore, since the multilayer electronic component in which external terminals are formed as in Patent Document 3 has a through hole when the ceramic layer is printed, the shape of the through hole varies due to sagging or bleeding of the ceramic paste. In addition, in a small type such as 0603 size or 0402 size, a through hole could not be formed.

  The present invention relates to a multilayer electronic component capable of preventing chip standing (tombstone phenomenon) and reducing migration between external terminals on the top surface even in a multilayer electronic component having a reduced shape, and a method for manufacturing the same. The purpose is to provide.

The present invention is a laminated type in which an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. In electronic components, the width of the external terminals formed on the side surface of the multilayer body is the same as the width of the external terminals formed on the end surface of the multilayer body, and the lengths of all the external terminals are stacked. It is formed by forming a conductor using a photolithographic technique from the bottom surface to the side surface and from the bottom surface to the end surface so as to be thinner than the thickness of the body. The external terminal is formed with a width of 100 μm or less.
In the present invention, an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. In a multilayer electronic component manufacturing method, a photosensitive insulating film is formed using a photosensitive insulating paste, and the photosensitive insulating film is dried, exposed and developed to penetrate an insulating layer into a portion that becomes an external terminal. A step of forming a through hole and a step of forming a photosensitive conductor using a photosensitive conductor paste in the through hole of the insulator layer and drying, exposing and developing to form a conductor constituting an external terminal. Or forming a photosensitive conductor film using a photosensitive conductor paste, drying, exposing and developing the photosensitive conductor film to form a conductor constituting an external terminal; and a photosensitive insulator around the conductor Use a paste to remove the photosensitive insulator film Forming, drying, exposing, and developing the photosensitive insulator film to form an insulator layer having a conductor in a portion to be an external terminal, thereby repeating the width of the external terminal formed on the side surface of the laminate. The width of the external terminals formed on the end face of the laminate is the same, and the length of all the external terminals is thinner than the thickness of the laminate, spanning the bottom face to the side face and the bottom face to the end face of the laminate. External terminals are formed.

In the multilayer electronic component of the present invention, the plurality of external terminals have the same width of the external terminals formed on the side surface of the multilayer body and the width of the external terminals formed on the end surface of the multilayer body, and all the external terminals As the length of the chip becomes thinner than the thickness of the laminate, it is formed by forming a conductor using photolithography technology from the bottom surface to the side surface and from the bottom surface to the end surface. ) And the migration between external terminals on the upper surface can be reduced even in a multilayer electronic component having a reduced size.
In the method for manufacturing a multilayer electronic component according to the present invention, a photosensitive insulator film is formed using a photosensitive insulator paste, and the photosensitive insulator film is dried, exposed, and developed to form a portion serving as an external terminal. Forming a through-hole penetrating the insulator layer, forming a photosensitive conductor using a photosensitive conductor paste in the through-hole of the insulator layer, drying, exposing and developing a conductor constituting the external terminal; Repeating the forming step or forming a photosensitive conductor film using a photosensitive conductor paste, drying, exposing and developing the photosensitive conductor film to form a conductor constituting an external terminal, and the periphery of the conductor Forming a photosensitive insulator film using a photosensitive insulator paste, and drying, exposing and developing the photosensitive insulator film to form an insulator layer having a conductor in a portion serving as an external terminal. The width of the external terminals formed on the side surface of the laminate The width of the external terminals formed on the end face of the laminate is the same, and the length of all the external terminals is thinner than the thickness of the laminate, spanning the bottom face to the side face and the bottom face to the end face of the laminate. Since external terminals are formed, chip standing (tombstone phenomenon) can be prevented, and migration between external terminals on the top surface can be reduced even in a multilayer electronic component having a reduced shape.

In the multilayer electronic component of the present invention, an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is formed between a plurality of external terminals formed on the outer surface of the laminate. Connected. In the plurality of external terminals, the width of the external terminals formed on the side surface of the laminate is the same as the width of the external terminals formed on the end surface of the laminate, and the length of all the external terminals is the thickness of the laminate. It is formed by forming a conductor using a photolithographic technique from the bottom surface to the side surface and from the bottom surface to the end surface so as to be thinner. At this time, the width of the external terminal is formed to be 100 μm or less.
In such a multilayer electronic component of the present invention, the thickness of the external terminal plating formed on the side surface of the multilayer body is equal to the thickness of the external terminal plating formed on the end surface of the multilayer body. The stability of the device is improved. In the multilayer electronic component of the present invention, since no external terminal exists on the upper surface of the multilayer body, it is not necessary to consider the distance between the external terminals on the upper surface of the multilayer body, and the upper surface can be flattened. Furthermore, even if the multilayer electronic component of the present invention has a small shape or a large number of external terminals, variations in the shape of the external terminals can be reduced, so that highly accurate external terminals can be formed.

Hereinafter, a multilayer electronic component and a manufacturing method thereof according to the present invention will be described with reference to FIGS.
FIG. 1 is an exploded perspective view showing a first embodiment of the multilayer electronic component of the present invention, and FIG. 2 is an explanatory view of the embodiment of the multilayer electronic component of the present invention.
In FIG. 1, 11A to 11H are insulator layers, and 12A, 12B, 12C, 13A, and 13B are conductor patterns.
The insulator layers 11A to 11H are formed using an insulating material such as a magnetic material, a nonmagnetic material, and a dielectric material.
In the insulator layer 11A, through holes (four in FIG. 1) are formed at positions where external terminals on opposite end surfaces are to be formed and positions where external terminals on opposite side surfaces are to be formed. Conductors 14A1, 14A2, 14A3, and 14A4 having the same thickness as the insulator layer 11A are formed in the through holes. The conductors 14A1 and 14A3 are formed so that their end faces are exposed at the end faces of the insulator layer 11A. The conductors 14A2 and 14A4 are formed so that their end faces are exposed on the side surfaces of the insulator layer 11A. The conductor 14A1, the conductor 14A2, the conductor 14A3, and the conductor 14A4 are formed so that the width exposed on the end face or the side surface of the insulator layer 11A is the same.
The insulator layer 11B has through holes formed at positions corresponding to the through holes of the insulator layer 11A (that is, positions where external terminals on opposite side surfaces should be formed and external terminals on opposite side surfaces should be formed). Is done. These through holes are formed such that the distance from the end surface or side surface of the insulator layer 11B to the tip is shorter than the through holes formed in the insulator layer 11A. Conductors 14B1, 14B2, 14B3, and 14B4 having the same thickness as the insulator layer 11B are formed in the through holes. The conductors 14B1 and 14B3 are formed so that their end faces are exposed on the end face of the insulator layer 11B. The conductors 14B2 and 14B4 are formed so that their end faces are exposed on the side surfaces of the insulator layer 11B. The conductors 14B1 to 14B4 are formed to have the same width exposed on the end face or side face of the insulator layer 11B. At this time, the widths of the conductors 14B1 to 14B4 are formed to be the same as the widths of the conductors 14A1 to 14A4.
Insulator layer 11C has through holes formed at positions corresponding to the through holes of insulator layer 11B. These through holes are formed so that the distance from the end surface or side surface of the insulator layer 11C to the tip is equal to the through hole formed in the insulator layer 11B. Conductors 14C1, 14C2, 14C3, and 14C4 are formed in the through holes. The conductors 14C1 and 14C3 are formed so that their end faces are exposed at the end faces of the insulator layer 11C. The conductors 14C2 and 14C4 are formed so that their end faces are exposed on the side surfaces of the insulator layer 11C. The conductors 14C1 to 14C4 are formed to have the same width exposed at the end face or side face of the insulator layer 11C. At this time, the conductors 14C1 to 14C4 are formed to have the same width as the conductors 14B1 to 14B4. A capacitor conductor pattern 12A is formed on the surface of the insulator layer 11C on which the conductors 14C1 to 14C4 are thus formed. The capacitor conductive pattern 12A is formed continuously with the conductor 14C2 and the conductor 14C4.
The insulating layer 11D has through holes formed at positions corresponding to the through holes of the insulating layer 11C. Conductors 14D1, 14D2, 14D3, and 14D4 are formed in the through holes. The conductors 14D1 and 14D3 are formed so that their end faces are exposed on the end face of the insulator layer 11D. The conductors 14D2 and 14D4 are formed so that their end faces are exposed on the side surfaces of the insulator layer 11D. The conductors 14D1 to 14D4 are formed to have the same width exposed at the end face or side face of the insulator layer 11D. At this time, the conductors 14D1 to 14D4 are formed to have the same width as the conductors 14C1 to 14C4. A capacitor conductor pattern 12B and a capacitor conductor pattern 12C are formed on the surface of the insulator layer 11D on which the conductors 14D1 to 14D4 are thus formed. The capacitor conductor pattern 12B and the capacitor conductor pattern 12C are formed at positions facing the capacitor conductor pattern 12A. The capacitor conductor pattern 12B is formed continuously with the conductor 14D1. Further, the capacitor conductor pattern 12C is formed continuously with the conductor 14D3.
The insulator layer 11E has through holes formed at positions corresponding to the through holes of the insulator layer 11D. Conductors 14E1, 14E2, 14E3, and 14E4 are formed in the through holes. The conductors 14E1 and 14E3 are formed so that the end faces thereof are exposed at the end faces of the insulator layer 11E. The conductors 14E2 and 14E4 are formed so that their end faces are exposed on the side surfaces of the insulator layer 11E. The conductors 14E1 to 14E4 are formed to have the same width exposed at the end face or side face of the insulator layer 11E. At this time, the widths of the conductors 14E1 to 14E4 are formed to be the same as the widths of the conductors 14D1 to 14D4.
Insulator layer 11F has through holes formed at positions corresponding to the through holes formed on the end face of insulator layer 11E (that is, positions where external terminals on opposite end faces are to be formed). Conductors 14F1 and 14F2 are formed in the through holes. The conductors 14F1 and 14F2 are formed so that the end faces thereof are exposed on the end faces of the insulator layer 11F. The conductor 14F1 and the conductor 14F2 are formed to have the same width exposed at the end face of the insulator layer 11F. At this time, the widths of the conductors 14F1 and 14F2 are formed to be the same as the widths of the conductors 14E1 and 14E3. A coil conductor pattern 13A is formed on the surface of the insulator layer 11F on which the conductors 14F1 and 14F2 are thus formed. One end of the coil conductor pattern 13A is formed to be continuous with the conductor 14F1.
The insulating layer 11G has through holes formed at positions corresponding to the through holes of the insulating layer 11F. Conductors 14G1 and 14G2 are formed in the through holes. The conductors 14G1 and 14G2 are formed so that the end faces thereof are exposed on the end faces of the insulator layer 11G. The conductors 14G1 and 14G2 are formed to have the same width exposed at the end face of the insulator layer 11G. At this time, the conductors 14G1 and 14G2 are formed to have the same width as the conductors 14F1 and 14F2. A coil conductor pattern 13B is formed on the surface of the insulator layer 11G on which the conductors 14G1 and 14G2 are thus formed. The coil conductor pattern 13B has one end connected to the other end of the coil conductor pattern 13A and the other end connected to the conductor 14G2. A coil is formed by connecting the coil conductor pattern 13A and the coil conductor pattern 13B.
An insulator layer 11H is stacked on the upper surface of the insulator layer 11G.
A coil and a capacitor are formed by a conductor pattern in these laminates, and as shown in FIG. 2A, external terminals 21 are provided on opposite end surfaces of the laminate 20, and external terminals 22 are provided on opposite sides of the laminate 20. It is formed. The external terminal 21 is a conductor 14A1, 14B1, 14C1, 14D1, 14E1, 14F1, 14G1 exposed on one end face of the multilayer body, or a conductor 14A3, 14B3, 14C3, 14D3, 14E3 exposed on the other end face of the multilayer body. 14F3 and 14G3. The external terminal 22 is formed by the conductors 14A2, 14B2, 14C2, 14D2, 14E2 exposed on one side surface of the multilayer body, or the conductors 14A4, 14B4, 14C4, 14D4, 14E4 exposed on the other side surface of the multilayer body. As shown in FIGS. 2B and 2C, the external terminal 21 and the external terminal 22 have the same width W, and the length H1 of the external terminal 21 and the length H2 of the external terminal 22 are the same as those of the laminate. It is formed smaller than the thickness H. Further, the length H1 of the external terminal 21 connected to the coil disposed in the upper layer than the capacitor is formed to be longer than the length H2 of the external terminal 22 connected to the capacitor. As shown in FIG. 2D, the conductor 14A1, the conductor 14A2, the conductor 14A3, and the conductor 14A4 are exposed on the bottom surface of the laminate 20 to form an external terminal 21 and an external terminal 22. The distance between the end face of the laminated body of the external terminals 21 and the tip and the distance between the side face of the laminated body of the external terminals 22 and the tip are formed to be equal.
The external terminal 21 and the external terminal 22 formed in the laminate are plated.
In the multilayer electronic component formed in this way, external terminals are not formed on the top surface of the multilayer body, and the width of the external terminals formed on the side surfaces of the multilayer body and the external terminals formed on the end surfaces of the multilayer body. The terminal width is the same, and the length of all external terminals is smaller than the thickness of the laminate.

Such a multilayer electronic component is manufactured as follows. First, as shown in FIG. 3 (A), a photosensitive insulator paste is applied to the entire surface of a support (not shown) such as a PET film and dried, and then a photosensitive insulator film 31 is formed on the support. Is formed. The photosensitive insulator paste is formed into a paste form by mixing a photosensitive agent with insulating ceramics such as a magnetic substance and a dielectric, and the thickness is uniform using a method such as screen printing, spin coating, doctor blade, etc. In this manner, it is coated on a support.
Next, the photosensitive insulator film 31 is exposed to light and exposed to light, and then developed with a developing solution and dried. As a result, as shown in FIG. An insulator layer 11A having a through hole H is formed at a position where an external terminal is to be formed.
Subsequently, as shown in FIG. 3C, a photosensitive conductor paste is applied on the surface of the insulator layer 11A and in the through holes, dried, and the photosensitive conductor 34 is put in the through holes of the insulator layer 11A. Is filled. The photosensitive conductor paste is formed into a paste by mixing a photosensitive material into a conductive material such as silver, silver-palladium alloy, copper, nickel, etc., and is an insulator using methods such as screen printing, spin coating, doctor blade, etc. By coating the surface of the layer 11A, the through hole H is filled.
Further, the photosensitive conductor 34 is exposed to light and exposed to light, and then developed with a developing solution and dried. As a result, as shown in FIG. 3D, the conductor is placed in the through hole of the insulator layer 11A. 14A1, 14A2, 14A3, 14A4 are formed.
Next, by repeating the steps of FIGS. 3A to 3D a predetermined number of times, insulation having conductors 14B1, 14B2, 14B3, and 14B4 on the insulator layer 11A on which the conductors 14A1 to 14A4 are formed. A predetermined number of body layers 11B are formed (one layer in FIG. 3). At this time, the through hole of the insulator layer 11B is formed so that the lower layer conductor is exposed, and the conductor formed in the through hole is connected to the lower layer conductor.
Subsequently, a photosensitive insulator paste is applied to the entire surface of the insulator layer 11B having the conductors 14B1 to 14B4 so as to have a uniform thickness, and dried, as shown in FIG. A photosensitive insulator film 31C is formed on the insulator layer 11B.
Further, after exposing the photosensitive insulator film 31C to light by irradiating with light, developing with a developer and drying it, each element is formed on the insulator layer 11B as shown in FIG. 4B. An insulating layer 11C having a through hole H is formed at a position where external terminals on the end face and side face are to be formed. The conductors 14B1 to 14B4 are exposed on the bottom surface of the through hole H of the insulator layer 11C.
Next, a photosensitive conductor paste is applied to the entire surface of the insulator layer 11C so as to have a uniform thickness, and is dried, so that the through-holes of the insulator layer 11C are formed as shown in FIG. A photosensitive conductor is filled therein, and a photosensitive conductor film 32 is formed on the surface of the insulator layer 11C.
Subsequently, the photosensitive conductor film 32 is exposed to light and exposed to light, and then developed with a developing solution and dried. As a result, as shown in FIG. The conductors 14C1, 14C2, 14C3, and 14C4 are formed, and the capacitor conductor pattern 12A connected to the conductors 14C2 and 14C4 is formed on the surface of the insulator layer 11C. The conductors 14C1, 14C2, 14C3, and 14C4 are connected to the conductors 14B1, 14B2, 14B3, and 14B4 exposed on the bottom surfaces of the through holes of the insulator layer 11C, respectively.
Further, a photosensitive insulator paste is applied to the entire surface of the insulator layer 11C on which the capacitor conductor pattern 12A is formed so as to have a uniform thickness, and is dried, as shown in FIG. In addition, a photosensitive insulator film 31D is formed on the insulator layer 11C.
Subsequently, the photosensitive insulator film 31D is exposed to light and exposed to light, and then developed with a developing solution, and then dried, as shown in FIG. 4F, on the insulator layer 11C. An insulator layer 11D having a through-hole H is formed at a position where an external terminal on the end face and side face of each element is to be formed. Conductors 14C1 to 14C4 are exposed on the bottom surface of the through hole H of the insulator layer 11D.
Next, a photosensitive conductor paste is applied over the entire surface of the insulator layer 11D so as to have a uniform thickness, and is dried to obtain through-holes in the insulator layer 11D as shown in FIG. A photosensitive conductor is filled therein, and a photosensitive conductor film 32 is formed on the surface of the insulator layer 11D.
Subsequently, the photosensitive conductor film 32 is exposed to light and exposed to light, and then developed with a developing solution and dried. As a result, as shown in FIG. The conductors 14D1, 14D2, 14D3, and 14D4 are formed on the insulating layer 11D, and the capacitor conductor pattern 12B connected to the conductor 14D1 and the capacitor conductor pattern 12C connected to the conductor 14D3 are formed on the surface of the insulator layer 11D. . The conductors 14D1 to 14D4 are connected to the conductors 14C1 to 14C4 exposed on the bottom surfaces of the through holes of the insulator layer 11D, respectively.
Further, a photosensitive insulator paste is applied to the entire surface of the insulator layer 11D on which the capacitor conductor patterns 12B and 12C are formed, dried, exposed, developed, and dried, thereby obtaining the structure shown in FIG. As shown in (I), an insulator layer 11E having a through hole H is formed on the insulator layer 11D.
Subsequently, as shown in FIG. 4 (J), a photosensitive conductor paste is applied to the surface of the insulator layer 11E and the through holes, and dried to dry the photosensitive conductor in the through holes of the insulator layer 11E. 34E is filled.
Next, the photosensitive conductor 34E is exposed to light and exposed to light, and then developed with a developing solution, and then dried. As shown in FIG. 4 (K), the photosensitive conductor 34E enters the through hole of the insulator layer 11E. Conductors 14E1, 14E2, 14E3, and 14E4 are formed.
Further, a photosensitive insulator paste is applied to the entire surface of the insulator layer 11E on which the conductors 14E1 to 14E4 are formed so as to have a uniform thickness, and is dried, as shown in FIG. A photosensitive insulator film 31F is formed on the insulator layer 11E.
Subsequently, the photosensitive insulator film 31F is exposed to light and exposed to light, and then developed with a developing solution, and then dried, as shown in FIG. An insulator layer 11F having a through hole H is formed at a position where an external terminal on the end face of the element is to be formed. The conductors 14E1 and 14E3 are exposed on the bottom surface of the through hole H of the insulator layer 11F.
Next, a photosensitive conductor paste is applied to the entire surface of the insulator layer 11F so as to have a uniform thickness, and is dried, so that the through holes of the insulator layer 11F are formed as shown in FIG. A photosensitive conductor is filled therein, and a photosensitive conductor film 33 is formed on the surface of the insulator layer 11F.
Subsequently, the photosensitive conductor film 33 is exposed to light and exposed to light, and then developed with a developing solution, and then dried. As a result, as shown in FIG. The conductors 14F1 and 14F2 are formed on the insulating layer 11F, and the coil conductor pattern 13A connected to the conductor 14F1 is formed on the surface of the insulator layer 11F. The conductors 14F1 and 14F2 are connected to the conductors 14E1 and 14E3 exposed on the bottom surfaces of the through holes of the insulator layer 11F, respectively.
Subsequently, a photosensitive insulator paste is applied to the entire surface of the insulator layer 11F on which the coil conductor pattern 13A is formed so as to have a uniform thickness, and dried, as shown in FIG. Similarly, the photosensitive insulator film 31G is formed on the insulator layer 11F.
Next, the photosensitive insulator film 31G is exposed to light and exposed to light, and then developed with a developing solution, and then dried, as shown in FIG. An insulator layer 11G having a through hole H at a position where an external terminal of the element is to be formed and a through hole S at a position facing one end of the coil conductor pattern 13A is formed. The conductors 14F1 and 14F2 are exposed on the bottom surface of the through hole H, and the coil conductor pattern 13A is exposed on the bottom surface of the through hole S.
Subsequently, a photosensitive conductor paste is applied to the entire surface of the insulator layer 11G so as to have a uniform thickness, and is dried, whereby the through-holes of the insulator layer 11G are formed as shown in FIG. A photosensitive conductor is filled in the inside and the through hole, and a photosensitive conductor film 33 is formed on the surface of the insulator layer 11G.
Subsequently, the photosensitive conductor film 33 is exposed to light and exposed to light, and then developed with a developing solution and dried to obtain a through-hole in the insulator layer 11G as shown in FIG. 5 (H). Conductors 14G1 and 14G2 are formed therein, and a coil conductor pattern 13B connected to the conductor 14G2 is formed on the surface of the insulator layer 11G. The conductors 14G1 and 14G2 are connected to the conductors 14F1 and 14F2 exposed on the bottom surfaces of the through holes of the insulator layer 11G, respectively.
An insulator layer 11H is formed on the surface of the insulator layer 11G on which the coil conductor pattern 13B is formed. As shown in FIG. 5I, the stacked body thus stacked is cut at a portion indicated by a one-dot chain line and divided into each element. As shown in FIGS. 1 and 2, each of the divided elements is formed with an external terminal 21 on the opposite end face of the laminate and an external terminal 22 on the opposite side face of the laminate. The external terminals 21 and 22 are plated.
In the multilayer electronic component of the present invention formed in this way, the size of the diameter can be made equal above and below the through-hole, so that the external terminals do not have irregularities for the number of layers and become serrated, and A highly accurate external terminal can be formed without damaging the underlying conductor constituting the external terminal.

FIG. 6 is an exploded perspective view showing a second embodiment of the multilayer electronic component of the present invention.
In the insulator layer 61A, four through holes are formed at positions where external terminals are to be formed, and a conductor 64A having the same thickness as the insulator layer 61A is formed in each through hole. The four conductors 64A are formed so as to have the same width exposed at the end face or side face of the insulating layer 61A.
In the insulator layer 11B, four through holes are formed at positions where external terminals are to be formed, and a conductor 64B having the same thickness as the insulator layer 61B is formed in each through hole. The four conductors 64B are formed so that the width exposed at the end face or side face of the insulating layer 61B is the same as that of the conductor 64A, and the distance from the end face to the tip is shorter than the conductor 64A.
In the insulating layer 61C, four through holes are formed at positions where external terminals are to be formed, and a through hole H having the same size as the capacitor conductor pattern is formed in the central portion. In the four through-holes, a conductor 64C whose end face is exposed on the end face or side face of the insulating layer 61C is formed. In the through hole H, a capacitor conductor pattern 62A connected to the two conductors 64C exposed on the side surface of the insulator layer 61C is formed. The conductor 64C and the capacitor conductor pattern 62A are formed to have the same thickness as the insulator layer 61C.
In the insulator layer 61D, four through holes are formed at positions where external terminals are to be formed, and a conductor 64D having the same thickness as the insulator layer 61D is formed in each through hole. The conductor 64D is formed so that the end surface is exposed on the end surface or the side surface of the insulator layer 61D.
In the insulating layer 61E, four through holes are formed at positions where external terminals are to be formed, and two through holes H having the same size as the capacitor conductor pattern are formed at the center. In the four through-holes, a conductor 64E whose end face is exposed on the end face or side face of the insulator layer 61E is formed. In the two through holes H, capacitor conductor patterns 62B and 62C connected to the conductors 64E exposed at the end faces of the insulator layer 61E are formed. The conductor 64E and the capacitor conductor patterns 62B and 62C are formed to have the same thickness as the insulator layer 61E.
In the insulator layer 61F, four through holes are formed at positions where external terminals are to be formed, and a conductor 64F having the same thickness as the insulator layer 61F is formed in each through hole. The conductor 64F is formed so that the end face is exposed on the end face or side face of the insulator layer 61F.
In the insulator layer 61G, two through holes are formed at positions where external terminals are to be formed, and a conductor 64G having the same thickness as the insulator layer 61G is formed in each through hole. The conductor 64G is formed so that the end face is exposed at the end face of the insulator layer 61G.
In the insulating layer 61H, two through holes are formed at positions where external terminals are to be formed, and a through hole H having the same size as the coil conductor pattern is formed at the center. A conductor 64H whose end face is exposed at the end face of the insulator layer 61H is formed in the two through holes. In the through hole H, a coil conductor pattern 63A having one end connected to the conductor 64H exposed on one end face of the insulator layer 61H is formed. The conductor 64H and the coil conductor pattern 63A are formed to have the same thickness as the insulator layer 61H.
In the insulating layer 61I, two through holes are formed at positions where external terminals are to be formed, and through holes are formed at positions corresponding to the other ends of the coil conductor patterns. A conductor 64I having the same thickness as that of the insulator layer 61I is formed in the two through holes. The end face of the two through holes is exposed at the end face of the insulator layer 61I. A conductor S is formed in the through hole.
In the insulator layer 61J, two through holes are formed at positions where external terminals are to be formed, and a through hole H having the same size as the coil conductor pattern is formed at the center. In the two through holes, a conductor 64J is formed whose end face is exposed at the end face of the insulating layer 61J. In the through hole H, a coil conductor pattern 63B is formed in which one end is connected to the conductor 64J exposed on the other end face of the insulator layer 61J. The conductor 64J and the coil conductor pattern 63B are formed to have the same thickness as the insulator layer 61J. The other end of the coil conductor pattern 63B is connected to the other end of the coil conductor pattern 63A via the conductor S. A coil is formed by connecting the coil conductor pattern 63A and the coil conductor pattern 63B.
An insulator layer 61K is laminated on the upper surface of the insulator layer 61J.
A coil and a capacitor are formed by a conductor pattern in these laminates, and as shown in FIG. 2A, external terminals 21 are provided on opposite end surfaces of the laminate 20, and external terminals 22 are provided on opposite sides of the laminate 20. It is formed. As shown in FIGS. 2B and 2C, the external terminal 21 and the external terminal 22 have the same width W, and the length H1 of the external terminal 21 and the length H2 of the external terminal 22 are the same as those of the laminate. It is formed smaller than the thickness H. Further, the length H1 of the external terminal 21 connected to the coil disposed in the upper layer than the capacitor is formed to be longer than the length H2 of the external terminal 22 connected to the capacitor.

Such a multilayer electronic component is manufactured as follows. First, as shown in FIG. 7A, an end face and a side face of each element formed by applying a photosensitive insulator paste on a support (not shown) such as a PET film, exposing, and developing. Insulator layers 61A and 61B having through holes at positions where external terminals are to be formed, and a conductor formed in the through holes of the insulator layers 61A and 61B by applying a photosensitive conductive paste, exposing and developing. Then, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61B and dried to form a photosensitive insulator film 71C on the insulator layer 61B.
Next, the photosensitive insulator film 71C is irradiated with light and exposed to light, and then developed with a developing solution and dried. As a result, as shown in FIG. An insulator layer 61C having four through holes at positions where external terminals are to be formed and through holes H having the same shape as the capacitor conductor pattern at the center of each element is formed. The through-hole H is formed so as to be connected to two through-holes formed at positions where the external terminals on the side surfaces facing each element are to be formed. The conductor formed on the insulator layer 61B is exposed at the bottom surface of the four through holes.
Subsequently, a photosensitive conductor paste is applied to the surface of the insulator layer 61C, in the four through holes at positions where the external terminals on the end face and side face of each element are to be formed, and in the through hole H in the center of each element. Then, as shown in FIG. 7C, the insulating layer 61C has through-holes in four through holes at positions where the end terminals and side external terminals of the elements are to be formed, and through the center of each element. After the photosensitive conductor 72 is filled in the hole H, the photosensitive conductor 72 is exposed and developed, and then dried, as shown in FIG. A conductor 64C is formed in the four through holes at positions to be formed, and a capacitor conductor pattern 62A is formed in the through hole at the center of each element. The capacitor conductive pattern 62A is formed continuously to the conductor 64C exposed on the opposing side surfaces of each element. The conductor 64C is connected to the conductor exposed on the bottom surface of each of the four through holes of the insulator layer 61C.
Further, a photosensitive insulator paste is applied over the entire surface of the insulator layer 61C having the capacitor conductor pattern 62A and the conductor 64C so as to have a uniform thickness, and is dried, as shown in FIG. In the same manner, after forming the photosensitive insulator film 71D on the insulator layer 61C, the photosensitive insulator film 71D is exposed and developed, and dried, as shown in FIG. An insulating layer 61D having four through holes is formed at positions where external terminals on the end face and side face are to be formed. The conductor 64C is exposed on the bottom surfaces of the four through holes.
Next, a photosensitive conductive paste is applied to the surface of the insulator layer 61D and the four through holes at positions where the external terminals on the end face and side face of each element are to be formed, and dried to obtain FIG. 7 (G). As shown in FIG. 4, after the photosensitive conductor 74 is filled into the four through holes at positions where the external terminals on the end face and side face of each element of the insulator layer 61D are to be formed, the photosensitive conductor 74 is exposed and developed. By drying this, as shown in FIG. 7H, conductors 64D are formed in the four through holes at positions where the external terminals on the end face and side face of each element are to be formed. The conductor 64D is connected to the conductor 64C exposed on the bottom surface of the four through holes of the insulator layer 61D.
Subsequently, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61D provided with the conductor 64D so as to have a uniform thickness, and dried, as shown in FIG. 7 (I). After the photosensitive insulator film 71E is formed on the layer 61D, the photosensitive insulator film 71E is exposed and developed, and then dried, as shown in FIG. An insulating layer 61E having four through holes at positions where external terminals are to be formed and through holes H1 and H2 having the same shape as the capacitor conductor pattern at the center of each element is formed. The through holes H1 and H2 are formed so as to be continuous with two through holes formed at positions where external terminals on the opposing end surfaces of the respective elements are to be formed. The conductor 64D is exposed on the bottom surface of the four through holes.
Further, photosensitive conductor paste is applied to the surface of the insulator layer 61E, the four through holes at positions where the external terminals on the end face and side face of each element are to be formed, and the through holes H1 and H2 in the center of each element. After applying and drying, as shown in FIG. 7 (K), in the four through holes at positions where the end terminals and side external terminals of each element of the insulator layer 61E are to be formed, and in the central part of each element After the photosensitive conductor 72 is filled in the through holes H1 and H2, the photosensitive conductor 72 is exposed and developed, and dried, as shown in FIG. Conductors 64E are formed in the four through holes at positions where the terminals are to be formed, and capacitor conductor patterns 62B and 62C are formed in the through holes in the center of each element. Capacitor conductor patterns 62B and 62C are formed to be continuous with conductors 64E exposed at the opposing end faces of the respective elements. The conductor 64E is connected to the conductor 64D exposed on the bottom surfaces of the four through holes of the insulator layer 61E.
Next, the photosensitive insulator paste is applied to the entire surface of the insulator layer 61E having the conductor 64E and the capacitor conductor patterns 62B and 62C so as to have a uniform thickness, and is dried, whereby FIG. ), A photosensitive insulator film 71F is formed on the insulator layer 61E.
Subsequently, after exposing and developing the photosensitive insulator film 71F and drying it, an insulator layer having four through holes is formed at positions where the end terminals and side external terminals of each element are to be formed. The photosensitive conductor paste is applied to the surface of the insulator layer and the four through-holes at positions where the external terminals on the end face and side face of each element are to be formed, exposed, developed, and dried. As shown in (N), conductors 64F are formed in four through holes at positions where the external terminals on the end face and side face of each element of the insulator layer 61F are to be formed. The conductor 64F is connected to the conductor 64E exposed on the bottom surfaces of the four through holes of the insulator layer 61F.
Further, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61F provided with the conductor 64F so as to have a uniform thickness, and dried, as shown in FIG. 8A, the insulator layer 61F. After the photosensitive insulator film 71G is formed on the photosensitive insulator film 71G, the photosensitive insulator film 71G is exposed to light, developed, and dried. As shown in FIG. An insulator layer 61G having two through holes at positions to be formed is formed. The conductors 64F are exposed at the bottom surfaces of the two through holes.
Subsequently, a photosensitive conductor paste is applied to the surface of the insulating layer 61G and the two through holes at positions where the external terminals of the end faces of the respective elements are to be formed, and dried, as shown in FIG. Similarly, after the photosensitive conductor 74 is filled in the through hole of the insulator layer 61G, the photosensitive conductor 74 is exposed and developed, and dried, as shown in FIG. A conductor 64G is formed in the two through holes at positions where the external terminals on the end face are to be formed. The conductor 64G is connected to the conductor 64F exposed on the bottom surface of the through hole of the insulator layer 61G.
Next, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61G including the conductor 64G so as to have a uniform thickness, and dried, as shown in FIG. 8E. After the photosensitive insulator film 71H is formed on 61G, the photosensitive insulator film 71H is exposed and developed, and then dried, as shown in FIG. An insulator layer 61H having two through holes and a through hole H having the same shape as the coil conductor pattern at the center of each element is formed at a position where a terminal is to be formed. The conductors 64G are exposed at the bottom surfaces of the two through holes.
Subsequently, a photosensitive conductive paste is applied to the surface of the insulator layer 61H, the two through holes at positions where the external terminals on the end faces of the elements are to be formed, and the through hole H in the center of each element, and dried. As shown in FIG. 8G, the photosensitive conductor 73 is placed in the two through holes at positions where the external terminals of the end faces of the respective elements of the insulator layer 61G are to be formed and the through hole H at the center of each element. Then, the photosensitive conductor 73 is exposed to light, developed, and dried. As shown in FIG. 8 (H), the external terminal 2 on the end face of each element of the insulator layer 61H is to be formed. A conductor 64H is formed in one through hole, and a coil conductor pattern 63A is formed in a through hole in the center of each element of the insulator layer 61H. The coil conductor pattern 63A is formed so as to be continuous with the conductor 64H having one end exposed at one end face of each element.
Further, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61H provided with the conductor 64H and the coil conductor pattern 63A so as to have a uniform thickness, and dried, as shown in FIG. Further, after forming the photosensitive insulator film 71I on the insulator layer 61H, the photosensitive insulator film 71I is exposed and developed, and dried, as shown in FIG. An insulator layer 61I is formed having two through holes at positions where the external terminals on the end face and side face are to be formed, and a through hole at a position corresponding to the other end of the coil conductor pattern.
Subsequently, the surface of the insulator layer 61I, the two through holes at positions where the external terminals of the end faces of the respective elements are to be formed, and the photosensitive conductors in the through holes at positions corresponding to the other ends of the coil conductor patterns. After applying the paste and drying, as shown in FIG. 8 (K), through holes at positions corresponding to the two through holes at positions where the external terminals of the end faces of the respective elements are to be formed and the other end of the coil conductor pattern are formed. After filling the hole with the photosensitive conductor 74, the photosensitive conductor 74 is exposed and developed, and then dried, as shown in FIG. 8 (L), the external terminals on the end faces of the respective elements of the insulator layer 61I. The conductor 64I is formed in the two through holes at the positions to be formed, and the conductor S is formed in the through hole of the insulator layer 61I.
Next, a photosensitive insulator paste is applied to the entire surface of the insulator layer 61I including the conductor 64I and the conductor S so as to have a uniform thickness, and dried, as shown in FIG. After forming the photosensitive insulator film 71J, the insulator film 71J is exposed and developed, and dried to form external terminals on the end faces and side faces of each element as shown in FIG. An insulating layer 61J having two through holes and through holes H having the same shape as the coil conductor pattern at the center of each element is formed at the power position.
Subsequently, a photosensitive conductor paste is applied to the surface of the insulator layer 61J, the two through holes at positions where the external terminals on the end faces of the elements are to be formed, and the through hole H at the center of each element, and exposure is performed. By developing, as shown in FIG. 8 (O), the conductor 64J is placed in the two through holes at positions where the external terminals of the end faces of the elements of the insulator layer 61J are to be formed, and the insulator layer 61J A coil conductor pattern 63B is formed in the through hole H at the center of the element.
After the insulator layer 61K is formed on the upper surface of the insulator layer 61J provided with the conductor 64J and the coil conductor pattern 63B, the laminate is cut at the portion indicated by the alternate long and short dash line as in FIG. Divided into elements. As shown in FIGS. 1 and 2, each of the divided elements is formed with an external terminal 21 on the opposite end face of the laminate and an external terminal 22 on the opposite side face of the laminate. The external terminals 21 and 22 are plated.

  As mentioned above, although the Example of the multilayer electronic component of this invention and its manufacturing method was described, this invention is not limited to this Example. For example, the conductor, the conductor pattern, and the insulator layer are formed by applying a photosensitive conductor paste on a support as shown in FIG. 9A to form a photosensitive conductor film, and exposing the photosensitive conductor film. 9B, a conductor 14 is formed on a support conductor as shown in FIG. 9B, a photosensitive insulator paste is applied around the conductor 14, exposed to light, and developed. As shown in FIG. 9D, an insulator layer 11 having a conductor 14 is formed, a photosensitive conductor paste is applied to the entire surface of the insulator layer 11 as shown in FIG. 9D, and the photosensitive conductor paste is exposed and developed. Then, as shown in FIG. 9E, a conductor 14 is formed on the insulator layer 11, and a photosensitive insulator paste is applied around the conductor 14 on the insulator layer 11, and exposed and developed. As shown in FIG. 9F, the insulator layer 11 having the conductor 14 is formed, and these steps are repeated a predetermined number of times. By, it may be stacked.

1 is an exploded perspective view showing a first embodiment of a multilayer electronic component of the present invention. FIG. 2 is an explanatory view of an embodiment of the multilayer electronic component of the present invention. It is a figure explaining the manufacturing method of the 1st Example of the multilayer electronic component of this invention. It is a figure explaining the manufacturing method of the 1st Example of the multilayer electronic component of this invention. It is a figure explaining the manufacturing method of the 1st Example of the multilayer electronic component of this invention. It is a disassembled perspective view which shows the 2nd Example of the multilayer electronic component of this invention. It is a figure explaining the manufacturing method of the 2nd Example of the multilayer electronic component of this invention. It is a figure explaining the manufacturing method of the 2nd Example of the multilayer electronic component of this invention. It is a figure explaining another manufacturing method of the multilayer type electronic component of the present invention. It is a disassembled perspective view of the conventional multilayer electronic component. It is a figure explaining the manufacturing method of the conventional multilayer electronic component.

Explanation of symbols

11A to 11H Insulator layers 12A to 12C Capacitor conductor patterns 13A and 13B Coil conductor patterns

Claims (4)

A laminated electronic component in which an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. In
In the plurality of external terminals, the width of the external terminals formed on the side surface of the laminate and the width of the external terminals formed on the end surface of the laminate are the same, and the length of all the external terminals is the laminate. A multilayer electronic component formed by forming a conductor using a photolithographic technique from the bottom surface to the side surface and from the bottom surface to the end surface so as to be thinner than the thickness of the multilayer body.   The multilayer electronic component according to claim 1, wherein a width of the external terminal is 100 μm or less. A laminated electronic component in which an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. In the manufacturing method of
Forming a photosensitive insulator film using a photosensitive insulator paste, drying, exposing and developing the photosensitive insulator film to form a through-hole penetrating the insulator layer in a portion to be an external terminal; The step of forming a photosensitive conductor using a photosensitive conductor paste in the through-hole of the insulator layer, drying, exposing and developing to form a conductor constituting an external terminal is repeated, and the side surface of the laminated body The laminated body has the same width as the external terminals formed on the end face of the laminate, and the length of all the external terminals is smaller than the thickness of the laminate. An external terminal is formed from the bottom surface to the side surface and from the bottom surface to the end surface. A laminated electronic component in which an insulator layer and a conductor pattern are laminated, a circuit element is formed by the conductor pattern in the laminate, and the circuit element is connected between a plurality of external terminals formed on the outer surface of the laminate. In the manufacturing method of
Forming a photosensitive conductor film using the photosensitive conductor paste, drying, exposing and developing the photosensitive conductor film to form a conductor constituting an external terminal; and a photosensitive insulator paste around the conductor The step of forming a photosensitive insulator film using the substrate, drying, exposing, and developing the photosensitive insulator film to form an insulator layer having the conductor in a portion that becomes an external terminal is repeated to form the laminate. The width of the external terminal formed on the side surface of the external body is the same as the width of the external terminal formed on the end surface of the laminate, and the length of all the external terminals is thinner than the thickness of the laminate. An external terminal is formed from the bottom surface to the side surface and from the bottom surface to the end surface of the multilayer body.

Images